Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and a memory system. The semiconductor device includes a semiconductor body, a gate structure, an isolation structure, and a first conductive structure. The semiconductor body extends in a first direction. The gate structure is located on one side of the semiconductor body in the second direction. The isolation structure is located on the other side of the semiconductor body in the second direction. The first conductive structure is located on one side of the isolation structure in the first direction. Wherein the first direction is intersected with the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for fabricating a semiconductor device, and a memory system. Background Technology

[0002] As technology evolves, traditional semiconductor devices (such as DRAM devices) are facing process challenges, while constraints such as architecture and material physics limits are slowing down miniaturization. During this period of technological change, the integration capabilities and electrical characteristics of semiconductor devices are receiving widespread attention. Summary of the Invention

[0003] In a first aspect, some embodiments of this application provide a semiconductor device. The semiconductor device includes a semiconductor body, a gate structure, an isolation structure, and a first conductive structure. The semiconductor body extends along a first direction. The gate structure is located on one side of the semiconductor body in a second direction. The isolation structure is located on the other side of the semiconductor body in the second direction. The first conductive structure is located on one side of the isolation structure in the first direction. The first direction intersects the second direction.

[0004] In an exemplary embodiment, the first conductive structure is located on one side of the gate structure in a first direction, and in the first direction, the distance between the end face of the gate structure near the first conductive structure and the end face of the first conductive structure near the isolation structure is greater than or equal to zero.

[0005] In an exemplary embodiment, the gate structure and the first conductive structure partially overlap in the second direction.

[0006] In an exemplary embodiment, in the first direction, the distance between the end face of the gate structure near the first conductive structure and the end face of the first conductive structure near the isolation structure is less than 15 nm.

[0007] In an exemplary embodiment, the semiconductor body has a first doped portion and a second doped portion at the end near the first conductive structure, and the first doped portion and the second doped portion are disposed opposite to each other in a second direction.

[0008] In an exemplary embodiment, the second doped portion faces the first conductive structure, the first doped portion has an N-type dopant element, and the second doped portion has a P-type dopant element.

[0009] In an exemplary embodiment, the semiconductor device further includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located between the gate structure and the semiconductor body. The second dielectric layer is located between the first conductive structure and the semiconductor body.

[0010] In an exemplary embodiment, the isolation structure includes a shielding structure and a third dielectric layer, wherein the shielding structure is located on the side of the semiconductor body away from the gate structure and on the side of the first conductive structure in a first direction, and the third dielectric layer is located between the shielding structure and the semiconductor body and between the shielding structure and the first conductive structure.

[0011] In an exemplary embodiment, the shielding structure includes a second conductive structure. In a first direction, the size of the second conductive structure is smaller than the size of the gate structure, and the two end faces of the second conductive structure in the first direction are located between the two end faces of the gate structure in the first direction.

[0012] In an exemplary embodiment, the third dielectric layer includes a first sublayer and a second sublayer that are bonded to each other. The first sublayer is in contact with the semiconductor body, and the second sublayer is in contact with both the first conductive structure and the second conductive structure. The first sublayer and the second sublayer are made of different materials.

[0013] In an exemplary embodiment, the shielding structure includes an air gap.

[0014] In an exemplary embodiment, the semiconductor device further includes a capacitor and a bit line structure. The capacitor is connected to the end of the semiconductor body remote from the first conductive structure. The bit line structure is connected to the end of the semiconductor body near the first conductive structure.

[0015] In an exemplary embodiment, in the first direction, the size of the gate structure is smaller than the size of the semiconductor body, and the two end faces of the gate structure in the first direction are located between the two end faces of the semiconductor body in the first direction.

[0016] In an exemplary embodiment, the ends of a plurality of semiconductor bodies arranged in a second direction near the first conductive structure are connected to each other.

[0017] In an exemplary embodiment, a first conductive structure extends along a third direction, a second conductive structure extends along a third direction, and the semiconductor device further includes a first connection structure and a second connection structure. The first connection structure extends along a first direction and is connected to the first conductive structure. The second connection structure extends along the first direction and is connected to the second conductive structure. The first direction, the second direction, and the third direction intersect each other.

[0018] In an exemplary embodiment, the gate structure is configured to apply a turn-off voltage, and the first conductive structure is configured to apply a negative voltage; the gate structure is configured to apply a turn-on voltage, and the first conductive structure is configured to apply a positive voltage.

[0019] In an exemplary embodiment, the second conductive structure is configured to apply a ground voltage or a negative voltage.

[0020] Secondly, some embodiments of this application provide a memory system. The memory system includes a memory and a controller. The memory includes semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0021] Thirdly, some embodiments of this application provide a method for fabricating a semiconductor device. The method includes: forming a semiconductor body extending along a first direction; forming a gate structure on one side of the semiconductor body in a second direction; forming an isolation structure on the other side of the semiconductor body in the second direction; and forming a first conductive structure on one side of the isolation structure in the first direction; wherein the first direction intersects the second direction.

[0022] In an exemplary embodiment, the fabrication method further includes forming a first doped portion and a second doped portion at the end of the semiconductor body near the first conductive structure, wherein the first doped portion and the second doped portion are disposed opposite to each other in a second direction.

[0023] In an exemplary embodiment, forming a second doped portion at the end of the semiconductor body near the first conductive structure includes: forming a doped semiconductor layer on the surface of the semiconductor body away from the gate structure; removing a portion of the doped semiconductor layer and retaining the portion of the doped semiconductor layer located at the end of the semiconductor body near the first conductive structure; forming the second doped portion in the region of the semiconductor body covered by the doped semiconductor layer by annealing; and removing the doped semiconductor layer.

[0024] In an exemplary embodiment, the fabrication method further includes: forming a first dielectric layer between the semiconductor body and the gate structure; and forming a second dielectric layer between the semiconductor body and the first conductive structure.

[0025] In an exemplary embodiment, forming a trench between adjacent semiconductor bodies in the second direction and forming a first conductive structure on one side of the isolation structure in the first direction includes forming a first conductive structure at the bottom of the trench; wherein forming an isolation structure on the other side of the semiconductor bodies in the second direction includes forming an isolation structure on one side of the first conductive structure in the first direction.

[0026] In an exemplary embodiment, forming an isolation structure on one side of the first conductive structure in a first direction includes: forming a third dielectric layer on the sidewall of the trench and the end face of the first conductive structure in the first direction; and forming a shielding structure inside the third dielectric layer, wherein the third dielectric layer and the shielding structure are isolation structures.

[0027] In an exemplary embodiment, the third dielectric layer includes a first sublayer and a second sublayer that are bonded to each other. The first sublayer and the second sublayer are made of different materials. The formation of the third dielectric layer on the sidewall of the trench and the end face of the first conductive structure in the first direction includes: forming the first sublayer on the sidewall of the trench; and forming the second sublayer on the surface of the first sublayer and the end face of the first conductive structure in the first direction. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0029] Figure 1A This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application;

[0030] Figure 1B This is a cross-sectional schematic diagram of the shielding structure, the first connection structure, and the second connection structure in the semiconductor device provided in the embodiments of this application;

[0031] Figure 2A and Figure 2B This is a schematic diagram of the semiconductor device provided in the embodiments of this application under different operating states;

[0032] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0033] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0034] Figure 5A This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application;

[0035] Figure 5B This is a cross-sectional schematic diagram of the shielding structure and the first connection structure in a semiconductor device provided in another embodiment of this application;

[0036] Figure 6 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application;

[0037] Figures 7A to 7I This is a schematic diagram of the semiconductor device provided in the embodiments of this application during the fabrication process;

[0038] Figure 8 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application; and

[0039] Figure 9A and Figure 9B This is a schematic block diagram of a memory system provided in an embodiment of this application. Detailed Implementation

[0040] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first conductive structure discussed herein may also be referred to as the second conductive structure, and vice versa.

[0042] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0043] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0044] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0045] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0046] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or can be inferred from the context.

[0047] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0048] Some embodiments of this application provide a semiconductor device. Figure 1A This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this application. Figure 1B This is a cross-sectional schematic diagram of the shielding structure, the first connection structure, and the second connection structure in the semiconductor device provided in the embodiments of this application.

[0049] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in the various figures illustrate the spatial relationships of the components in the semiconductor device. For example, the D1 direction may be the extension direction of the semiconductor body, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the D1 direction. The same concepts will be used throughout this application to describe the spatial relationships of the components in the semiconductor device.

[0050] like Figure 1A As shown, the semiconductor device 100 may include a semiconductor body 111, a gate structure 112, an isolation structure 113, and a first conductive structure 114. The semiconductor body 111 extends along the D1 direction. The gate structure 112 is located on one side of the semiconductor body 111 in the D2 direction. The isolation structure 113 is located on the other side of the semiconductor body 111 in the D2 direction. The first conductive structure 114 is located on one side of the isolation structure 113 in the D1 direction.

[0051] In this embodiment, a first conductive structure 114 is provided on one side of the isolation structure 113 in the D1 direction. On the one hand, it can suppress the floating body effect, reduce leakage current, improve data retention time, and improve temperature yield; on the other hand, it can increase the on-state current and improve the read and write speed of the storage cell.

[0052] The following is combined Figure 1A and Figure 1B The various components in the semiconductor device 100 of this embodiment will be further described.

[0053] In some embodiments, the semiconductor body 111 may be a columnar structure and include a first end 1111, a second end 1112, and a middle portion 1113 located between the first end 1111 and the second end 1112. For example, the semiconductor body 111 may have opposing surfaces in the D2 direction and opposing surfaces in the D3 direction. The semiconductor body 111 may be a quadrangular prism structure. The first end 1111 may be the end closer to the first conductive structure 114 in the D1 direction, and the second end 1112 may be the end farther away from the first conductive structure 114 in the D1 direction.

[0054] In some embodiments, a plurality of semiconductor bodies 111 may be arranged at intervals in the D2 and D3 directions. For example, in a row of semiconductor bodies 111 arranged in the D2 direction, a portion of each first end 1111 opposite to the middle portion 1113 is connected to each other.

[0055] In some embodiments, the material of the semiconductor body 111 may include silicon, germanium, germanium-silicon, silicon carbide, gallium nitride, or any other suitable semiconductor material. In one example, the material of the semiconductor body 111 is silicon (e.g., single-crystal silicon). For example, the central portion 1113 of the semiconductor body 111 may have a P-type dopant element. The P-type dopant element may include, but is not limited to, boron, gallium, and indium.

[0056] In some embodiments, the first end portion 1111 of the semiconductor body 111 may have a first doped portion 115 and a second doped portion 116. The second doped portion 116 will be described in detail below. In some examples, the first doped portion 115 may be a portion of the first end portion 1111 facing the gate structure 112 in the D2 direction. For example, the first doped portion 115 may have an N-type dopant element. The N-type dopant element may include, but is not limited to, phosphorus, arsenic, and antimony. For example, the first doped portion 115 may be formed by ion implantation or diffusion of the semiconductor body 111.

[0057] In some embodiments, the second end 1112 of the semiconductor body 111 may have an N-type doped element.

[0058] In some embodiments, the doping concentration of the first doped portion 115 varies along the D1 direction. For example, in the D1 direction, the doping concentration of the portion of the first doped portion 115 closer to the gate structure 112 is less than the doping concentration of the portion farther from the gate structure 112. Optionally, the doping concentration of the second end portion 1112 varies along the D1 direction. For example, in the D1 direction, the doping concentration of the portion of the second end portion 1112 closer to the gate structure 112 is less than the doping concentration of the portion farther from the gate structure 112.

[0059] In some embodiments, the gate structure 112 may be located on one side of the middle portion 1113 of the semiconductor body 111 in the D2 direction. In other words, in the D1 direction, the size of the gate structure 112 is smaller than the size of the semiconductor body 111, and the two end faces of the gate structure 112 in the D1 direction are located between the two end faces of the semiconductor body 111 in the D1 direction. The gate structure 112 may extend along the D3 direction.

[0060] In some embodiments, the material of the gate structure 112 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. In some examples, the gate structure 112 may be made of a single metallic material. In other examples, the gate structure 112 may include an adhesive layer and a metal structure (not shown) bonded together. The adhesive layer may be located on the side of the metal structure closer to the semiconductor body 111 in the D2 direction and on the side of the metal structure closer to the first conductive structure 114 in the D1 direction. The material of the adhesive layer may include, but is not limited to, titanium, titanium nitride, tantalum, and tantalum nitride. The material of the metal structure may include, but is not limited to, tungsten, molybdenum, copper, aluminum, and ruthenium.

[0061] In some embodiments, the semiconductor device 100 may further include a first dielectric layer 118. The first dielectric layer 118 may be located between the semiconductor body 111 (e.g., the middle portion 1113) and the gate structure 112. The first dielectric layer 118 may contact the gate structure 112 and the middle portion 1113 of the semiconductor body 111. The material of the first dielectric layer 118 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. High dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.

[0062] The semiconductor body 111, the first dielectric layer 118, and the gate structure 112 constitute a transistor T. The first end 1111 and the second end 1112 serve as the two active terminals of the transistor T. For example, the first end 1111 can be the drain terminal, and the second end 1112 can be the source terminal. When both the first doped portion 115 of the first end 1111 and the second end 1112 have N-type doped elements, the transistor T can be an N-type transistor. Integrating the two active terminals of the transistor T in the vertical direction helps to save planar area overhead.

[0063] It should be noted that the first doped portion 115 of the first end 1111 and the second end 1112 may have P-type doped elements. In this case, the transistor T may be a P-type crystal.

[0064] In some embodiments, isolation structure 113 can be used to electrically isolate adjacent transistors T in the D2 direction. In other words, isolation structure 113 can be located between adjacent transistors T in the D2 direction. For example, transistors T are symmetrically distributed in the D2 direction with respect to isolation structure 113.

[0065] In some embodiments, the first conductive structure 114 may be located on one side of the gate structure 112 in the D1 direction. In the D1 direction, the distance between the end face of the gate structure 112 near the first conductive structure 114 and the end face of the first conductive structure 114 near the isolation structure 113 is zero. In other words, the gate structure 112 and the first conductive structure 114 do not overlap in the D2 direction. When the semiconductor device 100 is in… Figure 1A In the illustrated placement position, the upper end face of the first conductive structure 114 is substantially flush with the lower end face of the gate structure 112. Furthermore, the first conductive structure 114 may extend along the D3 direction. The material of the first conductive structure 114 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material.

[0066] In some embodiments, the semiconductor device 100 may further include a second dielectric layer 119. The second dielectric layer 119 may be located between the semiconductor body 111 (e.g., the first end 1111) and the first conductive structure 114. The second dielectric layer 119 may be in contact with the first conductive structure 114 and with the first end 1111 of the semiconductor body 111. The material of the second dielectric layer 119 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. High dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.

[0067] In some embodiments, the semiconductor device 100 may further include a capacitor C. The capacitor C may be located on the side of the second end 1112 opposite to the middle portion 1113. The capacitor C may include, but is not limited to, a multilayer capacitor, a cup capacitor, a cylindrical capacitor, and a barrel capacitor. The capacitor C may include a first electrode, a second electrode, and an insulating medium located between the first electrode and the second electrode. For example, the first electrode of the capacitor C may be connected to the second end 1112 of the semiconductor body 111. Optionally, the first electrode of the capacitor C and the second end 1112 of the semiconductor body 111 may be connected via a capacitor connection structure 120. For example, the capacitor connection structure 120 may be used to improve the electrical connection performance between the semiconductor body 111 and the capacitor C.

[0068] One active terminal (e.g., the source terminal) of transistor T is connected to the first electrode of capacitor C. Transistor T and capacitor C constitute a memory cell, such as a DRAM memory cell. Capacitor C can be used to store data, and transistor T can act as a switch to access the stored data.

[0069] In an exemplary embodiment, the semiconductor device does not have a first conductive structure. Due to the floating body effect, DRAM memory cells are prone to leakage, especially at high temperatures. Specifically, in a DRAM memory cell, the amount of charge stored in capacitor C represents the stored binary data; for example, more charge represents logic data "1", and less charge represents logic data "0". When capacitor C stores logic data "1", charge (e.g., holes) accumulates in the semiconductor body 111 of transistor T through the GIDL / TAT mechanism, causing the potential barrier of semiconductor body 111 to decrease, and transistor T to "weakly turn on". This results in the storage time of logic data "1" in the DRAM memory cell being significantly shorter than the storage time of logic data "0". Under high-temperature conditions, the storage time of logic data "1" in the DRAM memory cell is further shortened.

[0070] During the operation of the semiconductor device 100 provided in this application embodiment, in the data storage stage of the DRAM memory cell, such as Figure 2A As shown, the gate structure 112 is configured to apply a turn-off voltage, and the first conductive structure 114 can be configured to apply a negative voltage. Due to the GIDL / TAT mechanism, the charge (e.g., holes) accumulated in the semiconductor body 111 can be released through the first end 1111 (e.g., generally along the arrow direction), thereby suppressing the "weak turn-on" of the transistor T caused by the lowering of the potential barrier in the semiconductor body 111, thus improving leakage current. During the DRAM memory cell write or read data phase, such as... Figure 2B As shown, the first gate structure 112 is configured to apply a turn-on voltage, and the first conductive structure 114 can be configured to apply a positive voltage. A portion of the first end 1111 of the semiconductor body 111 facing the first conductive structure 114 is inverted, thereby enhancing the on-state current I of the transistor T. on This improves the read and write speed of the storage unit.

[0071] In some implementations, reference continues. Figure 1AThe first doped portion 115 and the second doped portion 116 are disposed opposite to each other in the D2 direction. The second doped portion 116 may be the portion of the first end 1111 that faces the first conductive structure 114 in the D2 direction. The first doped portion 115 and the second doped portion 116 have a spacing distance in the D2 direction. For example, if the first doped portion 115 has an N-type dopant element, the second doped portion 116 may have a P-type dopant element. In this embodiment, the second doped portion 116 can further suppress the floating body effect, reduce leakage current, improve storage time, and improve temperature yield. It can also further improve the on-state current and improve the read / write speed of the memory cell.

[0072] In some embodiments, the isolation structure 113 may include a shielding structure 121. The shielding structure 121 may be located on the side of the semiconductor body 111 opposite to the gate structure 112 and on the side of the first conductive structure 114 in the D1 direction. The shielding structure 121 can reduce the coupling effect between adjacent semiconductor bodies 111 in the D2 direction. For example, the shielding structure 121 may be implemented as a second conductive structure 1211.

[0073] In some embodiments, the semiconductor device 100 may further include a third dielectric layer 122. The third dielectric layer 122 may be located between the shielding structure 121 and the semiconductor body 111, and between the shielding structure 121 and the first conductive structure 114. The material of the third dielectric layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, when the shielding structure 121 is implemented as a second conductive structure 1211, the portion of the third dielectric layer 122 located between the shielding structure 121 and the first conductive structure 114 can serve as insulation to prevent crosstalk between the first conductive structure 114 and the second conductive structure 1211 when different signals are applied.

[0074] In some embodiments, when the shielding structure 121 is implemented as a second conductive structure 1211, the size of the second conductive structure 1211 is smaller than the size of the gate structure 112 in the D1 direction, and the two end faces of the second conductive structure 1211 in the D1 direction are located between the two end faces of the gate structure 112 in the D1 direction. When the semiconductor device 100 is in Figure 1A In the illustrated placement position, the upper end face of the second conductive structure 1211 may be higher than the lower end face of the gate structure 112, and the lower end face of the second conductive structure 1211 may be lower than the upper end face of the gate structure 112. Furthermore, the second conductive structure 1211 may extend along the D3 direction. The material of the second conductive structure 1211 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material.

[0075] In some embodiments, the second conductive structure 1211 can be configured to a ground voltage or a negative voltage. For example, as... Figure 2A and Figure 2B As shown, when the gate structure 112 is configured to apply a turn-off voltage or a turn-on voltage, the second conductive structure 1211 can be configured to apply a ground voltage or a negative voltage.

[0076] In some implementations, refer again Figure 1A The third dielectric layer 122 may include a first sublayer 1221 and a second sublayer 1222 bonded together. The first sublayer 1221 may be in contact with the semiconductor body 111, and the second sublayer 1222 may be in contact with both the first conductive structure 114 and the second conductive structure 1211. For example, in the D2 direction, the second sublayer 1222 may be located between the first sublayer 1221 and the second conductive structure 1211. In the D1 direction, the second sublayer 1222 may be located between the second conductive structure 1211 and the first conductive structure 114. The first sublayer 1221 and the second sublayer 1222 may be made of different materials. For example, the first sublayer 1221 may be made of silicon oxide, and the second sublayer 1222 may be made of silicon nitride. It should be noted that when the material of the first sublayer 1221 is the same as that of the second dielectric layer 119, there is no obvious interface between them, and they can be a single integrated structure. In this embodiment, selecting a first sublayer 1221 and a second sublayer 1222 made of different materials as the third dielectric layer 122 helps to protect the third dielectric layer 122 from damage, thereby improving the yield of the semiconductor device 100.

[0077] In some embodiments, the semiconductor device 100 may further include a bit line structure 123. The bit line structure 123 may be located on a side of the first end 1111 of the semiconductor body 111 opposite to the middle portion 1113. The bit line structure 123 may extend along the D2 direction and connect to a plurality of semiconductor bodies 111 arranged in the D2 direction. For example, the plurality of bit line structures 123 may be spaced apart in the D3 direction. The material of the bit line structure 123 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material.

[0078] In some embodiments, as described above, the first conductive structure 114 may extend along the D3 direction, and the second conductive structure 1211 may extend along the D3 direction. For example... Figure 1BAs shown, the semiconductor device 100 further includes a first connection structure 124 and a second connection structure 125. The first connection structure 124 extends along the D1 direction and is connected (e.g., in contact) to the first conductive structure 114. The second connection structure 125 extends along the D1 direction and is connected (e.g., in contact) to the second conductive structure 1211. The first connection structure 124 and the second connection structure 125 are respectively used to lead the first conductive structure 114 and the second conductive structure 1211 out from the D1 direction.

[0079] In some embodiments, the materials of the first connection structure 124 and the second connection structure 125 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material.

[0080] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of this application. The same reference numerals refer to the same components. For the purpose of brevity, content identical to that in the previous embodiment will not be repeated in this embodiment and the following embodiments.

[0081] like Figure 3 As shown, the first conductive structure 114 may be located on one side of the gate structure 112 in the D1 direction. In the D1 direction, the distance d1 between the end face of the gate structure 112 near the first conductive structure 114 and the end face of the first conductive structure 114 near the isolation structure 113 is greater than zero. In other words, the gate structure 112 and the first conductive structure 114 do not overlap in the D2 direction. When the semiconductor device 100 is in Figure 3 In the placement shown, the upper end face of the first conductive structure 114 is located below the lower end face of the gate structure 112.

[0082] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application. For example... Figure 4 As shown, the gate structure 112 and the first conductive structure 114 overlap in the D2 direction. In some examples, in the D1 direction, the distance between the end face of the gate structure 112 near the first conductive structure 114 and the end face of the first conductive structure 114 near the isolation structure 113 is less than 15 nm. When the semiconductor device 100 is in Figure 4 When placed in the position shown, the upper end face of the first conductive structure 114 can be located above the lower end face of the gate structure 112, and the distance d1 between the upper end face of the first conductive structure 114 and the lower end face of the gate structure 112 is less than 15mm.

[0083] In this embodiment, the distance between the first conductive structure 114 and the gate structure 112 is less than 15mm, which ensures that the transistor T will not be affected when the first conductive structure 114 is subjected to a working voltage, and also helps to increase the process margin of the first conductive structure 114.

[0084] Figure 5A This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this application. Figure 5B This is a cross-sectional schematic diagram of the shielding structure and the first connection structure in a semiconductor device provided in another embodiment of this application. Figure 5A and Figure 5B As shown, the shielding structure 121 can be implemented as an air gap 1212. For example, the air gap 1212 can increase the equivalent capacitance between adjacent transistors T in the D2 direction, thereby improving the coupling effect and providing a shielding function. Alternatively, the air gap 1212 can be formed during the fabrication of the third dielectric layer 122 by controlling the thin film deposition process.

[0085] It should be pointed out that, Figure 5A The air gap 1212 shown is a relatively regular shape. In other examples, the air gap 1212 may be an irregular shape. No specific restrictions are imposed on this.

[0086] In some embodiments, the semiconductor device 100 may not have a second connection structure. The first connection structure 124 extends along the D1 direction and is used to lead out the first conductive structure 114 extending along the D3 direction from the D1 direction.

[0087] In other embodiments, the isolation structure 113 may not have a second conductive structure 1211 (see reference). Figure 1A The shielding structure 121 includes the air gap 1212. For example, the isolation structure 113 may be a solid structure made of one or more insulating materials.

[0088] Some embodiments of this application also provide a method for fabricating a semiconductor device. Figure 6 This is a schematic flowchart illustrating the fabrication method of the semiconductor device provided in this application. Figure 6 As shown, the semiconductor device fabrication method 200 (hereinafter referred to as fabrication method 200) may include the following steps.

[0089] S210, forming a semiconductor body extending along the first direction.

[0090] S220, a gate structure is formed on one side of the semiconductor body in the second direction.

[0091] S230, an isolation structure is formed on the other side of the semiconductor body in the second direction.

[0092] S240, a first conductive structure is formed on one side of the isolation structure in the first direction.

[0093] According to the preparation method provided in the embodiments of this application, a first conductive structure is formed on one side of the isolation structure in the first direction. On the one hand, it can suppress the floating body effect, reduce leakage current, improve data storage time, and improve temperature yield; on the other hand, it can increase the on-state current and improve the read and write speed of the storage cell.

[0094] Figures 7A to 7I This is a schematic diagram of the semiconductor device provided in the embodiments of this application during its fabrication process. Wherein, Figure 7A The intermediate structure 300a after the semiconductor body is formed is shown. Figure 7B The intermediate structure 300b after the formation of the doped semiconductor layer is shown. Figure 7C The intermediate structure 300c after removing part of the doped semiconductor layer is shown. Figure 7D The intermediate structure 300d after the formation of the second doped portion is shown. Figure 7E The intermediate structure 300e after the doped semiconductor layer has been removed is shown. Figure 7F An intermediate structure 300f is shown after the formation of the second dielectric layer, the first sublayer, and the first conductive structure. Figure 7G The intermediate structure 300g after the formation of the second sublayer is shown. Figure 7H The intermediate structure 300h is shown after the formation of the second conductive structure (i.e., the isolation structure). Figure 7I The semiconductor device 300 is shown after the formation of the capacitor connection structure, capacitor, and bit line structure.

[0095] The following is combined Figures 7A to 7I The preparation method 200, which includes steps S210 to S240, will be described by way of example.

[0096] S210

[0097] In this step, such as Figure 7A As shown, the semiconductor body 311 can be formed by etching a substrate (not shown). For example, the substrate may extend along the D2 and D3 directions. On one side of the substrate in the D1 direction, etching is performed to form a plurality of first trenches (e.g., 326) extending along the D3 direction and a plurality of second trenches extending along the D2 direction, thereby forming a plurality of semiconductor bodies 311 extending along the D1 direction. The semiconductor body 311 may include a first end 3111, a second end 3112, and a central portion 3113 located between the first end 3111 and the second end 3112.

[0098] In some embodiments, the substrate may not be completely etched during the formation of the first trench (e.g., 326), such that portions of each first end 3111 of a row of semiconductor bodies 311 arranged in the D2 direction away from the center 3113 are connected to each other.

[0099] In some embodiments, the substrate material may include silicon, germanium, germanium-silicon, silicon carbide, gallium nitride, or any other suitable semiconductor material. In one example, the substrate may be a silicon substrate, such as a single-crystal silicon substrate. Since the semiconductor body 311 is formed by etching the substrate, the material of the semiconductor body 311 is the same as the material of the substrate. For example, the material of the semiconductor body 311 may be silicon (e.g., single-crystal silicon).

[0100] In some embodiments, the fabrication method 200 may include forming a first dielectric layer 318 on one side of the semiconductor body 311 in the D2 direction. For example, adjacent semiconductor bodies 311 in the D3 direction may be filled and isolated by an insulating material. A first trench 326 is defined between a row of semiconductor bodies 311 that are adjacent in the D2 direction and arranged in the D3 direction. During the formation of the first dielectric layer 318, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to deposit an insulating material on the sidewalls of a portion of the first trench 326. It should be noted that the first trench 326 for forming the first dielectric layer 318 is alternately arranged with other first trenches 326 in the D2 direction.

[0101] In some embodiments, the fabrication method 200 further includes forming a first doped portion 315. Exemplarily, prior to forming the first dielectric layer 318, a doping process (e.g., diffusion and / or ion implantation) may be used to form the first doped portion 3111 at a first end 3111 of the semiconductor body 311. Optionally, the same doping element as the first doped portion 315 may be incorporated into a second end 3112 of the semiconductor body 311.

[0102] It should be noted that the first doped portion 315 and the second end portion 3112 doped with doped elements can be formed via the first trench 326 where the first dielectric layer 318 will be formed. For example, the type, concentration, and range of doped elements in the first doped portion 315 and the second end portion 3112 can be ensured by controlling the process parameters of the ion implantation process.

[0103] In some embodiments, during the formation of the first doped portion 315, the second end portion 3112 doped with the doped element, and the first dielectric layer 318, another portion of the first trench 326 may be filled with a sacrificial material. For example, this sacrificial material may be retained after the gate structure 312 is formed.

[0104] S220

[0105] In this step, continue to refer to Figure 7A The gate structure 312 can be formed on one side of the semiconductor body 311 in the D2 direction using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, a first dielectric layer 318 can be formed between the semiconductor body 311 and the gate structure 312.

[0106] In some embodiments, the gate structure 312 may be formed using the following process steps. First, an insulating material is filled at the bottom of the first trench 326 where the first dielectric layer 318 is formed. For example, the insulating material may be the same material as the first dielectric layer 318 and may be used to provide a relatively flat surface perpendicular to the D1 direction. Next, a conductive material may be deposited on the surface of the first dielectric layer 318 and the surface of the insulating material, and an etching process may be used to remove a portion of the conductive material located on the surface of the insulating material, thereby disconnecting the conductive material in the D2 direction. Subsequently, an etch-back process may be used to remove a portion of the disconnected individual conductive material facing away from the insulating material; this individual conductive material may be the gate structure 312.

[0107] In some implementations, such as Figures 7B to 7D As shown, the preparation method 200 may further include a second doped portion 316. In the first end portion 3111, the first doped portion 315 and the second doped portion 316 are disposed opposite to each other in the D2 direction.

[0108] In some examples, the second doped portion 316 can be formed through the following steps. First, as... Figure 7B As shown, a doped semiconductor layer 327 can be formed on the surface of the semiconductor body 311 away from the gate structure 312 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, the doped semiconductor layer 327 can be formed on the inner wall of the first trench 326. Optionally, a first filling material 328 can be formed inside the doped semiconductor layer 327. The type of dopant element in the doped semiconductor layer 327 is the same as the type of dopant element in the second doped portion 316 to be formed. Next, as... Figure 7CAs shown, a portion of the doped semiconductor layer 327 can be removed using an etch-back process, while retaining the portion of the doped semiconductor layer 327 located on one side of the first end 3111 of the semiconductor body 311 in the D2 direction. Optionally, the portion of the first filling structure 328 located on one side of the first end 3111 in the D2 direction can be removed. For example, to remove a predetermined portion of the doped semiconductor layer 327, the first filling structure 328 can be removed first, followed by the removal of the doped semiconductor layer 327. Additionally, as... Figure 7D As shown, a second filling structure 329 can be formed again in the first trench 326. The materials of the first filling structure 328 and the second filling structure 329 can be the same. Then, referring to... Figure 7D A second doped portion 316 can be formed in the region of the first end 3111 of the semiconductor body 311 covered by the doped semiconductor layer 327 through annealing. During annealing, the dopant element of the doped semiconductor layer 327 diffuses towards the first end 3111 of the semiconductor body 311 in contact with it, thereby forming the second doped portion 316 in the first end 3111. The first filling structure 328 and the second filling structure 329 ensure uniform stress distribution during annealing. Finally, as... Figure 7E As shown, the doped semiconductor layer 327 can be removed. Furthermore, if a first filling structure 328 and a second filling structure 329 are formed, both can be removed, thereby re-exposing the first trench 326. As the size of the first trench 326 in the D2 direction decreases, the difficulty of forming the second doped portion 316 via ion implantation increases. In the above example, forming the doped semiconductor layer 327 first via thin film deposition, and then using an annealing process to diffuse the dopant element towards the first end 3111 to form the second doped portion 316, reduces the fabrication difficulty of the second doped portion 316.

[0109] In some implementations, such as Figure 7F As shown, the fabrication method 200 may further include forming a second dielectric layer 319 and a first sublayer 3221. For example, the second dielectric layer 319 may be formed on the bottom inner wall of the first trench 326 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The second dielectric layer 319 may be formed on the side of the first end 3111 of the semiconductor body 311 facing away from the gate structure 312 in the D2 direction.

[0110] In some embodiments, during the formation of the second dielectric layer 319, insulating material may be deposited on the middle and upper sidewalls of the first trench 326, and this portion of insulating material may serve as the first sublayer 3221.

[0111] S240

[0112] In this step, continue to refer to Figure 7FThe first conductive structure 314 can be formed at the bottom of the first trench 326 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The first conductive structure 314 can be formed on the side of the first end 3111 of the semiconductor body 311 facing away from the gate structure 312 in the D2 direction.

[0113] In some embodiments, when a second dielectric layer 319 is formed, the second dielectric layer 319 may be formed between the semiconductor body 311 and the first conductive structure 314.

[0114] S230

[0115] In this step, in some implementations, such as Figure 7F and Figure 7G As shown, a second sublayer 3222 can be formed on the surface of the first sublayer 3221 and the end face of the first conductive structure 314 in the D1 direction using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Further, as... Figure 7G and Figure 7H A second conductive structure 3211 can be formed inside the second sublayer 3222 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The first sublayer 3221 and the second sublayer 3222 can constitute a third dielectric layer 322. The second conductive structure 3211 can serve as a shielding structure 321. The third dielectric layer 322 and the shielding structure 321 can be referred to as an isolation structure 313. The isolation structure 313 can be formed on the side of the semiconductor body 311 (e.g., the middle portion 3113) facing away from the gate structure 312 in the D2 direction. In addition, a first conductive structure 314 can be formed on the side of the isolation structure 313 in the D1 direction.

[0116] In some embodiments, the materials of the first sublayer 3221 and the second sublayer 3222 may be different. For example, the material of the first sublayer 3221 may be silicon oxide, and the material of the second sublayer 3222 may be silicon nitride. Figure 7H As shown, in the D1 direction, the side of the second conductive structure 3211 facing away from the first conductive structure 314 may be filled with an insulating material. For example, the insulating material may be the same as the material of the first sublayer 3221, such as silicon oxide. When this insulating material is etched back, since the material of the second sublayer 3222 is different from the insulating material, the second sublayer 3222 can act as a barrier to etching, thereby improving the yield.

[0117] In some embodiments, during the formation of the second sublayer 3222, an air gap (not shown) can be formed by controlling the thin film deposition process. This air gap can also serve as a shielding structure 321.

[0118] In other embodiments, a solid isolation structure (not shown) made of one or more insulating materials may be formed on one side of the middle portion 3113 of the semiconductor body 311 and the second end portion 3112 in the D2 direction and on one side of the first conductive structure 314 in the D1 direction.

[0119] In some implementations, such as Figure 7I As shown, the fabrication method 200 further includes forming a capacitor C. The capacitor C may be formed on one side of the semiconductor body 311 near the second end 3112 in the D1 direction. Optionally, a capacitor connection structure 320 may also be formed between the second end 3112 of the semiconductor body 311 and the capacitor C.

[0120] In some implementations, such as Figure 7I As shown, the fabrication method 200 may further include forming a bit line structure 323. The bit line structure 323 may be formed on one side of the first end 3111 in the D1 direction. The bit line structure 323 may extend in the D2 direction and, for example, contact a row of semiconductor bodies 311 arranged in the D2 direction.

[0121] This application also provides a memory system. Figure 8 This is a schematic block diagram of a system with a memory system provided in the embodiments of this application. Figure 9A and Figure 9B This is a schematic block diagram of a memory system provided in an embodiment of this application.

[0122] like Figure 8 As shown, system 40 can be a mobile phone, desktop computer, laptop computer, tablet computer, onboard computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 41 located therein). Figure 8 As shown, system 40 may include a host 44 and a memory system 41, the memory system 41 having one or more memories 42 and a controller 43. The host 44 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 44 may be configured to send or receive data to and from the memory 42.

[0123] Memory 42 may include the semiconductor devices described in any embodiment of this application. According to some embodiments, controller 43 is coupled to memory 42 and host 44 and is configured to control memory 42. Controller 43 may manage data stored in memory 42 and communicate with host 44. In some embodiments, controller 43 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 43 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 43 may be configured to control the operation of memory 42, such as read, erase, and program operations. Controller 43 may also be configured to manage various functions related to data stored in or to be stored in memory 42, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 43 is further configured to process error correction codes (ECCs) related to data read from or written to memory 42. Controller 43 may also perform any other appropriate functions, such as formatting memory 42. Controller 43 may communicate with external devices (e.g., host 44) according to a specific communication protocol. For example, controller 43 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0124] The controller 43 and one or more memories 42 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 41 can be implemented and packaged into different types of end electronic products. Figure 9AIn one example shown, the controller 43 and a single memory 42 may be integrated into a memory card 45. The memory card 45 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 45 may further include a connector for connecting the memory card 45 to a host computer (e.g., Figure 8 The host 44) is coupled to the memory card connector 46. In such a way... Figure 9B In another example shown, the controller 43 and multiple memories 42 may be integrated into the SSD 47. The SSD 47 may further include a connection between the SSD 47 and the host (e.g., Figure 8 The SSD connector 48 is coupled to the host 44. In some embodiments, the storage capacity and / or operating speed of the SSD 47 is higher than that of the memory card 45.

[0125] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, comprising: The semiconductor body extends along a first direction; A gate structure is located on one side of the semiconductor body in the second direction; An isolation structure is located on the other side of the semiconductor body in the second direction; as well as A first conductive structure is located on one side of the isolation structure in the first direction; Wherein, the first direction intersects with the second direction.

2. The semiconductor device according to claim 1, wherein, The first conductive structure is located on one side of the gate structure in the first direction. In the first direction, the distance between the end face of the gate structure near the first conductive structure and the end face of the first conductive structure near the isolation structure is greater than or equal to zero.

3. The semiconductor device according to claim 1, wherein, The gate structure and the first conductive structure partially overlap in the second direction.

4. The semiconductor device according to claim 3, wherein, In the first direction, the distance between the end face of the gate structure near the first conductive structure and the end face of the first conductive structure near the isolation structure is less than 15 nm.

5. The semiconductor device according to claim 1, wherein, The semiconductor body has a first doped portion and a second doped portion at the end near the first conductive structure, and the first doped portion and the second doped portion are disposed opposite to each other in the second direction.

6. The semiconductor device according to claim 5, wherein, The second doped portion faces the first conductive structure, the first doped portion has an N-type dopant element, and the second doped portion has a P-type dopant element.

7. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A first dielectric layer is located between the gate structure and the semiconductor body; and The second dielectric layer is located between the first conductive structure and the semiconductor body.

8. The semiconductor device according to claim 1, wherein, The isolation structure includes a shielding structure and a third dielectric layer, wherein the shielding structure is located on the side of the semiconductor body away from the gate structure and on the side of the first conductive structure in the first direction, and the third dielectric layer is located between the shielding structure and the semiconductor body and between the shielding structure and the first conductive structure.

9. The semiconductor device according to claim 8, wherein, The shielding structure includes a second conductive structure. In the first direction, the size of the second conductive structure is smaller than the size of the gate structure, and the two end faces of the second conductive structure in the first direction are located between the two end faces of the gate structure in the first direction.

10. The semiconductor device according to claim 9, wherein, The third dielectric layer includes a first sublayer and a second sublayer that are bonded together. The first sublayer is in contact with the semiconductor body, and the second sublayer is in contact with both the first conductive structure and the second conductive structure. The first sublayer and the second sublayer are made of different materials.

11. The semiconductor device according to claim 8, wherein, The shielding structure includes an air gap.

12. The semiconductor device according to claim 9, wherein, The first conductive structure extends along a third direction, the second conductive structure extends along the third direction, and the semiconductor device further includes: A first connecting structure extends along the first direction and is connected to the first conductive structure; and The second connection structure extends along the first direction and is connected to the second conductive structure; The first direction, the second direction, and the third direction intersect each other.

13. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 12; as well as A controller, coupled to the memory, is used to control the memory to store data.

14. A method for fabricating a semiconductor device, comprising: A semiconductor body extending along the first direction is formed; A gate structure is formed on one side of the semiconductor body in the second direction; An isolation structure is formed on the other side of the semiconductor body in the second direction; as well as A first conductive structure is formed on one side of the isolation structure in the first direction; Wherein, the first direction intersects with the second direction.

15. The preparation method according to claim 14, wherein, The preparation method further includes: A first doped portion and a second doped portion are formed at the end of the semiconductor body near the first conductive structure, wherein the first doped portion and the second doped portion are disposed opposite to each other in the second direction.

16. The preparation method according to claim 15, wherein, Forming a second doped portion at the end of the semiconductor body near the first conductive structure includes: A doped semiconductor layer is formed on the surface of the semiconductor body opposite to the gate structure; Remove a portion of the doped semiconductor layer, and retain the portion of the doped semiconductor layer located at the end of the semiconductor body near the first conductive structure; The second doped portion is formed in the region of the semiconductor body covered by the doped semiconductor layer by an annealing process; and Remove the doped semiconductor layer.

17. The preparation method according to claim 14, wherein, The preparation method further includes: A first dielectric layer is formed between the semiconductor body and the gate structure; and A second dielectric layer is formed between the semiconductor body and the first conductive structure.

18. The preparation method according to claim 14, wherein, A trench is formed between adjacent semiconductor bodies in the second direction, and a first conductive structure is formed on one side of the isolation structure in the first direction, comprising: The first conductive structure is formed at the bottom of the trench; The formation of an isolation structure on the other side of the semiconductor body in the second direction includes: The isolation structure is formed on one side of the first conductive structure in the first direction.

19. The preparation method according to claim 18, wherein, Forming an isolation structure on one side of the first conductive structure in the first direction includes: A third dielectric layer is formed on the sidewall of the trench and on the end face of the first conductive structure in the first direction; and A shielding structure is formed inside the third dielectric layer, wherein the third dielectric layer and the shielding structure constitute the isolation structure.

20. The preparation method according to claim 19, wherein, The third dielectric layer includes a first sublayer and a second sublayer bonded together, wherein the first sublayer and the second sublayer are made of different materials, and wherein forming the third dielectric layer on the sidewall of the trench and the end face of the first conductive structure in the first direction includes: The first sub-layer is formed on the sidewall of the trench; and A second sublayer is formed on the surface of the first sublayer and at the end face of the first conductive structure in the first direction.

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