Semiconductor device and method of manufacturing the same
By injecting dopants into the dielectric layer of DRAM to adjust the etching characteristics, the problem of electrical short circuits during DRAM manufacturing was solved, improving the reliability and stability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-07
- Publication Date
- 2026-03-27
AI Technical Summary
Dynamic random access memory (DRAM) is prone to defects such as electrical short circuits during manufacturing, especially short circuits caused by the movement of the cover layer of the container and landing pad, which are difficult to solve effectively.
By implanting dopants such as germanium (Ge) or nitrogen (N) into the first dielectric layer, its etching characteristics are adjusted to make it more etch-resistant in the etching process, and a second dielectric layer is deposited on it to form a capacitor structure, ensuring that the etching process does not damage the isolation layer and avoids electrical short circuits.
This improves the manufacturing reliability of DRAM, reduces the occurrence of electrical short circuits, and enhances the stability and reliability of the device.
Smart Images
Figure CN121751629A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] Dynamic random-access memory (DRAM) is a type of random-access semiconductor memory that stores each bit of data in a memory cell. DRAM is known for its high speed, high density, and scalability. However, as DRAM production scales up, its manufacturing becomes more challenging and prone to defects. These defects can lead to device malfunctions and / or failures. For example, a short circuit can occur in DRAM when the cover layer of a container or landing pad shifts. Therefore, there is a need for an efficient semiconductor device and its manufacturing method. Summary of the Invention
[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device, including providing an initial structure comprising a bit line structure, a placement pad layer adjacent to the bit line structure, and an isolation layer adjacent to the placement pad layer; depositing a first dielectric layer on the initial structure; modifying the etching characteristics of the first dielectric layer; performing an etching process on the first dielectric layer to form a first opening; and forming a capacitor structure in the first opening.
[0004] In some embodiments, modifying the etch characteristics of the first dielectric layer includes implanting dopant species into the first dielectric layer.
[0005] In some embodiments, the dopant species is germanium (Ge).
[0006] In some embodiments, the implantation of dopant species into the first dielectric layer is performed using energy in the range of about 20 keV to about 25 keV.
[0007] In some embodiments, the dopant species are implanted into the first dielectric layer using approximately 3 × 10⁻⁶ cells / layer. 16 (ions / cm) 2 ) to approximately 5×10 16 (ions / cm) 2 It is performed using Ge doses within the range of )
[0008] In some embodiments, the dopant species is nitrogen (N).
[0009] In some embodiments, the implantation of dopant species into the first dielectric layer is performed using energy in the range of about 6 keV to about 11 keV.
[0010] In some embodiments, the dopant species are implanted into the first dielectric layer using approximately 3 × 10⁻⁶ cells / layer. 16 (ions / cm) 2 ) to approximately 5×10 16 (ions / cm) 2 It is administered within the range of N doses.
[0011] In some embodiments, the first dielectric layer and the isolation layer are made of the same material, and the etching properties of the first dielectric layer are modified so that the isolation layer has higher etch resistance to etching processes than the first dielectric layer.
[0012] In some embodiments, the method further includes depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is also etched to form a first opening in both the first and second dielectric layers.
[0013] Embodiments of the present invention provide a semiconductor device including a bit line structure, a placement pad layer adjacent to the bit line structure, an isolation layer adjacent to the placement pad layer, a first dielectric layer on the isolation layer and the placement pad layer, wherein the first dielectric layer has a higher germanium (Ge) concentration or a higher nitrogen (N) concentration than the isolation layer, and a capacitor structure in the first dielectric layer.
[0014] In some embodiments, the isolation layer and the first dielectric layer have the same material.
[0015] In some embodiments, the same material is silicon nitride.
[0016] In some embodiments, a second dielectric layer is also included, which is located above the first dielectric layer, wherein the capacitor structure is located in the second dielectric layer.
[0017] In some embodiments, the second dielectric layer includes a vertical thickness, and the vertical thickness is greater than the vertical thickness of the first dielectric layer.
[0018] In some embodiments, the capacitor structure is in contact with the insulating layer and the seating pad layer.
[0019] In some embodiments, the lateral width of the capacitor structure is greater than the lateral width of the top surface of the mating layer.
[0020] In some embodiments, bit line spacers are also included along the sidewalls of the bit line structure, wherein the bit line spacers are made of the same material as the first dielectric layer.
[0021] In some embodiments, the first dielectric layer has a higher Ge concentration than the bit line spacers.
[0022] In some embodiments, the first dielectric layer has a higher N concentration than the bit line spacer. Attached Figure Description
[0023] The scope of the invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
[0024] Figure 1 This is a schematic diagram of a memory array according to a partial embodiment of the present invention.
[0025] Figure 2 This is a schematic diagram of a memory cell according to a partial embodiment of the present invention.
[0026] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a partial embodiment of the present invention.
[0027] Figure 4 This is a flowchart illustrating the patterning of first and second dielectric layers in a method of manufacturing a semiconductor device according to a partial embodiment of the present invention.
[0028] Figures 5 to 17 This is a cross-sectional view of different steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.
[0029] Figure 18 This is a cross-sectional view of a memory cell according to a partial embodiment of the present invention. Detailed Implementation
[0030] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the content of the invention. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, the content of the invention may repeatedly refer to numbers and / or letters. This repetition is for simplicity and clarity and does not itself define the relationship between the various embodiments and / or configurations discussed.
[0031] Additionally, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper,” and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. These spatial relative terms are intended to cover not only the orientations depicted in the figures but also different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.
[0032] As used herein, “approximately,” “about,” “roughly,” or “substantially” can generally mean within 20%, 10%, or 5% of a given value or range. The values given herein are approximate, meaning that the terms “approximately,” “about,” “roughly,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits shrink in size.
[0033] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including” as used in this specification designate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence of said features, integrals, steps, operations, elements, and / or components.
[0034] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection area illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection area to the non-injection area. Similarly, a buried area formed by injection can result in some injection in the area between the buried area and the surface through which the injection is carried out. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of the invention.
[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense, unless expressly defined herein.
[0036] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.
[0037] Figure 1 This is a schematic diagram of a memory array according to some embodiments of the present invention. In some embodiments, the memory array 100 includes a plurality of memory cells 101 arranged in a rectangular matrix. Figure 1 This illustrates a simple example of a 4×4 cell matrix. Other memory matrices may have thousands of cells in height and width. In some embodiments, memory array 100 may be dynamic random-access memory (DRAM).
[0038] Each row of memory cells 101 is connected by word lines 200, and each column of memory cells 101 is connected by bit lines 300. The word lines 200 can extend horizontally. The word lines 200 are parallel to each other. Furthermore, the word lines 200 can be spaced apart from each other at substantially equal intervals.
[0039] On the other hand, bit lines 300 can extend vertically. Similar to word lines 200, bit lines 300 are parallel to each other and can be spaced apart from each other at substantially equal intervals.
[0040] Figure 2 This is a schematic diagram of a memory cell according to a partial embodiment of the present invention. Specifically, Figure 2 yes Figure 1 A close-up view. In some embodiments, memory cell 101 includes access transistor 101T and storage capacitor 101C electrically connected to access transistor 101T. In some embodiments, access transistor 101T is an NMOS transistor and is configured to control a channel to memory cell 101 by turning the gate of access transistor 101T on or off.
[0041] In some embodiments, the storage capacitor 101C is configured to store information based on the state of the charge stored therein. A storage capacitor 101C in an empty state (i.e., not charged) is represented as a logic value of 0. A storage capacitor 101C in a fully charged state is represented as a logic value of 1. The memory cell 101 uses the two extreme charge states stored in the storage capacitor 101C to store one bit of data. In some embodiments, a word line 200 connected to the access transistor 101T is used to control the gate of the access transistor 101T by applying a voltage to the gate of the access transistor 101T. In some embodiments, a bit line 300 is perpendicular to the arrangement of the word line 200 and is also connected to the access transistor 101T. When the gate of the access transistor 101T is turned on, the access transistor 101T connects the storage capacitor 101C to the bit line 300, such that the logic value stored in the storage capacitor 101C is read on the bit line 300.
[0042] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor device according to a partial embodiment of the present invention. Figures 5 to 17 This is a cross-sectional view of different steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention.
[0043] Figure 3 The manufacturing method M50 can be applied to semiconductor devices. It will combine... Figures 5 to 17 Semiconductor devices and manufacturing methods M50 are discussed together. For example... Figure 3 As shown, the manufacturing method M50 may include the following operations S100, S200, S300, S400, S500, S600, S700, S800, S900 and S1000.
[0044] This document provides various operations of the embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood to benefit from this description. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.
[0045] Method M50 begins with operation S100 by providing an initial structure. (See reference...) Figure 5 In some embodiments, the initial structure 50 includes a bit line structure 400, a bit line spacer 450, a dielectric layer 500, a contact layer 600, a contact plug 700, a conductive layer 800, a barrier layer 900, and a settling pad material 1000.
[0046] In some embodiments, the bit line structure 400 includes a first bit line conductive layer 401, a second bit line conductive layer 402 located above the first bit line conductive layer 401, and a cover layer 403 located above the second bit line conductive layer 402.
[0047] In some embodiments, the bit line spacer 450 includes a first spacer layer 451, a second spacer layer 452, and a third spacer layer 453, wherein the second spacer layer 452 is located between the first spacer layer 451 and the third spacer layer 453.
[0048] In some embodiments, the initial structure 50 includes a plurality of bit line structures 400. The plurality of bit line structures 400 project upward from a substrate (not shown). Specifically, the bit line structures 400 are located above a dielectric layer 500 or a contact layer 600 on top of the substrate. The bit line structures 400 may extend vertically from the dielectric layer 500 or the contact layer 600 and are parallel to each other. In some embodiments, the bit line structures 400 may be arranged regularly at substantially equal intervals.
[0049] The formation of the first bit line conductive layer 401, the second bit line conductive layer 402, and the capping layer 403 may include sequentially forming two conductive material layers and a dielectric material capping layer over the dielectric layer 500 or the contact layer 600. In some embodiments, etching may be performed on the two conductive material layers and the dielectric material capping layer, which may cause each bit line structure 400 to be horizontally spaced apart from each other and extend perpendicularly parallel to each other.
[0050] The first bit-line conductive layer 401 and the second bit-line conductive layer 402 are made of different conductive materials. In some embodiments, the first bit-line conductive layer 401 and the second bit-line conductive layer 402 are made of metal, metal nitride, or metal silicide. In some embodiments, the first bit-line conductive layer 401 and the second bit-line conductive layer 402 may include doped polycrystalline silicon, tungsten, tungsten nitride, and / or titanium nitride. The vertical length of the second bit-line conductive layer 402 may be greater than the vertical length of the first bit-line conductive layer 401.
[0051] The capping layer 403 is made of a dielectric material. In some embodiments, the capping layer 403 comprises silicon nitride. The vertical length of the capping layer 403 may be greater than the vertical length of the first bit line conductive layer 401 or the second bit line conductive layer 402.
[0052] The dielectric layer 500 and the contact layer 600 are located on the substrate and below the first bit line conductive layer 401. The first bit line conductive layer 401 may have either the dielectric layer 500 or the contact layer 600 between itself and the substrate, but not both simultaneously. The dielectric layer 500 is configured to provide electrical isolation between at least one bit line structure 400 and an underlying structure in the substrate (not shown). The dielectric layer 500 is made of a dielectric material.
[0053] On the other hand, the contact layer 600 is configured to provide an electrical connection between the bit line structure 400 and underlying structures in the substrate (such as access transistors (not shown)). The contact layer 600 is made of a conductive material. The contact layer 600 may contact the first bit line conductive layer 401.
[0054] Bit line spacers 450 are located horizontally around bit line structure 400. Specifically, bit line spacers 450 extend along the sidewalls of bit line structure 400. Bit line spacers 450 may include a first spacer layer 451, a second spacer layer 452, and a third spacer layer 453 located around bit line structure 400. Bit line spacers 450 are configured to electrically isolate bit line structure 400 from adjacent structures such as contact plug 700, conductive layer 800, and settling pad material 1000.
[0055] In some embodiments, the second spacer layer 452 can serve as a sacrificial layer for conversion into an air gap in subsequent manufacturing steps. Therefore, the second spacer layer 452 can have etch selectivity relative to the first spacer layer 451 and / or the third spacer layer 453. In other words, in the same etching process, the etch rate of the second spacer layer 452 is faster than the etch rate of the first spacer layer 451 and / or the third spacer layer 453.
[0056] In some embodiments, the first spacer layer 451, the second spacer layer 452, and the third spacer layer 453 comprise a dielectric material. In some embodiments, the first spacer layer 451 comprises silicon nitride. In some embodiments, the second spacer layer 452 comprises an oxide, such as silicon oxide. In some embodiments, the third spacer layer 453 comprises silicon nitride. Other data as described above may be used based on the disclosure herein, and such data are within the spirit and scope of the invention.
[0057] The contact plug 700 is horizontally positioned between two bit line spacers 450 and vertically positioned below the conductive layer 800. The contact plug 700 can be electrically connected to an underlying structure, such as an access transistor (not shown) in the substrate. The contact plug 700 can be made of a conductive material. In some embodiments, the contact plug 700 comprises doped polysilicon.
[0058] The conductive layer 800 is horizontally located between the two bit line spacers 450 and vertically located between the contact plug 700 and the barrier layer 900. The conductive layer 800 may be made of a conductive material. In some embodiments, the conductive layer 800 comprises a metal nitride or a metal. In some embodiments, the conductive layer 800 comprises tungsten, tungsten nitride, and / or titanium nitride.
[0059] The barrier layer 900 is horizontally located between the two bit line spacers 450 and vertically located between the contact plug 700 and the seat pad material 1000.
[0060] The placement pad material 1000 is located above the barrier layer 900 and may overlap with at least a portion of the corresponding bit line structure 400 and at least a portion of the corresponding bit line spacer 450. In some embodiments, the placement pad material 1000 may include several portions extending between two bit line spacers 450, and these portions are surrounded by the corresponding barrier layer 900.
[0061] The cushioning material 1000 can be made of a conductive material. The cushioning material 1000 is configured in a conventional dynamic random access memory (DRAM) cell for electrical connection with the subsequently formed material.
[0062] The above description summarizes the initial structure 50. However, in some embodiments, not all structures in the initial structure 50 are necessary.
[0063] Method M50 proceeds to operation S200 by etching the substrate material to form a first opening. (See reference) Figure 6 A mask pattern (not shown) may be formed on the cushion material 1000. Subsequently, the cushion material 1000 is etched through the mask pattern to form a first opening 1004 in the cushion material 1000, and the first opening 1004 divides the cushion material 1000 into several cushion layers 1002.
[0064] In some embodiments, the etching process may also remove a portion of the barrier layer 900, the bit line spacers 450, and the cover layer 403. After etching, the seat pads 1002 can be separated from each other through first openings 1004, each of which can expose a corresponding bit line spacer 450.
[0065] Method M50 proceeds to operation S300 by removing the spacer layer of the bit line spacers. (See reference) Figure 7The second spacer layer 452 of the bit line spacer 450 is selectively removed, thus forming an air gap 1100 within the bit line spacer 450. The air gap 1100 is formed between the first spacer layer 451 and the third spacer layer 453. Therefore, the bit line spacer 450 can now include the first spacer layer 451, the air gap 1100, and the third spacer layer 453.
[0066] Removal of the second spacer layer 452 may include selective etching. The second spacer layer 452, comprising oxides, has different etching selectivity relative to the first spacer layer 451 and the third spacer layer 453. In other words, the etching rate on the second spacer layer 452 may be higher than the etching rates on the first spacer layer 451 and the third spacer layer 453. In some embodiments, the second spacer layer 452 is subjected to a vapor phase etching process. In some embodiments, the vapor phase etching process includes hydrogen fluoride.
[0067] Method M50 proceeds to operation S400 by depositing an isolation layer on the first opening. (Reference) Figure 8 An isolation layer 1200 is deposited into the first opening 1004, and the air gap 1100 is covered by the isolation layer 1200. The isolation layer 1200 covers at least a portion of the settling pad 1002, at least a portion of the barrier layer 900, at least a portion of the bit line spacers 450, and / or at least a portion of the cover layer 403. In other words, the isolation layer 1200 replaces the first opening 1004.
[0068] The isolation layer 1200 can be deposited by any suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD) or other suitable processes.
[0069] In some embodiments, the isolation layer 1200 may include a dielectric material. In some embodiments, the isolation layer 1200 may include silicon nitride (SiN). In some embodiments, the isolation layer 1200 may include a material substantially the same as the first spacer layer 451 or the third spacer layer 453. In some embodiments, the isolation layer 1200 may seal the air gap 1100 within the bit line spacer 450.
[0070] In some embodiments, the isolation layer 1200 may not be flat, but may include a plurality of protrusions 1202. The protrusions 1202 may be created by a deposition process on an uneven surface. In some embodiments, a portion of the isolation layer 1200 may be deposited at a lower level, such as the first opening 1004, while a portion of the isolation layer 1200 may be deposited at a higher level, such as the top surface of the settling pad layer 1002. Thus, a plurality of protrusions 1202 may be formed above the top surface of the settling pad layer 1002.
[0071] Method M50 proceeds to operation S500 by planarizing the isolation layer. (See reference) Figure 9 A planarization process is performed to remove excess portions of the isolation layer 1200, making the isolation layer 1200 flush with the landing pad layer 1002. The planarized isolation layer 1200 and the landing pad layer 1002 are coplanar and therefore share the same top surface. That is, the top surfaces of the isolation layer 1200 and the landing pad layer 1002 can be adjacent to each other. A chemical-mechanical polishing (CMP) process can be used for the planarization process. The CMP process can continue until a signal from one of the materials contained in the landing pad layer 1002 is detected.
[0072] Method M50 proceeds to operation S600 by depositing a first dielectric layer. (Reference) Figure 10 A first dielectric layer 1300 is formed on the planarized isolation layer 1200 and the settling pad layer 1002. The first dielectric layer 1300 can be deposited using CVD, ALD, PVD or other suitable deposition processes.
[0073] In some embodiments, the first dielectric layer 1300 may include a dielectric material. In some embodiments, the first dielectric layer 1300 may include silicon nitride (SiN). In some embodiments, the first dielectric layer 1300 may include the same material as the isolation layer 1200, the first spacer layer 451, and the third spacer layer 453. In some embodiments, the first dielectric layer 1300 has a vertical length of approximately 20 nm.
[0074] Method M50 proceeds to operation S700 by modifying the first dielectric layer. (See reference) Figure 11 The first dielectric layer 1300 is modified by implanting dopant species into it to change the etch selectivity of the first dielectric layer 1300. In some embodiments, operation S700 is configured to modify the etch characteristics of the first dielectric layer 1300 such that the isolation layer 1200 has higher etch characteristics for subsequent etch processes than the first dielectric layer 1300.
[0075] In some embodiments, operation S700 is ion implantation. In some embodiments, operation S700 is plasma treatment. In some embodiments, the first dielectric layer 1300 is implanted with certain substances that alter film selectivity. In some embodiments, during a subsequent etching process, substances that increase the dry etch rate (DER) of the first dielectric layer 1300 are implanted into the first dielectric layer 1300. In some embodiments, the first dielectric layer 1300 is implanted with germanium (Ge) and / or nitrogen (N).
[0076] In some embodiments, Ge and / or N are distributed near the surface of the first dielectric layer 1300. In some embodiments, Ge and / or N are distributed at a distance of approximately 20 nm from the surface of the first dielectric layer 1300.
[0077] In some embodiments where the doped species is Ge, the energy range is from about 20 keV to about 25 keV and the energy range is about 3 × 10⁻⁶. 16 (ions / cm) 2 ) to approximately 5×10 16 (ions / cm) 2 Ion implantation is performed using Ge doses within the range described above. In some embodiments, if the energy and dose exceed the range described above, the modified etching characteristics of the first dielectric layer 1300 may not be particularly desirable.
[0078] In some embodiments where the dopant species is N, the energy range is from about 6 keV to about 11 keV, and the energy range is about 3 × 10⁻⁶. 16 (ions / cm) 2 ) to approximately 5×10 16 (ions / cm) 2 Ion implantation is performed using an N dose within the range described above. In some embodiments, if the energy and dose exceed the range described above, the modified etching characteristics of the first dielectric layer 1300 may not be particularly desirable.
[0079] As described above, the first dielectric layer 1300 may comprise the same material (e.g., silicon nitride) as the isolation layer 1200, the first spacer layer 451, and the third spacer layer 453. However, because the first dielectric layer 1300 is implanted with Ge and / or N, the Ge concentration and / or N concentration in the first dielectric layer 1300 may be higher than the Ge concentration and / or N concentration in the isolation layer 1200, the first spacer layer 451, and the isolation layer 1200.
[0080] In some embodiments, after modification, the first dielectric layer 1300 is etched by processes (e.g., Figure 15The dry etch rate of the etch process discussed herein is increased by approximately 15.9% to approximately 58.6%. In some embodiments, the selectivity ratio of the dry etch rate between the unmodified and modified first dielectric layer 1300 is in the range of at least about 1:1.76 to about 1:3.78. That is, the modified first dielectric layer 1300 may have an etch selectivity of at least about 1.76 to about 3.78 times that of the isolation layer 1200.
[0081] In some embodiments, ion implantation may also drive dopant species into the top portion of the isolation layer 1200, such that the top portion of the isolation layer 1200 may include a higher Ge concentration and / or N concentration than the bottom portion. In some embodiments, ion implantation may also drive dopant species into the top portion of the settling pad layer 1002, such that the top portion of the settling pad layer 1002 may include a higher Ge concentration and / or N concentration than the bottom portion of the settling pad layer 1002.
[0082] Method M50 proceeds to operation S800 by depositing a second dielectric layer. (Reference) Figure 12 A second dielectric layer 1400 is formed on the modified first dielectric layer 1300. The second dielectric layer 1400 can be deposited using CVD, ALD, PVD, or other suitable deposition processes. In some embodiments, the second dielectric layer 1400 may include a dielectric material. In some embodiments, the second dielectric layer 1400 may include an oxide. In some embodiments, the vertical thickness of the second dielectric layer 1400 is greater than the vertical thickness of the first dielectric layer 1300.
[0083] Method M50 proceeds to operation S900 by patterning the first and second dielectric layers to form the second opening. Figure 4 A flowchart illustrating the patterning of first and second dielectric layers in a method of manufacturing a semiconductor device according to a partial embodiment of the present invention. (See also...) Figure 4 and Figures 13 to 16 Operation S900 may include operations S900-1, S900-2, S900-3, and S900-4. In some embodiments, operation S900 includes photolithography.
[0084] Method M50 proceeds to operation S900-1 by forming a masking layer. (See reference...) Figure 13 A mask layer 1500 is formed on the second dielectric layer 1400. In some embodiments, the mask layer 1500 includes a photoresist material. The mask layer 1500 can be formed using a suitable deposition process (e.g., spin coating).
[0085] Method M50 proceeds to operation S900-2 via a patterned mask layer. (See reference) Figure 14The mask layer 1500 is patterned to form openings within it. The mask layer 1500 is exposed to a light source via a photomask (not shown) with a specific pattern. In some embodiments, regions of the mask layer 1500 become soluble upon exposure to light. Consequently, the exposed areas of the mask layer 1500 can be washed away to define openings within it. The patterned mask layer 1500 is configured to act as an etch protection layer over the underlying second dielectric layer 1400 and the first dielectric layer 1300 in subsequent etching processes.
[0086] Method M50 proceeds to operation S900-3, where the second dielectric layer and the first dielectric layer are etched through the mask layer. (See reference...) Figure 15 The second dielectric layer 1400 and the first dielectric layer 1300 are etched through a patterned mask layer 1500 to form a second opening 1504 through the second dielectric layer 1400 and the first dielectric layer 1300. In some embodiments, the second opening 1504 exposes a corresponding settling pad layer 1002. In some embodiments, etchants of C4F6, CH2F2, C4F8, and O2 can be used to perform the etching process of operation S900-3.
[0087] In some embodiments, during the patterning of the mask layer 1500, an overlap problem may occur, causing lateral offset of the second opening 1504 in the first dielectric layer 1300 and the second dielectric layer 1400, as well as a portion of the isolation layer 1200. Therefore, once the covering first dielectric layer 1300 is removed, the exposed isolation layer 1200 may undergo an etching process.
[0088] As described above, the isolation layer 1200 and the first dielectric layer 1300 may comprise the same material, and the etching process may unintentionally remove the exposed isolation layer 1200. However, because the first dielectric layer 1300 has been modified as described above, the modified first dielectric layer 1300 may comprise an increased etch rate for the etching process, thereby producing etch selectivity for the unmodified isolation layer 1200. As a result, the etching conditions can be controlled such that the unmodified isolation layer 1200 may comprise higher etch resistance to the etching process and can act as an etch stop layer to protect the underlying structure.
[0089] However, if the first dielectric layer 1300 is not modified, the first dielectric layer 1300 and the isolation layer 1200 comprise the same material and will have approximately the same dry etch rate. In this case, the etching process can also remove a portion of the isolation layer 1200 or even etch through the isolation layer 1200. The problem with etching through the isolation layer 1200 is that it may open the sealed air gap 1100, causing the subsequent bottom electrode metal of the capacitor structure to fill the air gap 1100, resulting in a possible electrical short circuit and loss of function of the air gap 1100.
[0090] Therefore, the present invention provides a method for modifying the first dielectric layer 1300 to have a higher dry etch rate than the isolation layer 1200. In some embodiments, the modified first dielectric layer 1300 and isolation layer 1200 have dry etch rates that are significantly different from those of the etching process.
[0091] Therefore, etching can be stopped after the modified first dielectric layer 1300 has been etched, and through-etching of the isolation layer 1200 can be avoided. This configuration improves the reliability of the device.
[0092] In summary, by modifying the first dielectric layer 1300, even if the second opening 1504 exposes the isolation layer 1200 due to coverage issues, the isolation layer 1200 can be left unetched or etched negligibly.
[0093] Method M50 proceeds to operation S900-4 by removing the masking layer. (See reference) Figure 16 The masking layer 1500 is removed. In some embodiments, operation S900-4 includes a liquid resist stripper (not shown) that chemically alters the masking layer 1500 so that it no longer adheres to the second dielectric layer 1400.
[0094] Method M50 proceeds to operation S1000 by forming a capacitor structure on the second opening. (Reference) Figure 17 Capacitor structures 1600 are formed in the second opening 1504. The capacitor structures 1600 can be electrically connected to underlying structures in the substrate, such as access transistors (not shown), via the mounting pad 1002, barrier layer 900, conductive layer 800, and contact plug 700. The capacitor structure 1600 may include a bottom electrode 1602, a capacitor dielectric 1604 above the bottom electrode 1602, and a top electrode 1606 above the capacitor dielectric 1604.
[0095] In some embodiments, the bottom electrode 1602 and the top electrode 1606 may include a conductive material. In some embodiments, the bottom electrode 1602 and the top electrode 1606 may include a metal. In some embodiments, the bottom electrode 1602 and the top electrode 1606 may include titanium nitride (TiN).
[0096] In some embodiments, capacitor dielectric 1604 may include a dielectric material. Each of the bottom electrode 1602, capacitor dielectric 1604, and top electrode 1606 may be deposited sequentially using CVD, ALD, PVD, or other suitable deposition processes.
[0097] refer to Figure 17When a coverage problem occurs, the capacitor structure 1600 is positioned slightly to the upper right of the intended top of the landing pad 1002. In some embodiments, the bottom surface of the bottom electrode 1602 contacts a small portion of the top surface of the landing pad 1002 and the top surface of the insulating layer 1200.
[0098] Based on the above discussion, the critical dimension (CD) of the second opening 1504 in the modified first dielectric layer 1300 can be enlarged to be larger than the CD of the settling pad layer 1002. That is, a capacitor structure 1600 with a larger CD can be deposited in the enlarged second opening 1504. As a result, the capacitor structure 1600 with a larger CD in the enlarged CD of the second opening 1504 can benefit from higher fill capability and lower contact resistance at the interface between the bottom electrode 1602 of the capacitor structure 1600 and the bonding region.
[0099] In some embodiments, the lateral width of the second opening 1504 may be greater than the lateral width of the top surface of the mating pad 1002. Therefore, the lateral width of the capacitor structure 1600 may be greater than the lateral width of the top surface of the mating pad 1002.
[0100] Figure 18 This is a cross-sectional view of a memory cell according to a partial embodiment of the present invention. Figure 18 and Figure 17 Similarly, for the sake of brevity, the relevant details will not be repeated.
[0101] Figure 18 This illustrates that, without any overlap issues, the capacitor structure 1600 is positioned precisely on top of the intended seating pad 1002. In some embodiments, the bottom surface of the bottom electrode 1602 completely conforms to the top surface of the seating pad 1002.
[0102] The foregoing summary outlines several features of the embodiments, enabling those skilled in the art to better understand the nature of the invention. Those skilled in the art will understand that the invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.
[0103] [Symbol Explanation]
[0104] 50: Initial Structure
[0105] 100: Memory Array
[0106] 101: Memory Unit
[0107] 101C: Storage Capacitor
[0108] 101T: Access Transistor
[0109] 200: Character Line
[0110] 300: Bit line
[0111] 400: Bitline Structure
[0112] 401: First element line conductive layer
[0113] 402: Second bit line conductive layer
[0114] 403: Overlay
[0115] 450: Bit line spacers
[0116] 451: First spacer layer
[0117] 452: Second spacer layer
[0118] 453: Third spacer layer
[0119] 500: Dielectric layer
[0120] 600: Contact layer
[0121] 700: Contact Plug
[0122] 800: Conductive layer
[0123] 900: Barrier layer
[0124] 1000: Foundation material
[0125] 1002: Foundation layer
[0126] 1004: First Opening
[0127] 1100: Air gap
[0128] 1200: Isolation layer
[0129] 1202: Protrusion
[0130] 1300: First dielectric layer
[0131] 1400: Second dielectric layer
[0132] 1500: Mask layer
[0133] 1504: Second opening
[0134] 1600: Capacitor Structure
[0135] 1602: Bottom Electrode
[0136] 1604: Capacitor dielectric
[0137] 1606: Top Electrode
[0138] M50: Method
[0139] S100: Operation
[0140] S200: Operation
[0141] S300: Operation
[0142] S400: Operation
[0143] S500: Operation
[0144] S600: Operation
[0145] S700: Operation
[0146] S800: Operation
[0147] S900: Operation
[0148] S900-1: Operation
[0149] S900-2: Operation
[0150] S900-3: Operation
[0151] S900-4: Operation
[0152] S1000: Operation.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Provide an initial structure, which includes: Bit line structure; The foundation layer is located adjacent to the cell line structure; and An isolation layer, adjacent to the foundation layer; A first dielectric layer is deposited on this initial structure; Modify the etching characteristics of the first dielectric layer; The first dielectric layer is etched to form a first opening; and A capacitor structure is formed in the first opening.
2. The method of claim 1, wherein modifying the etching characteristics of the first dielectric layer comprises implanting dopant species into the first dielectric layer.
3. The method according to claim 2, wherein the dopant species is germanium.
4. The method of claim 3, wherein the implantation of the dopant species into the first dielectric layer is performed using an energy in the range of 20 keV to 25 keV.
5. The method of claim 4, wherein the dopant species is implanted into the first dielectric layer using a 3×10⁻⁶ layer. 16 ions / cm 2 Up to 5×10 16 ions / cm 2 It is performed using germanium doses within a certain range.
6. The method of claim 2, wherein the dopant species is nitrogen.
7. The method of claim 6, wherein the implantation of the dopant species into the first dielectric layer is performed using an energy in the range of 6 keV to 11 keV.
8. The method of claim 7, wherein the dopant species is implanted into the first dielectric layer using a 3×10⁻⁶ layer. 16 ions / cm 2 Up to 5×10 16 ions / cm 2 It is performed using nitrogen dosages within a certain range.
9. The method of claim 1, wherein the first dielectric layer and the isolation layer are made of the same material, and wherein the etch characteristics of the first dielectric layer are modified such that the isolation layer has higher etch resistance to the etch process than the first dielectric layer.
10. The method according to claim 1, wherein, It also includes depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer is also etched so that the first dielectric layer and the second dielectric layer both form the first opening.
11. A semiconductor device, characterized in that, include: Bit line structure; The cushion layer is located adjacent to the cell line structure. An isolation layer, adjacent to the foundation layer; A first dielectric layer is disposed on the insulating layer and the settling pad layer, wherein the first dielectric layer has a higher germanium concentration or a higher nitrogen concentration than the insulating layer; and A capacitor structure is located in the first dielectric layer.
12. The semiconductor device of claim 11, wherein the isolation layer and the first dielectric layer have the same material.
13. The semiconductor device of claim 12, wherein the same material is silicon nitride.
14. The semiconductor device according to claim 11, wherein, It also includes a second dielectric layer located above the first dielectric layer, wherein the capacitor structure is located within the second dielectric layer.
15. The semiconductor device of claim 14, wherein the second dielectric layer has a vertical thickness, and wherein the vertical thickness is greater than the vertical thickness of the first dielectric layer.
16. The semiconductor device of claim 11, wherein the capacitor structure is in contact with the isolation layer and the mounting pad layer.
17. The semiconductor device of claim 11, wherein the lateral width of the capacitor structure is greater than the lateral width of the top surface of the mounting pad.
18. The semiconductor device according to claim 11, wherein, It also includes bit line spacers along the sidewalls of the bit line structure, wherein the bit line spacers are made of the same material as the first dielectric layer.
19. The semiconductor device of claim 18, wherein the first dielectric layer has a higher germanium concentration than the bit line spacer.
20. The semiconductor device of claim 18, wherein the first dielectric layer has a higher nitrogen concentration than the bit line spacer.