Three-dimensional semiconductor device and method of manufacturing same

Abstract

A three-dimensional semiconductor device may include: a substrate; semiconductor patterns on the substrate, spaced apart from the substrate, the semiconductor patterns spaced apart from each other in a first direction parallel to a top surface of the substrate; a first gate pattern on a top surface of the semiconductor pattern and extending in a first direction; a second gate pattern on a bottom surface of the semiconductor pattern, extending in the first direction, and spaced apart from the first gate pattern; and a bridge pattern between the semiconductor patterns, in which each of the first gate pattern and the second gate pattern includes: a gate region overlapping the semiconductor patterns; and an extension region overlapping the bridge pattern, and wherein the extension region of the first gate pattern protrudes to a region below the gate region of the first gate pattern.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2024-0131882, filed with the Korean Intellectual Property Office on September 27, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a three-dimensional semiconductor device and a method for manufacturing the three-dimensional semiconductor device, and more particularly, to a three-dimensional semiconductor device having improved productivity and electrical characteristics. Background Technology

[0004] Due to their small size, versatility, and / or low cost, semiconductor devices are considered essential components in the electronics industry. Semiconductor devices are categorized into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.

[0005] With the recent trend towards high speed and low power consumption in electronic devices, semiconductor devices within these devices are also required to have high operating speeds and / or low operating voltages. To meet these requirements, it is important to increase the integration density of semiconductor devices. However, as the integration density of semiconductor devices increases, they may suffer from degraded electrical characteristics and low production yields.

[0006] Therefore, many studies are underway to improve the electrical characteristics and production yield of semiconductor devices. Summary of the Invention

[0007] According to one aspect of this disclosure, a three-dimensional semiconductor device with improved productivity and electrical characteristics and a method for manufacturing the three-dimensional semiconductor device are provided.

[0008] According to one aspect of this disclosure, a three-dimensional semiconductor device may be provided, comprising: a substrate; semiconductor patterns spaced apart from the substrate on the substrate, the semiconductor patterns being spaced apart from each other in a first direction parallel to a top surface of the substrate; a first gate pattern extending along the first direction on the top surface of the semiconductor patterns; a second gate pattern extending along the first direction on the bottom surface of the semiconductor patterns and spaced apart from the first gate pattern; and a bridging pattern located between the semiconductor patterns, wherein each of the first gate pattern and the second gate pattern includes: a gate region overlapping the semiconductor pattern; and an extension region overlapping the bridging pattern, wherein the extension region of the first gate pattern protrudes into a region below the gate region of the first gate pattern.

[0009] According to an aspect of the disclosure, a three-dimensional semiconductor device can be provided, and the three-dimensional semiconductor device includes a substrate, semiconductor patterns spaced apart from the substrate on the substrate, the semiconductor patterns being spaced apart from each other in a first direction parallel to a top surface of the substrate, first gate patterns on top surfaces of the semiconductor patterns and extending in the first direction, second gate patterns on bottom surfaces of the semiconductor patterns, extending in the first direction, and spaced apart from the first gate patterns, and bridge patterns between the semiconductor patterns, wherein each of the first gate patterns and the second gate patterns includes a gate region overlapping the semiconductor patterns, and an extension region overlapping the bridge patterns, and wherein a distance between the extension region of the first gate pattern and the extension region of the second gate pattern is less than a distance between the gate region of the first gate pattern and the gate region of the second gate pattern.

[0010] According to an aspect of the disclosure, a three-dimensional semiconductor device can be provided, and the three-dimensional semiconductor device includes a substrate, first semiconductor patterns spaced apart from the substrate on the substrate, the first semiconductor patterns being spaced apart from each other in a first direction parallel to a top surface of the substrate and extending in a second direction parallel to the top surface of the substrate and intersecting the first direction, second semiconductor patterns spaced apart from the first semiconductor patterns in a third direction perpendicular to the top surface of the substrate, first gate patterns on top surfaces of the first semiconductor patterns and extending in the first direction, second gate patterns on bottom surfaces of the first semiconductor patterns, extending in the first direction, and spaced apart from the first gate patterns, bridge patterns between the first semiconductor patterns, a bit line on a first end of one of the first semiconductor patterns and extending in the third direction, and a data storage pattern on a second end of the one of the first semiconductor patterns opposite the first end and extending in the third direction, wherein each of the first gate patterns and the second gate patterns includes a gate region overlapping the first semiconductor patterns, and an extension region overlapping the bridge patterns, and wherein the extension region of the first gate pattern protrudes to a region lower than the gate region of the first gate pattern.

[0011] According to one aspect of this disclosure, a method for manufacturing a three-dimensional semiconductor device can be provided, the method comprising: forming semiconductor patterns spaced apart from the substrate on a substrate, wherein the semiconductor patterns are spaced apart from each other in a first direction parallel to the top surface of the substrate; forming a bridging layer surrounding each of the semiconductor patterns and extending in the first direction; performing a removal process on a portion of the bridging layer; forming a sacrificial layer on the semiconductor patterns, the sacrificial layer extending in the first direction; forming an interlayer insulating layer on the sacrificial layer; removing a portion of the sacrificial layer from a region between the interlayer insulating layer and the semiconductor patterns; and forming a gate pattern in an empty region, the empty region being formed by removing a portion of the sacrificial layer, wherein the removal process performed on a portion of the bridging layer reduces the thickness of the bridging layer. Attached Figure Description

[0012] FIG. 1 This is a schematic circuit diagram of a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0013] FIG. 2A , FIG. 2B and FIG. 2C This is a perspective view schematically illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0014] FIG. 3 This is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0015] FIG. 4A It corresponds to FIG. 3 A cross-sectional view of line A-A'.

[0016] FIG. 4B It corresponds to FIG. 3 A cross-sectional view of line B-B'.

[0017] FIG. 5A , FIG. 5B , FIG. 5C and FIG. 5D It is shown FIG. 4A A magnified view of part P1.

[0018] FIG. 6 It corresponds to FIG. 3 A cross-sectional view of line A-A'.

[0019] FIG. 7 to FIG. 25 This is a diagram illustrating a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0020] Non-limiting example embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can indicate like elements throughout the drawings and repeated description can be omitted.

[0021] FIG. 1 is a circuit diagram schematically showing a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0022] Referring to FIG. 1 , the three-dimensional semiconductor device can include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0023] The memory cell array 1 can include word lines WL, bit lines BL, source lines SL, and memory cells MC. The memory cells MC can be arranged three-dimensionally, and each memory cell MC can be connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL. In an embodiment, each of the memory cells MC can be constituted by one transistor including a memory layer or a data storage layer.

[0024] The row decoder 2 can be configured to decode address information input from the outside and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 can be provided to a row driver, and in this case, the row driver can provide respective voltages to the selected one of the word lines WL and the unselected ones of the word lines WL in response to control by a control circuit.

[0025] The sense amplifier 3 can be configured to sense, amplify, and output a voltage difference between one of the bit lines BL that can be selected based on address information decoded by the column decoder 4 and a reference bit line.

[0026] The column decoder 4 can establish a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can be configured to decode address information input from the outside and select one of the bit lines BL based on the decoded address information.

[0027] The control logic 5 can be configured to generate a control signal that can be used to control a data write operation or a data read operation on the memory cell array 1.

[0028] FIG. 2A 、 FIG. 2B and FIG. 2C is a perspective view schematically showing a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0029] Referring to FIG. 2A, the three-dimensional semiconductor device can include a substrate 100, a peripheral circuit structure PS on the substrate 100, and a cell array structure CS on the peripheral circuit structure PS.

[0030] The peripheral circuit structure PS can include a core circuit and a peripheral circuit (SWD / PERI) which can be formed on the substrate 100. The core circuit and the peripheral circuit can include the row decoder 2, the column decoder 4, the sense amplifier (S / A) 3, and the control logic 5 described with reference to FIG. 1

[0031] The substrate 100 can be a plate-shaped structure extending in parallel to a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can be parallel to a top surface of the substrate 100, and can be non-parallel to each other. For example, the first direction D1 and the second direction D2 can be horizontal directions orthogonal to each other. The peripheral circuit structure PS and the cell array structure CS can be sequentially stacked on the substrate 100 in a third direction D3 perpendicular to the top surface of the substrate 100.

[0032] The cell array structure CS can include bit lines BL, source lines SL, word lines WL, and memory cells MC therebetween. Each of the memory cells MC can be connected to one of the word lines WL, one of the bit lines BL, and one of the source lines SL.

[0033] Referring to FIG. 2B , the semiconductor device can include a cell array structure CS on a substrate 100 and a peripheral circuit structure PS on the cell array structure CS. The cell array structure CS can be disposed between the substrate 100 and the peripheral circuit structure PS. The peripheral circuit structure PS can include a core circuit and a peripheral circuit.

[0034] Referring to FIG. 2C , the semiconductor device can have a chip-to-chip (C2C) structure. The peripheral circuit structure PS can include a first substrate 100a. A lower metal pad LMP can be disposed in an uppermost portion of the peripheral circuit structure PS. The lower metal pad LMP can be electrically connected to the core circuit and the peripheral circuit. The lower metal pad LMP can be bonded to an upper metal pad UMP of the cell array structure CS.

[0035] The cell array structure CS can include a second substrate 200a, and the upper metal pad UMP can be disposed in a lowermost portion of the cell array structure CS. The upper metal pad UMP can be electrically connected to the bit lines BL, the source lines SL, and the word lines WL. The upper metal pad UMP can be electrically connected to the memory cells MC.

[0036] FIG. 3 is a plan view showing a three-dimensional semiconductor device according to an embodiment of the present disclosure. FIG. 4A ​is a cross-sectional view corresponding to line A-A' of FIG. 3 FIG. 4B is a cross-sectional view corresponding to line B-B' of FIG. 3 FIG. 5A , FIG. 5B , FIG. 5C and FIG. 5D are enlarged views showing part PI of FIG. 4A

[0037] Referring to FIG. 3 , FIG. 4A and FIG. 4B , the three-dimensional semiconductor device can include a substrate 100. In an embodiment, the substrate 100 can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate can be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 can be a plate-shaped structure extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can be parallel to a top surface of the substrate 100, and can not be parallel to each other. In an embodiment, the substrate 100 can include a peripheral circuit structure PS described with reference to FIG. 2A and FIG. 2C .

[0038] A cell array structure CS can be disposed on the substrate 100. The drawings show an example in which one cell array structure CS is disposed on the substrate 100, but embodiments of the present disclosure are not limited to this example. For example, the cell array structures CS can be a plurality of cell array structures CS adjacent to each other in the second direction D2. Hereinafter, for the sake of brevity, only one cell array structure CS will be described, but other cell array structures CS can also have substantially the same features as described below.

[0039] The cell array structure CS can include a semiconductor pattern SP, a word line WL, a data storage pattern DSP, and peripheral elements surrounding them. Each of them will be described in more detail below.

[0040] The semiconductor pattern SP can be spaced apart from the substrate 100 in a third direction D3. That is, the semiconductor pattern SP can be floating from the substrate 100. The semiconductor pattern SP can extend along the second direction D2 on the substrate 100. In an embodiment, the semiconductor pattern SP can be a strip-shaped pattern extending in the second direction D2.

[0041] ​​​The semiconductor pattern SP can include a first edge portion EA1 and a second edge portion EA2 which can be spaced apart from each other in the second direction D2, and a channel region CH which can be provided therebetween. The channel region CH of the semiconductor pattern SP can vertically overlap with the word line WL, which will be described later. The first edge portion EA1 of the semiconductor pattern SP can be connected to the bit line BL, which will be described later. The second edge portion EA2 can be connected to the data storage pattern DSP, which will be described later. In this specification, the expression "elements A and B are connected" can be used to mean that the elements A and B are directly connected to each other or indirectly connected to each other through another element C (e.g., a conductive element) therebetween. Here, the element C can be a single element or a plurality of elements.

[0042] The semiconductor pattern SP can be formed of or include at least one of a single-crystal semiconductor material, a polycrystal semiconductor material, an oxide semiconductor material, and a two-dimensional material. In an embodiment, the single-crystal semiconductor material can be single-crystal silicon. In an embodiment, the polycrystal semiconductor material can be polycrystal silicon. In an embodiment, the oxide semiconductor material can be indium gallium zinc oxide (IGZO). In an embodiment, the two-dimensional material can be MoS2, WS2, MoSe2, or WSe2. In this specification, each of the expressions "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can be used to mean one of the elements listed in the expression or any possible combination of the listed elements.

[0043] In an embodiment, each of the first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP can include an impurity region doped with an impurity (e.g., an n-type impurity or a p-type impurity). The impurity region can constitute a source / drain region of a transistor.

[0044] In an embodiment, a plurality of semiconductor patterns SP can be provided. The semiconductor patterns SP can be spaced apart from each other in the first direction D1 and the third direction D3. In an embodiment, top surfaces of the semiconductor patterns SP which can extend in the first direction D1 can be aligned with each other (e.g., coplanar with each other). The semiconductor patterns SP stacked in the third direction D3 can vertically overlap with each other. In an embodiment, side surfaces of the semiconductor patterns SP stacked in the third direction D3 can be aligned with each other (e.g., coplanar with each other).

[0045] The word line WL can extend on the channel region CH of the semiconductor pattern SP in the first direction D1. The word line WL can include a gate insulating pattern GI which can be disposed to surround the channel region CH of the semiconductor pattern SP and a gate pattern GE which can be disposed on the gate insulating pattern GI and extend in the first direction D1. The gate pattern GE can be disposed as a plurality of pairs of gate patterns GE which can be spaced apart from each other by the semiconductor pattern SP interposed therebetween in the third direction D3. The gate pattern GE can not include a void therein.

[0046] In an embodiment, the gate insulating pattern GI can be formed of or include at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride, and can be disposed to have a single layer structure or a multi-layer structure. In the present specification, the high-k dielectric material can be defined as a material having a dielectric constant higher than that of silicon oxide.

[0047] In an embodiment, the gate pattern GE can be formed of or include at least one of Ti, TiN, TiSiN, TiON, W, WN, Mo, MoN, MoOxNy, Ta, TaN, Poly Si, Li, Na, K, Cs, Rb, Sr, Ba, Ca, Ce, Sm, Eu, Mg, Sc, Y, Hf, Tl, As, La, Nd, Gd, Tb, Lu, Th, U, Mn, Al, Ga, In, Pb, Cd, Bi, and Zr. The gate pattern GE can be a single layer or a composite layer.

[0048] The bridge pattern BP can be interposed between the semiconductor patterns SP spaced apart from each other in the first direction D1. The bridge pattern BP can be interposed between the above-mentioned pair of gate patterns GE. Accordingly, the pair of gate patterns GE can be spaced apart from each other by the bridge pattern BP.

[0049] In an embodiment, the bridge pattern BP can be formed of or include at least one of SiO2, SiON, SiOC, SiN, SiC, SiBN, C, and CN. In the case where the bridge pattern BP includes the same material as that of the gate insulating pattern GI, there can be no observable interface between the bridge pattern BP and the gate insulating pattern GI.

[0050] In an embodiment, a plurality of bridge patterns BP can be provided. The bridge patterns BP can be spaced apart from each other in the first direction D1. The bridge patterns BP and the semiconductor patterns SP can be alternately arranged in the first direction D1.

[0051] An interlayer insulating layer ILD can be interposed between the semiconductor patterns SP spaced apart from each other in the third direction D3 and can extend in the first direction D1. The interlayer insulating layer ILD can include an insulating material.

[0052] Referring to FIG. 5A The plurality of gate patterns GE can include a first gate pattern GE1 which can be disposed on the top surface Sa of the semiconductor pattern SP and extend in the first direction D1, and a second gate pattern GE2 which can be disposed on the bottom surface Sb of the semiconductor pattern SP and extend in the first direction D1. The first gate pattern GE1 and the second gate pattern GE2 can be spaced apart from each other by the bridging pattern BP.

[0053] The plurality of semiconductor patterns SP can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 which can be spaced apart from each other in the third direction D3. The interlayer insulating layer ILD can be interposed between the first gate pattern GE1 which can be located on the top surface Sa of the first semiconductor pattern SP1 and the second gate pattern GE2 which can be located on the bottom surface Sb of the second semiconductor pattern SP2.

[0054] Each of the first gate pattern GE1 and the second gate pattern GE2 can include a gate region GR which can vertically overlap the semiconductor pattern SP and an extension region CR which can vertically overlap the bridging pattern BP.

[0055] The extension region CR of the first gate pattern GE1 can protrude (e.g., in the opposite direction of the third direction D3) to a region lower than the gate region GR of the first gate pattern GE1. Also, the extension region CR of the second gate pattern GE2 can protrude (e.g., in the third direction D3) to a region higher than the gate region GR of the second gate pattern GE2.

[0056] A distance DS1 (e.g., a minimum distance) between the extension regions CR of the first gate pattern GE1 and the second gate pattern GE2 can be less than a distance DS2 between the gate regions GR of the first gate pattern GE1 and the second gate pattern GE2. The distance DS1 between the extension regions CR of the first gate pattern GE1 and the second gate pattern GE2 can decrease as it moves in the first direction D1 and then increase again. The distance between the extension region CR of the first gate pattern GE1 on the top surface Sa of the first semiconductor pattern SP1 and the extension region CR of the second gate pattern GE2 on the bottom surface Sb of the second semiconductor pattern SP2 can increase as it moves in the first direction D1 and then decrease again.

[0057] The extension region CR of the first gate pattern GE1 can have a top surface G1a and a bottom surface G1b formed to have a profile convex upward and a profile concave downward, respectively. The extension region CR of the second gate pattern GE2 can have a top surface G2a and a bottom surface G2b formed to have a profile concave downward and a profile convex upward, respectively. The lowermost surface of the extension region CR of the first gate pattern GE1 can be located at a vertical level lower than the top surface Sa of the semiconductor pattern SP. The uppermost surface of the extension region CR of the second gate pattern GE2 can be located at a vertical level higher than the bottom surface Sb of the semiconductor pattern SP. The top surface G1a of the extension region CR of the first gate pattern GE1 can be located at a vertical level lower than the top surface of the gate region GR of the first gate pattern GE1. The bottom surface G1b of the extension region CR of the first gate pattern GE1 can be located at a vertical level lower than the bottom surface of the gate region GR of the first gate pattern GE1. The top surface G2a of the extension region CR of the second gate pattern GE2 can be located at a vertical level higher than the top surface of the gate region GR of the second gate pattern GE2. The bottom surface G2b of the extension region CR of the second gate pattern GE2 can be located at a vertical level higher than the bottom surface of the gate region GR of the second gate pattern GE2.

[0058] In an embodiment, each of the first gate pattern GE1 and the second gate pattern GE2 can extend in the first direction D1 to have a wavy shape.

[0059] The thickness BT of the bridge pattern BP can decrease as it moves in the first direction D1 and then increase again. The minimum thickness of the bridge pattern BP can be less than the thickness of the semiconductor pattern SP. The top surface of the bridge pattern BP can have a profile convex upward. The bottom surface of the bridge pattern BP can have a profile convex downward.

[0060] The interlayer insulating layer ILD can include a protruding portion which can extend in the third direction D3 and a direction opposite to the third direction D3. The protruding portion of the interlayer insulating layer ILD can be repeatedly disposed in the first direction D1.

[0061] Referring to FIG. 5B , the first gate pattern GE1 and the second gate pattern GE2 can have the same or similar shape as that in FIG. 5A . The first gate pattern GE1 and the second gate pattern GE2 can have a shape different from that in FIG. 5AThe bridge pattern BP can be disposed to surround the channel region CH of the semiconductor pattern SP and extend in the first direction D1. The bridge pattern BP can be disposed to surround the gate insulating pattern GI and extend in the first direction D1. Thus, a portion of the bridge pattern BP can be interposed between the semiconductor pattern SP and the first gate pattern GE1 and between the semiconductor pattern SP and the second gate pattern GE2.

[0062] The uppermost surface of the bridge pattern BP can be located at a vertical level higher than a top surface of the gate insulating pattern GI. The lowermost surface of the bridge pattern BP can be located at a vertical level lower than a bottom surface of the gate insulating pattern GI. Each of the first gate pattern GE1 and the second gate pattern GE2 can be spaced apart from the gate insulating pattern GI by the bridge pattern BP.

[0063] Referring to FIG. 5C , the top surface G1a of the extension region CR of the first gate pattern GE1 can have a stepped portion. The bottom surface G2b of the extension region CR of the second gate pattern GE2 can have a stepped portion. In an embodiment, the bottom surface G1b of the extension region CR of the first gate pattern GE1 and the top surface G2a of the extension region CR of the second gate pattern GE2 can have a flat profile, where there is no stepped portion.

[0064] The distance DS1 between the extension regions CR of the first gate pattern GE1 and the second gate pattern GE2 can be smaller than the distance DS2 between the gate regions GR of the first gate pattern GE1 and the second gate pattern GE2. The distance DS1 between the extension regions CR of the first gate pattern GE1 and the second gate pattern GE2 can be substantially constant when measured along the first direction D1.

[0065] The thickness BT of the bridge pattern BP can be substantially constant when measured along the first direction D1.

[0066] Referring to FIG. 5D , the distance DS1 between the extension regions CR of the first gate pattern GE1 and the second gate pattern GE2 can be substantially equal to the distance DS2 between the gate regions GR of the first gate pattern GE1 and the second gate pattern GE2. The bottom surface G1b of the extension region CR of the first gate pattern GE1 can be located at a vertical level higher than a top surface Sa of the semiconductor pattern SP. The top surface G2a of the extension region CR of the second gate pattern GE2 can be located at a vertical level lower than a bottom surface Sb of the semiconductor pattern SP.

[0067] Referring back to FIG. 3 , FIG. 4A and FIG. 4BThe bit lines BL can extend on the side surfaces of the first edge portions EA1 of the semiconductor patterns SP in the third direction D3. Thus, each of the bit lines BL can be connected to the side surfaces of the first edge portions EA1 of the semiconductor patterns SP adjacent to each other in the third direction D3. In an embodiment, a plurality of bit lines BL can be provided. The bit lines BL can be disposed to be spaced apart from each other in the second direction D2.

[0068] The bit lines BL can be a single layer formable of a single material, or can be a composite layer formable of two or more materials. In an embodiment, the bit lines BL can be formed of or include at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co), a metal nitride material (e.g., a nitride material including Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co), and a metal silicide material (e.g., a silicide material including Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0069] The data storage patterns DSP can extend on the side surfaces of the second edge portions EA2 of the semiconductor patterns SP in the third direction D3. Thus, each of the data storage patterns DSP can be connected to the side surfaces of the second edge portions EA2 of the semiconductor patterns SP adjacent to each other in the third direction D3.

[0070] The data storage patterns DSP can include a storage electrode SE, a plate electrode PE, and a dielectric layer CIL between the storage electrode SE and the plate electrode PE. In an embodiment, the three-dimensional semiconductor device can be a dynamic random access memory (DRAM) device, and the data storage patterns DSP can function as capacitors. The storage electrode SE can be spaced apart from the plate electrode PE by the dielectric layer CIL.

[0071] Each of the storage electrode SE and the plate electrode PE can include an electrically conductive material. In embodiments, each of the storage electrode SE and the plate electrode PE can be formed of or include at least one of doped silicon (Si), doped silicon germanium (SiGe), a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), a metal nitride material (e.g., a nitride material including Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, and Ag), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN), tantalum aluminum nitride (e.g., TaAlN), an electrically conductive oxide material (e.g., PtO, RuO2, IrO2, SrRuO3 (SRO), (Ba,Sr)RuO3 (BSRO), CaRuO3 (CRO), and LSCo), and a metal silicide material. Each of the storage electrode SE and the plate electrode PE can be a single layer that can be made of a single material, or can be a composite layer including two or more materials.

[0072] In embodiments, the dielectric layer CIL can include at least one of a metal oxide material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and a perovskite dielectric material (e.g., SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT).

[0073] In another embodiment, the data storage pattern DSP can be a variable resistance pattern whose resistance can be switched to one of at least two states by an electrical pulse applied thereto. For example, the data storage pattern DSP can be formed of or include at least one of a phase change material whose crystalline state can change according to an amount of current applied thereto, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, and an antiferromagnetic material.

[0074] According to some embodiments of the disclosure, a silicide pattern can be disposed between the storage electrode SE and the semiconductor pattern SP. The silicide pattern can be formed of or include a metal silicide material (e.g., including at least one of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, or Co). In embodiments, a plurality of storage electrodes SE can be disposed adjacent to each other in the third direction D3.

[0075] The plate electrode PE can include a first region which can extend in the third direction D3, and a second region which can extend from the first region in a direction opposite to the second direction D2. The second region of the plate electrode PE can be interposed between the storage electrodes SE arranged along the third direction D3.

[0076] The first capping pattern CP1 can be interposed between the gate pattern GE and the data storage pattern DSP. In an embodiment, the first capping pattern CP1 can be formed of or include at least one of SiN, SiO2, SiC, SiOC, SiON, and SiBN. Accordingly, the gate pattern GE can be spaced apart from and electrically disconnected (e.g., electrically insulated) from the data storage pattern DSP by the first capping pattern CP1. In an embodiment, the first capping pattern CP1 can be disposed to conformally and continuously cover a bottom surface of one of a pair of semiconductor patterns SP adjacent to each other in the third direction D3, a dielectric layer CIL of the data storage pattern DSP, and a top surface of the other of the pair of semiconductor patterns SP.

[0077] The second capping pattern CP2 can be interposed between the gate pattern GE and the bit line BL. In an embodiment, the second capping pattern CP2 can be formed of or include at least one of SiN, SiO2, SiC, SiOC, SiON, or SiBN. Accordingly, the gate pattern GE can be spaced apart from and electrically disconnected (e.g., electrically insulated) from the bit line BL by the second capping pattern CP2.

[0078] Each of the first capping pattern CP1 and the second capping pattern CP2 can be formed of or include a material having etch selectivity with respect to the bridging pattern BP.

[0079] The device isolation pattern ST can be formed on the substrate 100. The device isolation pattern ST can cover a side surface of the bit line BL. In an embodiment, the device isolation pattern ST can be interposed between adjacent cell array structures in the cell array structure CS. Accordingly, the adjacent cell array structures in the cell array structure CS can be spaced apart from each other by the device isolation pattern ST.

[0080] An upper insulating layer UIL can be disposed in an upper portion of the cell array structure CS. The upper insulating layer UIL can be disposed on a top surface of each of the bit lines BL and the data storage patterns DSP. The upper insulating layer UIL can be formed of or include at least one of an insulating material, and can have a single layer structure or a multi-layer structure. According to an embodiment of the disclosure, a plurality of upper interconnection lines can be disposed in the upper insulating layer UIL. Some of the upper interconnection lines can be connected to the bit lines BL, and other upper interconnection lines among the upper interconnection lines can be connected to the data storage patterns DSP. Word line pads can be disposed on side surfaces of the cell array structure CS, and can be connected to the word lines WL.

[0081] FIG. 6 is a cross-sectional view corresponding to FIG. 3 line A-A'.

[0082] Referring to FIG. 3 and FIG. 6 , unlike referring to FIG. 3 , FIG. 4A and FIG. 4B , the bridge pattern BP can include an electrically conductive material. In an embodiment, the bridge pattern BP can be formed of or include at least one of TiN, TaN, WN, W, and Ti. Since the bridge pattern BP includes an electrically conductive material, the gate pattern GE and the gate insulating pattern GI can constitute the word line WL together with the bridge pattern BP.

[0083] In a case where the bridge pattern BP includes a material different from the gate pattern GE, there can be an observable interface between them. However, in a case where the bridge pattern BP includes the same material as the gate pattern GE, there can be no observable interface between them.

[0084] In a case where the bridge pattern BP and the gate pattern GE include an electrically conductive material, the word line WL can be disposed to surround the channel region CH of the semiconductor pattern SP and extend in the first direction D1. In an embodiment, the word line WL can have a structure that completely surrounds the channel region CH of the semiconductor pattern SP (e.g., a gate full wrap structure). Each of the word lines WL can be disposed to surround the channel region CH of each of the semiconductor patterns SP spaced apart from each other in the first direction D1.

[0085] Hereinafter, a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the disclosure will be described in more detail with reference to FIG. 7 to FIG. 25 In the following description, for the sake of clear description, previously described elements can be identified by the same reference numerals without repeating the repetitive description thereof.

[0086] FIG. 7 to FIG. 21is a diagram illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the disclosure. In detail, FIG. 7 , FIG. 9 , FIG. 11 , FIG. 13 , FIG. 16 , FIG. 18 and FIG. 20 are plan views of a three-dimensional semiconductor device according to an embodiment of the disclosure. FIG. 10A , FIG. 12A , FIG. 14A , FIG. 17A and FIG. 19A are cross-sectional views taken along lines A-A' of FIG. 9 , FIG. 11 , FIG. 13 , FIG. 16 and FIG. 18 , respectively. FIG. 9 , FIG. 10B , FIG. 12B , FIG. 14B , FIG. 17B , FIG. 19B and FIG. 21 are cross-sectional views taken along lines B-B' of FIG. 9 , FIG. 11 , FIG. 13 , FIG. 16 and FIG. 18 , respectively. FIG. 15 is an enlarged view of a portion P2 corresponding to FIG. 14A .

[0087] Referring to FIG. 7 and FIG. 8 , a substrate 100 can be prepared. A stack in which first sacrificial layers SAL1 and active layers ACL are alternately stacked can be formed on the substrate 100. Each of the first sacrificial layers SAL1 and the active layers ACL can include a semiconductor material. The first sacrificial layers SAL1 can include a material having etch selectivity with respect to the active layers ACL. Thus, even when the first sacrificial layers SAL1 are removed in a subsequent removal process, the active layers ACL can remain unremoved or are only slightly removed. In an embodiment, the active layers ACL and the first sacrificial layers SAL1 can be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), but the material of the first sacrificial layers SAL1 can be different from that of the active layers ACL. In an embodiment, the active layers ACL can include silicon (Si), and the first sacrificial layers SAL1 can include silicon germanium (SiGe). The thickness of the first sacrificial layers SAL1 can be less than that of the active layers ACL when measured along a third direction D3.

[0088] According to some embodiments of the disclosure, a support pattern can be further provided to penetrate the stack. Since the support pattern is in contact with the stack, the support pattern can be used to support the stack in a subsequent removal process of the first sacrificial layers SAL1 or the active layers ACL. As a result, the support pattern can prevent the stack from collapsing during the manufacturing process.

[0089] Referring to FIG. 9 , FIG. 10A and FIG. 10B , a removal process can be performed on a portion of the stack. Accordingly, the first trenches TR1 can be formed on the opposite side surfaces of the stack. The first sacrificial layers SAL1 of the FIG. 8 may be removed from the substrate 100 through the first trenches TR1. Next, a removal process can be performed on a portion of each of the active layers ACL. Accordingly, the thickness of each of the active layers ACL can be reduced.

[0090] Referring to FIG. 11 , FIG. 12A , FIG. 12B , an initial device isolation pattern PST can be formed to fill a space within the first trenches TR1 and between the active layers ACL. Thereafter, a removal process can be performed on a portion of each of the active layers ACL. When the removal process is performed, a portion of the initial device isolation pattern PST vertically overlapping with the removed portion of the active layers ACL can also be removed. Accordingly, each of the active layers ACL can be divided into semiconductor patterns SP spaced apart from each other in the first direction D1. A fill pattern FL can be formed in a vacant region formed by the removal process.

[0091] Referring to FIG. 13 , FIG. 14A , FIG. 14B and FIG. 15 , a second trench TR2 can be formed by removing a portion of the initial device isolation pattern PST on the side surface of the stack.

[0092] In an embodiment, the fill pattern FL and a portion of the initial device isolation pattern PST interposed between the semiconductor patterns SP in the third direction D3 can be removed by the second trench TR2. FIG. 12A

[0093] ​Next, a gate insulating pattern GI can be formed to conformally cover the semiconductor patterns SP. Thereafter, a bridge layer BPL can be formed to conformally surround the channel regions CH of the semiconductor patterns SP spaced apart from each other in the first direction D1 and extend in the first direction D1. The bridge layer BPL can be formed to cover the semiconductor patterns SP spaced apart from each other in the third direction D3. The bridge layer BPL can be formed to fill a space between the semiconductor patterns SP spaced apart from each other in the first direction D1. In an embodiment, the bridge layer BPL can include an insulating material. For example, the bridge layer BPL can be formed of or include at least one of SiO2, SiON, SiOC, SiN, SiC, SiBN, C, and CN.

[0094] Referring to FIG. 15 , an initial bridge layer PBL can be formed to conformally surround the channel regions CH of the semiconductor patterns SP spaced apart from each other in the first direction D1. As the height and width of the initial bridge layer PBL increase, the initial bridge layers PBL formed on the channel regions CH of the semiconductor patterns SP spaced apart from each other in the first direction D1 can be connected to each other. Accordingly, the bridge layer BPL can be formed to fill a space between the semiconductor patterns SP spaced apart from each other in the first direction D1. Since the initial bridge layer PBL is conformally formed on the semiconductor patterns SP until they contact each other, the initial bridge layer PBL can form a curved portion at a region where they meet each other. Accordingly, the initial bridge layer PBL can be formed to have a top surface with a profile protruding upward and a bottom surface with a profile protruding downward. In an embodiment, the process of forming and growing the initial bridge layer PBL can be performed through a single deposition process.

[0095] Referring to FIG. 16 , FIG. 17A and FIG. 17B , a removal process can be performed on a portion of the bridge layer BPL of FIG. 15 . Accordingly, only a portion of the bridge layer BPL of FIG. 15 may remain in a space between the semiconductor patterns SP spaced apart from each other in the first direction D1. FIG. 15 The remaining portion of the bridge layer BPL of FIG. 15 may form a bridge pattern BP. For example, in a case where there is an observable interface between the bridge layer BPL and the gate insulating pattern GI of FIG. 15 , the bridge layer BPL of may be divided into bridge patterns BP spaced apart from each other in the first direction D1 by the removal process.

[0096] In an embodiment, FIG. 15The bridge layer BPL can be formed of or include a material having etch selectivity with respect to the gate insulating pattern GI. Accordingly, when the bridge layer BPL is removed FIG. 15 , the gate insulating pattern GI can remain unremoved or only slightly removed. Here, a removal process can be performed to expose the top and bottom surfaces of the gate insulating pattern GI, but embodiments of the present disclosure are not limited to this example.

[0097] In another embodiment, a removal process can be performed to remove the gate insulating pattern GI on the top and bottom surfaces of the channel region CH of the semiconductor pattern SP and expose the top and bottom surfaces of the channel region CH. In this case, the gate insulating pattern GI can be formed again on the top and bottom surfaces of the channel region CH through a subsequent oxidation process.

[0098] In an embodiment, the removal process can be performed in a wet etching manner, and the thickness of the bridge layer BPL can be controlled by adjusting the process time. Even when the removal process is completed, FIG. 15 , the curved portions of the top and bottom surfaces of the bridge layer BPL can remain. FIG. 18

[0099] Thereafter, a second sacrificial layer SAL2 can be formed on each of the top and bottom surfaces of the semiconductor pattern SP so as to extend in the first direction D1. The second sacrificial layer SAL2 can be formed to conformingly cover the side surface of the initial device isolation pattern PST. The second sacrificial layer SAL2 can be formed to conformingly cover the exposed top, bottom, and side surfaces of the semiconductor pattern SP and the side surface of the initial device isolation pattern PST and extend in the third direction D3. The second sacrificial layer SAL2 can include a material having etch selectivity with respect to the bridge pattern BP. In an embodiment, the second sacrificial layer SAL2 can be formed of or include at least one of SiN, SiO2, SiC, SiOC, SiON, and SiBN.

[0100] Next, an interlayer insulating layer ILD can be formed on the substrate 100. The interlayer insulating layer ILD can be formed on the second sacrificial layer SAL2. The interlayer insulating layer ILD can be formed between the semiconductor patterns SP spaced apart from each other in the third direction D3.

[0101] Referring to FIG. 19A , FIG. 19B , and FIG. 17B , a removal process can be performed on a portion of the interlayer insulating layer ILD. Accordingly, a third trench TR3 can be formed on the substrate 100. As a result of the removal process, the bridge pattern BP can be exposed. FIG. 17B ​The second sacrificial layer SAL2 is divided into multiple second sacrificial layers SAL2 spaced apart from each other on the third-direction D3 (e.g., FIG. 17B Multiple second sacrificial layers (SAL2). As a result of the removal process, the side surfaces of each of the semiconductor pattern SP can be exposed to the outside.

[0102] Partial removal can be achieved through the third trench TR3. FIG. 17B Each of the second sacrifice layers in SAL2. For example, this can be achieved by partially removing... FIG. 17B The second sacrificial layer SAL2 is used to form the internal region INR. FIG. 4A The remaining portion of the second sacrificial layer SAL2 can form the first capping pattern CP1. In the inner region INR, the side surface IS of the first capping pattern CP1 can be exposed to the outside. Each of the inner regions INR can be formed on the top surface Sa of the semiconductor pattern SP. Each of the inner regions INR can be formed on the bottom surface Sb of the semiconductor pattern SP.

[0103] According to some embodiments of this disclosure, after forming the inner region INR, additional processes can be performed to increase the thickness of the gate insulating pattern GI. Alternatively, a portion of the gate insulating pattern GI can be removed when forming the inner region INR. This exposes the top and bottom surfaces of the channel region CH of the semiconductor pattern SP. In this case, an oxidation process can be performed to re-form the gate insulating pattern GI on the top and bottom surfaces of the channel region CH.

[0104] Reference FIG. 20 , FIG. 21 and FIG. 18 You can refer to FIG. 19A , FIG. 19B and FIG. 5A to FIG. 5C A gate pattern GE is formed in the described internal region INR. The gate pattern GE can be formed on the exposed side surface IS of the first capping pattern CP1. In an embodiment, forming the gate pattern GE may include forming a gate layer to fill the internal region INR, and performing a removal process on the gate layer to separate the gate patterns GE formed to partially fill the internal region INR from one another.

[0105] Depending on the shape of the bridging pattern BP, the extended region CR of the gate pattern GE can have FIG. 19B At least one of the shapes shown can be formed on the top surface Sa of the semiconductor pattern SP. FIG. 19B The first gate pattern GE1 is formed in the internal region INR. It can be formed on the bottom surface Sb of the semiconductor pattern SP. FIG. 19B The second gate pattern GE2 is formed in the internal region INR.

[0106] A second cap pattern CP2 can be formed on the side surface of the gate pattern GE. The second cap pattern CP2 can be formed to fill the remaining portion of the inner region INR of the FIG. 17A .

[0107] According to embodiments of the disclosure, the process of forming and removing the bridge layer BPL can be performed before the process of forming the second sacrificial layer SAL2 of FIG. 17A , and in this case, the bridge pattern BP can be formed to fill the space between the semiconductor patterns SP spaced apart from each other in the first direction D1. Accordingly, the second sacrificial layer SAL2 of FIG. 17A can be formed on each of the top surface and the bottom surface of the semiconductor pattern SP so that the second sacrificial layer SAL2 of FIG. 17A extends in the first direction D1 without filling the space between the semiconductor patterns SP. As a result, when the gate pattern GE is formed in the empty region formed by removing the second sacrificial layer SAL2 of FIG. 17A , a void can not be formed in the gate pattern GE.

[0108] On the contrary, if the bridge pattern BP is not provided, the second sacrificial layer SAL2 of FIG. 17A may extend in the first direction D1 to surround the semiconductor pattern SP and can be formed to fill the space between the semiconductor patterns SP. Next, if the gate pattern GE is formed by replacing the second sacrificial layer SAL2 of FIG. 3 , the gate pattern GE can include a void formed between the semiconductor patterns SP. Due to the presence of the void, the gate pattern GE extending in the first direction D1 can be cut, which can cause a process failure. In addition, due to the presence of the void, the electrical characteristics of the gate pattern GE can be deteriorated.

[0109] According to embodiments of the disclosure, since the bridge pattern BP is provided, the above-described process failure and deterioration of electrical characteristics can be prevented. Accordingly, the productivity and electrical characteristics of the three-dimensional semiconductor device can be improved.

[0110] Referring back to FIG. 4A , FIG. 4B , and FIG. 21 , a device isolation pattern ST can be formed on the substrate 100. A bit line BL can be formed in the device isolation pattern ST. The initial device isolation pattern PST of FIG. 22 can be removed. A data storage pattern DSP can be formed on the second edge portion EA2 of the semiconductor pattern SP. Next, an upper insulating layer UIL can be formed to cover the substrate 100.

[0111] FIG. 22is a diagram illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure. In detail, FIG. 16 is a cross-sectional view taken along line A-A' of FIG. 16 .

[0112] Referring to FIG. 22 and FIG. 17A , the bridge layer BPL of FIG. 15 can be removed less than the process of removing the bridge layer BPL of FIG. 15 described with reference to FIG. 5B . Accordingly, the bridge pattern BP can be formed to surround the channel region CH of the semiconductor pattern SP and extend in the first direction D1. Then, the aforementioned manufacturing process can be further performed to manufacture the three-dimensional semiconductor device described with reference to FIG. 23 .

[0113] FIG. 24 and FIG. 23 are diagrams illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure. In detail, FIG. 24 and FIG. 16 are cross-sectional views taken along line A-A' of FIG. 16 .

[0114] Referring to FIG. 23 , FIG. 24 and FIG. 15 , the bridge pattern BP can be formed by a method different from the method of forming the bridge pattern BP described with reference to FIG. 17A and FIG. 15 .

[0115] In detail, a method of alternately and repeatedly performing a process of forming and removing the initial bridge layer PBL of FIG. 15 can be used instead of a method of performing a removing process after a process of forming the bridge layer BPL of FIG. 23 . In this case, as shown in FIG. 5C , a stepped portion can be formed between the gate insulating pattern GI and the bridge pattern BP, and the bridge pattern BP can be formed to have substantially the same features as those described with reference to FIG. 24 . Similarly, as shown in FIG. 5D , the gate insulating pattern GI and the bridge pattern BP can be formed to have top surfaces coplanar with each other, and the bridge pattern BP can be formed to have substantially the same features as those described with reference to FIG. 5C .

[0116] Then, the aforementioned manufacturing process can be further performed to manufacture the three-dimensional semiconductor device described with reference to FIG. 5D or FIG. 25 .

[0117] FIG. 25 is a diagram illustrating a method of manufacturing a three-dimensional semiconductor device according to an embodiment of the disclosure. In detail, FIG. 13 is a cross-sectional view taken along line A-A' of FIG. 13 .

[0118] Referring to FIG. 25 and FIG. 3 , a bridge layer BPL including a conductive material can be formed to surround the channel regions CH of the semiconductor patterns SP and extend in the first direction D1. In an embodiment, the bridge layer BPL can be formed of or include at least one of TiN, TaN, WN, W, and Ti. Then, the aforementioned manufacturing process can be further performed to manufacture the three-dimensional semiconductor device described with reference to FIG. 6 and ​ .

[0119] According to an embodiment of the disclosure, the process of forming and removing the bridge layer can be performed before the sacrificial layer is formed, and in this case, the bridge pattern can be formed to fill the space between the semiconductor patterns. Accordingly, the sacrificial layer can be formed on each of the top and bottom surfaces of the semiconductor patterns to extend in a certain direction without filling the space between the semiconductor patterns. As a result, when the gate pattern is formed in the empty region formed by removing the sacrificial layer through the etching process, a void can not be formed in the gate pattern.

[0120] If the bridge pattern is not provided, the sacrificial layer can be formed to fill the space between the semiconductor patterns. Here, if the gate pattern is formed by replacing the sacrificial layer, the gate pattern can include a void between the semiconductor patterns. Due to the presence of the void, the gate pattern extending in a certain direction can be cut, and in this case, a process failure can occur. In addition, due to the presence of the void, the electrical characteristics of the gate pattern can be deteriorated.

[0121] Due to the provision of the bridge pattern, a process failure and deterioration of electrical characteristics can be prevented. This can enable improvement in the productivity and electrical characteristics of the three-dimensional semiconductor device.

[0122] While non-limiting example embodiments of the disclosure have been specifically shown and described, it will be understood by those skilled in the art that changes in form and details can be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A three-dimensional semiconductor device, comprising: Substrate; Semiconductor patterns on the substrate, spaced apart from the substrate, the semiconductor patterns being spaced apart from each other in a first direction parallel to the top surface of the substrate; A first gate pattern extends on the top surface of the semiconductor pattern along the first direction. A second gate pattern extends along the first direction on the bottom surface of the semiconductor pattern and is spaced apart from the first gate pattern. as well as A bridging pattern, located between the semiconductor patterns. Each of the first gate pattern and the second gate pattern includes: A gate region that overlaps with the semiconductor pattern; and The extended region overlaps with the bridging pattern, and Wherein, the extended region of the first gate pattern protrudes into the region below the gate region of the first gate pattern.

2. The three-dimensional semiconductor device according to claim 1, wherein, The extended region of the second gate pattern protrudes into a region higher than the gate region of the second gate pattern.

3. The three-dimensional semiconductor device according to claim 1, wherein, The distance between the extended regions of the first gate pattern and the extended regions of the second gate pattern is less than the distance between the gate regions of the first gate pattern and the gate regions of the second gate pattern.

4. The three-dimensional semiconductor device according to claim 1, wherein, The lowest surface of the extended region of the first gate pattern is located at a vertical level below the top surface of each of the semiconductor patterns.

5. The three-dimensional semiconductor device according to claim 1, wherein, The uppermost surface of the extended region of the second gate pattern is located at a vertical level above the bottom surface of each of the semiconductor patterns.

6. The three-dimensional semiconductor device according to claim 1, wherein, The bottom surface of the extended region of the first gate pattern is located at a vertical level below the bottom surface of the gate region of the first gate pattern.

7. The three-dimensional semiconductor device according to claim 1, wherein, The top surface of the extended region of the first gate pattern has a downwardly recessed profile.

8. The three-dimensional semiconductor device according to claim 1, wherein, Each of the top and bottom surfaces of the extended region of the second gate pattern has an upwardly convex profile.

9. The three-dimensional semiconductor device according to claim 1, wherein, The thickness of the bridging pattern in a second direction perpendicular to the top surface of the substrate decreases in the first direction and then increases thereafter.

10. The three-dimensional semiconductor device according to claim 1, wherein, The minimum thickness of the bridging pattern is less than the thickness of each of the semiconductor patterns.

11. The three-dimensional semiconductor device according to claim 1, wherein, The top surface of the bridging pattern has a downwardly concave profile, and The bottom surface of the bridging pattern has an upwardly convex profile.

12. The three-dimensional semiconductor device according to claim 1, wherein, The bridging pattern includes at least one of SiO2, SiON, SiOC, SiN, SiC, SiBN, C, CN, TiN, TaN, WN, W, and Ti.

13. The three-dimensional semiconductor device according to claim 1, wherein, The semiconductor pattern extends in a second direction parallel to the top surface of the substrate and intersecting the first direction, and The three-dimensional semiconductor device further includes: Bit lines, which extend upward at a first end of one of the semiconductor patterns and at a third point perpendicular to the top surface of the substrate; and A data storage pattern is located at a second end of one of the semiconductor patterns opposite to the first end and extends along the third direction.

14. A three-dimensional semiconductor device, comprising: Substrate; Semiconductor patterns on the substrate, spaced apart from the substrate, the semiconductor patterns being spaced apart from each other in a first direction parallel to the top surface of the substrate; A first gate pattern extends on the top surface of the semiconductor pattern along the first direction. A second gate pattern extends along the first direction on the bottom surface of the semiconductor pattern and is spaced apart from the first gate pattern. as well as A bridging pattern, located between the semiconductor patterns. Each of the first gate pattern and the second gate pattern includes: A gate region that overlaps with the semiconductor pattern; and The extended region overlaps with the bridging pattern, and Wherein, the distance between the extended region of the first gate pattern and the extended region of the second gate pattern is less than the distance between the gate region of the first gate pattern and the gate region of the second gate pattern.

15. The three-dimensional semiconductor device according to claim 14, wherein, The lowest surface of the extended region of the first gate pattern is located at a vertical level below the top surface of each of the semiconductor patterns, and The uppermost surface of the extended region of the second gate pattern is located at a vertical level above the bottom surface of each of the semiconductor patterns.

16. The three-dimensional semiconductor device according to claim 14, wherein, Each of the top and bottom surfaces of the extended region of the first gate pattern has a downwardly recessed profile, and Each of the top and bottom surfaces of the extended region of the second gate pattern has an upwardly convex profile.

17. The three-dimensional semiconductor device according to claim 14, wherein, The thickness of the bridging pattern in a second direction perpendicular to the top surface of the substrate decreases in the first direction and then increases thereafter.

18. The three-dimensional semiconductor device according to claim 14, wherein, The top surface of the bridging pattern has a downwardly concave profile, and The bottom surface of the bridging pattern has an upwardly convex profile.

19. The three-dimensional semiconductor device according to claim 14, wherein, The bridging pattern includes at least one of SiO2, SiON, SiOC, SiN, SiC, SiBN, C, CN, TiN, TaN, WN, W, and Ti.

20. A three-dimensional semiconductor device, comprising: Substrate; A first semiconductor pattern is spaced apart from the substrate on the substrate. The first semiconductor patterns are spaced apart from each other in a first direction parallel to the top surface of the substrate, and the first semiconductor patterns extend in a second direction parallel to the top surface of the substrate and intersecting the first direction. A second semiconductor pattern is spaced apart from the first semiconductor pattern in a third direction perpendicular to the top surface of the substrate; A first gate pattern extends on the top surface of the first semiconductor pattern and along the first direction. A second gate pattern extends along the first direction on the bottom surface of the first semiconductor pattern and is spaced apart from the first gate pattern. A bridging pattern located between the first semiconductor patterns; Bit lines, which are located at a first end of a first semiconductor pattern in the first semiconductor pattern and extend upward in the third party; as well as A data storage pattern, which is located at a second end of one of the first semiconductor patterns opposite to the first end, and extends along the third direction. Each of the first gate pattern and the second gate pattern includes: A gate region that overlaps with the first semiconductor pattern; and The extended region overlaps with the bridging pattern, and Wherein, the extended region of the first gate pattern protrudes into a region below the gate region of the first gate pattern.

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