Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device includes: a support structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked with each other; a gate structure including a conductive layer and including a first section at a height corresponding to a height of the support structure and a second section on the support structure; a contact plug extending through the gate structure and connected to a first conductive layer of the plurality of conductive layers; and a first support including a plurality of posts extending between the first section and the support structure and extending through the second section, and first protrusions protruding from the posts into the support structure.

Description

TECHNICAL FIELD

[0001] The disclosure relates to electronic devices and methods of manufacturing electronic devices, including but not limited to semiconductor devices and methods of manufacturing semiconductor devices. BACKGROUND

[0002] The integration density of a semiconductor device is determined by the area occupied by a unit memory cell. As the improvement of the integration density of a semiconductor device in which memory cells are formed as a single layer on a substrate reaches a limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate are being developed. In order to improve the operation reliability of a semiconductor device, various structures and manufacturing methods are being developed. SUMMARY

[0003] According to an embodiment of the disclosure, a semiconductor device can include a support structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked with each other, a gate structure including a plurality of conductive layers and including a first section at a height corresponding to a height of the support structure and a second section on the support structure, a contact plug extending through the gate structure and connected to a first conductive layer of the plurality of conductive layers, and a first support including a plurality of pillars extending between the first section and the support structure and extending through the second section and a plurality of first protrusions protruding from the plurality of pillars into the support structure.

[0004] According to an embodiment of the disclosure, a semiconductor device can include a support structure including a plurality of first insulating layers and a plurality of second insulating layers alternately stacked with each other, a gate structure including a plurality of conductive layers and including a first section at a height corresponding to a height of the support structure and a second section on the support structure, a contact plug extending through the gate structure and connected to a first conductive layer of the plurality of conductive layers, a first support extending between the first section and the support structure and through the second section, and a second support spaced apart from the first support and extending through the gate structure.

[0005] According to embodiments of the present disclosure, a method of manufacturing a semiconductor device can include: forming a laminate by alternately stacking a plurality of first material layers and a plurality of second material layers; forming a plurality of preliminary first support holes extending through the laminate; forming a first support sacrificial layer in a corresponding one of the plurality of preliminary first support holes; forming a preliminary contact hole in a region surrounded by the plurality of preliminary first support holes and extending through the laminate, and at least one of the plurality of second material layers being exposed through the preliminary contact hole; selectively removing the second material layers through the preliminary contact hole to form a plurality of first openings through which the plurality of first support sacrificial layers are exposed; removing the plurality of first support sacrificial layers from the plurality of preliminary first support holes, thereby forming a plurality of first support holes; enlarging the plurality of first support holes by selectively removing the plurality of second material layers through the plurality of first support holes, thereby forming enlarged first support holes; and forming first supports in the enlarged first support holes. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1A-1C is a diagram illustrating a semiconductor device according to embodiments of the present disclosure.

[0007] Figures 2A-2C is a diagram illustrating a semiconductor device according to embodiments of the present disclosure.

[0008] Figures 3A-3C 、 Figures 4A-4C 、 Figures 5A-5C 、 Figures 6A-6C 、 Figures 7A-7C 、 Figures 8A-8C and Figures 9A-9C are diagrams illustrating semiconductor devices formed using a method of manufacturing a semiconductor device according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0009] Cross-hatching throughout the drawings is intended to illustrate corresponding or similar areas of the figures, not that the materials associated with those areas are the same. The drawings are not necessarily to scale, and measurements of objects within the cross-sectioned views are not necessarily to scale with measurements of the same objects in corresponding plan views.

[0010] Terms such as “vertical,” “horizontal,” “below,” “above,” “sidewall,” “upper,” “lower,” “height,” and other terms that imply relative spatial relationships or orientations are used for the purpose of convenience and reference in the description and the drawings, and are not otherwise limiting.

[0011] Embodiments of the present disclosure provide semiconductor devices having stable structures and improved characteristics, and methods of manufacturing semiconductor devices.

[0012] According to the present disclosure, a semiconductor device having a stable structure and improved reliability can be provided.

[0013] Embodiments of the present disclosure are described in detail with reference to the attached drawings. The detailed description of embodiments is provided as an example in order to describe the concepts disclosed in the present application. The examples or embodiments according to the concepts can be implemented in various forms, and the scope of the present disclosure is not limited to the examples or embodiments described in the present disclosure.

[0014] Figures 1A-1C is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A is a cross-sectional view taken along a line A-A’ of Figure 1B and Figure 1C is a plan view at a height B of Figure 1B is a plan view at a height C of Figure 1A . Figure 1C Figure 1A

[0015] Referring to Figures 1A-1C , the semiconductor device includes a support structure 110S, a gate structure 110G, a channel structure 120, a first support 130, a second support 140, a slit structure 150, a contact plug 160, and an insulating spacer 170.

[0016] The support structure 110S includes first insulating layers 110A and second insulating layers 110B alternately stacked with each other. The support structure 110S supports a stack forming the gate structure 110G during a process of forming the gate structure 110G.

[0017] The thickness of the first insulating layers 110A can be substantially equal to or different from the thickness of the second insulating layers 110B. For example, the thickness of the first insulating layers 110A can be substantially equal to the thickness of the second insulating layers 110B. Alternatively, the first insulating layers 110A can be thinner than the second insulating layers 110B. The first insulating layers 110A and the second insulating layers 110B can include different materials. For example, the first insulating layers 110A can include an insulating material such as an oxide, and the second insulating layers 110B can include an insulating material such as a nitride.

[0018] The gate structure 110G includes the first insulating layers 110A and conductive layers 110C alternately stacked with each other. The gate structure 110G includes a first section 110G1 at a vertical height corresponding to or flush with a vertical height of the support structure 110S, and a second section 110G2 on the first section 110G1 and the support structure 110S, wherein the vertical is with respect to Figure 1A ​​The orientation is referenced. For example, the conductive layer 110C of the first segment 110G1 is located at a height corresponding to the height of the second insulating layer 110B of the support structure 110S.

[0019] The conductive layer 110C may be a gate line such as a source select line, word line, or drain select line. A source select transistor, memory cell, or drain select transistor may be located in the region where the channel structure 120 and the conductive layer 110C intersect. For example, a string may include at least one source select transistor, a plurality of memory cells, and at least one drain select transistor stacked along the channel structure 120. The first insulating layer 110A may include an insulating material such as an oxide. The conductive layer 110C may include a conductive material such as tungsten, molybdenum, or polysilicon.

[0020] A channel structure 120 extends through a gate structure 110G. Each channel structure 120 includes a channel layer 120A and a memory layer 120B surrounding the channel layer 120A. Each channel structure 120 may include an insulating core (not shown) within the channel layer 120A. The channel layer 120A may include a semiconductor material such as polysilicon or germanium. The insulating core may include an insulating material such as oxide.

[0021] Contact plug 160 extends through gate structure 110G and is connected to at least one of conductive layers 110C. Contact plug 160 is located on or above support structure 110S. Support structure 110S is located in the region near contact plug 160 to prevent or reduce bending of the stack forming gate structure 110G below contact plug 160. Contact plug 160 may comprise a conductive material such as tungsten.

[0022] An insulating spacer 170 surrounds the sidewall of the contact plug 160. The insulating spacer 170 insulates the contact plug 160 from the conductive layer 110C, except for the conductive layer 110C electrically connected to the contact plug 160. The insulating spacer 170 may include an insulating material such as an oxide.

[0023] A first support member 130 extends through the gate structure 110G. During the process of forming the gate structure 110G, the first support member 130 prevents or reduces bending of the stack forming the gate structure 110G. The first support member 130 may include a first protrusion 130A and a post 130B. For example, each first support member 130 includes a post 130B disposed between the first segment 110G1 and the support structure 110S and extending through the second segment 110G2, and includes a first protrusion 130A protruding from the post 130B into the support structure 110S.

[0024] First protrusions 130A are interconnected in a plane and surround a closed region 130C. A support structure 110S is located within the closed region 130C. A second insulating layer 110B of the support structure 110S is located at a height corresponding to the height of the first protrusions 130A. Posts 130B are spaced apart around a contact plug 160. In an embodiment, the posts 130B are arranged equidistantly along the periphery of a circle centered on the contact plug 160. Relative to the figures, the width of the first protrusions 130A in the horizontal direction is wider than the width of the channel structure 120. The posts 130B may have a width substantially the same as the width of the channel structure 120. The width is relative to... Figure 1A They are compared at essentially the same height in the vertical direction. For example, they can be compared at approximately the same height in the vertical direction. Figure 1A The width is compared on the upper surface. The first support 130 may include an insulating material such as an oxide.

[0025] The second support 140 extends through the gate structure 110G. The second support 140 is spaced apart from the first support 130. During the process of forming the gate structure 110G, the second support 140 prevents or reduces bending of the stack forming the gate structure 110G. The second support 140 may have a structure similar to that of the channel structure 120. For example, each second support 140 includes at least one of a dummy channel layer, a dummy memory layer surrounding the dummy channel layer, and a dummy insulating core within the dummy channel layer. Alternatively, the second support 140 may include an insulating material such as an oxide. Alternatively, the second support 140 may include a conductive layer such as tungsten and an insulating layer surrounding the conductive layer.

[0026] The slit structure 150 extends through the gate structure 110G in a horizontal direction relative to the figures. The slit structure 150 extends through the gate structure 110G and includes a second protrusion 150A projecting into the gate structure 110G. The slit structure 150 can be used during the process of forming the gate structure 110G during the fabrication of the semiconductor device. The slit structure 150 may include an insulating material, a conductive material, or a semiconductor material.

[0027] The contact plug 160 is disposed on or above the support structure 110S. The support structure 110S prevents or reduces bending of the stack forming the gate structure 110G below the contact plug 160 during the process of forming the gate structure 110G.

[0028] Figures 2A-2C This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A It is along Figure 2B and Figure 2C A cross-sectional view taken from line D-D'. Figure 2B yes Figure 2A Plan view at height E,Figure 2C yes Figure 2A Plan view at height F.

[0029] Reference Figures 2A-2C The semiconductor device includes a support structure 210S, a gate structure 210G, a channel structure 220, a first support member 230, a second support member 240, a slit structure 250, a contact plug 260, and an insulating spacer 270.

[0030] Each support structure 210S includes a first insulating layer 210A and a second insulating layer 210B that are alternately stacked on top of each other. The support structures 210S have different heights. For example, each support structure 210S includes different numbers of alternately stacked insulating layers 210A and 210B.

[0031] The thickness of each first insulating layer 210A may differ from the thickness of each second insulating layer 210B. For example, the first insulating layer 210A may be thinner than the second insulating layer 210B. The first insulating layer 210A and the second insulating layer 210B may comprise different materials. For example, the first insulating layer 210A may comprise an insulating material such as an oxide, and the second insulating layer 210B may comprise an insulating material such as a nitride.

[0032] The gate structure 210G includes a first insulating layer 210A and a conductive layer 210C alternately stacked on top of each other. The gate structure 210G includes a first segment 210G1 located at a vertical height corresponding to or flush with the vertical height of the support structure 210S, and a second segment 210G2 located on the first segment 210G1 and the support structure 210S, wherein vertical is relative to... Figure 2A The orientation is referenced. For example, the conductive layer 210C of the first segment 210G1 is located at a height corresponding to the height of the second insulating layer 210B of the support structure 210S.

[0033] The channel structure 220 extends through the gate structure 210G. Each channel structure 220 includes a channel layer 220A and a memory layer 220B surrounding the channel layer 220A. The channel layer 220A may include a semiconductor material such as polysilicon or germanium.

[0034] Contact plugs 260 extend through the gate structure 210G and are each connected to a conductive layer in the conductive layer 210C. Contact plugs 260 are located on or above corresponding support structures 210S. For example, each contact plug 260 is located in a region near its corresponding support structure 210S. The number of contact plugs 260 may be the same as the number of support structures 210S. In this example, the contact plugs 260 have different heights, and the support structures 210S have different heights. The height of the contact plug 260 is inversely proportional to the height of its corresponding support structure 210S. For example, when the height of the contact plug 260 is smaller, the height of the corresponding support structure 210S is larger. Contact plugs 160 may comprise a conductive material such as tungsten.

[0035] An insulating spacer 270 surrounds the sidewall of each contact plug 260. The insulating spacer 270 insulates the contact plug 260 from the conductive layer 210C except for the conductive layer 210C electrically connected to the contact plug 260. The insulating spacer 270 may include an insulating material such as an oxide.

[0036] The first support member 230 extends through the gate structure 210G. Each first support member 230 includes a first protrusion 230A and a post 230B. For example, the first support member 230 includes a post 230B disposed between the first section 210G1 and the support structure 210S and extending through the second section 210G2, and includes a first protrusion 230A protruding from the post 230B into the support structure 210S.

[0037] The second support 240 extends through the gate structure 210G. The second support 240 is spaced apart from the first support 230. The second support 240 may have a structure similar to that of the channel structure 220. Alternatively, the second support 240 comprises an insulating material such as an oxide. Alternatively, the second support 240 may comprise a conductive layer such as tungsten and an insulating layer surrounding the conductive layer.

[0038] The slit structure 250 extends through the gate structure 210G in a horizontal direction relative to the figures. The slit structure 250 extends through the gate structure 210G and includes a second protrusion 250A projecting into the gate structure 210G. The slit structure 250 may include an insulating material, a conductive material, or a semiconductor material.

[0039] The contact plugs 260 are located on or above the corresponding support structures 210S. For example, the number of contact plugs 260 and the number of support structures 210S can be the same, and the contact plugs 260 can be located in the region near the support structures 210S. By forming the support structures 210S at different heights corresponding to contact plugs 260 with different heights, the support below the contact plugs 260 can be improved.

[0040] Figures 3A-3C , Figures 4A-4C , Figures 5A-5C , Figures 6A-6C , Figures 7A-7C , Figures 8A-8C as well as Figures 9A-9C This is a diagram illustrating a semiconductor device formed using a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A They are respectively along Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B The lines G-G' and along respectively Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C A cross-sectional view taken from line G-G'. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B They are Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A Plan view at height H. Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C They are Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A Plan view at height I.

[0041] Reference Figure 3CA laminate 310S is formed by alternately stacking a first material layer 310A and a second material layer 310B. The thickness of the first material layer 310A may be substantially equal to or less than the thickness of the second material layer 310B. For example, the thickness of the first material layer 310A may be substantially equal to the thickness of the second material layer 310B. Alternatively, the first material layer 310A may be thinner than the second material layer 310B. The first material layer 310A and the second material layer 310B may comprise different materials. For example, the first material layer 310A may comprise an insulating material such as an oxide, and the second material layer 310B may comprise an insulating material such as a nitride.

[0042] A preliminary channel hole CHH is formed extending through the laminate 310S. A preliminary slit hole SLH is formed extending through the laminate 310S. The preliminary slit hole SLH is arranged such that, relative to... Figure 4C , Figure 5C and Figure 6C They are spaced apart from each other in a horizontal or similar direction. A preliminary first support hole SPH1 is formed extending through the stack 310S. The preliminary first support hole SPH1 is formed near the area where the contact plug will be formed in a subsequent process. This area can be determined by connecting the center of the preliminary first support hole SPH1.

[0043] A preliminary second support via SPH2 is formed, extending through the laminate 310S. The preliminary second support via SPH2 is spaced apart from the preliminary first support via SPH1. When forming the preliminary channel via CHH, a preliminary slit via SLH, a preliminary first support via SPH1, and / or a preliminary second support via SPH2 can be formed. By simultaneously forming vias for different structures in a single process, the manufacturing cost of semiconductor devices can be reduced.

[0044] Sacrificial material is formed in the preliminary channel hole CHH, the preliminary slit hole SLH, the preliminary first support hole SPH1, and the preliminary second support hole SPH2. A channel sacrificial layer 320S is formed in the preliminary channel hole CHH. A first support sacrificial layer 330S is formed in the preliminary first support hole SPH1. A second support sacrificial layer 340S is formed in the preliminary second support hole SPH2. A slit sacrificial layer 350S is formed in the preliminary slit hole SLH. The sacrificial material may include materials such as carbon.

[0045] Reference Figure 7C , forming a first mask pattern MP1 covering the first support sacrificial layer 330S, and ( Figure 8C The second support sacrificial layer 340S is exposed through an opening in the first mask pattern MP1. For example, a first mask pattern MP1 is formed covering the first support sacrificial layer 330S and the slit sacrificial layer 350S, and ( Figure 9CThe channel sacrificial layer 320S and the second support sacrificial layer 340S are exposed through openings in the first mask pattern MP1.

[0046] A channel structure 320 is formed. The channel sacrificial layer 320S is removed through an opening in the first mask pattern MP1, and a channel hole is formed at a position substantially the same as the initial channel hole CHH. A memory layer 320B and a channel layer 320A of the channel structure 320 are formed in the channel hole. For example, the memory layer 320B and the channel layer 320A can be formed sequentially in the channel hole.

[0047] A second support member 340 is formed. The second support sacrificial layer 340S is removed through the opening in the first mask pattern MP1, and a second support hole is formed at a position substantially the same as the initial second support hole SPH2. Each second support member 340 is formed in the corresponding second support hole. The first mask pattern MP1 is then removed.

[0048] The second support 340 may be formed during the formation of the channel structure 320. The second support 340 may have a structure similar to that of the channel structure 320. For example, the second support 340 may have a dummy memory layer and a dummy channel layer. This disclosure is not limited to this example, and the second support 340 may include a material different from that of the channel structure 320. The second support 340 may include an insulating material such as an oxide. Alternatively, the second support 340 may include a conductive layer such as tungsten and an insulating layer covering the conductive layer.

[0049] Reference Figure 3A A second mask pattern MP2 is formed covering the laminate 310S including the first support sacrificial layer 330S. The area surrounded by the first support hole SPH1 is exposed through the opening in the second mask pattern MP2. For example, a second mask pattern MP2 is formed covering the channel structure 320, the first support sacrificial layer 330S, the second support 340, and the slit sacrificial layer 350S, and the area surrounded by the first support hole SPH1 is exposed through the opening in the second mask pattern MP2.

[0050] A preliminary contact hole CTH is formed. For example, the preliminary contact hole CTH can be formed by etching the laminate 310S using a second mask pattern MP2 as an etching barrier. At least one second material layer 310B is exposed through the preliminary contact hole CTH.

[0051] A preliminary first opening OP1 is formed. The second material layer 310B is selectively removed through the contact hole CTH to expose the first support sacrificial layer 330S and form the preliminary first opening OP1. A sacrificial layer CTS is formed in the preliminary first opening OP1. The sacrificial layer CTS may comprise a material having an etch selectivity ratio relative to the first material layer 310A and the second material layer 310B. Alternatively, the sacrificial layer CTS may comprise a material having an etch selectivity ratio relative to the first support sacrificial layer 330S. For example, the sacrificial layer CTS may comprise polysilicon.

[0052] A preliminary insulating spacer 370A is formed within the preliminary contact hole CTH. A contact sacrificial layer 360S is formed within the preliminary insulating spacer 370A. The preliminary insulating spacer 370A may include an insulating material such as oxide, and the contact sacrificial layer 360S may include a sacrificial material such as carbon. The second mask pattern MP2 is removed.

[0053] Reference Figure 4A A third mask pattern MP3 is formed covering the contact hole CTH, and the first support sacrificial layer 330S is exposed through an opening in the third mask pattern MP3. For example, a third mask pattern MP3 is formed covering the channel structure 320, the second support 340, the slit sacrificial layer 350S, and the contact sacrificial layer 360S, and the first support sacrificial layer 330S (see...) Figure 5A It is exposed through the opening in the third mask pattern MP3.

[0054] The first support sacrificial layer 330S is removed through an opening in the third mask pattern MP3, forming a first support hole at a location substantially the same as the initial first support hole SPH1. The first support hole is enlarged by selectively removing some of the second material layer 310B via the first support hole. For example... Figure 6A As shown, the first support holes are enlarged to interconnect. An enlarged first support hole is formed by enlarging the first support hole such that the second material layer 310B below the initial contact hole CTH is isolated in the region surrounded by the first support holes. The region surrounded by the first support holes and located below the contact hole CTH is called the closed region.

[0055] A first support member 330 is formed in the enlarged first support hole. For example, the first support member 330 is formed by forming an insulating material such as an oxide in the enlarged first support hole. The third mask pattern MP3 is removed.

[0056] Reference Figure 7AA fourth mask pattern MP4 is formed covering the contact sacrificial layer 360S and the first support 330, and the slit sacrificial layer 350S is exposed through an opening in the fourth mask pattern MP4. For example, a fourth mask pattern MP4 is formed covering the channel structure 320, the first support 330, the second support 340, the contact sacrificial layer 360S, and the preliminary insulating spacer 370A, and the slit sacrificial layer 350S (see...) Figure 8A It is exposed through the opening in the fourth mask pattern MP4.

[0057] The slit sacrificial layer 350S is removed through the opening in the fourth mask pattern MP4, forming a slit hole at a position substantially the same as the initial slit hole SLH. This is achieved by removing the slit sacrificial layer 350S relative to the opening in the fourth mask pattern MP4. Figure 9A and Figures 3A-3C The slits SL are formed by enlarging the slit holes in the vertical direction so that the slit holes are interconnected. The slits SL can be formed by etching the laminate 310S using a fourth mask pattern MP4 as an etching barrier.

[0058] The second material layer 310B is removed through the slit SL, forming a second opening OP2 at substantially the same location where the second material layer 310B was formed. The sacrificial layer CTS is exposed through the second opening OP2. The sacrificial layer CTS is removed through the second opening OP2, forming a first opening OP1 at substantially the same location where the initial first opening OP1 was formed. The laminate 310S remains in the region surrounded by the first support hole, thus the second material layer 310B remains in the closed region. The first material layer 310A and the second material layer 310B, which are alternately laminated below the contact hole CTH, are referred to as the support structure. The laminate 310S is referred to as the support structure.

[0059] Reference Figure 3A A gate structure 310G is formed. A third material layer 310C is formed in the first opening OP1 and the second opening OP2. For example, the third material layer 310C can be formed by placing a conductive material such as tungsten in the first opening OP1 and the second opening OP2. Each third material layer 310C can be used as a gate line. Thus, a gate structure 310G is formed comprising a first material layer 310A and a third material layer 310C that are alternately stacked on top of each other.

[0060] The height of the stack 310S can be increased to improve the integration density of the semiconductor device. The first material layer 310A can be thinner than the second material layer 310B. As the height of the stack 310S increases, the target depth of the contact hole CTH (which forms a contact plug that connects to at least one of the third material layers 310C of the gate structure 310G) increases, and the width of the contact hole CTH increases. When a support is not formed below the contact hole CTH, the stack 310S below the contact hole CTH may not be adequately supported.

[0061] During the process of manufacturing a semiconductor device, a second opening OP2 is formed by removing a second material layer 310B to form a gate structure 310G. Because the first material layer 310A is thinner than the second material layer 310B, the stack 310S may be prone to bending when the second material layer 310B is removed. As the size of the region forming the contact hole CTH increases, the size of the region forming the second support 340 supporting the stack 310S decreases, so the stack 310S may be prone to bending during the process of forming the gate structure 310G.

[0062] According to an embodiment of this disclosure, a preliminary first support hole SPH1 is formed near the region where the contact hole CTH is formed. Because a support structure is formed in the first support hole below the contact hole CTH, the preliminary first support hole SPH1 is formed to surround the contact hole CTH. The first support holes are enlarged so that they interconnect to form a closed region, and the laminate 310S is retained in the closed region. The laminate 310S retained in the closed region serves as a support structure. As a result, because the laminate 310S is retained below the contact hole CTH during the process of removing the second material layer 310B to form the gate structure 310G, bending of the laminate 310S can be prevented or reduced.

[0063] A slit structure 350 is formed in the slit SL. The slit structure 350 may include insulating materials, conductive materials, semiconductor materials, etc. The fourth mask pattern MP4 is removed.

[0064] Reference Figure 3B A fifth mask pattern MP5 is formed covering the first support 330, and the contact sacrificial layer 360S is exposed through an opening in the fifth mask pattern MP5. For example, a fifth mask pattern MP5 is formed covering the channel structure 320, the first support 330, the second support 340, and the slit structure 350, and the contact sacrificial layer 360S and the initial insulating spacer 370A (see...). Figure 3C Figures 4A-4C Figures 3A-3C Figures 3A-3C Figures 5A-5C Figures 6A-6C Figures 5A-5C Figure 6B Figures 7A-7C Figures 6A-6C Figure 7B Figure 7C Figures 8A-8C Figures 9A-9C Figures 8A-8C It is exposed through the opening in the fifth mask pattern MP5.

[0065] The fifth mask pattern MP5 is used as an etching barrier to remove the contact sacrificial layer 360S, forming a contact hole at a location substantially the same as the initial contact hole CTH. The third material layer 310C is exposed by etching the lower surface of the initial insulating spacer 370A. The remaining material in the initial insulating spacer 370A forms an insulating spacer 370 surrounding the contact plug sidewall. The contact plug 360 is formed in the contact hole. The contact plug 360 may be formed to include a conductive material such as tungsten. The fifth mask pattern MP5 is then removed.

[0066] The example shown in the figure illustrates one contact plug 360, but the number of contact plugs 360 is not limited to one. For example, the number of contact plugs can be the same as the number of third material layers 310C. Each contact plug is formed with a different height and is connected to a corresponding third material layer 310C. A support structure can be formed below each contact plug.

[0067] According to the manufacturing method, a first support hole is formed near the area where the contact hole is formed, and the first support hole is enlarged so that the first support holes are interconnected. The stack 310S remains in the area surrounded by the enlarged first support holes, and the remaining stack 310S forms a support structure, which prevents the stack 310S from bending during the process of forming the gate structure 310G.

[0068] Although detailed embodiments have been described in this disclosure, those skilled in the art will understand that various modifications, additions, and substitutions are possible related to these embodiments without departing from the scope and technical concept of this disclosure. Therefore, the scope of this disclosure should not be limited to the foregoing embodiments. All changes within the meaning and equivalent scope of the claims are included within its scope.

[0069] Cross-references to related applications

[0070] This application claims priority to Korean Patent Application No. 10-2024-0130218, filed on September 25, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A support structure comprising a plurality of first insulating layers and a plurality of second insulating layers that are alternately stacked on top of each other; A gate structure comprising multiple conductive layers and including a first segment and a second segment, the first segment being located at a height corresponding to the height of the support structure, and the second segment being located on the support structure; A contact plug that extends through the gate structure and is connected to a first conductive layer of the plurality of conductive layers; as well as A first support member includes a plurality of posts extending between the first section and the support structure and extending through the second section, and a plurality of first protrusions projecting from the plurality of posts into the support structure.

2. The semiconductor device according to claim 1, wherein, The plurality of first protrusions are interconnected on a plane and surround a closed region.

3. The semiconductor device according to claim 2, wherein, The plurality of second insulating layers are located at a height corresponding to the height of the plurality of first protrusions and are located within the closed region.

4. The semiconductor device according to claim 1, wherein, The plurality of posts surround the contact plug and are spaced apart from each other.

5. The semiconductor device according to claim 4, further comprising: A channel structure extending through the gate structure; as well as A second support extending through the gate structure.

6. The semiconductor device according to claim 5, wherein, The plurality of columns have a width substantially the same as the width of the channel structure.

7. The semiconductor device according to claim 5, wherein, The second support member has a width that is substantially the same as the width of the channel structure.

8. The semiconductor device of claim 1, further comprising a channel structure extending through the gate structure.

9. The semiconductor device according to claim 8, wherein, The width of one of the plurality of first protrusions is wider than the width of the channel structure.

10. The semiconductor device of claim 1, further comprising a slit structure extending through the gate structure and including a plurality of second protrusions projecting into the gate structure.

11. The semiconductor device according to claim 1, wherein, Each of the plurality of first insulating layers is thinner than one of the plurality of second insulating layers or one of the plurality of conductive layers.

12. A semiconductor device, the semiconductor device comprising: A support structure comprising a plurality of first insulating layers and a plurality of second insulating layers that are alternately stacked on top of each other; A gate structure comprising multiple conductive layers and including a first segment and a second segment, the first segment being located at a height corresponding to the height of the support structure, and the second segment being located on the support structure; A contact plug located on the support structure, extending through the gate structure and connected to a first conductive layer of the plurality of conductive layers; A first support member extends between the first section and the support structure and extends through the second section; as well as A second support member is spaced apart from the first support member and extends through the gate structure.

13. The semiconductor device according to claim 12, wherein, The first support member includes a plurality of posts extending between the first section and the support structure and through the second section, and a plurality of first protrusions protruding from each of the plurality of posts into the support structure.

14. The semiconductor device according to claim 13, wherein, The plurality of first protrusions are interconnected on a plane and surround a closed region.

15. The semiconductor device according to claim 14, wherein, The plurality of second insulating layers are located at a height corresponding to the height of the plurality of first protrusions and are located within the closed region.

16. The semiconductor device according to claim 13, wherein, The plurality of posts surround the contact plug and are spaced apart from each other.

17. The semiconductor device of claim 13, further comprising a channel structure extending through the gate structure.

18. The semiconductor device according to claim 17, wherein, The width of one of the columns is substantially the same as the width of the channel structure.

19. The semiconductor device according to claim 17, wherein, The width of one of the plurality of first protrusions is wider than the width of the channel structure.

20. The semiconductor device according to claim 17, wherein, The width of the second support member is basically the same as the width of the channel structure.

21. The semiconductor device of claim 12, further comprising a slit structure extending through the gate structure and including a plurality of second protrusions projecting into the gate structure.

22. The semiconductor device according to claim 12, wherein, One of the plurality of first insulating layers is thinner than one of the plurality of second insulating layers or one of the plurality of conductive layers.

23. A method for manufacturing a semiconductor device, the method comprising the following steps: A laminate is formed by alternately stacking multiple first material layers and multiple second material layers; Forming a plurality of preliminary first support holes extending through the stack; A first support sacrificial layer is formed in one of the corresponding preliminary first support holes among the plurality of preliminary first support holes; An initial contact hole is formed in the region surrounded by the plurality of initial first support holes and extends through the laminate, and at least one of the plurality of second material layers is exposed through the initial contact hole; The second material layer is selectively removed through the initial contact hole to form a plurality of first openings, through which a plurality of first support sacrificial layers are exposed; The plurality of first support sacrificial layers are removed from the plurality of preliminary first support holes, thereby forming a plurality of first support holes; The plurality of first support holes are enlarged by selectively removing the plurality of second material layers through the plurality of first support holes, thereby forming enlarged first support holes; as well as A first support member is formed in the enlarged first support hole.

24. The method according to claim 23, wherein, The step of enlarging the plurality of first support holes includes enlarging the plurality of first support holes so that the first support holes are interconnected.

25. The method according to claim 23, further comprising the following step: Forming a plurality of preliminary second support holes extending through the stack; A second support sacrificial layer is formed in one of the corresponding preliminary second support holes among the plurality of preliminary second support holes; A first mask pattern is formed to cover the plurality of first support sacrificial layers, and the plurality of second support sacrificial layers are exposed through the first mask pattern; The second support sacrificial layer is removed by the first mask pattern, thereby forming a plurality of second support holes; as well as A second support member is formed in each of the plurality of second support holes.

26. The method according to claim 23, wherein, The steps for forming the initial contact hole include the following: A second mask pattern is formed covering the plurality of first support sacrificial layers, and the area surrounded by the plurality of first support holes is exposed through the second mask pattern; and The initial contact hole is formed by etching the stack using the second mask pattern as an etching barrier.

27. The method according to claim 23, wherein, The step of removing the plurality of first support sacrificial layers includes the following steps: A third mask pattern is formed covering the initial contact hole, through which the plurality of first support sacrificial layers are exposed; and The plurality of first support sacrificial layers are removed by the third mask pattern.

28. The method according to claim 23, further comprising the following steps: A sacrificial layer is formed in each of the plurality of first openings; as well as A contact sacrificial layer is formed in the initial contact hole.

29. The method of claim 28, further comprising the step of: Forming a plurality of slits extending through the stack; A fourth mask pattern is formed covering the contact sacrificial layer and the first support member, through which the plurality of slit holes are exposed; The plurality of slit holes are enlarged by etching the laminate using the fourth mask pattern as an etching barrier, so that the plurality of slit holes are connected to each other to form a slit extending in one direction. as well as A slit structure is formed in the slit.

30. The method according to claim 29, further comprising the following steps: The plurality of second material layers are removed through the slits, thereby forming a plurality of second openings through which the plurality of sacrificial layers are exposed. Wherein, the plurality of sacrificial layers are removed through the plurality of second openings; and Multiple third material layers are formed in the first opening and the second opening.

31. The method according to claim 28, further comprising the following steps: A fifth mask pattern is formed to cover the first support member, and the contact sacrificial layer is exposed through the fifth mask pattern; The fifth mask pattern is used as an etching barrier to remove the contact sacrificial layer, thereby forming a contact hole; as well as A contact plug is formed in the contact hole.

32. The method according to claim 28, wherein, The multiple sacrificial layers have an etch selectivity ratio relative to the multiple first material layers and the multiple second material layers.

33. The method according to claim 32, wherein, The plurality of sacrificial layers include polycrystalline silicon.

34. The method according to claim 23, further comprising the following steps: Forming a plurality of channel holes extending through the laminate; and A channel structure is formed in one of the corresponding channels among the plurality of channels.

35. The method according to claim 34, wherein, The plurality of preliminary first support holes are formed when the plurality of channel holes are formed.

36. The method according to claim 23, wherein, One of the plurality of first material layers is thinner than one of the plurality of second material layers.

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