Nonvolatile memory device with ferroelectric layer

Abstract

A non-volatile memory device according to an embodiment includes a substrate having an upper surface and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked in a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. One sidewall surface of the gate structure forms a plane substantially parallel to the first direction and the second direction. The nonvolatile memory device includes: a channel layer disposed on a ferroelectric layer; and a source electrode structure and a drain electrode structure disposed in contact with the channel layer and spaced apart from each other in the second direction.

Description

[0001] This application is a divisional application of the invention patent application with application number 202010651872.X, the original application being filed on July 8, 2020, and entitled: Non-volatile storage device with ferroelectric layer. Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0163139, filed on December 9, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a non-volatile memory device, and more specifically, to a non-volatile memory device having a ferroelectric layer. Background Technology

[0004] As design rules become more restrictive and integration density increases, research continues on semiconductor device structures that can simultaneously guarantee structural stability and signal storage reliability. Currently, flash memory devices employing a three-layer stacked structure of charge tunneling layer, charge trapping layer, and charge blocking layer are widely used for charge storage.

[0005] Recently, various non-volatile memory devices with structures different from existing flash memory devices have been proposed. An example of a non-volatile memory device is a ferroelectric memory device with a transistor structure. Ferroelectric memory devices can non-volatilely store any residual polarization of different sizes and orientations as signal information in the gate ferroelectric layer. Furthermore, the signal information can be read out by utilizing the characteristic that the magnitude of the operating current flowing through the channel layer between the source and drain electrodes changes according to the stored residual polarization. Summary of the Invention

[0006] A non-volatile memory device according to one aspect of this disclosure includes a substrate having an upper surface and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. Additionally, the non-volatile memory device includes a ferroelectric layer disposed above the substrate on at least a portion of a sidewall surface of the gate structure. The sidewall surface of the gate structure is a plane defined by the first and second directions. The non-volatile memory device includes: a channel layer disposed above the substrate and on the ferroelectric layer; and a source electrode structure and a drain electrode structure, each disposed above the substrate and configured to contact the channel layer. The source electrode structure and the drain electrode structure are spaced apart from each other in the second direction.

[0007] A non-volatile memory device according to another aspect of this disclosure includes a substrate having an upper surface and a gate structure disposed above the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The non-volatile memory device includes a ferroelectric layer disposed above the substrate on at least a portion of a sidewall surface of the gate structure. One sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The non-volatile memory device includes: a source electrode structure and a drain electrode structure disposed on the ferroelectric layer and spaced apart from each other in the second direction; and a channel structure disposed above the substrate and between the source electrode structure and the drain electrode structure. Each of the source electrode structure and the drain electrode structure is disposed on the ferroelectric layer.

[0008] A non-volatile memory device according to another aspect of this disclosure includes a substrate and a gate structure disposed above the substrate having an upper surface. The gate structure includes at least one gate functional layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The non-volatile memory device includes an interface insulating layer and a channel layer sequentially disposed on a sidewall surface of the gate structure. The sidewall surface of the gate structure is a plane defined by the first and second directions. The non-volatile memory device includes a source electrode structure and a drain electrode structure spaced apart from each other in the second direction. Each of the source electrode structure and the drain electrode structure contacts the channel layer. The gate functional layer pattern includes: a floating electrode layer portion disposed on the interface insulating layer and the gate insulating layer pattern; a ferroelectric layer portion disposed on the floating electrode layer portion and the interface insulating layer; and a gate electrode layer portion configured to contact the ferroelectric layer portion. Attached Figure Description

[0009] Figure 1 This is a perspective view schematically illustrating a non-volatile storage device according to an embodiment of the present disclosure.

[0010] Figure 2 yes Figure 1 A plan view of a non-volatile storage device.

[0011] Figure 3 It is along Figure 1 A cross-sectional view of line AA′ of a non-volatile storage device.

[0012] Figures 4A to 4E This is a view schematically illustrating the operation of a non-volatile storage device according to an embodiment of the present disclosure.

[0013] Figure 5This is a perspective view schematically illustrating a non-volatile storage device according to another embodiment of the present disclosure.

[0014] Figure 6A It is shown schematically. Figure 5 Circuit diagram of non-volatile memory devices.

[0015] Figure 6B Is with Figure 6A A partial plan view of the non-volatile storage device corresponding to the circuit.

[0016] Figure 6C It is along Figure 6B The cross-sectional view taken by line CC′.

[0017] Figure 7 This is a perspective view schematically illustrating a non-volatile storage device according to another embodiment of the present disclosure.

[0018] Figure 8 yes Figure 7 A plan view of a non-volatile storage device.

[0019] Figure 9 It is along Figure 7 A cross-sectional view of the non-volatile storage device DD′.

[0020] Figure 10 This is a perspective view schematically illustrating a non-volatile storage device according to yet another embodiment of the present disclosure.

[0021] Figure 11 yes Figure 10 A plan view of a non-volatile storage device.

[0022] Figure 12 It is along Figure 10 A cross-sectional view of the non-volatile storage device EE′.

[0023] Figure 13 This is a perspective view schematically illustrating a non-volatile storage device according to yet another embodiment of the present disclosure.

[0024] Figure 14 yes Figure 13 A plan view of a non-volatile storage device.

[0025] Figure 15 It is along Figure 13 A cross-sectional view of the non-volatile storage device taken from line FF′.

[0026] Figure 16 This is a perspective view schematically illustrating a non-volatile storage device according to yet another embodiment of the present disclosure.

[0027] Figure 17 yes Figure 16 A plan view of a non-volatile storage device.

[0028] Figure 18 It is along Figure 16 A cross-sectional view of line GG′ of a non-volatile storage device.

[0029] Figure 19 This is a perspective view schematically illustrating a non-volatile storage device according to a further embodiment of the present disclosure.

[0030] Figure 20 yes Figure 19 A plan view of a non-volatile storage device.

[0031] Figure 21 It is along Figure 19 A cross-sectional view of line HH′ of a non-volatile storage device.

[0032] Figure 22 This is a perspective view schematically illustrating a non-volatile storage device according to a further embodiment of the present disclosure.

[0033] Figure 23 yes Figure 22 A plan view of a non-volatile storage device.

[0034] Figure 24 It is along Figure 22 A cross-sectional view of line II′ of a non-volatile storage device. Detailed Implementation

[0035] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (such as the width and thickness of the components) are enlarged to clearly illustrate the components of each device. The terms used herein may correspond to words chosen in consideration of their function in the embodiments, and the meaning of these terms may be interpreted differently by those skilled in the art to which the embodiments pertain. Where explicitly defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0036] Furthermore, unless explicitly omitted in the context, the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms “comprising” or “having” are intended to specify the presence of a feature, number, step, operation, component, element, part, or combination thereof, and not to exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

[0037] In this specification, the term "predetermined direction" can refer to a direction defined in a coordinate system and a direction opposite to that direction. For example, in the xyz coordinate system, the z-direction can refer to the direction in which the absolute value of the z-axis increases from the origin 0 along the positive z-axis direction and the direction in which the absolute value of the z-axis increases from the origin 0 along the negative z-axis direction. In the xyz coordinate system, the x-direction and y-direction can each be interpreted in substantially the same way.

[0038] Figure 1 This is a perspective view schematically showing a non-volatile storage device 1 according to an embodiment of the present disclosure. Figure 2 yes Figure 1 A plan view of a non-volatile storage device. Figure 3 It is along Figure 1 A cross-sectional view of line AA′ of a non-volatile storage device.

[0039] refer to Figures 1 to 3 The non-volatile memory device 1 may include a substrate 101, a first gate structure 12 and a second gate structure 14, a source electrode structure 22, a drain electrode structure 24, a first ferroelectric layer 312 and a second ferroelectric layer 314, and a first channel layer 322 and a second channel layer 324. Furthermore, the non-volatile memory device 1 may also include a substrate insulating layer 110 disposed on the substrate 101 and an insulating structure 26 extending in a first direction (i.e., the z-direction) perpendicular to the substrate 101. The memory device structure including the first gate structure 12, the first ferroelectric layer 312, and the first channel layer 322 may share the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26 with the memory device structure including the second gate structure 14, the second ferroelectric layer 314, and the second channel layer 324.

[0040] Substrate 101 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), and gallium arsenide (GaAs), etc. Substrate 101 may be doped with n-type dopant or p-type dopant. As an example, substrate 101 may include a well region doped with n-type dopant or p-type dopant.

[0041] The substrate insulating layer 110 can be disposed on the substrate 101. The substrate insulating layer 110 can electrically insulate the first gate structure 12 and the second gate structure 14, the first ferroelectric layer 312 and the second ferroelectric layer 314, the first channel layer 322 and the second channel layer 324, the source electrode structure 22 and the drain electrode structure 24 from the substrate 101.

[0042] Although not in Figure 1As shown, but at least one conductive layer and at least one insulating layer may be disposed between the substrate 101 and the base insulating layer 110. The conductive layer and the insulating layer may form various circuit patterns. That is, as a non-limiting example, the conductive layer and the insulating layer may form multiple wirings, or may constitute passive components (such as capacitors or resistors), or active components (such as diodes or transistors).

[0043] refer to Figure 1 The first gate electrode structure 12 may be disposed on the substrate insulating layer 110. The first gate electrode structure 12 may include first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d alternately stacked with first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e along a first direction perpendicular to the substrate 101 (i.e., the z-direction) on the substrate insulating layer 110. The first gate insulating layer pattern 132a may be configured to contact the substrate insulating layer 110. The fifth gate insulating layer pattern 132e may be configured as the uppermost layer of the first gate electrode structure 12.

[0044] The first gate electrode structure 12 can extend in a second direction (i.e., the y-direction) perpendicular to the first direction. The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can be electrically insulated from each other by the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e. The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can be conductive lines extending in the second direction (i.e., the y-direction). The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d can each maintain a predetermined potential.

[0045] In one embodiment, the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d may each include a conductive material. For example, the conductive material may include a doped semiconductor material, a metal, a conductive metal silicide, a conductive metal nitride, or a conductive metal oxide. For example, the conductive material may include n-type doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more of these. The first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e may each include an insulating material. For example, the insulating material may include oxides, nitrides, and oxynitrides.

[0046] In some other embodiments, the number of gate electrode layer patterns in the first gate electrode structure 12 is not necessarily limited to four. The number of gate electrode layer patterns can be set to various different numbers, and the gate insulating layer pattern can make various numbers of source electrode layer patterns insulating along the first direction (i.e., the z direction).

[0047] refer to Figures 1 to 3 The first ferroelectric layer 312 can be disposed on the substrate insulating layer 110 and on a sidewall surface S1 of the first gate structure 12. Here, the sidewall surface S1 can be formed into a plane substantially parallel to the first direction and the second direction (i.e., a yz plane parallel to the z and y directions). The first ferroelectric layer 312 can have a predetermined thickness t1 along a third direction perpendicular to the first and second directions (i.e., the x direction). For example, the thickness t1 can be from 1 nanometer (nm) to 50 nanometers (nm) (inclusive).

[0048] The first ferroelectric layer 312 may include a ferroelectric material. In the absence of an external electric field, the ferroelectric material may exhibit electroresidual polarization. Furthermore, when an external electric field is applied, the polarization in the ferroelectric material may exhibit hysteresis behavior. By controlling the external electric field, one of multiple stable polarization states on the polarization hysteresis curve can be written into the ferroelectric material. After removing the external electric field from the ferroelectric material, the written polarization can be stored in the ferroelectric material as residual polarization. Residual polarization can be used for non-volatile storage of multiple signal information. For example, the first ferroelectric layer 312 may include hafnium oxide, zirconium oxide, and hafnium zirconium oxide. The first ferroelectric layer 312 may have an orthorhombic crystal structure.

[0049] The first channel layer 322 can be disposed on the substrate insulating layer 110 and contact the first ferroelectric layer 312. Specifically, the first channel layer 322 can be disposed on a surface S2 of the first ferroelectric layer 312 defined by a first direction and a second direction (i.e., the z-direction and the y-direction). The first channel layer 322 can have a predetermined thickness t2 along a third direction (i.e., the x-direction). For example, the thickness t2 can be from 1 nanometer (nm) to 50 nanometers (nm) (inclusive). Although in Figure 3 The thickness of the first ferroelectric layer 312 is shown to be greater than the thickness of the first channel layer 322, but the thickness of the first ferroelectric layer 312 is not limited thereto, and in other embodiments, the thickness of the first ferroelectric layer 312 may be less than or equal to the thickness of the first channel layer 322.

[0050] The first channel layer 322 can provide a path for charge carriers (such as electrons or holes) to move between the source electrode structure 22 and the drain electrode structure 24. As will be described later, the resistance of the first channel layer 322 can be reduced when a conductive channel is formed in the first channel layer 322. However, the resistance of the conductive channel can also vary depending on the magnitude and orientation of the residual polarization stored in the first ferroelectric layer 312.

[0051] The first channel layer 322 may include, for example, a doped semiconductor material or a metal oxide. For example, the semiconductor material may include silicon (Si), germanium (Ge), and gallium arsenide (GaAs). The metal oxide may include indium gallium zinc (In-Ga-Zn) oxide. In one embodiment, the first channel layer 322 may include silicon (Si) doped with an n-type dopant. Alternatively, the first channel layer 322 may include c-axis aligned indium gallium zinc (In-Ga-Zn) oxide. The first channel layer 322 may have a single-crystal structure or a polycrystalline structure.

[0052] Refer again Figures 1 to 3 The source electrode structure 22 and the drain electrode structure 24 can each be disposed on the substrate insulating layer 110 to contact the surface S3 of the first channel layer 322, while being spaced apart from each other in the second direction (i.e., the y-direction). The source electrode structure 22 and the drain electrode structure 24 can each have a columnar shape extending along the first direction (i.e., the z-direction). The source electrode structure 22 and the drain electrode structure 24 can each be configured to contact the first channel layer 322 and the second channel layer 324.

[0053] An insulating structure 26 may be disposed between the source electrode structure 22 and the drain electrode structure 24. The insulating structure 26 may be configured to contact the first channel layer 322 and the second channel layer 324. The insulating structure 26 may have a columnar shape extending in a first direction (i.e., the z-direction) from the substrate insulating layer 110. The insulating structure 26 serves to suppress the movement of charge carriers between the source electrode structure 22 and the drain electrode structure 24 via paths other than the first channel layer 322 or the second channel layer 324.

[0054] The source electrode structure 22 and the drain electrode structure 24 can each maintain a predetermined potential. The potentials of each of the source electrode structure 22 and the drain electrode structure 24 can be the same or different from each other. In one embodiment, during operation of the non-volatile memory device, if a conductive channel is formed in the first channel layer 322 or the second channel layer 324 and a predetermined potential difference occurs between the source electrode structure 22 and the drain electrode structure 24, charge carriers can move through the conductive channel.

[0055] The source electrode structure 22 and the drain electrode structure 24 may each include a conductive material. For example, the conductive material may include doped semiconductor materials, metals, conductive metal nitrides, conductive metal oxides, conductive metal carbides, and conductive metal silicides. For instance, the conductive material may include doped silicon, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more of these. The insulating structure 26 may include oxides, nitrides, or oxynitrides. As an example, the insulating structure 26 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0056] refer to Figures 1 to 3 The second channel layer 324 can be disposed on the substrate insulating layer 110 and can contact the sidewalls of the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. The sidewalls of the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26 can be located on the same plane S4. The plane S4 can be formed as a plane substantially parallel to the first direction and the second direction (i.e., a yz plane parallel to the z and y directions). The second channel layer 324 can have a predetermined thickness t2 along a third direction (i.e., the x direction). The configuration of the second channel layer 324 can be substantially the same as the configuration of the first channel layer 322.

[0057] The second ferroelectric layer 314 may be disposed on the substrate insulating layer 110 and on one surface S5 of the second channel layer 324. This surface S5 may be a plane defined by a first direction and a second direction (i.e., a yz plane parallel to the z and y directions). The second ferroelectric layer 314 may have a predetermined thickness t1 along a third direction (i.e., the x direction). The configuration of the second ferroelectric layer 314 may be substantially the same as the configuration of the first ferroelectric layer 312.

[0058] The second gate structure 14 may be disposed on the substrate insulating layer 110 and contact a surface S6 of the second ferroelectric layer 314. The plane S6 may be formed substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). The second gate structure 14 may include alternating stacked first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d and first to fifth gate insulating layer patterns 134a, 134b, 134c, 134d, and 134e along the first direction (i.e., the z direction). The first gate insulating layer pattern 134a may be configured to contact the substrate insulating layer 110. The fifth gate insulating layer pattern 134e may be configured as the uppermost layer of the second gate structure 14. The second gate structure 14 may extend in the second direction (i.e., the y direction). The configuration of the first to fourth gate electrode layer patterns 124a, 124b, 124c and 124d of the second gate structure 14 and the first to fifth gate insulating layer patterns 134a, 134b, 134c, 134d and 134e can be substantially the same as the configuration of the first to fourth gate electrode layer patterns 122a, 122b, 122c and 122d of the first gate structure 12 and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d and 132e.

[0059] As described above, in the non-volatile memory device 1 according to an embodiment of the present disclosure, the first gate structure 12 and the second gate structure 14 can be symmetrically disposed on both sides of the yz plane centered on the source electrode structure 22, the insulating structure 26, and the drain electrode structure 24. Similarly, the first ferroelectric layer 312 and the second ferroelectric layer 314 can be symmetrically disposed on both sides, and the first channel layer 322 and the second channel layer 324 can be symmetrically disposed on both sides.

[0060] In one embodiment, the first gate structure 12, the first ferroelectric layer 312, the first channel layer 322, the source electrode structure 22, and the drain electrode structure 24 can constitute one operating unit of the non-volatile memory device 1, and the second gate structure 14, the second ferroelectric layer 314, the second channel layer 324, the source electrode structure 22, and the drain electrode structure 24 can constitute another operating unit of the non-volatile memory device 1. The source electrode structure 22 and the drain electrode structure 24 can be shared by different operating units. That is, the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12, the first ferroelectric layer 312, and the first channel layer 322 can work with the source electrode structure 22 and the drain electrode structure 24. Furthermore, the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14, the second ferroelectric layer 314, and the second channel layer 324 can work with the source electrode structure 22 and the drain electrode structure 24.

[0061] Figures 4A to 4E This is a view schematically illustrating the operation of a non-volatile storage device according to an embodiment of the present disclosure. Figure 4A This is a circuit diagram of a non-volatile storage device according to an embodiment of the present disclosure. Figure 4B Is with Figure 4A The circuit diagram corresponds to a partial plan view of a non-volatile storage device. Figure 4C and Figure 4D This is a schematic view illustrating different residual polarizations stored in the ferroelectric layer of a non-volatile memory device according to embodiments of the present disclosure. Figure 4E It is along Figure 4B The cross-sectional view taken from line BB′.

[0062] Specifically, Figure 4B The above references are shown schematically. Figures 1 to 3 A plan view of an operating unit 1a of a described non-volatile memory device 1. An operating unit 1a may, for example, include a first gate structure 12, a first ferroelectric layer 312, a first channel layer 322, a source electrode structure 22, a drain electrode structure 24, and an insulating structure 26. For ease of explanation regarding the operation of an operating unit 1a, in... Figure 4B The uppermost gate insulating layer pattern 132e of the first gate structure 12 is omitted.

[0063] refer to Figure 4A The first to fourth memory cells MC1, MC2, MC3 and MC4 are disclosed. The first to fourth memory cells MC1, MC2, MC3 and MC4 may each have the form of a transistor and may each include the first to fourth ferroelectric layers FD1, FD2, FD3 and FD4 used as memory layers.

[0064] The source and drain of each of the first to fourth memory cells MC1, MC2, MC3 and MC4 can be electrically connected to the global source line (GSL) and the global drain line (GDL). The gate electrodes of the first to fourth memory cells MC1, MC2, MC3 and MC4 can be electrically connected to the first to fourth word lines GL1, GL2, GL3 and GL4, respectively.

[0065] For a write operation targeting at least one of the first to fourth memory cells MC1, MC2, MC3, and MC4, at least one of the first to fourth word lines GL1, GL2, GL3, and GL4 can be selected. A polarization switching voltage with an amplitude greater than or equal to a predetermined threshold voltage can be applied to the two ends of each of the first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 of the corresponding first to fourth memory cells MC1, MC2, MC3, and MC4 via at least one selected word line. At this time, the global source line GSL and the global drain line GDL can be grounded. By applying the polarization switching voltage, the polarization of the first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 can be switched and then aligned in a predetermined direction. After the polarization switching voltage is removed, the switched polarization can be stored in the corresponding first to fourth ferroelectric layers FD1, FD2, FD3, and FD4 as residual polarization. As a result, as described above, by applying a polarization switching voltage through at least one of the first to fourth word lines GL1, GL2, GL3, and GL4, a write operation can be performed on at least one of the first to fourth memory cells MC1, MC2, MC3, and MC4. After the write operation is completed, a predetermined signal can be stored in the corresponding memory cell in a non-volatile manner.

[0066] Simultaneously, operations can be performed to read signals that are non-volatilely stored in the first to fourth memory cells MC1, MC2, MC3, and MC4. As an exemplary example, the process of reading a signal stored in the fourth memory cell MC4 will be described. First, the fourth word line GL4 corresponding to the fourth memory cell MC4 is selected. Subsequently, a read voltage greater than or equal to a predetermined threshold voltage can be applied to the gate electrode of the fourth memory cell MC4 through the fourth word line GL4. The absolute value of the read voltage can be less than the absolute value of the polarization switching voltage. That is, the polarization inside the fourth ferroelectric layer FD4 may not be switched by the read voltage. The transistor of the fourth memory cell MC4 is turned on by the read voltage, and a conductive channel can be formed in the channel layer of the transistor. As a result, when a source-drain potential difference is formed between the global source line GSL and the global drain line GDL, a source-drain current can flow through the conductive channel.

[0067] The source-drain current can vary depending on the orientation and magnitude of the residual polarization stored in the fourth ferroelectric layer FD4. As an example, when the residual polarization is oriented from the gate electrode toward the channel layer (corresponding to...) Figure 4CIn the first polarization DP1, positive charges accumulate inside the fourth ferroelectric layer FD4 adjacent to the channel layer, thereby increasing the electron density of the conductive channel. Therefore, the magnitude of the current flowing along the conductive channel can be increased. As another example, when the residual polarization is oriented from the channel layer toward the gate electrode (corresponding to...), Figure 4D The second polarization (DP2) in the channel layer accumulates negative charges within the fourth ferroelectric layer (FD4) adjacent to the channel layer, thereby reducing the electron density of the conductive channel. Therefore, the magnitude of the current flowing along the conductive channel can be reduced. As described above, by turning on the transistor of the memory cell to be read and measuring the current flowing through the channel layer, the signal stored in the memory cell can be read.

[0068] In other embodiments, the number of memory cells disposed between the global source line GSL and the global drain line GDL is not limited to four, and can be various other numbers. Similarly, the number of word lines is not limited to four, and can be various other numbers.

[0069] refer to Figure 4B The above reference Figure 4A The described global source line GSL can correspond to source electrode structure 22, and the global drain line GDL can correspond to drain electrode structure 24. Additionally, the first to fourth word lines GL1, GL2, GL3, and GL4 can correspond to... Figures 1-3 The first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12 in the middle. Therefore, Figure 4A The fourth word line GL4 and the fourth ferroelectric layer FD4 of the fourth memory cell MC4 shown can correspond to Figure 4B The fourth gate electrode layer pattern 122d and the area of ​​the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d are shown in the diagram. (Reference) Figure 4B and Figure 4E , Figure 4A The channel layer of the fourth memory cell MC4 shown can correspond to the eighth region 322-h of the first channel layer 322, which is covered by the fourth gate electrode layer pattern 122d, between the source electrode structure 22 and the drain electrode structure 24. (See reference...) Figures 1 to 3 and Figure 4E The first channel layer 322 may include first to ninth regions 322-a, 322-b, 322-c, 322-d, 322-e, 322-f, 322-g, 322-h, and 322-i, which correspond to the regions that overlap with the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, and 132e in a third direction (i.e., the x-direction) between the source electrode structure 22 and the drain electrode structure 24. As an example, Figure 4AThe channel layers of the first to third memory cells MC1, MC2 and MC3 shown can correspond to Figure 4E The second region 322-b, the fourth region 322-d, and the sixth region 322-f of the first channel layer 322.

[0070] In the following text, as an example, a description will be given for including Figures 4B to 4E The write and read operations of the memory cell structure shown are for the fourth gate electrode layer pattern 122d, the first ferroelectric layer 312, and the eighth part 322-h of the first channel layer 322. The memory cell structure corresponds to... Figure 4A The fourth memory cell MC4 of the non-volatile memory device is shown. It can correspond to the first to third memory cells MC1, MC2, and MC3. Figures 4B to 4E The storage cell structure applies essentially the same write and read operations.

[0071] Can be used Figures 4B to 4D This describes the write operation to the fourth memory cell, MC4. (See reference...) Figure 4B The fourth gate electrode layer pattern 122d is selected from the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12. Subsequently, the source electrode structure 22 and the drain electrode structure 24 are grounded, and a first polarization switching voltage with positive polarity is applied to the fourth gate electrode layer pattern 122d. The first polarization switching voltage can be a voltage with an absolute value equal to or greater than a predetermined threshold voltage, enabling the switching of the polarization orientation of the first ferroelectric layer 312. When the first polarization switching voltage is applied, as... Figure 4C As shown, a first polarization DP1 can be formed in the region of the first ferroelectric layer 312 that is covered by or shares the region with the fourth gate electrode layer pattern 122d. The first polarization DP1 can be oriented from the interface region of the first ferroelectric layer 312 that contacts the fourth gate electrode layer pattern 122d toward the interface region of the first ferroelectric layer 312 that contacts the first channel layer 322. Subsequently, the first polarization switching voltage is removed. Even after the first polarization switching voltage is removed, the first polarization DP1 can be stored in the form of residual polarization. In addition, the formation of the first polarization DP1 allows positive charge CP and negative charge CN to be generated in the internal region of the first ferroelectric layer 312. Even after the first polarization switching voltage is removed, the positive charge CP can be distributed in the interface region of the first ferroelectric layer 312 that contacts the first channel layer 322, while the negative charge CN can be distributed in the interface region of the first ferroelectric layer 312 that contacts the fourth gate electrode layer pattern 122d.

[0072] As another embodiment, in Figure 4BIn this process, the fourth gate electrode layer pattern 122d is selected from the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d. Subsequently, after grounding the source electrode structure 22 and the drain electrode structure 24, a second polarization switching voltage with negative polarity is applied to the fourth gate electrode layer pattern 122d. The second polarization switching voltage can be a voltage whose absolute value is equal to or greater than a predetermined threshold voltage to switch the polarization orientation of the first ferroelectric layer 312. When the second polarization switching voltage is applied, as... Figure 4D As shown, a second polarization DP2 can be formed in the internal region of the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d. The second polarization DP2 can be oriented from the interface region of the first ferroelectric layer 312 contacting the first channel layer 322 toward the interface region of the first ferroelectric layer 312 contacting the fourth gate electrode layer pattern 122d. Subsequently, the second polarization switching voltage is removed. Even after the second polarization switching voltage is removed, the second polarization DP2 can be stored in the form of residual polarization. Furthermore, the formation of the second polarization DP2 allows positive charges CP and negative charges CN to be generated in the internal region of the first ferroelectric layer 312. Even after the second polarization switching voltage is removed, the positive charge CP can be distributed in the interface region of the first ferroelectric layer 312 contacting the fourth gate electrode layer pattern 122d, while the negative charge CN can be distributed in the interface region of the first ferroelectric layer 312 contacting the first channel layer 322. As described above, it is possible to achieve this through the above reference. Figures 4B to 4D The polarization orientation switching operation of the first ferroelectric layer 312 is described to perform the write operation. As an example, with Figure 4C The formation operation of the first polarization DP1 can be called a programming operation, and is related to... Figure 4D The formation operation of the second polarization DP2 can be referred to as the erasure operation.

[0073] At the same time, will refer to Figure 4B and Figure 4E The following describes the operation of reading signal information stored in the fourth memory cell MC4. First, a read voltage with an absolute value equal to or greater than a predetermined threshold voltage is applied to the fourth gate electrode layer pattern 122d. The absolute value of the read voltage can be less than the absolute values ​​of the first polarization switching voltage and the second polarization switching voltage. That is, the polarization of the first ferroelectric layer 312 covered by the fourth gate electrode layer pattern 122d may not be switched due to the read voltage.

[0074] Conversely, a conductive channel CH4 can be formed in the eighth region 322-h of the first channel layer 322 adjacent to the first ferroelectric layer 312 by reading the voltage. (Reference) Figure 4EThe conductive channel CH4 can electrically connect the source electrode structure 22 to the drain electrode structure 24. The electron density inside the conductive channel CH4 can be higher than the electron density of the first channel layer 322 outside the conductive channel CH4.

[0075] After the conductive channel CH4 is formed, a source-drain potential difference is created between the source electrode structure 22 and the drain electrode structure 24. As an example, after grounding the source electrode structure 22, a positive drain voltage can be applied to the drain electrode structure 24. Therefore, electrons can flow from the source electrode structure 22 to the drain electrode structure 24 through the conductive channel CH4. At this time, the current density generated by the electron flow may be affected by the orientation of the residual polarization stored in the adjacent first ferroelectric layer 312. When the orientation of the residual polarization is... Figure 4C When the orientation of the first polarization DP1 is the same, the electron density inside the conductive channel CH4 increases, allowing for an increase in the current density flowing along the conductive channel CH4. Conversely, when the orientation of the residual polarization is the same as... Figure 4D When the orientations of the second polarization DP2 are the same, the electron density inside the conductive channel CH4 decreases, thereby reducing the current density flowing along the conductive channel CH4. As described above, by forming a conductive channel in the channel layer of the memory cell to be read, and by measuring the current flowing through the conductive channel, the signal stored in the memory cell can be read.

[0076] According to one embodiment of this disclosure, a non-volatile memory device may include a gate structure, a source electrode structure, and a drain electrode structure disposed in a direction perpendicular to the substrate. Additionally, the non-volatile memory device may include a ferroelectric layer and a channel layer disposed adjacent to the gate structure, source electrode structure, and drain electrode structure. In the non-volatile memory device, multiple memory cells can be randomly accessed through independently selectable gate electrode layer patterns. Thus, the non-volatile memory device can independently perform write and read operations on the accessed memory cells.

[0077] Figure 5 This is a perspective view schematically showing a non-volatile storage device 2 according to another embodiment of the present disclosure. Figure 6A It is shown schematically. Figure 5 Circuit diagram of non-volatile memory devices. Figure 6B Is with Figure 6A The circuit diagram corresponds to a partial plan view of the non-volatile memory device, and Figure 6C It is along Figure 6B The cross-sectional view taken by line CC′. Figure 6A and Figure 6B It can be shown schematically. Figure 5 A view of an operation unit 2a of a non-volatile storage device 2.

[0078] refer to Figure 5 , and the above reference Figures 1 to 3 Compared to the described non-volatile memory device 1, the non-volatile memory device 2 may include a plurality of source electrode structures 22a and 22b, a plurality of drain electrode structures 24a and 24b, and insulating structures 26a, 26b, and 27 disposed along a second direction (i.e., the y-direction) on a substrate insulating layer 110. As an embodiment, as shown, the first source electrode structure 22a, the first insulating structure 26a, the first drain electrode structure 24a, the inter-element insulating structure 27, the second source electrode structure 22b, the second insulating structure 26b, and the second drain electrode structure 24b may be arranged sequentially along the second direction (i.e., the y-direction). Although in Figure 5 The number of source electrode structures, drain electrode structures, and insulating structures shown in this disclosure is two, but the device contemplated by this disclosure is not necessarily limited to this. In other embodiments, the number of source electrode structures, drain electrode structures, and insulating structures may vary along a second direction (i.e., the y-direction).

[0079] At the same time, refer to Figure 5 The first gate structure 12 and the second gate structure 14, the first ferroelectric layer 312 and the second ferroelectric layer 314, and the first channel layer 322 and the second channel layer 324 can extend on the substrate insulating layer 110 along the second direction (i.e., the y direction) and cover multiple source electrode structures 22a and 22b, multiple drain electrode structures 24a and 24b, and insulating structures 26a, 26b and 27. Figure 6B and Figure 6C The first operation unit 2a shown can correspond to Figure 5 This is part of a non-volatile memory device 2. As an example, the first operating unit 2a may include a first gate structure 12, a first ferroelectric layer 312, a first channel layer 322, a first source electrode structure 22a and a second source electrode structure 22b, a first drain electrode structure 24a and a second drain electrode structure 24b, and insulating structures 26a, 26b, and 27. (See reference...) Figure 5 The second operation unit 2b may correspond to another part of the non-volatile memory device 2. As an example, the second operation unit 2b may include a second gate structure 14, a second ferroelectric layer 314, a second channel layer 324, a first source electrode structure 22a and a second source electrode structure 22b, a first drain electrode structure 24a and a second drain electrode structure 24b, and insulating structures 26a, 26b, and 27. In the following description of the operation method of the non-volatile memory device 2, the first operation unit 2a will be used as an example; however, this method can be applied substantially equivalently to the second operation unit 2b and operation units in other embodiments.

[0080] refer to Figure 5 , Figures 6A to 6C , Figure 6AThe first global source line GSL1 and the first global drain line GDL1 can respectively correspond to Figure 5 , Figure 6B and Figure 6C The first source electrode structure 22a and the first drain electrode structure 24a of the first operation unit 2a are shown. Figure 6A The second global source line GSL2 and the second global drain line GDL2 can respectively correspond to Figure 5 , Figure 6B and Figure 6C The first operating unit 2a shown has a second source electrode structure 22b and a second drain electrode structure 24b. Figure 6A The first global gate line GGL1 can correspond to Figure 5 , Figure 6B and Figure 6C The first gate electrode layer pattern 122a of the first operating unit 2a is shown. Similarly, Figure 6A The second to fourth global gate lines GGL2, GGL3 and GGL4 can respectively correspond to Figure 5 , Figure 6B and Figure 6C The second to fourth gate electrode layer patterns 122b, 122c and 122d of the first operating unit 2a are shown.

[0081] refer to Figure 6A The first to fourth memory cells MC1, MC2, MC3, and MC4 can each be connected to the first global source line GSL1 and the first global drain line GDL1. Similarly, the fifth to eighth memory cells MC5, MC6, MC7, and MC8 can each be connected to the second global source line GSL2 and the second global drain line GDL2. The first memory cell MC1 and the fifth memory cell MC5 can each be connected to the first global gate line GGL1 and can each have a first ferroelectric layer FD1 and a fifth ferroelectric layer FD5. Similarly, the second memory cell MC2 and the sixth memory cell MC6 can each be connected to the second global gate line GGL2 and can each have a second ferroelectric layer FD2 and a sixth ferroelectric layer FD6. The third memory cell MC3 and the seventh memory cell MC7 can each be connected to the third global gate line GGL3 and can each have a third ferroelectric layer FD3 and a seventh ferroelectric layer FD7. The fourth memory cell MC4 and the eighth memory cell MC8 can each be connected to the fourth global gate line GGL4 and can each have a fourth ferroelectric layer FD4 and an eighth ferroelectric layer FD8.

[0082] In the following, as an example of an embodiment, a description will be given for including Figure 5 , Figure 6B and Figure 6CThe write and read operations of the memory cell structure shown are for the fourth gate electrode layer pattern 122d of the first operating unit 2a, the first ferroelectric layer 312, and the eighth portion 322a-8 of the first channel portion 322a. These structures correspond to... Figure 6A The fourth memory cell MC4 of the non-volatile memory device shown is an assembly. Similarly, substantially the same write and read operations can be performed using structures corresponding to the first to third memory cells and the fifth to eighth memory cells MC1, MC2, MC3, MC5, MC6, MC7 and MC8.

[0083] refer to Figure 6C Along the second direction (i.e., the y-direction), the first channel layer 322 may include: a first channel portion 322a disposed between the first source electrode structure 22a and the first drain electrode structure 24a; a second channel portion 322b disposed between the second source electrode structure 22b and the second drain electrode structure 24b; and a third channel portion 322c disposed between the first drain electrode structure 24a and the second source electrode structure 22b. The first to third channel portions 322a, 322b and 322c may include: second portions 322a-2, 322b-2 and 322c-2, which overlap with the first gate electrode layer pattern 122a; fourth portions 322a-4, 322b-4 and 322c-4, which overlap with the second gate electrode layer pattern 122b; sixth portions 322a-6, 322b-6 and 322c-6, which overlap with the third gate electrode layer pattern 122c; and eighth portions 322a-8, 322b-8 and 322c-8, which overlap with the fourth gate electrode layer pattern 122d. Similarly, the first to third channel portions 322a, 322b and 322c may include: first portions 322a-1, 322b-1 and 322c-1 that overlap with the first gate insulating layer pattern 132a; third portions 322a-3, 322b-3 and 322c-3 that overlap with the second gate insulating layer pattern 132b; fifth portions 322a-5, 322b-5 and 322c-5 that overlap with the third gate insulating layer pattern 132c; seventh portions 322a-7, 322b-7 and 322c-7 that overlap with the fourth gate insulating layer pattern 132d; and ninth portions 322a-9, 322b-9 and 322c-9 that overlap with the fifth gate insulating layer pattern 132e.

[0084] At the same time, with targeting Figure 6AThe write operation is related to the fourth memory cell MC4. The fourth global word line GGL4 is selected from the first to fourth global word lines GGL1, GGL2, GGL3, and GGL4. A polarization switching voltage Vs with an amplitude equal to or greater than a predetermined threshold voltage can be applied to the fourth global word line GGL4, and the polarization switching voltage Vs can be applied to the gate electrodes of the fourth memory cell MC4 and the eighth memory cell MC8. The polarization switching voltage Vs is a voltage that enables polarization switching of the fourth ferroelectric layer FD4 of the fourth memory cell MC4 and the eighth ferroelectric layer FD8 of the eighth memory cell MC8. However, in order to perform a write operation only on the fourth memory cell MC4, the first global source line GSL1 and the first global drain line GDL1 can be grounded, and predetermined voltages Vp, whose absolute values ​​are less than the absolute value of the polarization switching voltage Vs, can be applied to the second global source line GSL2 and the second global drain line GDL2, respectively. In this way, the polarization switching voltage Vs is applied only to the fourth ferroelectric layer FD4 of the fourth memory cell MC4, and a voltage corresponding to the difference between the polarization switching voltage Vs and the predetermined voltage Vp can be applied to the eighth ferroelectric layer FD8 of the eighth memory cell MC8. Therefore, when the polarization switching voltage Vs is applied to the global gate line GGL4, the polarization of the fourth ferroelectric layer FD4 of the fourth memory cell MC4 is switched, while the polarization of the eighth ferroelectric layer FD8 of the eighth memory cell MC8 is not switched.

[0085] Write operations used to store the switched polarization in the residual polarization form in the fourth ferroelectric layer FD4 are referenced above. Figures 4A to 4D The write operation of the first ferroelectric layer 312 is essentially the same and will not be repeated here. However, a write operation can be performed on the fourth memory cell MC4 using a similar method.

[0086] The above-mentioned write operation for the fourth storage unit MC4 can also be used Figure 5 and Figure 6BThe corresponding structures 2 and 2a shown are used for explanation. First, a polarization switching voltage Vs is applied to the fourth gate electrode layer pattern 122d corresponding to the fourth global word line GGL4. At this time, the first source electrode structure 22a and the first drain electrode structure 24a corresponding to the first global source line GSL1 and the first global drain line GDL1, respectively, can be grounded. On the other hand, a predetermined voltage Vp with an amplitude smaller than the polarization switching voltage Vs can be applied to the second source electrode structure 22b and the second drain electrode structure 24b corresponding to the second global source line GSL2 and the second global drain line GDL2, respectively. By doing so, the polarization in the first region of the first ferroelectric layer 312 located between the first source electrode structure 22a and the first drain electrode structure 24a along the second direction and in contact with the fourth gate electrode layer pattern 122d can be switched. At the same time, a voltage substantially smaller than the polarization switching voltage Vs is applied to the second region of the first ferroelectric layer 312 located between the second source electrode structure 22b and the second drain electrode structure 24b along the second direction and in contact with the fourth gate electrode layer pattern 122d. Therefore, the polarization in the second region of the first ferroelectric layer 312 is not switched.

[0087] After the polarization switching voltage Vs is removed, the switched polarization can be stored as a residual polarization. The first region of the first ferroelectric layer 312 having the switched polarization can be... Figure 6C The region overlapping with the eighth portion 322a-8 of the first channel portion 322a. The second region of the first ferroelectric layer 312, which does not have the switched polarization, can be with... Figure 6C The area where the eighth part 322b-8 of the second channel section 322b overlaps.

[0088] Simultaneously, the read operation for the residual polarization stored in the fourth memory cell MC4 will be explained. First, in Figure 6AIn this process, the fourth global word line GGL4 is selected. Subsequently, a read voltage Vr, equal to or greater than a predetermined threshold voltage, can be applied to the gate electrode of the fourth memory cell MC4 and the gate electrode of the eighth memory cell MC8 via the fourth global word line GGL4. The absolute value of the read voltage Vr can be less than the absolute value of the polarization switching voltage Vs. That is, the polarization within the fourth ferroelectric layer FD4 and the eighth ferroelectric layer FD8 can be independent of the read voltage Vr. The transistors of the fourth memory cell MC4 and the eighth memory cell MC8 are turned on by the read voltage Vr, and a conductive channel can be formed in the channel layer of the transistor. When a source-drain potential difference is formed between the first global source line GSL1 and the first global drain line GDL1, the source-drain current can flow only through the conductive channel of the fourth memory cell MC4. Because the magnitude of the source-drain current changes according to the orientation of the residual polarization stored in the fourth ferroelectric layer FD4 of the fourth memory cell MC4, the signal information of the residual polarization stored in the fourth memory cell MC4 can be read by measuring the magnitude of the source-drain current. On the other hand, when no potential difference is formed between the second global source line GSL2 and the second global drain line GDL2, the operating current may not flow through the conductive channel of the eighth memory cell MC8.

[0089] The above-mentioned read operation for the fourth storage unit MC4 can also be referred to Figure 5 , Figure 6B and Figure 6C The same approach can be used to explain this. First, a read voltage Vr is applied to the fourth gate electrode layer pattern 122d corresponding to the fourth global word line GGL4. The read voltage Vr forms a conductive channel CH100 in the channel layer 322 overlapping with the fourth gate electrode layer pattern 122d. Subsequently, a source-drain voltage is applied between the first source electrode structure 22a and the first drain electrode structure 24a to create a potential difference, the first source electrode structure 22a and the first drain electrode structure 24a corresponding to the first global source line GSL1 and the first global drain line GDL1, respectively. No potential difference is formed between the second global source line GSL2 and the second global drain line GDL2. As a result, the source-drain current can flow only through the conductive channel CH100 between the first source electrode structure 22a and the first drain electrode structure 24a. A read operation for the fourth memory cell MC4 can be performed by measuring the source-drain current.

[0090] Through the above method, random access can be achieved. Figure 5 , Figure 6B and Figure 6C The first operation unit 2a of the non-volatile storage device 2 performs write and read operations in its storage cell. Figure 5 , Figure 6B and Figure 6CThe write and read operations of the first operation unit 2a of the non-volatile storage device 2 can be applied equally to the second operation unit 2b of the non-volatile storage device 2.

[0091] Figure 7 This is a perspective view schematically showing a non-volatile storage device 3 according to another embodiment of the present disclosure. Figure 8 yes Figure 7 A plan view of a non-volatile storage device. Figure 9 It is along Figure 7 A cross-sectional view of the non-volatile storage device DD′.

[0092] refer to Figures 7 to 9 ,and Figures 1 to 3 Compared to the non-volatile storage device 1, the non-volatile storage device 3 may further include a first interface insulating layer 332 and a second interface insulating layer 334.

[0093] A first interface insulating layer 332 may be disposed between the first ferroelectric layer 312 and the first channel layer 322. One surface of the first interface insulating layer 322 may contact the first ferroelectric layer 312, while the other surface of the first interface insulating layer 332 may contact the first channel layer 322. In one embodiment, the first interface insulating layer 332 may be disposed on a plane substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). The first interface insulating layer 332 may have a predetermined thickness t3 along a third direction (i.e., the x direction). In one embodiment, the thickness t3 of the first interface insulating layer 332 may be less than the thickness t1 of the first ferroelectric layer 312.

[0094] The first interface insulating layer 332 prevents the first ferroelectric layer from directly contacting the first channel layer 322. That is, the first interface insulating layer 332 prevents the formation of defect sites, such as oxygen vacancies, at the interface between the first ferroelectric layer 312 and the first channel layer 322. The first interface insulating layer 332 may have an amorphous structure. The first interface insulating layer 332 may have a lower dielectric constant than the first ferroelectric layer 312. The first interface insulating layer 332 may be non-ferroelectric. For example, the first interface insulating layer 332 may include silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, etc.

[0095] A second interface insulating layer 334 may be disposed between the second ferroelectric layer 314 and the second channel layer 324. One surface of the second interface insulating layer 334 may contact the second ferroelectric layer 314, and the other surface of the second interface insulating layer 334 may contact the second channel layer 324. The second interface insulating layer 334 can prevent the second ferroelectric layer 314 from directly contacting the second channel layer 324.

[0096] The second interface insulating layer 334 may have substantially the same configuration as the first interface insulating layer 332. The second interface insulating layer 334 may have a predetermined thickness t3 along a third direction (i.e., the x-direction).

[0097] Figure 10 This is a perspective view schematically showing a non-volatile storage device 4 according to yet another embodiment of the present disclosure. Figure 11 yes Figure 10 A plan view of a non-volatile storage device. Figure 12 It is along Figure 10 A cross-sectional view of the non-volatile storage device EE′.

[0098] refer to Figures 10 to 12 ,and Figures 7 to 9 Compared to the non-volatile memory device 3, the non-volatile memory device 4 may further include a first floating electrode layer 342 and a second floating electrode layer 344. The first floating electrode layer 342 and the second floating electrode layer 344 may be formed of a conductive material.

[0099] A first floating electrode layer 342 may be disposed between the ferroelectric layer 312 and the first interface insulating layer 332. One surface of the first floating electrode layer 342 may contact the first ferroelectric layer 312, and the other surface of the first floating electrode layer 342 may contact the first interface insulating layer 332. In one embodiment, the first floating electrode layer 342 may be disposed on a plane defined by a first direction and a second direction (i.e., the z-direction and the y-direction). The first floating electrode layer 342 may have a predetermined thickness t4 along a third direction (i.e., the x-direction).

[0100] The first floating electrode layer 342 can remain electrically floating. As an example, the first floating electrode layer 342 is not electrically connected to the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12 and the first channel layer 322. The first floating electrode layer 342 can be charged with positive or negative charges depending on the polarity of the voltage applied to the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d. The charged positive or negative charges can stabilize the residual polarization stored in the first ferroelectric layer 312. Therefore, the presence of the floating electrode layer improves the durability and stability of the residual polarization of the non-volatile memory device 4.

[0101] In another embodiment, the non-volatile memory device includes a first ferroelectric layer 312 having a relatively high dielectric constant, which is electrically connected in series with a first interface insulating layer 332 having a relatively low dielectric constant. When a polarization switching voltage or read voltage is applied to this series connection structure, if the first floating electrode layer 342 is not present, a relatively high voltage can be applied to the first interface insulating layer 332 having a relatively low dielectric constant. Due to the thinness of the first ferroelectric layer 312 and the first interface insulating layer 332, the first interface insulating layer 332 can actually be electrically destroyed. Conversely, when the first floating electrode layer 342 is located between the first ferroelectric layer 312 and the first interface insulating layer 332, the first floating electrode layer 342 can suppress the application of a relatively high voltage to the first interface insulating layer 332, thereby improving the durability and reliability of the non-volatile memory device 4.

[0102] Similarly, a second floating electrode layer 344 may be disposed between the second ferroelectric layer 314 and the second interface insulating layer 334. As an example, the second floating electrode layer 344 is not electrically connected to the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14 and the second channel layer 324. One surface of the second floating electrode layer 344 may contact the second ferroelectric layer 314, while the other surface may contact the second interface insulating layer 334. In one embodiment, the second floating electrode layer 344 may be disposed on a plane substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). The second floating electrode layer 344 may have a predetermined thickness t4 along a third direction (i.e., the x direction). The configuration and function of the second floating electrode layer 344 may be substantially the same as those of the first floating electrode layer 342. In other words, the second floating electrode layer 344 can improve the retention of residual polarization stored in the second floating electrode layer 344 and the durability of the second interface insulating layer 334.

[0103] Figure 13 This is a perspective view schematically showing a non-volatile storage device 5 according to yet another embodiment of the present disclosure. Figure 14 yes Figure 13 A plan view of a non-volatile storage device. Figure 15 It is along Figure 13 A cross-sectional view of the non-volatile storage device taken from line FF′.

[0104] refer to Figures 13 to 15 ,and Figures 7 to 9 Compared to the non-volatile storage device 3, the non-volatile storage device 5 may further include a third interface insulating layer 352 and a fourth interface insulating layer 354.

[0105] A third interface insulating layer 352 may be disposed between the first gate structure 12 and the first ferroelectric layer 312. As an example, one surface of the third interface insulating layer 352 may contact the first gate structure 12, while the other surface may contact the first ferroelectric layer 312. In one embodiment, the third interface insulating layer 352 may be disposed on a plane substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). The third interface insulating layer 352 may have a predetermined thickness t5 along a third direction (i.e., the x direction). In one embodiment, the thickness t5 of the third interface insulating layer 352 may be less than the thickness t1 of the first ferroelectric layer 312.

[0106] The third interface insulating layer 352 prevents the first ferroelectric layer 312 from directly contacting the first gate structure 12. The third interface insulating layer 352 prevents defects from forming at the interfaces between the first ferroelectric layer 312 and the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12. The third interface insulating layer 352 may have an amorphous structure. The third interface insulating layer 352 may have a lower dielectric constant than the first ferroelectric layer 312. The third interface insulating layer 352 may be non-ferroelectric. As an example, the third interface insulating layer 352 may have paraelectric properties. For example, the third interface insulating layer 352 may include silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, etc.

[0107] The third interface insulating layer 352 may be formed of the same material as the first interface insulating layer 332. The thickness t5 of the third interface insulating layer 352 may be substantially the same as the thickness t3 of the first interface insulating layer 332.

[0108] Similarly, a fourth interface insulating layer 354 may be disposed between the second gate structure 14 and the second ferroelectric layer 314. As an example, one surface of the fourth interface insulating layer 354 may contact the second gate structure 14, while the other surface may contact the second ferroelectric layer 314. In one embodiment, the fourth interface insulating layer 354 may be disposed on a plane substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). The fourth interface insulating layer 354 may have a thickness t5 along a third direction (i.e., the x direction). In one embodiment, the thickness t5 of the fourth interface insulating layer 354 may be less than the thickness t1 of the second ferroelectric layer 314.

[0109] The fourth interface insulating layer 354 prevents the second ferroelectric layer 314 from directly contacting the second gate structure 14. The fourth interface insulating layer 354 prevents defects from forming at the interfaces between the second ferroelectric layer 314 and the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14. The fourth interface insulating layer 354 may have an amorphous structure. The fourth interface insulating layer 354 may have a lower dielectric constant than the second ferroelectric layer 314. The fourth interface insulating layer 354 may be non-ferroelectric. As an example, the fourth interface insulating layer 354 may have paraelectric properties. For example, the fourth interface insulating layer 354 may include silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, etc.

[0110] The fourth interface insulating layer 354 can be formed of the same material as the second interface insulating layer 334. The thickness t5 of the fourth interface insulating layer 354 can be substantially the same as the thickness t3 of the second interface insulating layer 334.

[0111] Figure 16 This is a perspective view schematically showing a non-volatile storage device 6 according to yet another embodiment of the present disclosure. Figure 17 yes Figure 16 A plan view of a non-volatile storage device. Figure 18 It is along Figure 16 A cross-sectional view of line GG′ of a non-volatile storage device.

[0112] refer to Figures 16 to 18 ,and Figures 7 to 9 Compared to the non-volatile memory device 3, the non-volatile memory device 6 may differ in the configuration of the first gate structure 1012 and the second gate structure 1014.

[0113] In this embodiment, the first gate structure 1012 may include alternating stacked first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d along a first direction (i.e., the z-direction) and first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e. The second gate structure 1014 may include alternating stacked first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d along a first direction (i.e., the z-direction) and first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e.

[0114] refer to Figure 16 and Figure 18The first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e of the first gate structure 1012 can separate the first ferroelectric layer 1312, the first interface insulating layer 1332, and the first channel layer 1322 relative to a second direction and a third direction (i.e., the y-direction and the x-direction). Therefore, the first ferroelectric layer 1312, the first interface insulating layer 1332, and the first channel layer 1322 can be discontinuously disposed in the first direction. (Referring to the above reference...) Figures 7 to 9 Compared to the described embodiments, the first ferroelectric layer 1312 in this embodiment can be configured to contact a portion of a sidewall surface of the first gate structure 1012 in the lateral direction (i.e., the x-direction), specifically, only the sidewall surfaces of the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d. In other words, the first ferroelectric layer 1312 does not contact the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e in the lateral direction (i.e., the x-direction). Furthermore, the first interface insulating layer 1332 and the first channel layer 1322 can be sequentially arranged in the lateral direction starting from the first ferroelectric layer 1312, and can be arranged between the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e.

[0115] refer to Figures 16 to 18 , and the above reference Figures 7 to 9 Compared to the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 132d, and 1132e in the described embodiments, the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e can be configured to directly contact the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In this embodiment, the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, and 1132e can more effectively achieve electrical insulation between the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, and 1122d in the first direction (i.e., the z-direction).

[0116] Similarly, refer to Figure 16 and Figure 18 The first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e of the second gate structure 1014 can separate the second ferroelectric layer 1314, the second interface insulating layer 1334, and the second channel layer 1324 from each other with respect to the second direction and the third direction (i.e., the y-direction and the x-direction). Therefore, the second ferroelectric layer 1314, the second interface insulating layer 1334, and the second channel layer 1324 can be discontinuously disposed in the first direction (i.e., the z-direction). Therefore, in conjunction with the above reference... Figures 7 to 9 Compared to the described embodiments, the second ferroelectric layer 1314 in this embodiment can be configured to contact a portion of a sidewall surface of the second gate structure 1014 in the lateral direction (i.e., the x-direction), specifically, only the sidewall surfaces of the first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d. In other words, the second ferroelectric layer 1314 does not contact the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e in the lateral direction (i.e., the x-direction).

[0117] refer to Figure 16 and Figure 18 , and the above reference Figures 7 to 9 Compared to the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 134d, and 1134e in the described embodiment, the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e can be configured to directly contact the source electrode structure 22, the drain electrode structure 24, and the insulating structure 26. In this embodiment, the first to fifth gate insulating layer patterns 1134a, 1134b, 1134c, 1134d, and 1134e can more effectively achieve electrical insulation between the first to fourth gate electrode layer patterns 1124a, 1124b, 1124c, and 1124d in the first direction (i.e., the z-direction).

[0118] Simultaneously, the first to fourth gate electrode layer patterns 1122a, 1122b, 1122c, 1122d, 1124a, 1124b, 1124c, and 1124d of the first gate structure 1012 and the second gate structure 1014, the first ferroelectric layer 1312 and the second ferroelectric layer 1314, the first interface insulating layer 1332 and the second interface insulating layer 1334, the first channel layer 1322 and the second channel layer 1324, and the first to fifth gate insulating layer patterns 1132a, 1132b, 1132c, 1132d, 1132e, 1134a, 1134b, 1134c, 1134d, and 1124d are also present. The material properties and functions of 134e are substantially the same as those of the first to fourth gate electrode layer patterns 122a, 122b, 122c, 122d, 124a, 124b, 124c and 124d of the first gate structure 12 and the second gate structure 14, the first ferroelectric layer 312 and the second ferroelectric layer 314, the first interface insulating layer 332 and the second interface insulating layer 334, the first channel layer 322 and the second channel layer 324, and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, 132e, 134a, 134b, 134c, 134d and 134e.

[0119] Figure 19This is a perspective view schematically illustrating a non-volatile storage device 7 according to a further embodiment of the present disclosure. Figure 20 yes Figure 19 A plan view of a non-volatile storage device. Figure 21 It is along Figure 19 A cross-sectional view of line HH′ of a non-volatile storage device.

[0120] refer to Figures 19 to 21 ,and Figures 10 to 12 Compared to the non-volatile memory device 4, the non-volatile memory device 7 may differ in the configuration of the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314, the first floating electrode layer portion 2342 and the second floating electrode layer portion 2344, and the first gate structure 2012 and the second gate structure 2014.

[0121] The first gate structure 2012 may include first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d and first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, and 2132e, alternately stacked on the substrate insulating layer 110 along a first direction (i.e., the z-direction). The first gate structure 2012 may extend in a second direction (i.e., the y-direction).

[0122] The first interface insulating layer 332 may be disposed on a sidewall surface S7 of the first gate structure 2012. That is, the first interface insulating layer 332 may be configured to cover a sidewall surface S7 of the first gate structure 2012. A sidewall surface S7 is a plane formed substantially parallel to the first and second directions (i.e., a yz plane parallel to the z and y directions). In a particular embodiment, the first interface insulating layer 332 may be configured to contact the first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, and 2132e, and the first floating electrode layer portion 2342.

[0123] Additionally, the first channel layer 322 can be configured to contact the first interface insulating layer 332. The first channel layer 322 can be disposed on a plane substantially parallel to the first direction and the second direction (i.e., a yz plane parallel to the z and y directions).

[0124] refer to Figure 21The first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d of the first gate structure 2012 may each have a first floating electrode layer portion 2342, a first ferroelectric layer portion 2312, and a first gate electrode layer portion 2122. As an example, in the first gate functional layer pattern 2112a, the first floating electrode layer portion 2342 may be disposed on the first interface insulating layer 332 and the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b. Starting from the first interface insulating layer 332 in the x-direction and from the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b in the z-direction, the first floating electrode layer portion 2342 may each have a predetermined thickness t6. The first ferroelectric layer portion 2312 may be disposed on the first floating electrode layer portion 2342 and the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b. The first ferroelectric layer portion 2312 may have a predetermined thickness t7 on the first floating electrode layer portion 2342. The first gate electrode layer portion 2122 may be configured to contact or cover the first ferroelectric layer portion 2312 between the first gate insulating layer pattern 2132a and the second gate insulating layer pattern 2132b.

[0125] Regarding the second gate functional layer pattern 2112b, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the second gate insulating layer pattern 2132b and the third gate insulating layer pattern 2312c and contact the first interface insulating layer 332 in substantially the same manner. As another example, for the third gate functional layer pattern 2112c, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the third gate insulating layer pattern 2132c and the fourth gate insulating layer pattern 2132d and contact the first interface insulating layer 332 in substantially the same manner. Regarding the fourth gate functional layer pattern 2112d, the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 can be disposed between the fourth gate insulating layer pattern 2132d and the fifth gate insulating layer pattern 2132e and contact the first interface insulating layer 332 in substantially the same manner.

[0126] refer to Figures 19 to 21 The source electrode structure 22, drain electrode structure 24, and insulating structure 26 can be disposed on the substrate insulating layer 110 to contact the first channel layer 322. Furthermore, the second channel layer 324 can be disposed on the substrate insulating layer 110 to contact one sidewall surface of each of the source electrode structure 22, drain electrode structure 24, and insulating structure 26. Additionally, the second interface insulating layer 334 can be configured to contact the second channel layer 324.

[0127] On the substrate insulating layer 110, the second gate structure 2014 can be configured to contact the second interface insulating layer 334. The second gate structure 2014 may include first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d and first to fifth gate insulating layer patterns 2134a, 2134b, 2134c, 2134d, and 2134e alternately stacked on the substrate insulating layer 110 along a first direction (i.e., the z-direction). The second gate structure 2014 may extend in a second direction (i.e., the y-direction).

[0128] The first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d of the second gate structure 2014 may each have a second floating electrode layer portion 2344, a second ferroelectric layer portion 2314, and a second gate electrode layer portion 2124. The configuration of the second floating electrode layer portion 2344, the second ferroelectric layer portion 2314, and the second gate electrode layer portion 2124 of the second gate structure 2014 may be substantially the same as the configuration of the first floating electrode layer portion 2342, the first ferroelectric layer portion 2312, and the first gate electrode layer portion 2122 of the first gate structure 2012.

[0129] When the non-volatile storage device 7 according to the above embodiment is combined with Figures 10 to 12 When comparing with the non-volatile memory device 4, in the first to fourth gate functional layer patterns 2112a, 2112b, 2112c, and 2112d of the first gate structure 2012 and the first to fourth gate functional layer patterns 2114a, 2114b, 2114c, and 2114d of the second gate structure 2014, the contact areas of the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 with the first gate electrode layer portion 2122 and the second gate electrode layer portion 2124, respectively, can be increased. Furthermore, the contact areas of the first floating electrode layer portion 2342 and the second floating electrode layer portion 2344 with the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 can be increased. As a result, by increasing the area of ​​the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314 used as storage layers, the density of residual polarization stored in the ferroelectric layer portions 2313 and 2314 can be increased. Consequently, the reliability of memory operations can be improved.

[0130] Meanwhile, the material properties and functions of the first gate electrode layer portion 2122 and the second gate electrode layer portion 2124, the first ferroelectric layer portion 2312 and the second ferroelectric layer portion 2314, the first floating electrode layer portion 2342 and the second floating electrode layer portion 2344, and the first to fifth gate insulating layer patterns 2132a, 2132b, 2132c, 2132d, 2132e, 2134a, 2134b, 2134c, 2134d and 2134e of the first gate structure 2012 and the second gate structure 2014 are respectively the same as those of the above reference. Figures 10 to 12 The material properties and functions of the first to fourth gate electrode layer patterns 122a, 122b, 122c, 122d, 124a, 124b, 124c and 124d, the first ferroelectric layer 312 and the second ferroelectric layer 314, the first floating electrode layer 342 and the second floating electrode layer 344, and the first to fifth gate insulating layer patterns 132a, 132b, 132c, 132d, 132e, 134a, 134b, 134c, 134d and 134e of the first gate structure 12 and the second gate structure 14 in the described embodiments are substantially the same.

[0131] Figure 22 This is a schematic perspective view of a non-volatile storage device 8 according to a further embodiment of the present disclosure. Figure 23 yes Figure 22 A plan view of a non-volatile storage device. Figure 24 It is along Figure 22 A cross-sectional view of line II′ of a non-volatile storage device.

[0132] refer to Figures 22 to 24 ,and Figures 1 to 3 Compared to the non-volatile memory device 1, the non-volatile memory device 8 differs in the configuration of the channel structure 28.

[0133] In this embodiment, the channel structure 28 replaces Figures 1 to 3 The insulating structure 26 in the non-volatile memory device 1. That is, the channel structure 28 can be configured to contact the source electrode structure 22 and the drain electrode structure 24 in the second direction (i.e., the y-direction). Furthermore, the channel structure 28 can be configured to contact the first ferroelectric layer 312 and the second ferroelectric layer 314 in the third direction (i.e., the x-direction). Therefore, the insulating structure 26 in the non-volatile memory device 8 of this embodiment is omitted. Figures 1 to 3 The first channel layer 322 and the second channel layer 324 of the non-volatile memory device 1.

[0134] The channel structure 28 may have a columnar shape extending in a first direction (i.e., the z-direction) starting from the substrate insulating layer 110. When a read voltage is applied to at least one of the first to fourth gate electrode layer patterns 122a, 122b, 122c, and 122d of the first gate structure 12, a conductive channel may be formed in the region of the channel structure 28 that overlaps with the at least one gate electrode layer pattern. Similarly, when a read voltage is applied to at least one of the first to fourth gate electrode layer patterns 124a, 124b, 124c, and 124d of the second gate structure 14, a conductive channel may be formed in the region of the channel structure 28 that overlaps with the at least one gate electrode layer pattern.

[0135] For example, the channel structure 28 may include a doped semiconductor material or a metal oxide. For example, the semiconductor material may include silicon (Si), germanium (Ge), and gallium arsenide (GaAs). The metal oxide may include indium gallium zinc (In-Ga-Zn) oxide. In one embodiment, the channel structure 28 may include silicon (Si) doped with an n-type dopant. Alternatively, the channel structure 28 may include c-axis aligned indium gallium zinc (In-Ga-Zn) oxide. The channel structure 28 may have a single-crystal structure or a polycrystalline structure.

[0136] As described above, the non-volatile storage device 8 of this embodiment may include a cylindrical channel structure 28. This is achieved by using the channel structure 28 instead of... Figures 1 to 3 The insulating structure 26 of the non-volatile memory device 1 simplifies the device structure and manufacturing process.

[0137] In other embodiments, in Figure 5 In the non-volatile memory device 2, a non-volatile memory device in which the insulating structures 26a and 26b are replaced by the channel structure 28 of this embodiment can be implemented, while omitting the first channel layer 322 and the second channel layer 324. Similarly, in Figures 7 to 9 3. Non-volatile storage devices Figures 10 to 12 4. Non-volatile storage devices Figures 13 to 15 Non-volatile memory devices 5 and Figures 19 to 21 In the non-volatile memory device 7, a non-volatile memory device in which the insulating structure 26 is replaced by the channel structure 28 of this embodiment can be implemented. In these embodiments, the first channel layer 322 and the second channel layer 324 can be omitted. Furthermore, in Figures 16 to 18 In the non-volatile memory device 6, a non-volatile memory device in which the insulating structure 26 is replaced by the channel structure 28 of this embodiment can be implemented, while omitting Figures 16 to 18 The first channel layer 1322 and the second channel layer 1324 of the non-volatile memory device 6.

[0138] The embodiments of the inventive concept have been disclosed above for illustrative purposes. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of the inventive concept disclosed in the appended claims.

Claims

1. A non-volatile storage device, comprising: A substrate having an upper surface; A gate structure disposed above the substrate, the gate structure comprising at least one gate electrode layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface, wherein the gate structure extends in a second direction perpendicular to the first direction; A ferroelectric layer is disposed on at least a portion of a sidewall surface of the gate structure, wherein the sidewall surface of the gate structure forms a plane substantially parallel to the first direction and the second direction; A source electrode structure and a drain electrode structure, spaced apart from each other in the second direction, are each disposed above the substrate and on the ferroelectric layer; and A channel structure is disposed above the substrate and between the source electrode structure and the drain electrode structure; The non-volatile storage device further includes conductive channels formed in some portions of the channel structure; The conductive channel extends along the second direction to electrically connect the source electrode structure and the drain electrode structure over the substrate; Wherein, the ferroelectric layer is separated by the gate insulating layer pattern in the first direction, and The ferroelectric layer is discontinuously disposed along one sidewall surface of the gate structure in the first direction.

2. The non-volatile storage device according to claim 1, further comprising: A substrate insulating layer is disposed on the substrate to contact the gate structure, the ferroelectric layer, the source electrode structure, the drain electrode structure and the channel structure in the first direction.

3. The non-volatile storage device according to claim 1, wherein, The channel structure has a column shape extending along the first direction.

4. The non-volatile storage device according to claim 1, wherein, The channel structure contacts the source electrode structure and the drain electrode structure in the second direction, and contacts the ferroelectric layer in a third direction perpendicular to the first and second directions.

5. The non-volatile storage device according to claim 1, further comprising: A non-ferroelectric first interface insulating layer is disposed above the substrate and between the ferroelectric layer and the channel structure.

6. The non-volatile storage device according to claim 1, further comprising: A non-ferroelectric second interface insulating layer is disposed above the substrate and between the gate structure and the ferroelectric layer.

7. The non-volatile storage device according to claim 1, further comprising: A floating electrode layer is disposed between the ferroelectric layer and the first interface insulating layer.

8. A non-volatile storage device, comprising: A substrate having an upper surface; A gate structure disposed above the substrate, the gate structure comprising at least one gate functional layer pattern and at least one gate insulating layer pattern alternately stacked along a first direction perpendicular to the upper surface, wherein the gate structure extends in a second direction perpendicular to the first direction; An interface insulating layer and a channel layer are sequentially disposed on a sidewall surface of the gate structure, wherein the sidewall surface of the gate structure is a plane defined by the first direction and the second direction; and The source electrode structure and the drain electrode structure are spaced apart from each other in the second direction, and each is disposed above the substrate and in contact with the channel layer. The gate functional layer pattern includes: The floating electrode layer portion is disposed on the pattern of the interface insulating layer and the gate insulating layer; The ferroelectric layer portion is disposed on the floating electrode layer portion and the interface insulating layer; and The gate electrode layer portion is configured to contact the ferroelectric layer portion. The non-volatile memory device further includes conductive channels formed in some portions of the channel configuration; The conductive channel extends along the second direction to electrically connect the source electrode structure and the drain electrode structure over the substrate; Wherein, the floating electrode layer portion and the ferroelectric layer portion are respectively separated by the gate insulating layer pattern in the first direction, and The floating electrode layer portion and the ferroelectric layer portion are discontinuously disposed along one sidewall surface of the gate structure in the first direction.

9. The non-volatile storage device according to claim 8, wherein, The interface insulating layer is configured to contact the gate insulating layer pattern and the floating electrode layer portion.

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