Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming at least two grids on the substrate; a patterned first mask layer is formed on the grid electrodes and the substrate, the patterned first mask layer defines a first injection window, and the first injection window exposes the surface of the substrate between the two grid electrodes, the opposite side walls of the two grid electrodes and part of the top surfaces; performing first ion implantation on the substrate to form a first doped region in the substrate; a patterned second mask layer is formed, the first mask layer, the exposed grid electrodes and part of the surface of the substrate are covered with the patterned second mask layer, a second injection window is defined by the patterned second mask layer, the part, between the two grid electrodes, of the surface of the substrate is exposed out of the second injection window, and the patterned first mask layer and the patterned second mask layer are formed through the same mask plate; second ion implantation is carried out on the substrate to form a second doped region in the substrate, and the depth of the first doped region in the substrate is smaller than that of the second doped region in the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] With the continuous development of integrated circuit technology, Lateral Double-Diffused Metal-Oxide Semiconductor Transistor (LDMOS) is widely used in power integrated circuits due to its high breakdown voltage and good compatibility with CMOS process. When preparing an LDMOS device based on a Bipolar-CMOS-DMOS (BCD) process, a complex doping structure usually needs to be constructed on the same substrate to balance the withstand voltage, conduction characteristics and reliability. Among them, the P-type body region (PBODY) as a key structure of the LDMOS device is used to connect the source and the substrate, and is responsible for forming a channel conduction path. The doping concentration, junction depth and spatial distribution of the P-type body region determine the electrical characteristics of the device, such as threshold voltage (V t ), drain current, latch-up resistance and hot carrier injection (HCI) reliability, etc.

[0003] In related technologies, ion implantation of the P-type body region usually adopts the following process flow: first, a patterned photoresist layer is formed on the substrate and the gate, and two times of ion implantation are performed on the substrate with the patterned photoresist layer as a mask; then, the photoresist layer is trimmed by a trimming process to adjust the subsequent implantation area; finally, two times of ion implantation are performed again on the substrate with the trimmed photoresist layer as a mask. However, in the trimming process, due to uneven plasma distribution or photoresist fluctuation, the Critical Dimension (CD) uniformity of the ion implantation window is poor, especially the CD at the wafer edge region is significantly smaller, and the exposed gate region presents an asymmetric morphology, which causes uneven ion implantation distribution, not only causing threshold voltage drift, hot carrier injection (HCI) reliability deterioration, but also exacerbating latch-up effect and source-drain punch-through risk, seriously affecting the consistency of device electrical performance and yield.

[0004] Therefore, it is necessary to make improvements to at least partially solve the above problems. SUMMARY

[0005] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiments section. The summary section of the present application is not intended to attempt to define the key features and essential technical features of the claimed technical solutions, nor is it intended to determine the protection scope of the claimed technical solutions.

[0006] To solve the existing problems, one aspect of the present application provides a semiconductor device manufacturing method, comprising: providing a substrate, at least two gates being formed on the substrate and being arranged at intervals; forming a patterned first mask layer on the gates and the substrate, the patterned first mask layer defining at least one first implantation window, each first implantation window exposing the substrate surface between adjacent two gates, the side walls of the adjacent two gates opposite to each other, and part of the top surface adjacent to the side walls; performing first ion implantation on the substrate through the first implantation window with the patterned first mask layer as a mask, to form a first doped region in the substrate; forming a patterned second mask layer covering the patterned first mask layer and part of the exposed gates and substrate surface, the patterned second mask layer defining a second implantation window exposing part of the substrate surface between two gates, wherein the patterned first mask layer and the patterned second mask layer are formed by using the same mask plate, and an overexposure process is used when forming the patterned first mask layer; performing second ion implantation on the substrate through the second implantation window with the patterned second mask layer as a mask, to form a second doped region in the substrate, wherein the depth of the first doped region in the substrate is less than the depth of the second doped region in the substrate.

[0007] Exemplarily, after forming the first doped region and before forming the second doped region, the method further comprises: performing third ion implantation on the substrate through the first implantation window with the patterned first mask layer as a mask, to form a third doped region in the first doped region, wherein the depth of the third doped region in the substrate is less than the depth of the first doped region in the substrate.

[0008] Exemplarily, after forming the second doped region, the method further comprises: performing fourth ion implantation on the substrate through the second implantation window with the patterned second mask layer as a mask, to form a fourth doped region in the second doped region, wherein the depth of the fourth doped region in the substrate is less than the depth of the second doped region in the substrate and greater than the depth of the first doped region in the substrate.

[0009] Exemplarily, the first mask layer is a first photoresist layer, and the second mask layer is a second photoresist layer, wherein an exposure energy for exposing the first photoresist layer is less than an exposure energy for exposing the second photoresist layer when forming the patterned first mask layer and the patterned second mask layer; and after forming the fourth doped region, the patterned first mask layer and the patterned second mask layer are removed.

[0010] Exemplarily, an implantation energy of the third ion implantation is less than an implantation energy of the first ion implantation, the implantation energy of the first ion implantation is less than an implantation energy of the fourth ion implantation, and the implantation energy of the fourth ion implantation is less than an implantation energy of the second ion implantation; an implantation dose of the first ion implantation is less than an implantation dose of the third ion implantation, the implantation dose of the fourth ion implantation is less than the implantation dose of the first ion implantation, and the implantation dose of the second ion implantation is less than the implantation dose of the fourth ion implantation.

[0011] Exemplarily, an ion conductivity type of the first ion implantation, the second ion implantation and the fourth ion implantation is different from an ion conductivity type of the third ion implantation.

[0012] Exemplarily, an ion type of the first ion implantation, the second ion implantation and the fourth ion implantation is P-type ion, and an ion type of the third ion implantation is N-type ion.

[0013] Exemplarily, a thickness of the first mask layer is less than or equal to 5000 Å, and a thickness of the second mask layer is greater than or equal to 25000 Å.

[0014] Exemplarily, before forming the gate, the method further comprises: forming a barrier layer on the substrate.

[0015] Another aspect of the present application provides a semiconductor device obtained by the above method.

[0016] The semiconductor device and the preparation method thereof provided by the present application can realize ion implantation windows with two different sizes without process adjustment by sequentially forming the patterned first mask layer and the patterned second mask layer by using the same mask plate, avoid non-uniformity of a key size of the ion implantation window and asymmetry of gate exposure, improve the implantation uniformity of the wafer edge, improve the electrical performance and yield of the device, and reduce the process cost and complexity. BRIEF DESCRIPTION OF DRAWINGS

[0017] The following drawings of the present application are hereby included as a part of the present application for understanding the present application. The embodiments of the present application and the description thereof shown in the drawings are used to explain the principles of the present application.

[0018] In the drawings: Figures 1A-1D A flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application is shown; Figure 2 A flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application is shown; Figures 3A-3D A flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The present application will be described in more detail by referring to the drawings, in which embodiments of the application are shown. The application can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0020] It should be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0021] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] For a thorough understanding of the present application, reference will be made to the following detailed description, in conjunction with the accompanying drawings, in which:

[0024] In the related art, as shown in FIG. 1, the ion implantation of the P-type body region is usually implemented by using a multi-step ion implantation combined with photoresist trimming to realize the doping structures with different depths and functions. Specifically, as shown in FIG. 2, a photoresist is first spin-coated on the substrate 10 and the gate 11, and then exposed and developed through a mask plate to form a patterned photoresist layer 12 covering the gate 11 and part of the surface of the substrate 10. The substrate 10 is then subjected to two ion implantations in sequence with the patterned photoresist layer 12 as a mask to form a well region 13 and a punch-through prevention region 14, as shown in FIG. 3. Next, a trimming process is performed on the photoresist layer 12 to adjust the subsequent implantation area. Finally, the substrate 10 is subjected to two ion implantations in sequence again with the trimmed photoresist layer 12 as a mask to form a threshold voltage adjustment region 15 and a reverse-type doped region 16. Figures 1A-1D Figure 1A Figure 1B Figure 1C ​​​and Figure 1D As shown, due to uneven plasma distribution or photoresist fluctuations, the uniformity of the critical dimension (CD) of the adjusted ion implantation window is poor, especially in the wafer edge region where the CD is significantly smaller. Figure 1C The ion implantation window shown is small in critical size, and the exposed gate region often exhibits an asymmetric morphology. Figure 1D The gate exposure asymmetry shown leads to uneven ion implantation distribution, which in turn causes source-drain punch-through risk, seriously affecting the electrical performance and yield of the device.

[0025] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps: Step S1: Provide a substrate and form at least two gates spaced apart on the substrate; Step S2: A patterned first mask layer is formed on the gate and the substrate. The patterned first mask layer defines at least one first injection window. Each first injection window exposes the substrate surface between two adjacent gates, the sidewalls of the two adjacent gates facing each other, and a portion of the top surface adjacent to the sidewalls. Step S3: Using the patterned first mask layer as a mask, perform first ion implantation on the substrate through the first implantation window to form a first doped region in the substrate; Step S4: Form a patterned second mask layer covering the patterned first mask layer, the exposed gate, and a portion of the substrate surface. The patterned second mask layer defines a second injection window, which exposes a portion of the substrate surface between the two gates. The patterned first mask layer and the patterned second mask layer are formed using the same mask. An overexposure process is used when forming the patterned first mask layer. Step S5: Using the patterned second mask layer as a mask, perform second ion implantation on the substrate through the second implantation window to form a second doped region in the substrate, wherein the depth of the first doped region in the substrate is less than the depth of the second doped region in the substrate.

[0026] The semiconductor device and its fabrication method in this application embodiment, by using the same mask to sequentially form a patterned first mask layer and a patterned second mask layer, can realize two different sizes of ion implantation windows without process adjustment, avoiding the problems of uneven critical dimensions of ion implantation windows and asymmetric gate exposure, improving the implantation uniformity of wafer edge regions, enhancing the electrical performance and yield of the device, and reducing process costs and complexity.

[0027] Example 1 Below, for reference Figure 2 as well as Figures 3A-3DThe method for fabricating the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 3A-3D The diagram shows a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0028] For example, the method for fabricating the semiconductor device of this application includes the following steps: First, step S1 is performed, providing a substrate on which at least two gates are formed at intervals.

[0029] In one example, such as Figure 3A As shown, a substrate 20 is provided, and the material of the substrate 20 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form the substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention.

[0030] Exemplarily, before forming the gate 21, a barrier layer 201 is formed on the surface of the substrate 20. This barrier layer 201 can be formed using processes including, but not limited to, thermal oxidation or chemical vapor deposition (CVD). The material of the barrier layer 201 includes, but is not limited to, silicon oxide. The barrier layer 201 serves to protect the surface of the substrate 20 during subsequent ion implantation processes. In other examples, the barrier layer may not be formed; this is not specifically limited.

[0031] In one example, such as Figure 3AAs shown, at least two gates 21 are formed on the substrate 20 at intervals. The specific steps for forming the gates 21 include: sequentially forming a gate dielectric layer and a gate material layer on the surface of the barrier layer 201; forming a patterned photoresist layer on the surface of the gate material layer, the patterned photoresist layer defining the shape and position of the gates; and etching the gate material layer and the gate dielectric layer using the patterned photoresist layer as a mask to form at least two gates 21 at intervals. The gate dielectric layer can be formed using methods including, but not limited to, thermal oxidation, and the material of the gate dielectric layer includes, but is not limited to, silicon dioxide; the gate material layer can be formed using processes including, but not limited to, low-pressure chemical vapor deposition (LPCVD), and the material of the gate material layer includes, but is not limited to, polysilicon; the etching of the gate dielectric layer and the gate material layer can be performed using dry etching, such as reactive ion etching (RIE), ion beam etching, or plasma etching; the two gates 21 are spaced apart in a direction parallel to the substrate surface.

[0032] After forming the gate 21, a sidewall can also be formed on the sidewall of each gate 21. The sidewall covers the sidewall surface of the gate 21 to protect the gate sidewall from damage in subsequent processes.

[0033] Next, step S2 is performed to form a patterned first mask layer on the gate and the substrate. The patterned first mask layer defines at least one first injection window. Each first injection window exposes the substrate surface between two adjacent gates, the sidewalls of the two adjacent gates facing each other, and a portion of the top surface adjacent to the sidewalls.

[0034] In one example, such as Figure 3A As shown, a patterned first mask layer 22 is formed on the gate 21 and the substrate 20 using a mask. The patterned first mask layer 22 defines at least one first injection window 23. Each first injection window 23 exposes the surface of the substrate 20 between two adjacent gates 21, the sidewalls of the two adjacent gates 21 facing each other, and a portion of the top surface adjacent to the sidewalls. Specifically, photoresist material is spin-coated onto the barrier layer 201 and the gate 21 as a first photoresist layer. The first mask layer is the first photoresist layer, and the first photoresist layer is exposed and developed using a mask with a predetermined pattern to form the patterned first mask layer 22, which defines the first injection window 23. During the formation of the patterned first mask layer 22, an overexposure process is used, for example, by adjusting the photolithography focal length to enhance the lateral exposure effect of the first photoresist layer, thereby defining a first injection window 23 with a larger CD.

[0035] In this embodiment, the first implantation window 23 exposes the surface of the barrier layer 201 between two adjacent gates 21, the sidewalls of the two adjacent gates 21 facing each other, and the portion of the top surface adjacent to the sidewalls. In other examples, when there is no barrier layer 201, a patterned first mask layer 22 is directly formed on the surface of the substrate 20 and the gates 21. Its first implantation window 23 directly exposes the surface of the substrate 20 between two adjacent gates 21, the sidewalls of the two adjacent gates 21 facing each other, and the portion of the top surface adjacent to the sidewalls, making subsequent ion implantation more accurate and effective, effectively avoiding one-sided effects. It is worth noting that when sidewalls are formed on the sidewalls of the gates 21, the exposure of the opposing sidewalls of the two gates 21 is also referred to as exposing the opposing sidewalls.

[0036] Continuing, step S3 is executed, using the patterned first mask layer as a mask, and performing first ion implantation on the substrate through the first implantation window to form a first doped region in the substrate.

[0037] In one example, such as Figure 3B As shown, using a patterned first mask layer 22 as a mask, first ion implantation is performed on the substrate 20 through the first implantation window 23. The implantation energy and implantation dose of the first ion implantation can be set according to process requirements and are not specifically limited. The first ion implantation forms a first doped region 24 with shallow junctions in the substrate 20 below the edge of the gate 21 and between the two gates 21. This first doped region is located near the surface of the channel region of the device. By increasing the doping concentration on the surface of the channel region, precise control of the device threshold voltage can be achieved.

[0038] In one example, such as Figure 3BAs shown, after forming the first doped region 24 and before forming the second doped region, the process further includes: using a patterned first mask layer 22 as a mask, performing third ion implantation on the substrate 20 through a first implantation window 23 to form a third doped region 25 in the first doped region 24, wherein the depth of the third doped region 25 in the substrate 20 is less than the depth of the first doped region 24 in the substrate 20. Specifically, continuing to use the patterned first mask layer 22 as a mask, performing third ion implantation on the substrate 20 to form the third doped region 25 in the surface region of the first doped region 24, its depth in the substrate 20 being less than the depth of the first doped region 24 in the substrate 20, thus constituting an ultra-shallow doped structure. Exemplarily, the implantation energy of the third ion implantation is less than the implantation energy of the first ion implantation to ensure that the impurity distribution is concentrated on the substrate surface below the gate edge, the implantation dose of the first ion implantation is less than the implantation dose of the third ion implantation, and the ion type of the third ion implantation is different from the ion type of the first ion implantation. For example, when the first ion implantation uses P-type doped ions (e.g., boron ions), the third ion implantation can use N-type doped ions (e.g., arsenic ions). This third doped region effectively reduces the peak electric field intensity near the drain, lowering the probability of hot carrier generation and thus significantly improving the reliability of hot carrier injection (HCI) of the device. Since this third doped region is extremely shallow and located on the local surface of the first doped region 24 (used to control the threshold voltage), it does not affect the threshold voltage characteristics set by the first doped region 24, maintaining the stability of the threshold voltage while improving HCI performance.

[0039] Then, step S4 is performed to form a patterned second mask layer that covers the patterned first mask layer, the exposed gate, and a portion of the substrate surface. The patterned second mask layer defines a second injection window that exposes a portion of the substrate surface between the two gates. The patterned first mask layer and the patterned second mask layer are formed using the same mask.

[0040] In one example, such as Figure 3C As shown, a patterned second mask layer 26 is formed on the patterned first mask layer 22, the gate 21, and a portion of the substrate 20. The patterned second mask layer 26 defines a second implantation window 27, which is smaller than the first implantation window 23. The second implantation window 27 exposes a portion of the substrate 20 surface between the two gates 21. Specifically, on the structure where the first and third ion implantations have been completed, the patterned first mask layer 22 is retained, and photoresist material is re-spin-coated directly onto its surface, the exposed gate top and sidewalls, and a portion of the substrate surface as a second photoresist layer. The second mask layer is the second photoresist layer. Subsequently, the second photoresist layer is exposed and developed using the same mask as the one used to form the patterned first mask layer 22, thereby forming the patterned second mask layer 26.

[0041] For example, when forming the patterned first mask layer 22 and the patterned second mask layer 26, the exposure energy used to expose the first photoresist layer is less than the exposure energy used to expose the second photoresist layer. Since the thickness of the second mask layer 26 (i.e., the second photoresist layer) is greater than the thickness of the first mask layer 22 (i.e., the first photoresist layer), in order to ensure that the exposure light can penetrate the thicker second photoresist layer, the exposure energy applied to the second photoresist layer is greater than the exposure energy applied to the first photoresist layer.

[0042] The second implantation window 27 is located between the two gates 21, exposing a portion of the substrate 20 surface between the two gates 21. The two gates 21 and the adjacent area are still covered by the patterned second mask layer 26. This process eliminates the need for a trimming step and achieves self-alignment definition of two different sized implantation windows using only a single mask and two different photolithography processes, providing precise masking for subsequent ion implantation.

[0043] In one example, the thickness of the second mask layer 26 is greater than the thickness of the first mask layer 22. For example, the thickness of the first mask layer 22 is less than or equal to 5000 Å, and the thickness of the second mask layer 26 is greater than or equal to 25000 Å. For example, the thickness of the first mask layer is 5000 Å, 4000 Å, 3500 Å, 3000 Å, or 2000 Å, and the thickness of the second mask layer is 25000 Å, 30000 Å, 35000 Å, 40000 Å, or 45000 Å, etc., without specific limitation.

[0044] Finally, step S5 is executed, using the patterned second mask layer as a mask, and performing second ion implantation on the substrate through the second implantation window to form a second doped region in the substrate, wherein the depth of the first doped region in the substrate is less than the depth of the second doped region in the substrate.

[0045] In one example, such as Figure 3D As shown, using a patterned second mask layer 26 as a mask, a second ion implantation is performed on the substrate 20 through a second implantation window 27 to form a second doped region 28 in the substrate 20. Exemplarily, after completing the first and third ion implantations and forming the patterned second mask layer 26, a second ion implantation is performed on the substrate 20 using the patterned second mask layer 26 as a mask through the second implantation window 27. The ion type of the second ion implantation is the same as that of the first ion implantation, but the ion type of the second ion implantation is different from that of the third ion implantation. For example, the second and first ion implantations may use P-type doped ions (e.g., boron ions), and the third ion implantation may use N-type doped ions (e.g., arsenic ions).

[0046] For example, the implantation energy of the second ion implantation is greater than that of the first and third ions, and the implantation energy of the second ion implantation is also greater than that of the subsequent fourth ion implantation, without specific limitation. The implantation dose of the second ion implantation is less than that of the first and third ions, and the implantation dose of the second ion implantation is also less than that of the subsequent fourth ion implantation, without specific limitation. By forming a relatively deep second doped region 28 in the substrate 20 through the second ion implantation, the depth of the first doped region 24 in the substrate 20 is less than the depth of the second doped region 28 in the substrate 20. The second doped region 28 is located in the substrate between the two gates 21. By increasing the doping concentration of the well region, the base resistance of the parasitic bipolar transistor is reduced, effectively preventing latch-up effect. At the same time, since the second doped region 28 is relatively deep, it mainly affects the characteristics of the well region without interfering with the doping distribution of the channel region. Therefore, it does not change the threshold voltage and hot carrier injection reliability regulated by the first doped region 24 and the third doped region 25, realizing the synergistic improvement of well region optimization and electrical performance.

[0047] In one example, after forming the second doped region 28, the process further includes: using a patterned second mask layer 26 as a mask, performing a fourth ion implantation on the substrate 20 through a second implantation window 27 to form a fourth doped region 29 within the second doped region 28. The depth of the fourth doped region 29 in the substrate 20 is less than the depth of the second doped region 28 in the substrate 20, and the depth of the first doped region 24 in the substrate 20 is less than the depth of the fourth doped region 29 in the substrate 20. Specifically, using the patterned second mask layer 26 as a mask, the fourth ion implantation is further performed on the substrate 20 through the second implantation window 27 to form the fourth doped region 29 within the second doped region 28. The depth of the fourth doped region 29 in the substrate 20 is less than the depth of the second doped region 28 in the substrate 20, but greater than the depth of the first doped region 24 in the substrate 20. The fourth doped region 29 increases the potential barrier within the bulk region, making it difficult for charge carriers to directly pass from the source through the bulk region to the drain under high voltage conditions, effectively suppressing the punch-through effect between the source and drain. Meanwhile, since its depth does not extend to the channel surface, it will not interfere with the surface electrical characteristics established by the first doped region 24 (threshold voltage control region) and the third doped region 25 (HCI optimization region), thereby improving the device's off-state robustness while maintaining precise control over the threshold voltage (Vt) and hot carrier injection (HCI) reliability.

[0048] The third doped region 25, the first doped region 24, the fourth doped region 29, and the second doped region 28 are distributed sequentially from top to bottom in the substrate 20. The third doped region 25 is closest to the substrate surface, the first doped region 24 is located below the third doped region 25, the fourth doped region 29 is located below the first doped region 24, and the second doped region 28 is the deepest, forming a multi-level doped structure from shallow to deep, which is used to optimize HCI reliability, regulate threshold voltage, suppress source-drain punch-through, and prevent latch-up effect, respectively.

[0049] For example, the ion type of the fourth ion implantation is the same as that of the first and second ion implantations, but the ion type of the fourth ion implantation is different from that of the third ion implantation. For example, the fourth, second, and first ion implantations can use P-type doped ions (e.g., boron ions), and the third ion implantation can use N-type doped ions (e.g., arsenic ions). For example, the implantation energy of the fourth ion implantation is lower than that of the second ion implantation but higher than that of the first ion implantation; the implantation dose of the fourth ion implantation is lower than that of the first ion implantation but higher than that of the second ion implantation.

[0050] It should be noted that after completing all the ion implantation processes, including the first, second, third, and fourth ion implantations, an annealing process is also included to fully activate the implanted dopant ions, repair the lattice damage to the substrate caused by high-energy ion bombardment, and thus improve the performance of the device.

[0051] In one example, after forming the fourth doped region 29, the process further includes removing the patterned first mask layer 22 and the patterned second mask layer 26. Specifically, the patterned first mask layer 22 and the patterned second mask layer 26 can be removed using an ashing or wet resist removal process, thereby exposing the complete gate 21 and the surface of the substrate 20. When a barrier layer 201 is formed on the substrate 20, removing the patterned first mask layer 22 and the patterned second mask layer 26 exposes the surface of the gate 21 and the barrier layer 201, providing a clean interface foundation for subsequent process steps (such as source / drain implantation, silicide formation, or interlayer dielectric deposition).

[0052] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0053] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0054] In summary, the semiconductor device fabrication method of this application, by using the same mask to sequentially form a patterned first mask layer and a patterned second mask layer, can realize two different sizes of ion implantation windows without process adjustment, avoiding the problems of non-uniformity of critical dimensions of ion implantation windows and asymmetry of gate exposure, improving the implantation uniformity of wafer edges, enhancing the electrical performance and yield of the device, and reducing process cost and complexity.

[0055] This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or by other suitable preparation methods.

[0056] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substrate is provided on which at least two gates are formed at intervals; A patterned first mask layer is formed on the gate and the substrate, the patterned first mask layer defining at least one first injection window, each first injection window exposing the substrate surface between two adjacent gates, the sidewalls of the two adjacent gates facing each other, and a portion of the top surface adjacent to the sidewalls; Using the patterned first mask layer as a mask, the first ion implantation is performed on the substrate through the first implantation window to form a first doped region in the substrate; A patterned second mask layer is formed, covering the patterned first mask layer, the exposed gates, and a portion of the substrate surface. The patterned second mask layer defines a second injection window, which exposes a portion of the substrate surface between the two gates. The patterned first mask layer and the patterned second mask layer are formed using the same mask. An overexposure process is used when forming the patterned first mask layer. Using the patterned second mask layer as a mask, a second ion implantation is performed on the substrate through the second implantation window to form a second doped region in the substrate, wherein the depth of the first doped region in the substrate is less than the depth of the second doped region in the substrate.

2. The preparation method according to claim 1, characterized in that, After the formation of the first doped region and before the formation of the second doped region, the process further includes: Using the patterned first mask layer as a mask, a third ion implantation is performed on the substrate through the first implantation window to form a third doped region in the first doped region, wherein the depth of the third doped region in the substrate is less than the depth of the first doped region in the substrate.

3. The preparation method according to claim 2, characterized in that, After forming the second doped region, the process further includes: Using the patterned second mask layer as a mask, a fourth ion implantation is performed on the substrate through the second implantation window to form a fourth doped region in the second doped region, wherein the depth of the fourth doped region in the substrate is less than the depth of the second doped region in the substrate and greater than the depth of the first doped region in the substrate.

4. The preparation method according to claim 3, characterized in that, The first mask layer is a first photoresist layer, and the second mask layer is a second photoresist layer, wherein... When forming the patterned first mask layer and the patterned second mask layer, the exposure energy for exposing the first photoresist layer is less than the exposure energy for exposing the second photoresist layer. After forming the fourth doped region, the process also includes removing the patterned first mask layer and the patterned second mask layer.

5. The preparation method according to claim 3, characterized in that, The implantation energy of the third ion implantation is less than that of the first ion implantation, the implantation energy of the first ion implantation is less than that of the fourth ion implantation, and the implantation energy of the fourth ion implantation is less than that of the second ion implantation. The implantation dose of the first ion implantation is less than the implantation dose of the third ion implantation, the implantation dose of the fourth ion implantation is less than the implantation dose of the first ion implantation, and the implantation dose of the second ion implantation is less than the implantation dose of the fourth ion implantation.

6. The preparation method according to claim 5, characterized in that, The ionic conductivity types of the first ion implantation, the second ion implantation, and the fourth ion implantation are different from the ionic conductivity type of the third ion implantation.

7. The preparation method according to claim 6, characterized in that, The first, second, and fourth ion implantations involve P-type ions, while the third ion implantation involves N-type ions.

8. The preparation method according to claim 1, characterized in that, The thickness of the first mask layer is less than or equal to 5000 Å, and the thickness of the second mask layer is greater than or equal to 25000 Å.

9. The preparation method according to claim 1, characterized in that, Before forming the gate, the method further includes forming a barrier layer on the substrate.

10. A semiconductor device, characterized in that, The semiconductor device is obtained by the fabrication method according to any one of claims 1-9.

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