Semiconductor device and method of manufacturing semiconductor device
By introducing a silicon carbide epitaxial layer and a deeply doped p-type region into the semiconductor device, the problems of low breakdown voltage and reliability caused by the high electric field at the trench edge are solved, and higher breakdown voltage and faster switching speed are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2026-03-27
AI Technical Summary
In traditional power metal-oxide-semiconductor transistors, the high electric field at the trench edge leads to a lower drain-to-source breakdown voltage and reliability failure.
A silicon carbide epitaxial layer is introduced into a semiconductor device, comprising a p-type well region, a heavily doped n-type region, and a heavily doped p-type region, and first and second deeply doped p-type regions are formed below the gate trench. By adjusting the width and distance of these doped regions, the high electric field at the trench edge is released, while optimizing the on-resistance and reducing parasitic capacitance.
The drain-to-source breakdown voltage was increased, the on-resistance was optimized, and the switching speed of the transistor was improved.
Smart Images
Figure CN121751675A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor device, and more particularly to a power metal-oxide-semiconductor transistor. Background Technology
[0002] In traditional power metal-oxide-semiconductor transistors (MOSFETs), the high electric field at the trench edge can easily lead to low drain-to-source breakdown voltage (BVDSS) and reliability failure. Therefore, a new semiconductor device and a method for manufacturing semiconductor devices are needed to overcome these problems. Summary of the Invention
[0003] In view of the above, the present invention provides a semiconductor device comprising: a silicon carbide epitaxial layer including: a p-type well region; a heavily doped n-type region on the surface of the p-type well region; and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region. The semiconductor device further includes a first gate trench extending through the p-type well region; a first deeply doped p-type region below the first gate trench; a gate oxide layer on the bottom and side surfaces of the first gate trench and on the heavily doped n-type region; a polycrystalline silicon layer on the gate oxide layer; an interlayer dielectric layer on the polycrystalline silicon layer; and a source trench extending through the interlayer dielectric layer and the gate oxide layer and into the heavily doped n-type region and the heavily doped p-type region, wherein the width of the first deeply doped p-type region is narrower than the width of the first gate trench.
[0004] The present invention also provides a method for manufacturing a semiconductor device, comprising: providing a silicon carbide epitaxial layer, wherein a p-type well region, a heavily doped n-type region on the surface of the p-type well region, and a heavily doped p-type region below the heavily doped n-type region and within the p-type well region are predefined on the silicon carbide epitaxial layer; forming a first gate trench in the silicon carbide epitaxial layer through the p-type well region; forming a first deeply doped p-type region in the silicon carbide epitaxial layer below the first gate trench, wherein the width of the first deeply doped p-type region is narrower than the width of the first gate trench; forming a gate oxide layer on the bottom surface and side surface of the first gate trench and on the heavily doped n-type region; forming a polycrystalline silicon layer on the gate oxide layer; forming an interlayer dielectric layer on the polycrystalline silicon layer; and forming a source trench through the interlayer dielectric layer and the gate oxide layer and extending into the heavily doped n-type region and the heavily doped p-type region.
[0005] In summary, the drain-to-source breakdown voltage (BVDSS) is improved by releasing the high electric field at the trench edge through the first deeply doped p-type region below the first gate trench and the second deeply doped p-type region below the second gate trench. Furthermore, the on-resistance (Rdson) can be optimized by adjusting the distance between the first and second deeply doped p-type regions. Moreover, the junctions formed by the first and second deeply doped p-type regions and the N-type silicon carbide epitaxial layer 101 can reduce the parasitic capacitance Cgd, thereby improving the switching speed of the transistor. Attached Figure Description
[0006] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0007] Figure 1 This is a cross-sectional view of the semiconductor device 100 of the present invention;
[0008] Figure 2 This is a flowchart of the method 200 for manufacturing a semiconductor device according to the present invention;
[0009] Figure 3 This is another cross-sectional view of the semiconductor device 100;
[0010] Figure 4 This is another cross-sectional view of the semiconductor device 100;
[0011] Figure 5 This is another cross-sectional view of the semiconductor device 100;
[0012] Figure 6 This is another cross-sectional view of the semiconductor device 100;
[0013] Figure 7 This is another cross-sectional view of the semiconductor device 100;
[0014] Figure 8 This is another cross-sectional view of the semiconductor device 100;
[0015] Figure 9 This is another cross-sectional view of the semiconductor device 100;
[0016] Figure 10 This is another cross-sectional view of the semiconductor device 100;
[0017] Figure 11 This is another cross-sectional view of the semiconductor device 100;
[0018] Figure 12 This is another cross-sectional view of the semiconductor device 100;
[0019] Figure 13This is another cross-sectional view of the semiconductor device 100;
[0020] Figure 14 This is another cross-sectional view of the semiconductor device 100;
[0021] Figure 15 This is another cross-sectional view of the semiconductor device 100;
[0022] Figure 16 This is another cross-sectional view of the semiconductor device 100; and
[0023] Figure 17 This is another cross-sectional view of the semiconductor device 100.
[0024] Figure label:
[0025] 100: Semiconductor devices
[0026] 200: Method
[0027] 101: Silicon carbide epitaxial layer
[0028] 102: Gate oxide layer
[0029] 103: Polycrystalline silicon layer
[0030] 104: Interlayer dielectric layer
[0031] 105: Heavily doped p-region
[0032] 106: Metal layer
[0033] 107: Heavily doped n-region
[0034] 109: Passivation layer
[0035] 110: Polyimide layer
[0036] 111: Silicon carbide substrate
[0037] 112: Metal layer
[0038] ILD1: Interlayer dielectric layer
[0039] ILD2: Interlayer dielectric layer
[0040] DP1: Deeply doped p-type region
[0041] DP2: Deeply doped p-type region
[0042] PW: p-type well region
[0043] FOX: Field oxide layer
[0044] SC: Metal silicide
[0045] GR: Protective Ring Area
[0046] OP1: Opening
[0047] OP2: Opening
[0048] HM1: Hard shielding layer
[0049] HM2: Hard shielding layer
[0050] HM3: Hard shielding layer
[0051] HM4: Hard shielding layer
[0052] TR1: Gate Trench
[0053] TR2: Gate Trench
[0054] STR: Source Trench
[0055] TR3: Gate Trench
[0056] TR4: Gate Trench
[0057] 201: Steps
[0058] 202: Steps
[0059] 203: Steps
[0060] 204: Steps
[0061] 205: Steps
[0062] 206: Steps
[0063] 207: Steps Detailed Implementation
[0064] Figure 1 This is a cross-sectional view of the semiconductor device 100 of the present invention. Figure 1As shown, the semiconductor device 100 includes a silicon carbide epitaxial layer 101, gate trenches TR1 and TR2, deeply doped p-type regions DP1 and DP2, a gate oxide layer 102, a polysilicon layer 103, an interlayer dielectric layer 104, and a source trench STR. Specifically, the silicon carbide epitaxial layer 101 includes a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, and a heavily doped p-type region 105 below the heavily doped n-type region 107 and within the p-type well region PW. In some embodiments, the interlayer dielectric layer 104 further includes two interlayer dielectric layers ILD1 and ILD2 to reduce unevenness caused by the trenches. Additionally, the semiconductor device 100 includes a metal silicide SC, a metal layer 106 on the metal silicide SC, a silicon carbide substrate 111 below the silicon carbide epitaxial layer 101, and a metal layer 112 below the silicon carbide substrate 111. In detail, the metal layer 106 is contacted within the source trench STR via a metal silicide SC and heavily doped p-type regions 105 and 107. The patterned metal layer 106 is electrically connected to the polycrystalline silicon layers 103 of the gate trenches TR1 and TR2, which belong to different transistor cells, to serve as gate pads, while the metal layer 106 in the source trench STR can constitute source pads. The composition of metal layers 106 and 112 can include Ni, Ti, TiN, AlCu, etc., but is not limited thereto. In a preferred embodiment of the invention, metal layers 106 and 112 are aluminum-copper alloys.
[0065] Gate trenches TR1 and TR2 both penetrate the p-type well region PW. A deeply doped p-type region DP1 lies beneath gate trench TR1, while a deeply doped p-type region DP2 lies beneath gate trench TR2. In some embodiments, the width of the deeply doped p-type region DP1 is narrower than the width of gate trench TR1. Gate oxide layer 102 lies on the bottom and side surfaces of gate trench TR1, on the bottom and side surfaces of gate trench TR2, and on a portion of the heavily doped n-type region 107. A polycrystalline silicon layer 103 lies on gate oxide layer 102, and an interlayer dielectric layer 104 lies on polycrystalline silicon layer 103. Source trench STR penetrates the interlayer dielectric layer 104 and gate oxide layer 102 and extends into the heavily doped n-type region 107 and the heavily doped p-type region 105. Figure 1 As shown, the gate trench TR1 and the deeply doped p-type region DP1 are contained in one transistor cell, while the gate trench TR2 and the deeply doped p-type region DP2 are contained in another transistor cell adjacent to the aforementioned transistor cell.
[0066] exist Figure 1In the transistor, the bottom surface of the gate trench TR2 is lower than the bottom surface of the gate trench TR1, while the width of the deeply doped p-type region DP2 is wider than the width of the gate trench TR2. The gate trench TR1 and the deeply doped p-type region DP1 belong to different transistor cells than the gate trench TR2 and the deeply doped p-type region DP2.
[0067] In some embodiments, the pattern of gate trench TR2 can be replaced by the pattern of gate trench TR1 to form as shown in the figure. Figure 16 The gate trench TR3 in the middle, in other words, Figure 16 The gate trench TR3 has the same configuration as the gate trench TR1. Please refer to [link / reference]. Figure 16 The bottom surface of gate trench TR3 is at the same height as the bottom surface of gate trench TR1, and the width of the bottom surface of gate trench TR3 is equal to the width of the bottom surface of gate trench TR1. This makes the width of the deeply doped p-type region DP3 (which can be symmetrical with the deeply doped p-type region DP1) below gate trench TR3 narrower than the width of gate trench TR3. During etching, the polycrystalline silicon layer 103 in gate trench TR3 is cut open to expose the gate oxide layer 102, allowing the interlayer dielectric layer 104 to contact the gate oxide layer 102 within the gate trench TR3. Figure 16 As shown, gate trench TR1 and deeply doped p-type region DP1 can belong to different transistor cells than gate trench TR3 and deeply doped p-type region DP3.
[0068] In some embodiments, the pattern of the gate trench TR2 can be changed as follows: Figure 17 The pattern of gate trench TR4 in [the image / image]. Please refer to [the image / image]. Figure 17 The bottom surface of gate trench TR4 is at the same height as the bottom surface of gate trench TR1, but the width of the bottom surface of gate trench TR4 is narrower than that of gate trench TR1. Therefore, the width of the deeply doped p-type region DP4 (which can be the same as the deeply doped p-type region DP2, only differing in depth) below gate trench TR4 is wider than the width of gate trench TR4. However, the interlayer dielectric layer 104 does not contact the gate oxide layer 102 in gate trench TR4. Gate trench TR1 and deeply doped p-type region DP1 can belong to different transistor cells than gate trench TR4 and deeply doped p-type region DP4.
[0069] Figure 2 This is a flowchart of the method 200 for manufacturing a semiconductor device according to the present invention. Figures 3 to 15 This is a cross-sectional view of the semiconductor device 100, used to illustrate steps 201 to 207 of method 200.
[0070] First, in step 201, a silicon carbide epitaxial layer 101 is provided. For example... Figure 3As shown, a p-type well region PW, a heavily doped n-type region 107 on the surface of the p-type well region PW, a heavily doped p-type region 105 below the heavily doped n-type region 107 and within the p-type well region, a guard ring region GR, and a deeply doped p-type region DP2 (i.e., the second deeply doped p-type region) are predefined on the silicon carbide epitaxial layer 101. Figure 4 As shown, a hard shielding layer HM1 is deposited on a silicon carbide epitaxial layer 101. The hard shielding layer HM1 is patterned such that the opening OP1 of the patterned hard shielding layer HM1 is located between two heavily doped n-type regions 107. The opening OP1 defines the region of the gate trench TR1. The step of patterning the hard shielding layer HM1 includes forming a photoresist over the hard shielding layer HM1, then performing a photolithography process to pattern the photoresist, performing an etching process to form the opening OP1 in the hard shielding layer HM1, and then removing the photoresist.
[0071] In step 202, a first gate trench is formed in the silicon carbide epitaxial layer 101, penetrating the p-type well region PW. For example... Figure 5 As shown, an etching process is performed to remove the portion of the silicon carbide epitaxial layer 101 exposed by the opening OP1 to create a gate trench TR1 (i.e., the first gate trench) through the p-type well region PW. Figure 6 As shown, hard shielding layers HM2 and HM3 are sequentially deposited on the etched hard shielding layer HM1, wherein hard shielding layer HM3 has high etch selectivity relative to hard shielding layer HM2.
[0072] In step 203, a first deeply doped p-type region is formed within the silicon carbide epitaxial layer below the first gate trench. For example... Figure 7 As shown, the hard shielding layer HM3 is etched back to expose the hard shielding layer HM2 at the bottom of the gate trench TR1, and a deeply doped p-type region DP1 (i.e., the first deeply doped p-type region) is formed in the silicon carbide epitaxial layer 101 below the gate trench TR1 using an ion implantation process. Because a portion of the hard shielding layer HM3 remains in the gate trench TR1, the width of the deeply doped p-type region DP1 is smaller than the width of the gate trench TR1.
[0073] like Figure 8 As shown, a hard shielding layer HM4 is deposited after the ion implantation procedure is performed. Figure 9 As shown, the hard shielding layer HM4 is patterned to create an opening OP2 that defines the region of the gate trench TR2. The step of patterning the hard shielding layer HM4 includes forming a photoresist over the hard shielding layer HM4, then performing a photolithography process to pattern the photoresist, performing an etching process to form the opening OP2 in the hard shielding layer HM4, and then removing the photoresist. Figure 10As shown, an etching process is performed to remove the portion of the silicon carbide epitaxial layer 101 exposed by the opening OP2 to create the gate trench TR2. This etching stops at the deeply doped p-type region DP2. The deeply doped p-type region DP2 is deeper than the deeply doped p-type region DP1; in other words, the bottom surface of the gate trench TR1 is higher than the bottom surface of the gate trench TR2. Figure 11 As shown, remove the hard shielding layers HM4, HM3, HM2, and HM1, and perform thermal annealing. Figure 12 As shown, after thermal annealing, oxide is deposited and then patterned to form a field oxide layer FOX.
[0074] In step 204, a gate oxide layer is formed on the bottom and side surfaces of the first and second gate trenches, and on the heavily doped n-type region. In step 205, a polycrystalline silicon layer is formed on the gate oxide layer. Figure 13 As shown, a gate oxide layer 102 is deposited, and a polysilicon layer 103 is deposited on the gate oxide layer 102. As... Figure 14 As shown, a photoresist is formed on the polysilicon layer 103, and then a photolithography process is performed to pattern the photoresist. An etching process is performed to remove the polysilicon layer 103 outside the gate trenches TR1 and TR2 (i.e., the second gate trench). For the gate trench TR1, although the gate oxide layer 102 is exposed at the bottom of the gate trench TR1 after the polysilicon layer 103 is etched, the polysilicon layer 103 only exists on the sidewalls and part of the bottom of the gate trench TR1. However, since the channel is formed at the sidewalls of the gate trench TR1, the conduction characteristics of the semiconductor are not affected.
[0075] In step 206, an interlayer dielectric layer is formed on the polycrystalline silicon layer. For example... Figure 15 As shown, interlayer dielectric layers ILD1 and ILD2 are deposited sequentially, wherein the interlayer dielectric layer ILD2 has a planarization effect to reduce the height difference at the trench (e.g., gate trench TR1).
[0076] In step 207, a source trench is formed that passes through the interlayer dielectric layer and the gate oxide layer and extends into the heavily doped n-type and heavily doped p-type regions. Specifically, a photoresist is formed on the interlayer dielectric layer ILD2, and then a photolithography process is performed to pattern the photoresist to form a source contact shield. An etching process is performed to form a source trench STR in the source region that passes through the interlayer dielectric layer ILD2, the interlayer dielectric layer ILD1, and the gate oxide layer 102 to reach the heavily doped n-type region 107 and the heavily doped p-type region 105. The photoresist is then removed. A metal silicide SC is formed in the source trench STR. A patterned photoresist layer is formed by photolithography, and an etching process is performed to create a trench for the gate pad. The patterned photoresist layer is then removed. A metal layer 106 is deposited, and a patterned photoresist layer is formed by photolithography. An etching process is performed to pattern the metal layer 106 to create the gate pad and the source pad. A passivation layer 109 is deposited, and a patterned photoresist layer is formed using a photolithography process. An etching process is then performed to pattern the passivation layer 109, resulting in the passivation layer 109 being formed on the metal layer 106 and the interlayer dielectric layer 104. A polyimide layer 110 may also be disposed on the passivation layer 109, such as... Figure 1 As shown.
[0077] This invention improves the drain-to-source breakdown voltage (BVDSS) by releasing the high electric field at the trench edge through deeply doped p-type regions DP1 and DP2. The on-resistance (Rdson) can be optimized by adjusting the distance between the deeply doped p-type regions DP1 and DP2. Furthermore, the junctions formed by the deeply doped p-type regions DP1 and DP2 and the N-type silicon carbide epitaxial layer 101 can reduce the parasitic capacitance Cgd and improve the switching speed of the transistor.
[0078] The foregoing description of numerous embodiments enables those skilled in the art to clearly understand the form of this specification. Those skilled in the art will understand that they can utilize the disclosure of this invention to design or modify other processes and structures to achieve the same objectives and / or advantages as the above embodiments. Those skilled in the art will also understand that equivalent constructions without departing from the spirit and scope of this invention can be arbitrarily modified, substituted, and refined without departing from the spirit and scope of this invention.
Claims
1. A semiconductor device, comprising: a silicon carbide epitaxial layer, comprising: a p-type well region; a heavily doped n-type region on a surface of the p-type well region; and a heavily doped p-type region under the heavily doped n-type region and within the p-type well region; a first gate trench through the p-type well region; a first deep doped p-type region under the first gate trench, wherein a width of the first deep doped p-type region is narrower than a width of the first gate trench; a gate oxide layer on a bottom surface and side surfaces of the first gate trench, and on the heavily doped n-type region; a polysilicon layer on the gate oxide layer; an interlayer dielectric layer on the polysilicon layer; and a source trench through the interlayer dielectric layer and the gate oxide layer and extending into the heavily doped n-type region and the heavily doped p-type region.
2. The semiconductor device according to claim 1, wherein further comprising: a second gate trench through the p-type well region, wherein a bottom surface of the second gate trench is lower than a bottom surface of the first gate trench; and a second deep doped p-type region under the second gate trench, wherein a width of the second deep doped p-type region is wider than a width of the second gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the second gate trench and the second deep doped p-type region, respectively.
3. The semiconductor device according to claim 1, wherein further comprising: a third gate trench through the p-type well region, wherein a bottom surface of the third gate trench is level with a bottom surface of the first gate trench; and a third deep doped p-type region under the third gate trench, wherein a width of the third deep doped p-type region is narrower than a width of the third gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the third gate trench and the third deep doped p-type region, respectively.
4. The semiconductor device according to claim 1, wherein further comprising: a fourth gate trench through the p-type well region, wherein a bottom surface of the fourth gate trench is level with a bottom surface of the first gate trench; and a fourth deep doped p-type region under the fourth gate trench, wherein a width of the fourth deep doped p-type region is wider than a width of the fourth gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the fourth gate trench and the fourth deep doped p-type region, respectively.
5. The semiconductor device according to claim 1, wherein further comprising: a first metal layer within the source trench contacting the heavily doped p-type region and the heavily doped n-type region through a metal silicide.
6. The semiconductor device according to claim 1, wherein further comprising: a silicon carbide substrate under the silicon carbide epitaxial layer; and a second metal layer under the silicon carbide substrate.
7. A method of manufacturing a semiconductor device, comprising: providing a silicon carbide epitaxial layer, wherein the silicon carbide epitaxial layer has a p-type well region, a heavily doped n-type region on a surface of the p-type well region, and a heavily doped p-type region under the heavily doped n-type region and within the p-type well region predefined thereon; forming a first gate trench through the p-type well region in the silicon carbide epitaxial layer; forming a first deep doped p-type region in the silicon carbide epitaxial layer under the first gate trench, wherein a width of the first deep doped p-type region is narrower than a width of the first gate trench; forming a gate oxide layer on a bottom surface and a side surface of the first gate trench and on the heavily doped n-type region; forming a polysilicon layer on the gate oxide layer; forming an interlayer dielectric layer on the polysilicon layer; and forming a source trench through the interlayer dielectric layer and the gate oxide layer and extending into the heavily doped n-type region and the heavily doped p-type region.
8. The method of manufacturing a semiconductor device according to Claim 7, wherein Further comprising: forming a second gate trench through the p-type well region, wherein a bottom surface of the second gate trench is lower than a bottom surface of the first gate trench; forming a second deep doped p-type region under the second gate trench, wherein a width of the second deep doped p-type region is wider than a width of the second gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the second gate trench and the second deep doped p-type region, respectively.
9. The method of manufacturing a semiconductor device according to Claim 7, wherein Further comprising: forming a third gate trench through the p-type well region, wherein a bottom surface of the third gate trench is level with a bottom surface of the first gate trench; and forming a third deep doped p-type region under the third gate trench, wherein a width of the third deep doped p-type region is narrower than a width of the third gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the third gate trench and the third deep doped p-type region, respectively.
10. The method of manufacturing a semiconductor device according to claim 7, wherein Further comprising: forming a fourth gate trench through the p-type well region, wherein a bottom surface of the fourth gate trench is level with a bottom surface of the first gate trench; and forming a fourth deep doped p-type region under the fourth gate trench, wherein a width of the fourth deep doped p-type region is wider than a width of the fourth gate trench, wherein the first gate trench and the first deep doped p-type region belong to a different transistor cell than the fourth gate trench and the fourth deep doped p-type region, respectively.
11. The method of manufacturing a semiconductor device according to Claim 7, wherein Further comprising: forming a first metal layer within the source trench, wherein the first metal layer contacts the heavily doped p-type region and the heavily doped n-type region through metal silicide.
12. The method of manufacturing a semiconductor device according to claim 7, wherein Further comprising: forming a silicon carbide substrate under the silicon carbide epitaxial layer; and forming a second metal layer under the silicon carbide substrate.