Semiconductor device

Abstract

A semiconductor device may include: a first active pattern extending in a first direction and having a first width in a second direction; a second active pattern extending in the first direction and having a second width smaller than the first width in the second direction; a first gate structure extending on the first active pattern; a second gate structure extending on the second active pattern; a first source / drain region on the first active pattern between the first gate structures; a second source / drain region on the second active pattern between the second gate structures; a first fin spacer on a side surface of the first source / drain region; and a second fin spacer on a side surface of the second source / drain region. A height of the first fin spacer in a third direction may be less than a height of the second fin spacer in the third direction.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Specifically, it relates to three-dimensional (3D) semiconductor devices including field-effect transistors (FETs). Background Technology

[0002] As the demand for high performance, high speed, and / or multifunctionality in semiconductor devices increases, the integration density of semiconductor devices is also increasing. When manufacturing semiconductor devices with fine patterns corresponding to this trend of high integration, it is helpful to realize patterns with fine widths or fine separation distances. Furthermore, to overcome the limitations in operating characteristics caused by the shrinking size of planar metal-oxide-semiconductor FETs (MOSFETs), efforts are underway to develop semiconductor devices including FinFETs with three-dimensional channels. Summary of the Invention

[0003] Various aspects of the present invention provide a semiconductor device with improved reliability and electrical characteristics.

[0004] However, the inventive concept is not limited to the aspects described above, and the inventive concept can be extended in various ways within its scope.

[0005] According to some aspects of the present invention, a semiconductor device may include: a substrate including a first active pattern and a second active pattern, the first active pattern extending in a first direction and having a first width in a second direction intersecting the first direction, the second active pattern extending in the first direction and having a second width in the second direction less than the first width; a first gate structure located on the first active pattern, spaced apart from each other in the first direction and extending along the second direction; a second gate structure located on the second active pattern, spaced apart from each other in the first direction and extending along the second direction; a first source / drain region located on the first active pattern between the first gate structures; a second source / drain region located on the second active pattern between the second gate structures; a first fin spacer located on a side surface of the first source / drain region; and a second fin spacer located on a side surface of the second source / drain region, wherein the height of the first fin spacer in a third direction intersecting the first and second directions is less than the height of the second fin spacer in that third direction.

[0006] According to some aspects of the present invention, a semiconductor device may include: a substrate; a first active pattern extending on the substrate along a first direction and having a first width in a second direction intersecting the first direction; a second active pattern extending on the substrate along the first direction and having a second width in the second direction less than the first width; a first gate structure extending on the first active pattern along the second direction; a second gate structure extending on the second active pattern along the second direction; a first source / drain region located on the first active pattern between the first gate structures; and a second source / drain region located between the second gate structures. On the second active pattern, wherein the first source / drain region includes a first extension portion contacting the upper surface of the first active pattern and a first extended portion extending from the first extension portion, the first extended portion having a width that increases and then decreases in a second direction as it moves away from the substrate in a third direction, the third direction intersecting the first direction and the second direction, wherein the second source / drain region includes a second extension portion contacting the upper surface of the second active pattern and a second extended portion extending from the second extension portion, the second extended portion having a width that increases and then decreases in the second direction as it moves away from the substrate in a third direction, and wherein the height of the first extension portion in the third direction is less than the height of the second extension portion in the third direction.

[0007] According to some aspects of the present invention, a semiconductor device may include: a substrate including a first active pattern and a second active pattern, the first active pattern extending in a first direction and having a first width in a second direction intersecting the first direction, the second active pattern extending in the first direction and having a second width in the second direction less than the first width; a device isolation layer located on the substrate and located on two opposite side surfaces of the first active pattern and two opposite side surfaces of the second active pattern; a first gate structure located on the first active pattern, spaced apart from each other in the first direction and extending along the second direction; a second gate structure located on the second active pattern, spaced apart from each other in the first direction and extending along the second direction; and a first fin spacer located on the device isolation layer between the first gate structures. A second fin spacer is located on the device isolation layer between the second gate structures; a first source / drain region is located on the first active pattern between the first fin spacers; and a second source / drain region is located on the second active pattern between the second fin spacers, wherein the width of each of the first gate structures in the first direction is equal to the width of each of the second gate structures in the first direction, wherein there is no first fin spacer on the opposite side surface of the first portion of the first source / drain region in the second direction, and there is no second fin spacer on the opposite side surface of the second portion of the second source / drain region in the second direction, and wherein, when viewed along the second direction, the cross-sectional area of ​​the first portion of the first source / drain region is greater than the cross-sectional area of ​​the second portion of the second source / drain region. Attached Figure Description

[0008] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a top view showing a semiconductor device according to an embodiment.

[0009] Figure 2 It is along Figure 1 The cross-sectional view taken from lines Ia-Ia' and Ib-Ib'.

[0010] Figure 3 It is along Figure 1 The cross-sectional views taken from lines IIa-IIa' and IIb-IIb'.

[0011] Figure 4AIt is along Figure 1 Cross-sectional views taken from lines IIIa-IIIa' and IIIb-IIIb'.

[0012] Figure 4B , Figure 4C and Figure 4D According to another embodiment along Figure 1 Cross-sectional views taken from lines IIIa-IIIa' and IIIb-IIIb'.

[0013] Figure 5A and Figure 5B It is a view showing the electrical characteristics based on the width of the active pattern of a semiconductor device and the width of the active pattern of a reference semiconductor device.

[0014] Figure 6A , Figure 6B , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 11 and Figure 12 This is a view illustrating the process sequence of a method for manufacturing a semiconductor device according to an embodiment. Detailed Implementation

[0015] In the following description, exemplary embodiments will be presented in more detail with reference to the accompanying drawings. The same reference numerals may be used for the same parts in the drawings, and repeated descriptions of the same parts may be omitted.

[0016] Figure 1 This is a top view showing a semiconductor device according to an embodiment. Figure 2 It is along Figure 1 The cross-sectional view taken from lines Ia-Ia' and Ib-Ib'. Figure 3 It is along Figure 1 The cross-sectional views taken from lines IIa-IIa' and IIb-IIb'. Figure 4A It is along Figure 1 The cross-sectional views are taken from lines IIIa-IIIa' and IIIb-IIIb'. For ease of explanation, [the following is a possible interpretation] Figure 1 The diagram shows only some components of the semiconductor device. A cross-sectional view of an embodiment of the semiconductor device 100, taken along lines Ia-Ia' and Ib-Ib', is shown; these devices may have the same structure.

[0017] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4ASemiconductor device 100 may include a first region R1 and a second region R2. The first region R1 and the second region R2 may be spaced apart in a first direction (X direction). In some embodiments, the first region R1 and the second region R2 may be arranged side-by-side in the first direction (X direction) (i.e., adjacent to each other in the first direction (X direction)). The first region R1 may be referred to as the region having a first active pattern 105a (which has a first width W1a) and a region where a wide nanosheet transistor is disposed. The second region R2 may be referred to as the region having a second active pattern 105b (which has a second width W1b smaller than (i.e., less than) the first width W1a) and a region where a narrow nanosheet transistor is disposed. As used herein, components may be individually referred to by their respective reference numerals, and may also be collectively referred to by shared portions of their reference numerals. For example, the first active pattern 105a and the second active pattern 105b may be collectively referred to as active pattern 105.

[0018] Semiconductor device 100 may include: a substrate 101 including an active pattern 105; a channel structure 140 located on the active pattern 105, including first to fourth channel layers 141, 142, 143 and 144 disposed vertically (e.g., in a third direction (Z direction)) and spaced apart from each other; a gate structure 160 extending across the active pattern 105 and including a gate electrode 165; a source / drain region 150 contacting the channel structure 140; a first fin spacer 155a disposed on two (i.e., two opposing) sidewalls (i.e., side surfaces) of the first source / drain region 150a in the source / drain region 150; a second fin spacer 155b disposed on two sidewalls of the second source / drain region 150b in the source / drain region 150; and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may also include a device isolation layer 110 and an interlayer insulating layer 170.

[0019] In the semiconductor device 100, each active pattern 105 may have a fin structure, and a gate electrode 165 may be disposed between the active pattern 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of each channel structure 140, and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM A transistor with a gate-all-around (GAA) structure, which can be a field-effect transistor.

[0020] Substrate 101 may have an upper surface extending in a first direction (X direction) and a second direction (Y direction). Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may be configured as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0021] Substrate 101 may include an active pattern 105 disposed in the upper portion of substrate 101. The active pattern 105 may be defined in substrate 101 by device isolation layer 110 and may be configured to extend in a first direction (X direction). Depending on the manner of description, the active pattern 105 may be described as a configuration separate from substrate 101. As used herein, it will be understood that the active pattern 105 may be considered as part of or separate from substrate 101 without departing from the scope of this disclosure. The active pattern 105 may partially protrude above device isolation layer 110 such that the upper surface of the active pattern 105 may be located at a horizontal height higher than the horizontal height of the upper surface of device isolation layer 110. As used herein, unless otherwise indicated, the term "horizontal height" may refer to a distance above or relative to substrate 101 (e.g., the upper surface of substrate 101) in a vertical direction (e.g., a third direction (Z direction)). The active pattern 105 may be formed as part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. On both sides of the gate structure 160, the active pattern 105 may be partially recessed to form recessed regions, and the source / drain regions 150 may be disposed in the recessed regions.

[0022] The active pattern 105 may include a first active pattern 105a disposed in a first region R1 and a second active pattern 105b disposed in a second region R2. The first active pattern 105a may have a first width W1a in a second direction (Y direction), and the second active pattern 105b may have a second width W1b in the second direction (Y direction) that is smaller than the first width W1a. For example, the size of the first width W1a may be two to three times the size of the second width W1b. Each of the first active pattern 105a and the second active pattern 105b may extend in a first direction (X direction). The first active pattern 105a and the second active pattern 105b may be disposed side-by-side in the first direction (X direction). In another example, the first active pattern 105a and the second active pattern 105b may be spaced apart in the second direction (Y direction).

[0023] Each of the first active pattern 105a and the second active pattern 105b may or may not include a well region with impurities. For example, in an N-type transistor (e.g., an nFET), the well region may include a P-type impurity such as boron (B), gallium (Ga), or indium (In). For example, in a P-type transistor (e.g., a pFET), the well region may include an N-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb), and the well region may be located at a predetermined depth from the upper surface of the first active pattern 105a and the upper surface of the second active pattern 105b.

[0024] Device isolation layer 110 can define active pattern 105 within substrate 101. Device isolation layer 110 can be formed, for example, by a shallow trench isolation (STI) process. Device isolation layer 110 can expose the upper surface of active pattern 105, and can also expose a portion of the upper part of active pattern 105. In some embodiments, device isolation layer 110 can have a curved upper surface such that its horizontal height is higher toward active pattern 105. Device isolation layer 110 can be formed of an insulating material. Device isolation layer 110 can include, for example, oxides, nitrides, or combinations thereof. Device isolation layer 110 can be located on two sidewalls of first active pattern 105a and two sidewalls of second active pattern 105b (e.g., can cover two sidewalls of first active pattern 105a and two sidewalls of second active pattern 105b and / or overlap with them). As used herein, "element A overlaps with element B in direction X" (or similar language) means that there is at least one straight line extending in direction X and intersecting both element A and element B.

[0025] The gate structure 160 may be disposed on the active pattern 105 and the channel structure 140 to extend in the second direction (Y direction) and intersect with the active pattern 105 and the channel structure 140. The gate structure 160 may include a first gate structure 160a and a second gate structure 160b, wherein the first gate structure 160a is spaced apart from each other in the first direction (X direction) and extends in the second direction (Y direction) in the first region R1, and the second gate structure 160b is spaced apart from each other in the first direction (X direction) and extends in the second direction (Y direction) in the second region R2.

[0026] The first gate structures 160a may be spaced apart from each other in a first direction (X direction) and may extend in a second direction (Y direction) within a first region R1, and the second gate structures 160b may be spaced apart from each other in the first direction (X direction) and may extend in a second direction (Y direction) within a second region R2. In some embodiments, the first gate structures 160a and the second gate structures 160b may have a third width W2 in the first direction (X direction). For example, the width of each first gate structure 160a in the first direction (X direction) may be equal to the width of each second gate structure 160b in the first direction (X direction). In some embodiments, the first separation distance between the first gate structures 160a (e.g., in the first direction (X direction)) may be substantially equal to the second separation distance between the second gate structures 160b (e.g., in the first direction (X direction)).

[0027] The active pattern 105 and / or channel structure 140 can form the functional channel region of the transistor. Each gate structure 160 may include a gate electrode 165, a gate dielectric layer 162 located between the gate electrode 165 and the first to fourth channel layers 141, 142, 143 and 144, a gate spacer layer 164 located on the side surface of the gate electrode 165, and a gate capping layer 167 extending on the gate electrode 165 in a second direction (Y direction).

[0028] The gate dielectric layer 162 may be disposed between the active pattern 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to be located on at least a portion of the surface of the gate electrode 165 (e.g., covering at least a portion of the surface of the gate electrode 165 and / or overlapping therewith). For example, the gate dielectric layer 162 may be located on all surfaces of the gate electrode 165 except for the uppermost surface of the gate electrode 165 (e.g., surrounding all surfaces of the gate electrode 165 except for the uppermost surface of the gate electrode 165). The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but is not limited thereto. The gate dielectric layer 162 may include oxides, nitrides, or high-κ materials. A high-κ material may refer to a dielectric material with a dielectric constant higher than that of silicon oxide (SiO2). High-κ materials can be, for example, alumina (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y At least one of praseodymium oxide (Pr₂O₃) or praseodymium oxide (Pr₂O₃). According to some embodiments, the gate dielectric layer 162 may be formed into a multilayer film.

[0029] The gate electrode 165 may be positioned on the active pattern 105 within the gaps between the first to fourth channel layers 141, 142, 143, and 144 (e.g., configured to fill these gaps) and may extend onto the channel structure 140. The gate electrode 165 may be separated from the first to fourth channel layers 141, 142, 143, and 144 by a gate dielectric layer 162. The gate electrode 165 may comprise a conductive material and may comprise, for example, metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or metallic materials such as aluminum (Al), tungsten (W), or molybdenum (Mo), or semiconductor materials such as doped polycrystalline silicon. According to some embodiments, the gate electrode 165 may be formed as two or more multilayers.

[0030] A gate spacer layer 164 may be disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. According to some embodiments, the gate spacer layer 164 may be formed as a multilayer structure. The gate spacer layer 164 may be formed of at least one of oxide, nitride, or oxynitride, and may be formed, for example, as a low-k film.

[0031] The gate capping layer 167 may extend along a second direction (Y direction) over the gate electrode 165 and the gate spacer layer 164. The gate capping layer 167 may include at least one of oxide, nitride, or oxide oxynitride.

[0032] Each first gate structure 160a may include a first gate electrode 165a, a first gate dielectric layer 162a located between the first gate electrode 165a and the first to fourth channel layers 141a, 142a, 143a and 144a, a first gate spacer layer 164a located on the side surface of the first gate electrode 165a, and a first gate capping layer 167a extending on the first gate electrode 165a in a second direction (Y direction).

[0033] Each second gate structure 160b may include a second gate electrode 165b, a second gate dielectric layer 162b located between the second gate electrode 165b and the first to fourth channel layers 141b, 142b, 143b and 144b, a second gate spacer layer 164b located on the side surface of the second gate electrode 165b, and a second gate capping layer 167b extending on the second gate electrode 165b along a second direction (Y direction).

[0034] In the region where the active pattern 105 intersects with the gate structure 160, a channel structure 140 may be disposed on the active pattern 105. The channel structure 140 may include a first channel structure 140a surrounded by a first gate structure 160a in a first region R1, and a second channel structure 140b surrounded by a second gate structure 160b in a second region R2. As used herein, it will be understood that “element A surrounds element B” (or similar language) means that element A is at least partially around element B, but does not necessarily mean that element A completely surrounds element B. In some embodiments, the first channel length of the first channel structure 140a extending in a first direction (X direction) may be substantially equal to the second channel length of the second channel structure 140b extending in the first direction (X direction). For example, the first channel length of the first channel structure 140a extending in the first direction (X direction) and the second channel length of the second channel structure 140b extending in the first direction (X direction) can be substantially equal to the third width W2 of the first gate structure 160a in the first direction (X direction) and the third width W2 of the second gate structure 160b in the first direction (X direction).

[0035] Each channel structure 140 may include first to fourth channel layers 141, 142, 143, and 144, which may be multiple channel layers spaced apart from each other in a third direction (Z direction). The first to fourth channel layers 141, 142, 143, and 144 may be sequentially arranged from top to bottom, with the first channel layer 141 being the uppermost channel layer. The channel structure 140 may be connected to the source / drain region 150. The channel structure 140 may have a width equal to or similar to the width of the gate structure 160 in the first direction (X direction) and may have a width equal to or less than the width of the active pattern 105 in the second direction (Y direction). In the cross-section in the second direction (Y direction) (e.g., see...), Figure 3In the first to fourth channel layers 141, 142, 143, and 144, the width of the channel layer disposed in the lower part can be equal to or greater than the width of the channel layer disposed in the upper part. The number and shape of the channel layers forming a channel structure 140 can be varied in embodiments. For example, a channel structure 140 may include three channel layers, two channel layers, or five or more channel layers. The channel layer disposed at the lowest horizontal level among multiple channel layers may be referred to as the lowermost channel layer. For example, when a channel structure 140 includes four channel layers, the fourth channel layer 144 may be the lowermost channel layer. In some embodiments different from the illustrated embodiments, when a channel structure 140 includes three channel layers, the third channel layer 143 disposed from the top may be referred to as the lowermost channel layer.

[0036] The channel structure 140 may be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge). The channel structure 140 may be formed of, for example, the same material as the active pattern 105. In some embodiments, the channel structure 140 may include an impurity region located in a region adjacent to the source / drain region 150.

[0037] The channel structure 140 may include a first channel structure 140a disposed in the first region R1 and a second channel structure 140b disposed in the second region R2.

[0038] The first channel structure 140a may include first to fourth channel layers 141a, 142a, 143a, and 144a, which may be multiple channel layers spaced apart from each other in a third direction (Z direction). The first channel structure 140a may be connected to a first source / drain region 150a. The first channel structure 140a may have a width equal to or similar to the width of the first gate structure 160a in the first direction (X direction), and may have a width equal to or less than the width of the first active pattern 105a in the second direction (Y direction).

[0039] The second channel structure 140b may include first to fourth channel layers 141b, 142b, 143b, and 144b, which may be multiple channel layers spaced apart from each other in a third direction (Z direction). The second channel structure 140b may be connected to the second source / drain region 150b. The second channel structure 140b may have a width equal to or similar to the width of the second gate structure 160b in the first direction (X direction), and may have a width equal to or less than the width of the second active pattern 105b in the second direction (Y direction).

[0040] The width of each first channel structure 140a in the first direction (X direction) may be equal to or similar to the width of each second channel structure 140b in the first direction (X direction). In some embodiments, the width of each first channel structure 140a in the second direction (Y direction) may be greater than the width of each second channel structure 140b in the second direction (Y direction). For example, the widths of the first to fourth channel layers 141a, 142a, 143a, and 144a in the second direction (Y direction) may be greater than the widths of the first to fourth channel layers 141b, 142b, 143b, and 144b in the second direction (Y direction).

[0041] The source / drain region 150 may include a first source / drain region 150a disposed in the first region R1 and a second source / drain region 150b disposed in the second region R2.

[0042] The first source / drain region 150a may be disposed between the first gate structures 160a and may be disposed in a recessed region that is partially recessed into the upper part of the first active pattern 105a. The recessed region may extend along the side surface of the first channel structure 140a and the side surface of the first gate dielectric layer 162a. The first source / drain region 150a may be configured to be located on the side surface of the first to fourth channel layers 141a, 142a, 143a and 144a of the first channel structure 140a in the first direction (X direction) (e.g., covering the side surface of the first to fourth channel layers 141a, 142a, 143a and 144a of the first channel structure 140a in the first direction (X direction) and / or overlapping them). The upper surface of the first source / drain region 150a may be located at a horizontal height equal to or higher than the lower surface of the first gate electrode 165a on the first channel layer 141a, and this horizontal height may be varied in different embodiments. The side surface of the first source / drain region 150a may have a curvature according to the first to fourth channel layers 141a, 142a, 143a and 144a and the first gate structure 160a.

[0043] The second source / drain region 150b may be disposed between the second gate structures 160b and may be disposed in a recessed region that is partially recessed into the upper part of the second active pattern 105b. The recessed region may extend along the side surface of the second channel structure 140b and the side surface of the second gate dielectric layer 162b. The second source / drain region 150b may be configured to be located on the side surface of the first to fourth channel layers 141b, 142b, 143b and 144b of the second channel structure 140b in the first direction (X direction) (e.g., covering the side surface of the first to fourth channel layers 141b, 142b, 143b and 144b of the second channel structure 140b in the first direction (X direction) and / or overlapping with them). The upper surface of the second source / drain region 150b may be located at a horizontal height equal to or higher than the lower surface of the second gate electrode 165b on the first channel layer 141b, and this horizontal height may be varied in different embodiments. The side surface of the second source / drain region 150b may have a curvature according to the first to fourth channel layers 141b, 142b, 143b and 144b and the second gate structure 160b. The specific shape of the side surface of the first source / drain region 150a and the specific shape of the side surface of the second source / drain region 150b may vary in different embodiments.

[0044] When viewed in a section in the second direction (Y direction) (for example, see...) Figure 4A The first source / drain region 150a may include a first extension 151a and a first extension portion 152a extending from the first extension 151a. The first extension portion 151a may contact the upper surface of the first active pattern 105a and may have a width equal to or similar to the width of the first active pattern 105a in a second direction (Y direction). For example, the first extension portion 151a may extend over the first active pattern 105a in a third direction (Z direction). The first extension portion 152a may extend from the first extension portion 151a and may have a width that increases and then decreases in an upward direction (e.g., in the third direction (Z direction)). For example, the first extension portion 152a may have a width in the second direction (Y direction) that increases and then decreases as it moves away from the substrate 101 in the third direction (Z direction).

[0045] When viewed in a section in the second direction (Y direction) (for example, see...) Figure 4AThe second source / drain region 150b may include a second extension 151b and a second extension portion 152b extending from the second extension portion 151b. The second extension portion 151b may contact the upper surface of the second active pattern 105b and may have a width equal to or similar to the width of the second active pattern 105b in the second direction (Y direction). For example, the second extension portion 151b may extend along a third direction (Z direction) on the second active pattern 105b. The second extension portion 152b may extend from the second extension portion 151b and may have a width that increases and then decreases in the upward direction. For example, the second extension portion 152b may have a width in the second direction (Y direction) that increases and then decreases as it moves away from the substrate 101 in the third direction (Z direction).

[0046] The width of the first extension portion 151a of the first source / drain region 150a in the second direction (Y direction) may be greater than the width of the second extension portion 151b of the second source / drain region 150b in the second direction (Y direction). In some embodiments, the first height H1 of the first extension portion 151a of the first source / drain region 150a in the third direction (Z direction) may be less than the second height H2 of the second extension portion 151b of the second source / drain region 150b in the third direction (Z direction).

[0047] The upper surface of the first source / drain region 150a may be disposed at substantially the same horizontal height as the upper surface of the second source / drain region 150b (i.e., substantially coplanar with the upper surface of the second source / drain region 150b). The upper surface of the first extension portion 152a of the first source / drain region 150a may be disposed at substantially the same horizontal height as the upper surface of the second extension portion 152b of the second source / drain region 150b. In some embodiments, each of the first extension portion 152a and the second extension portion 152b may have a ramp inflection point where the width increases and then decreases in the upward direction. The ramp inflection point of the first extension portion 152a may be disposed at a lower horizontal height than the ramp inflection point of the second extension portion 152b. In other words, the width of the first extension portion 152a may change from increasing to decreasing at a first point in the third direction (Z direction) as it moves away from the substrate 101, and the width of the second extension portion 152b may change from increasing to decreasing at a second point in the third direction (Z direction) as it moves away from the substrate 101. In some embodiments, the first point may be lower than the second point in the third direction (Z direction) relative to the substrate 101 (e.g., relative to the upper surface of the substrate 101).

[0048] The cross-sectional shape of the first extension 151a of the first source / drain region 150a and the second extension 151b of the second source / drain region 150b in the second direction (Y direction) can be rectangular, and the cross-sectional shape of the first extended portion 152a of the first source / drain region 150a and the second extended portion 152b of the second source / drain region 150b in the second direction (Y direction) can be hexagonal. In some embodiments, the cross-sectional area of ​​the first extended portion 152a of the first source / drain region 150a in the second direction (Y direction) can be larger than the cross-sectional area of ​​the second extended portion 152b of the second source / drain region 150b in the second direction (Y direction). In other words, when viewed along the second direction (Y direction) (e.g., see...), the cross-sectional area of ​​the first extended portion 152a of the first source / drain region 150a in the second direction (Y direction) can be larger. Figure 4A The cross-sectional area of ​​the first extension portion 152a may be larger than the cross-sectional area of ​​the second extension portion 152b (for example, see...). Figure 4A ).

[0049] The source / drain region 150 may include a semiconductor material, such as at least one of silicon (Si) or germanium (Ge). The source / drain region 150 may include epitaxial layers formed as multiple layers, and the multiple epitaxial layers may have different compositions. For example, the concentrations of non-silicon elements in the multiple epitaxial layers may differ from one another. The non-silicon elements may be, for example, germanium (Ge) and / or doping elements.

[0050] The source / drain region 150 may also include impurities. For example, when the semiconductor device 100 is a pFET, the impurity may be at least one of boron (B), gallium (Ga), or indium (In), while when the semiconductor device 100 is an nFET, the impurity may be at least one of phosphorus (P), arsenic (As), or antimony (Sb). According to an example embodiment, the source / drain region 150 may include multiple regions with different concentrations of elements and / or dopants.

[0051] The first fin spacer 155a may be disposed on the side surface of the first source / drain region 150a, may surround the first extension 151a, and may expose the first extension 152a. For example, the first fin spacer 155a may be located on the side surface of the first extension 151a, and the first fin spacer 155a may not be present on the side surface of the first extension 152a. In other words, the first extension 151a may have opposing side surfaces in the second direction (Y direction) with the first fin spacer 155a thereon, and the first extension 152a may have opposing side surfaces in the second direction (Y direction) without the first fin spacer 155a thereon. The first fin spacers 155a may be configured to be spaced apart from each other in the second direction (Y direction), but may surround the first extension 151a exposed in the second direction (Y direction). For example, the first fin spacer 155a may extend from the outer surface of the first extension 151a of the first source / drain region 150a to the upper surface of the device isolation layer 110. In other words, the first fin spacer 155a can extend from the side surface of the first extension 151a onto the device isolation layer 110. For example... Figure 1 and Figure 4A As shown, the first fin spacers 155a may be located on the device isolation layer 110 between the first gate structures 160a (e.g., in the first direction (X direction)). For example, the first fin spacers 155a may define a region in which a first extension 151a of the first source / drain region 150a is formed. The gap between the first fin spacers 155a in the second direction (Y direction) may be substantially equal to the first width W1a of the first active pattern 105a in the second direction (Y direction).

[0052] The second fin spacer 155b may be disposed on the side surface of the second source / drain region 150b, may surround the second extension 151b, and may expose the second extension 152b. For example, the second fin spacer 155b may be located on the side surface of the second extension 151b, and the second fin spacer 155b may not be present on the side surface of the second extension 152b. In other words, the second extension 151b may have opposing side surfaces in the second direction (Y direction) with the second fin spacer 155b thereon, and the second extension 152b may have opposing side surfaces in the second direction (Y direction) without the second fin spacer 155b thereon. The second fin spacers 155b may be spaced apart in the second direction (Y direction) and may surround the second extension 151b exposed in the second direction (Y direction). The second fin spacers 155b may extend from the outer surface of the second extension 151b of the second source / drain region 150b to the upper surface of the device isolation layer 110. In other words, the second fin spacer 155b can extend from the side surface of the second extension 151b onto the device isolation layer 110. For example... Figure 1 and Figure 4A As shown, the second fin spacers 155b may be located on the device isolation layer 110 between the second gate structures 160b (e.g., in the first direction (X direction)). The second fin spacers 155b may define a region in which a second extension 151b of the second source / drain region 150b is formed. The gap between the second fin spacers 155b in the second direction (Y direction) may be substantially equal to the second width W1b of the second active pattern 105b in the second direction (Y direction). In some embodiments, the gap between the second fin spacers 155b in the second direction (Y direction) may be smaller than the gap between the first fin spacers 155a in the second direction (Y direction). In other words, the distance between the first fin spacers 155a in the second direction (Y direction) may be greater than the distance between the second fin spacers 155b in the second direction (Y direction). For example, the first fin spacer 155a may be located on the opposite side of the first source / drain region 150a (e.g., in the second direction (Y direction)), and the second fin spacer 155b may be located on the opposite side of the second source / drain region 150b (e.g., in the second direction (Y direction)).

[0053] The height of each first fin spacer 155a may correspond to the height of the first extension 151a of the first source / drain region 150a (e.g., a first height H1), and the height of each second fin spacer 155b may correspond to the height of the second extension 151b of the second source / drain region 150b (e.g., a second height H2). In some embodiments, the height of each first fin spacer 155a may be less than the height of each second fin spacer 155b. The height of each first fin spacer 155a may be the length from the lower surface to the upper surface of each first fin spacer 155a along a third direction (Z direction). The height of each second fin spacer 155b may be the length from the lower surface to the upper surface of each second fin spacer 155b along a third direction (Z direction). Since the lower surface of the first fin spacer 155a may be positioned at substantially the same horizontal height as the lower surface of the second fin spacer 155b, the upper surface of the first fin spacer 155a may be positioned at a horizontal height lower than the horizontal height of the upper surface of the second fin spacer 155b.

[0054] Since a second fin spacer 155b, which is higher than the first fin spacer 155a disposed on the side surface of the first source / drain region 150a, can be disposed on the side surface of the second source / drain region 150b, so that the capacitance of the field-effect transistor in the second region R2 is kept low, the reliability and electrical characteristics of the low-power components disposed in the second region R2 can be ensured.

[0055] The area of ​​the outer surface of the first extension portion 152a of the first source / drain region 150a exposed by the first fin spacer 155a may be greater than the area of ​​the outer surface of the second extension portion 152b of the second source / drain region 150b exposed by the second fin spacer 155b.

[0056] The first fin spacer 155a and the second fin spacer 155b may comprise the same material as the gate spacer layer 164. In some embodiments, the first fin spacer 155a and the second fin spacer 155b may comprise oxides, nitrides, or combinations thereof. In some embodiments, the first fin spacer 155a and the second fin spacer 155b may be formed as low-k films and may comprise at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, SiOCN, or combinations thereof.

[0057] Interlayer insulating layer 170 may be located on device isolation layer 110 to cover source / drain regions 150 and contact plugs 180 (e.g., covering source / drain regions 150 and contact plugs 180 and / or overlapping them). For example, interlayer insulating layer 170 may be located on first fin spacer 155a, second fin spacer 155b, first extension 152a, second extension 152b, and device isolation layer 110. Interlayer insulating layer 170 may include at least one of oxide, nitride, or oxynitride, and may include, for example, a low-k material. According to some embodiments, interlayer insulating layer 170 may include multiple insulating layers.

[0058] The contact plug 180 can penetrate the interlayer insulating layer 170 (i.e., extend into the interlayer insulating layer 170), can connect to the source / drain region 150, and can apply an electrical signal to the source / drain region 150. The contact plug 180 can be recessed into the source / drain region 150 and can extend into the source / drain region 150. For example, the contact plug 180 can extend into the upper surface of the source / drain region 150. The contact plug 180 can extend from the top, for example, below the upper surface of the first channel layer 141. In some embodiments, the contact plug 180 can extend below the lower surface of the first channel layer 141.

[0059] The contact plug 180 may include a first contact plug 180a that penetrates the interlayer insulating layer 170 and is connected to a first source / drain region 150a, and a second contact plug 180b that penetrates the interlayer insulating layer 170 and is connected to a second source / drain region 150b. For example, the first contact plug 180a may be recessed into the first source / drain region 150a and may extend into the first source / drain region 150a. The second contact plug 180b may be recessed into the second source / drain region 150b and may extend into the second source / drain region 150b. In some embodiments, the length of the lower surface of the first contact plug 180a in the second direction (Y direction) may be greater than the length of the lower surface of the second contact plug 180b in the second direction (Y direction).

[0060] The semiconductor device according to the example embodiment may include a first region R1 in which a high-power field-effect transistor is disposed, and a second region R2 in which a low-power field-effect transistor is disposed. In the first region R1, a first active pattern 105a having a first width W1a and a first source / drain region 150a having a first extension 151a connected to the first active pattern 105a and surrounded by a first fin spacer 155a may be disposed. In the second region R2, a second active pattern 105b having a second width W1b smaller than the first width W1a and a second source / drain region 150b having a second extension 151b connected to the second active pattern 105b and surrounded by a second fin spacer 155b and having a height greater than the height of the first extension 151a may be disposed. Therefore, relatively low capacitance of the low-power field-effect transistors can be ensured, and thus a semiconductor device with improved reliability and electrical characteristics can be provided.

[0061] Figure 4B , Figure 4C and Figure 4D According to another embodiment along Figure 1 Cross-sectional views taken from lines IIIa-IIIa' and IIIb-IIIb'.

[0062] refer to Figure 4B The semiconductor device 100' may include a first source / drain region 150a' and a second source / drain region 150b'. In addition to Figure 4B Apart from the first source / drain region 150a' and the second source / drain region 150b' shown, the remaining configuration of the semiconductor device 100' can be... Figure 4A The configurations shown are the same or corresponding. Therefore, repeated descriptions of the same or corresponding configurations can be omitted.

[0063] The first source / drain region 150a' may include a first extension 151a disposed on the first active pattern 105a and a first extended portion 152a' extending from the first extension 151a. The second source / drain region 150b' may include a second extension 151b disposed on the second active pattern 105b and a second extended portion 152b' extending from the second extension 151b.

[0064] The cross-sectional shape of the first extension 151a of the first source / drain region 150a' and the second extension 151b of the second source / drain region 150b' in the second direction (Y direction) can be rectangular. The first extension 152a' of the first source / drain region 150a' and the second extension 152b' of the second source / drain region 150b' can have a curve in which the width increases and then decreases in the second direction (Y direction). For example, the side surfaces of the first extension 152a' of the first source / drain region 150a' and the second extension 152b' of the second source / drain region 150b' can have a curved shape (e.g., a rounded shape). In some embodiments, the first extension 152a' of the first source / drain region 150a' and the second extension 152b' of the second source / drain region 150b' can have a width in the second direction (Y direction) that increases and then decreases as it moves away from the substrate 101 in the third direction (Z direction). The cross-sectional area of ​​the first extension portion 152a' of the first source / drain region 150a' in the second direction (Y direction) can be greater than the cross-sectional area of ​​the second extension portion 152b' of the second source / drain region 150b' in the second direction (Y direction).

[0065] refer to Figure 4C The semiconductor device 100a may include a first fin spacer 155a' disposed on the side surface of the first source / drain region 150a and a second fin spacer 155b' disposed on the side surface of the second source / drain region 150b. In addition to Figure 4C Apart from the first fin spacer 155a' and the second fin spacer 155b' shown, the remaining configuration of the semiconductor device 100a can be... Figure 4A The configurations shown are the same or corresponding. Therefore, repeated descriptions of the same or corresponding configurations can be omitted. The first fin spacer 155a' may surround the first extension 151a of the first source / drain region 150a and may not extend to the upper surface of the device isolation layer 110, and the second fin spacer 155b' may surround the second extension 151b of the second source / drain region 150b and may not extend to the upper surface of the device isolation layer 110. For example, each first fin spacer 155a' and each second fin spacer 155b' may be spaced apart from each other in the second direction (Y direction) and may be arranged in a plate type.

[0066] refer to Figure 4D The semiconductor device 100b may include a first source / drain region 150a" and a second source / drain region 150b. In addition to Figure 4DApart from the first source / drain region 150a shown, the remaining configuration of the semiconductor device 100b can be... Figure 4A The configurations shown are the same or corresponding. Therefore, repeated descriptions of the same or corresponding configurations can be omitted. The first source / drain region 150a" may contact the upper surface of the first active pattern 105a and may have a width that increases and then decreases in the upward direction. For example, the first source / drain region 150a" may have a width that increases and then decreases in the second direction (Y direction) as it moves away from the substrate 101 in the third direction (Z direction). Since there may be no spacers on the side surface of the first source / drain region 150a", the side surface of the first source / drain region 150a" may be exposed from the device isolation layer 110 and may contact the interlayer insulating layer 170. The second source / drain region 150b may include a second extension 151b covered by the second fin spacer 155b and a second extension 152b extending from the second extension 151b, exposed from the second fin spacer 155b, and having a width that increases and then decreases in the upward direction.

[0067] Figure 5A and Figure 5B This is a view showing the electrical characteristics based on the width of the active pattern of semiconductor device 100 and the width of the active pattern of reference semiconductor device 300.

[0068] refer to Figure 5A and Figure 5B The first transistor 1001 may be a low-power field-effect transistor disposed in a second region R2 of a semiconductor device 100 according to some embodiments, and the reference transistor Ref may be a low-power field-effect transistor disposed in a second region R2 of a reference semiconductor device 300. The reference semiconductor device 300 may have a reference active pattern 105_ref, the width of which in the second direction (Y direction) is the same as the width of the second active pattern 105b of the semiconductor device 100 according to some embodiments in the second direction (Y direction), and the reference semiconductor device 300 may have a reference source / drain region 150_ref not surrounded by fin spacers. For example, the cross-sectional area of ​​the second source / drain region 150b of the semiconductor device 100 in the second direction (Y direction) may be smaller than the cross-sectional area of ​​the reference source / drain region 150_ref of the reference semiconductor device 300 in the second direction (Y direction).

[0069] refer to Figure 5B Figure (a) represents the resistance based on the width of the active pattern, Figure (b) represents the capacitance based on the width of the active pattern, Figure (c) represents the frequency based on the width of the active pattern, and Figure (d) represents the power based on the width of the active pattern.

[0070] refer to Figure 5B In the diagram (a), compared to the reference transistor Ref, the resistance of the first transistor 1001 increases more rapidly as the width of the second active pattern 105b decreases. (Reference) Figure 5B In pattern (b), compared to reference transistor Ref, the capacitance of the first transistor 1001 decreases faster as the width of the second active pattern 105b decreases. (Reference) Figure 5B In the pattern (c), the first transistor 1001 can have a frequency value similar to that of the reference transistor Ref, depending on the width of the second active pattern 105b. Reference Figure 5B As the width of the second active pattern 105b decreases, the first transistor 1001 can have a lower power value compared to the reference transistor Ref.

[0071] Figure 6A , Figure 6B , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 11 and Figure 12 This is a view illustrating the process sequence of a method for manufacturing a semiconductor device according to an embodiment. Specifically, Figure 6A , Figure 8A , Figure 9A , Figure 10A , Figure 11 and Figure 12 Showing with Figure 2 The corresponding cross-sectional view, and Figure 6B , Figure 7 , Figure 8B , Figure 9B , Figure 9C and Figure 10B Showing with Figure 4A The corresponding cross-sectional view.

[0072] refer to Figure 6A and Figure 6B The first to fourth channel layers 141, 142, 143 and 144 and the sacrificial layer 120 can be alternately stacked on the substrate 101, and an active structure including an active pattern 105 can be formed.

[0073] The sacrificial layer 120 can be a layer that can be replaced by the gate dielectric layer 162 and the gate electrode 165 below the first channel layer 141 through subsequent processes, such as... Figure 2 and Figure 3As shown. The sacrificial layer 120 may be formed of a material having etch selectivity relative to the first to fourth channel layers 141, 142, 143, and 144, respectively. The first to fourth channel layers 141, 142, 143, and 144 may include materials different from those of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 may include semiconductor materials (including at least one of silicon (Si), silicon germanium (SiGe), or germanium (Ge), for example), but may include different materials and may include impurities or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), while the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0074] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143 and 144 can be formed by performing an epitaxial growth process from the stacked structure. The number of channel layers stacked alternately with the sacrificial layer 120 can be varied in the embodiments.

[0075] refer to Figure 7 The sacrificial layer 120, the first to fourth channel layers 141, 142, 143 and 144 and the active pattern 105 can be partially removed to form a first active structure ASa including a first active pattern 105a and a second active structure ASb including a second active pattern 105b.

[0076] The first active structure ASa may include a first active pattern 105a, a sacrificial layer 120, and first to fourth channel layers 141a, 142a, 143a, and 144a, and the first active structure ASa may be formed, for example, in a straight line shape extending in a first direction (X direction). The second active structure ASb may include a second active pattern 105b, a sacrificial layer 120, and first to fourth channel layers 141b, 142b, 143b, and 144b. The second active structure ASb may be formed, for example, in a straight line shape extending in the first direction (X direction). The first active pattern 105a and the second active pattern 105b may be arranged side by side in the first direction (X direction), but may have different widths in the second direction (Y direction). The first active pattern 105a may have a first width in the second direction (Y direction), while the second active pattern 105b may have a second width in the second direction (Y direction) that is smaller than the first width. The etching mask 10 may be disposed on the upper surface of the first channel layer 141 and may be formed as multiple layers, and may include, for example, a first etching mask layer formed of polysilicon and a second etching mask layer formed of nitride on the first etching mask layer.

[0077] In the regions where a portion of each of the first active pattern 105a, the second active pattern 105b, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144 is removed, insulating material may be buried, and then a portion of the insulating material may be removed such that the first active pattern 105a and the second active pattern 105b can protrude to form the device isolation layer 110. The upper surface of the device isolation layer 110 may be formed to be lower than the upper surface of the first active pattern 105a and the upper surface of the second active pattern 105b.

[0078] refer to Figure 8A and Figure 8B It can form a sacrificial gate structure 200 located on the first active structure ASa and the second active structure ASb, a gate spacer layer 164 located on the sacrificial gate structure 200 (e.g., covering the sacrificial gate structure 200 and / or overlapping it), and a first preliminary spacer 155Pa and a second preliminary spacer 155Pb located on the first active structure ASa and the second active structure ASb (e.g., covering the first active structure ASa and the second active structure ASb and / or overlapping them).

[0079] The sacrificial gate structure 200 may be located in the region of the channel structure 140 formed by a subsequent process between the gate dielectric layer 162 and the gate electrode 165 (e.g., Figure 2 and Figure 3 The sacrificial structure formed (as shown). For example... Figure 2 , Figure 8A and Figure 8B As shown, the sacrificial gate structure 200 may not be formed in the regions where the first source / drain region 150a and the second source / drain region 150b are to be formed. The sacrificial gate structure 200 may be a straight line extending in a second direction (Y direction) intersecting the first active structure ASa and the second active structure ASb. The sacrificial gate structures 200 may extend in the second direction (Y direction), for example, and may be configured to be spaced apart from each other in the first direction (X direction).

[0080] The sacrificial gate structure 200 may include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 sequentially stacked, and a mask patterning layer 206. The mask patterning layer 206 may be used to pattern the first sacrificial gate layer 202 and the second sacrificial gate layer 205. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask patterning layer 206 may include silicon oxide and / or silicon nitride.

[0081] The gate spacer layer 164 can be formed to conformally extend on the upper surface of the first channel layer 141 and the upper and side surfaces of the sacrificial gate structure 200 (e.g., to conformally cover the upper surface of the first channel layer 141 and the upper and side surfaces of the sacrificial gate structure 200). The first preliminary spacer 155Pa can be formed to conformally extend on the first active structure ASa (e.g., to conformally cover the first active structure ASa), and the second preliminary spacer 155Pb can be formed to conformally extend on the second active structure ASb (e.g., to conformally cover the second active structure ASb). The gate spacer layer 164, the first preliminary spacer 155Pa, and the second preliminary spacer 155Pb can be formed using the same process. For example, when depositing insulating material to form gate spacer layer 164, the insulating material may be formed on the first active structure ASa and the second active structure ASb (e.g., covering the first active structure ASa and the second active structure ASb and / or overlapping with them) to form first preliminary spacer 155Pa and second preliminary spacer 155Pb.

[0082] refer to Figure 9A The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143 and 144 exposed from the sacrificial gate structure 200 can be partially removed to form the recessed region RC.

[0083] Using the sacrificial gate structure 200 and the gate spacer layer 164 as a mask, a recessed region RC can be formed by removing a portion of the sacrificial layer 120 and portions of the first to fourth channel layers 141, 142, 143, and 144. As a result, the first to fourth channel layers 141, 142, 143, and 144 can form a channel structure 140 with a finite length in the first direction (X direction). In some embodiments different from the illustrated embodiment, the side surface of the sacrificial layer 120 can be selectively etched relative to the channel structure 140 using a wet etching process, and can be removed from the side surface to a predetermined depth in the first direction (X direction). Therefore, as described above, the sacrificial layer 120 can have an inwardly recessed side surface by lateral etching. The specific shape of the side surface of the sacrificial layer 120 is not limited to... Figure 9A The shape shown.

[0084] Figure 9B This illustrates a method for manufacturing according to an embodiment. Figure 4A A cross-sectional view of the method for the first fin spacer 155a and the second fin spacer 155b.

[0085] refer to Figure 9B A portion of the first active structure ASa and a portion of the first preliminary spacer 155Pa (see Figure 8B) can be removed to form the recessed region RC, and a portion of the second active structure ASb and a portion of the second initial spacer 155Pb (see Figure 8B The spacers 155a and 155pb can be removed to form the recessed region RC. For example, due to the etching process of the first active structure ASa, the first preliminary spacer 155Pa located on the first active structure ASa (e.g., covering the first active structure ASa and / or overlapping it) can be partially removed to form the first fin spacer 155a, and due to the etching process of the second active structure ASb, the second preliminary spacer 155Pb located on the second active structure ASb (e.g., covering the second active structure ASb and / or overlapping it) can be partially removed to form the second fin spacer 155b. The height of the first fin spacer 155a can be lower than the height of the second fin spacer 155b. For example, the height to which the first preliminary spacer 155Pa is removed can be greater than the height (or amount) to which the second preliminary spacer 155Pb is removed.

[0086] The height difference between the first fin spacer 155a and the second fin spacer 155b can be due to an etch loading effect. For example, since the width of the first active structure ASa in the second direction (Y direction) can be greater than the width of the second active structure ASb in the second direction (Y direction), the etching rate for the first preliminary spacer 155Pa can be faster than the etching rate for the second preliminary spacer 155Pb. Therefore, the height of the first fin spacer 155a can be lower than the height of the second fin spacer 155b.

[0087] Figure 9C This illustrates a method for manufacturing according to another embodiment. Figure 4A A cross-sectional view of the method for the first fin spacer 155a and the second fin spacer 155b.

[0088] refer to Figure 9C In the state of forming a mask MK located on the second active structure ASb (e.g., covering the second active structure ASb and / or overlapping it), the first active structure ASa and the first preliminary spacer 155Pa located on the first active structure ASa (e.g., covering the first active structure ASa and / or overlapping it) can be partially removed (see Figure 8B This process forms the recessed region RC and the first fin spacer 155a. Although not shown, after forming the first fin spacer 155a, while a mask MK is formed on (e.g., covering and / or overlapping) the first fin spacer 155a, the second active structure ASb and the second preliminary spacer 155Pb on (e.g., covering and / or overlapping) the second active structure ASb can be partially removed to form... Figure 9B The recessed area RC and the second fin spacer 155b.

[0089] refer to Figure 10A and Figure 10B , can Figure 9A and Figure 9B Source / drain regions 150 are formed in the recessed region RC, and an interlayer insulating layer 170 is located on the sacrificial gate structure 200 and the source / drain regions 150 (e.g., covering the sacrificial gate structure 200 and the source / drain regions 150 and / or overlapping them).

[0090] It can be achieved by selective epitaxy on the upper surface of the first active pattern 105a between the first fin spacers 155a and from the first channel structure 140a (see...) Figure 2 The first source / drain region 150a is formed by growing on the side surface of the second active pattern 105b between the second fin spacers 155b and from the second channel structure 140b (see [link to documentation]). Figure 2 The first source / drain region 150a is formed by growing on the side surface of the first active pattern 105a to form a second source / drain region 150b. The first source / drain region 150a may be formed including a first extension portion 151a and a first extension portion 152a. The first extension portion 151a is disposed between the upper surface of the first active pattern 105a and the first fin spacer 155a located on the device isolation layer 110. The first extension portion 152a extends from the first extension portion 151a and has a width that increases in the upward direction and then decreases. The second source / drain region 150b may be formed including a second extension portion 151b and a second extension portion 152b. The second extension portion 151b is disposed between the upper surface of the second active pattern 105b and the second fin spacer 155b located on the device isolation layer 110. The second extension portion 152b extends from the second extension portion 151b and has a width that increases in the upward direction and then decreases. In some embodiments, the source / drain region 150a may include a plurality of epitaxial layers. The epitaxial layer included in the source / drain region 150 may include impurities through in-situ doping and may have different compositions and / or doping concentrations.

[0091] An interlayer insulating layer 170 can be formed by forming an insulating film on the sacrificial gate structure 200 and the source / drain region 150 (e.g., covering the sacrificial gate structure 200 and the source / drain region 150 and / or overlapping them) and performing a planarization process.

[0092] refer to Figure 11 The sacrificial gate structure 200 and the sacrificial layer 120 can be removed.

[0093] The sacrificial gate structure 200 and the sacrificial layer 120 can be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 170, and the channel structure 140. First, the sacrificial gate structure 200 can be removed to form the upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR can be removed to form the lower gap region LR. For example, when the sacrificial layer 120 comprises silicon germanium (SiGe) and the channel structure 140 comprises silicon (Si), the sacrificial layer 120 can be selectively removed relative to the channel structure 140 and the source / drain region 150 by performing a wet etching process.

[0094] refer to Figure 12 The gate structure 160 can be formed by forming a gate dielectric layer 162, a gate electrode 165, and a gate capping layer 167.

[0095] The gate dielectric layer 162 and the gate electrode 165 can be formed within the upper gap region UR and the lower gap region LR (e.g., filling the upper gap region UR and the lower gap region LR). The gate dielectric layer 162 can be formed to conformally extend on the inner surfaces of the upper gap region UR and the lower gap region LR (e.g., conformally covering the inner surfaces of the upper gap region UR and the lower gap region LR). The gate electrode 165 can be formed to be completely located within the upper gap region UR and the lower gap region LR (e.g., completely filling the upper gap region UR and the lower gap region LR), and can then be removed from the upper gap region UR to a predetermined depth together with the gate dielectric layer 162 and the gate spacer layer 164. The gate capping layer 167 can be formed to extend along a second direction (Y direction) on the gate electrode 165 and the gate spacer layer 164.

[0096] Return to reference Figure 2 and Figure 4A The source / drain region 150 can be partially removed from the top through the interlayer insulating layer 170 to form a contact hole, and the contact hole can then be filled with a conductive material to form a contact plug 180. For example, the contact plug 180 can extend into the upper surface of the source / drain region 150. Therefore, it is possible to manufacture... Figure 1 , Figure 2 , Figure 3 and Figure 4A Semiconductor device 100. Although not specifically shown, a metal interconnect electrically connected to the contact plug 180 may be formed on the contact plug 180.

[0097] A semiconductor device according to an example embodiment may include a first source / drain region located on a first active pattern having a first width and a second source / drain region located on a second active pattern having a second width less than the first width. It may also include a first fin spacer having a first height on the outer wall of the first source / drain region and a second fin spacer having a second height on the outer wall of the second source / drain region, the second height being greater than the first height. Therefore, a semiconductor device with improved reliability and electrical characteristics can be provided.

[0098] The effects of this invention are not limited to those described above, and can be extended in different ways without departing from the scope of this invention.

[0099] As used herein, the terms “comprising,” “including,” “containing,” “having,” “comprising,” “having,” and any other variations thereof indicate the presence of the stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. Furthermore, it will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element can be referred to as a first element. Moreover, as used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerated items.

[0100] Although exemplary embodiments have been described and illustrated above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate comprising a first active pattern and a second active pattern, the first active pattern extending in a first direction and having a first width in a second direction that intersects the first direction, the second active pattern extending in the first direction and having a second width in the second direction that is less than the first width; first gate structures on the first active pattern, spaced apart from one another in the first direction and extending along the second direction; second gate structures on the second active pattern, spaced apart from one another in the first direction and extending along the second direction; first source / drain regions on the first active pattern between the first gate structures; second source / drain regions on the second active pattern between the second gate structures; first fin spacers on side surfaces of the first source / drain regions; and second fin spacers on side surfaces of the second source / drain regions, wherein a height of the first fin spacers in a third direction that intersects the first and second directions is less than a height of the second fin spacers in the third direction. a width of each of the first gate structures in the first direction is equal to a width of each of the second gate structures in the first direction.

2. The semiconductor device of claim 1, wherein, a first separation distance between the first gate structures in the first direction is equal to a second separation distance between the second gate structures in the first direction.

3. The semiconductor device of claim 1, wherein, each of the first gate structures and each of the second gate structures comprises a gate electrode and a gate spacer layer on side surfaces of the gate electrode, and 4. The semiconductor device of claim 1, wherein, wherein the gate spacer layer comprises a same material as the first and second fin spacers. the first source / drain regions comprise first extension portions extending along the third direction on the first active pattern and having a third width in the second direction and first extension portions extending from the first extension portions, 5. The semiconductor device of claim 1, wherein, wherein the second source / drain regions comprise second extension portions extending along the third direction on the second active pattern and having a fourth width in the second direction that is less than the third width and second extension portions extending from the second extension portions, and wherein the first and second extension portions each have a width in the second direction that increases and then decreases as moving away from the substrate in the third direction. the first fin spacers are on side surfaces of the first extension portions and there are no first fin spacers on side surfaces of the first extension portions, and 6. The semiconductor device of claim 5, wherein, wherein the second fin spacers are on side surfaces of the second extension portions and there are no second fin spacers on side surfaces of the second extension portions. ​ 7. The semiconductor device of claim 5, further comprising a device isolation layer on opposite sides of the first active pattern and on opposite sides of the second active pattern, wherein the first fin spacer extending from a side surface of the first extended portion of the first source / drain region onto the device isolation layer, and wherein the second fin spacer extends from a side surface of the second extended portion of the second source / drain region onto the device isolation layer.

8. The semiconductor device of claim 7, further comprising an interlayer insulating layer on the first fin spacer, the second fin spacer, the first extension portion, the second extension portion, and the device isolation layer.

9. The semiconductor device of claim 1, further comprising: a further first fin spacer on the first source / drain region opposite the first fin spacer; and a further second fin spacer on the second source / drain region opposite the second fin spacer, wherein a first distance between the first fin spacer and the further first fin spacer in the second direction is greater than a second distance between the second fin spacer and the further second fin spacer in the second direction.

10. The semiconductor device of claim 1, further comprising: a first contact plug extending into an upper surface of the first source / drain region and electrically connected to the first source / drain region; and a second contact plug extending into an upper surface of the second source / drain region and electrically connected to the second source / drain region, wherein a first length of a lower surface of the first contact plug in the second direction is greater than a second length of a lower surface of the second contact plug in the second direction. the first active pattern and the second active pattern are adjacent to each other in the first direction.

12. The semiconductor device of claim 1, further comprising:

11. The semiconductor device of claim 1, wherein, a first channel structure on the first active pattern, comprising a plurality of first channel layers spaced apart from each other in the third direction and at least partially surrounded by a respective one of the first gate structures; and a second channel structure on the second active pattern, comprising a plurality of second channel layers spaced apart from each other in the third direction and at least partially surrounded by a respective one of the second gate structures, wherein a lowermost one of the plurality of first channel layers has a fifth width in the second direction, and wherein a lowermost one of the plurality of second channel layers has a sixth width in the second direction that is less than the fifth width.

13. A semiconductor device, comprising: a substrate; ​ ​ ​ a first active pattern extending in a first direction on the substrate and having a first width in a second direction that intersects the first direction; a second active pattern extending in the first direction on the substrate and having a second width in the second direction that is less than the first width; a first gate structure extending in the second direction on the first active pattern; a second gate structure extending in the second direction on the second active pattern; a first source / drain region on the first active pattern between the first gate structures; and a second source / drain region on the second active pattern between the second gate structures, wherein the first source / drain region includes a first extension in contact with an upper surface of the first active pattern and a first extension portion extending from the first extension, the first extension portion having a width in the second direction that increases and then decreases as moving away from the substrate in a third direction that intersects the first and second directions, wherein the second source / drain region includes a second extension in contact with an upper surface of the second active pattern and a second extension portion extending from the second extension, the second extension portion having a width in the second direction that increases and then decreases as moving away from the substrate in the third direction, and wherein a height of the first extension in the third direction is less than a height of the second extension in the third direction.

14. The semiconductor device of claim 13, further comprising: a first fin spacer at least partially surrounding the first extension of the first source / drain region; and a second fin spacer at least partially surrounding the second extension of the second source / drain region. at least one of the first gate structure or the second gate structure includes a gate electrode and a gate spacer layer on side surfaces of the gate electrode, and wherein the gate spacer layer includes a same material as the first fin spacer and the second fin spacer.

15. The semiconductor device of claim 14, wherein, a third width of the first extension of the first source / drain region in the second direction is greater than a fourth width of the second extension of the second source / drain region in the second direction. the width of the first extension portion of the first source / drain region transitions from increasing to decreasing in the third direction at a first point as moving away from the substrate, 16. The semiconductor device of claim 13, wherein, wherein the width of the second extension portion of the second source / drain region transitions from increasing to decreasing in the third direction at a second point as moving away from the substrate, and 17. The semiconductor device of claim 13, wherein, wherein the first point is lower than the second point in the third direction relative to an upper surface of the substrate. ​ ​ 18. The semiconductor device of claim 13, wherein, The first source / drain region is spaced apart from the second source / drain region in the first direction.

19. A semiconductor device, comprising: a substrate including a first active pattern and a second active pattern, the first active pattern extending in a first direction and having a first width in a second direction that intersects the first direction, the second active pattern extending in the first direction and having a second width in the second direction that is less than the first width; a device isolation layer on the substrate and on two opposing side surfaces of the first active pattern and two opposing side surfaces of the second active pattern; first gate structures on the first active pattern, spaced apart from each other in the first direction, and extending along the second direction; second gate structures on the second active pattern, spaced apart from each other in the first direction, and extending along the second direction; first fin spacers on the device isolation layer between the first gate structures; second fin spacers on the device isolation layer between the second gate structures; first source / drain regions on the first active pattern between the first fin spacers; and second source / drain regions on the second active pattern between the second fin spacers, wherein a width of each of the first gate structures in the first direction is equal to a width of each of the second gate structures in the first direction, wherein a first portion of the first source / drain regions is free of the first fin spacers on opposing side surfaces thereof in the second direction, and a second portion of the second source / drain regions is free of the second fin spacers on opposing side surfaces thereof in the second direction, and wherein a cross-sectional area of the first portion of the first source / drain regions is greater than a cross-sectional area of the second portion of the second source / drain regions when viewed along the second direction.

20. The semiconductor device of claim 19, wherein, The first fin spacers are spaced apart from each other in the second direction, and the second fin spacers are spaced apart from each other in the second direction.

Images