Semiconductor device including high voltage device

Abstract

A semiconductor device (500) includes a high voltage device (510). The high voltage device includes a central region (200) having a first inner region (210). The termination region (300) laterally surrounds the central region (200) and includes a first extension region (310). A first extension region (310) is formed between the first inner region (210) and the first outer region (410). The lightly doped base portion (115) and the first extension region (310) form a pn junction. The central region (200) further comprises a second inner region (220) wherein the second inner region (220) and the first inner region (210) are laterally separated and connected to different inner contact structures (211, 221). Alternatively or additionally, the high voltage device (510) further comprises a second outer region (420), where the first outer region (410) and the second outer region (420) are laterally separated and connected to different outer contact structures (411, 421).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices having a high-voltage semiconductor element with a termination region. Examples of this disclosure relate to gate driver circuits having an active high-voltage semiconductor element electrically connected between a high-voltage portion and a low-voltage portion. Background Technology

[0002] High-voltage semiconductor devices employing CMOS (Complementary Metal-Oxide-Semiconductor) technology form an interface between standard CMOS devices with input voltages up to 5V and industrial or consumer circuits operating at signal voltage levels above 30V. Applications of such semiconductor devices exist in various types of power conversion and electrical drives ranging up to kV, for example, in power converters, robotics, and the automotive industry. High-voltage semiconductor devices typically comprise a low-voltage section operating in a low-voltage domain and a high-voltage section operating in a high-voltage domain. In the low-voltage section, most signal processing is performed at a low operating voltage. The high-voltage section operates at a higher voltage level. The low-voltage and high-voltage sections provide a signal interface for power semiconductors using higher voltage levels and / or with higher current drive and absorption capabilities. The potentials in different voltage domains can differ by hundreds of volts to approximately one thousand volts. An example of such a high-voltage semiconductor device is a gate driver circuit. Gate driver circuits enable microcontrollers or DSPs (Digital Signal Processors) to efficiently turn power semiconductor switches on and off. Such semiconductor devices include high-voltage semiconductor elements for exchanging power and / or electrical signals between CMOS circuits in different voltage domains.

[0003] In semiconductor devices with HV semiconductor elements, there is always a need to improve signal transmission with minimal additional effort. Summary of the Invention

[0004] High-voltage semiconductor devices typically include a large potential transition region formed between a first doped region associated with a low-voltage portion and a second doped region associated with a high-voltage portion. LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) includes a drain extension region extending into the potential transition region, wherein the drain extension region is not necessarily laterally diffused, but can also be formed by shallow ion implantation. HV diodes include an anode extension region extending into the potential transition region. This extension region can increase the parasitic capacitance of the HV semiconductor device and the semiconductor volume from which leakage current can be collected.

[0005] This disclosure relates to a semiconductor device including a high-voltage device. The high-voltage device includes a central region comprising a first internal region. A termination region (potential transition region) laterally surrounds the central region and includes a first extension region. The first extension region is formed between the first internal region and a first external region. A lightly doped substrate portion and the extension region form a semiconductor junction. According to alternative (a), the central region further includes a second internal region, wherein the first internal region and the second internal region are laterally separated and connected to different internal contact structures. According to alternative (b), the high-voltage device further includes a second external region, wherein the first external region and the second external region are laterally separated and connected to different external contact structures. Alternatives (a) and (b) can be combined.

[0006] When the internal contact structure is connected to the second internal region and / or the external contact structure is connected to the second external region, only the portion of the potential transition region including the first extended region contributes to the parasitic capacitance of the semiconductor element. The signal transmission rate between the low-voltage and high-voltage portions can be improved. Additionally, the junction volume from which the HV semiconductor element collects leakage current can be reduced. The internal contact structure connected to the second internal region and / or the external contact structure connected to the second external region form an idler device that includes a redundant portion of the potential transition region and protects the HV semiconductor element from the adverse effects of the redundant portion.

[0007] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0008] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which the same reference numerals denote similar or identical elements. The elements in the drawings are not necessarily proportional to each other. Features of the various illustrated examples can be combined unless they exclude each other.

[0009] Figure 1A and Figure 1B This includes schematic horizontal and vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device including an HV semiconductor diode and an idler device.

[0010] Figure 1C and Figure 1D Includes schematic horizontal and vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device including an HV semiconductor diode, an idler device, and additional contacts for the idler device.

[0011] Figures 2A to 2CIncludes a schematic horizontal cross-sectional view and two schematic vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device comprising two HV semiconductor diodes in a back-to-back configuration.

[0012] Figure 3A and Figure 3B The diagram includes schematic horizontal and vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device comprising an n-channel LDMOS in an adrain-inside and back-to-back configuration.

[0013] Figures 4A to 4C Includes a schematic horizontal cross-sectional view and two schematic vertical cross-sectional views of a portion of a semiconductor device according to another embodiment involving a high-voltage device comprising two LDMOS devices in a back-to-back configuration with their drains embedded.

[0014] Figure 5 This is a schematic horizontal cross-sectional view of a portion of a semiconductor device according to an embodiment involving a high-voltage device comprising three LDMOS in a drain-embedded configuration.

[0015] Figures 6A to 6C Includes a schematic horizontal cross-sectional view and two schematic vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device comprising a p-channel LDMOS in a source-embedded back-to-back configuration.

[0016] Figure 7A and Figure 7B The diagram includes schematic horizontal and vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device including an HV semiconductor diode in a cathode-embedded configuration.

[0017] Figure 8A and Figure 8B The diagram includes schematic horizontal and vertical cross-sectional views of a portion of a semiconductor device according to an embodiment involving a high-voltage device comprising an HV semiconductor diode in an anode-embedded configuration.

[0018] Figure 9 According to the implementation method, it includes Figure 8A / Figure 8B A simplified circuit diagram of the bootstrap circuit of the HV semiconductor diode.

[0019] Figure 10 This is a schematic vertical cross-sectional view of a portion of a semiconductor device according to another embodiment of a high-voltage device involving a field plate.

[0020] Figure 11 It is shown Figure 10 Timing diagrams of the switching response of the HV semiconductor diode and the leakage current and blocking voltage of the comparative example used to discuss the effects of the implementation.

[0021] Figure 12 This is a schematic block diagram of an LDMOS having a gate driver circuit for transmitting differential data signals from the high-side portion to the low-side portion and from the low-side portion to the high-side portion, according to an embodiment. Detailed Implementation

[0022] The terms “having,” “containing,” “including,” “comprising,” etc., are open-ended and indicate the presence of certain structures, elements, or features, but do not exclude the presence of additional elements or features. Unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” include both the plural and singular forms.

[0023] The terms "signal connection" and "electrical coupling" refer to permanent low-resistance ohmic connections between electrically connected elements, such as direct contact between related elements or low-resistance connections via metals and / or heavily doped semiconductor materials, but do not exclude the presence of additional passive and / or active elements in the signal path between "signal connection" or "electrical coupling" elements. For example, additional elements may include resistors, resistive conductors, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, etc.

[0024] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30V (e.g., 48V, 100V, 600V, 1.6kV, 3.3kV or higher) and a nominal on-state current or forward current of at least 200mA (e.g., 1A, 10A or higher).

[0025] An ohmic contact describes a non-rectifying electrical junction between two conductors (e.g., between a semiconductor and a metal). Similar to Ohm's law, an ohmic contact exhibits a linear or approximately linear current-voltage (IV) curve in the first and third quadrants of an IV diagram.

[0026] The range given for physical dimensions includes boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value, such as "at most" and "at least".

[0027] The term “on” should not be interpreted as simply “directly on”. Rather, if an element is “on” another element (e.g., a layer is “on” another layer or a substrate), then additional components (e.g., additional layers) may be located between the two elements (e.g., if a layer is “on” a substrate, then additional layers may be located between that layer and the substrate).

[0028] Two adjacent doped regions in a semiconductor layer form a semiconductor junction. Two adjacent doped regions with the same conductivity type but different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction, along the boundary surface between them. At the unipolar junction, the dopant concentration distribution orthogonal to the unipolar junction can exhibit a step or inflection point where the dopant concentration distribution changes from concave to convex, or vice versa. Two adjacent doped regions with complementary conductivity form a pn junction.

[0029] The accompanying diagram illustrates relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" indicates a doping concentration lower than that of the "n" doped region, while "n+" indicates a doping concentration higher than that of the "n" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations.

[0030] The examples described herein provide semiconductor devices including high-voltage devices. The high-voltage device may include a central region comprising a first inner region. A termination region may laterally surround the central region and may include a first extension region formed between the first inner region and a first outer region. A lightly doped substrate portion and the extension region may form a semiconductor junction. According to alternative (a), the central region further includes a second inner region, wherein the first and second inner regions may be laterally separated and connected to different internal contact structures. According to alternative (b), the HV semiconductor device further includes a second outer region, wherein the first and second outer regions may be laterally separated and connected to different outer contact structures. Alternatives (a) and (b) may be combined with each other.

[0031] The semiconductor regions of an HV semiconductor device, such as a first inner region and a second inner region, an extension region, and a first outer region and a second outer region, are doped regions formed in a semiconductor layer with homogeneous background doping. The semiconductor layer has a flat first surface on the front side and a flat second surface on the back side. The semiconductor layer can be formed of single-crystal silicon or other elemental semiconductors or compound semiconductors. The first and second surfaces are formed in parallel horizontal planes. The vertical orientation is orthogonal to the horizontal planes. The first inner region, the second inner region, the first outer region, and the second outer region can extend from the flat first surface into the semiconductor layer.

[0032] The substrate portion is formed between a first inner region, a second inner region, a first extended region, a first outer region, and a second outer region located on a first side, and a second surface located on the other side. The semiconductor junction between the lightly doped substrate portion and the extended region can be a pn junction or a unipolar junction, such as an n- / n or p- / p junction.

[0033] The central region may include additional internal regions of additional HV semiconductor elements. The terminal region may include additional extended regions of additional HV semiconductor elements, and the high-voltage device may include additional external regions of additional HV semiconductor elements.

[0034] High-voltage devices can be combined high-voltage devices comprising one or more HV semiconductor elements (e.g., one or more semiconductor diodes, one or more LDMOS, one or more BJTs and / or one or more JFETs) and one or more parasitic devices (idle devices) without any function. The termination region is a potential transition region and is capable of blocking relatively high voltages greater than 30V, 100V, or 600V between the first conductive structure in the central region and the second conductive structure formed outside the termination region.

[0035] The first extension region may be shallower than the first inner region and the first outer region. The first extension region may extend from a flat first surface into the semiconductor layer, or it may be vertically separated from the first surface. For example, a RESURF (reduced surface field) layer with a conductivity type complementary to that of the extension region may be formed between the first surface and the first extension region. The RESURF layer can vertically separate the first extension region from the first surface. In the lateral direction, the first extension region may extend from the first inner region to the first outer region. The first extension region may form a lateral unipolar junction with one of the first inner region and the first outer region, and may form a pn junction with the other of the first inner region and the first outer region.

[0036] The lateral spacing between the first and second inner regions and / or between the first and second outer regions can reduce the portion of the semiconductor volume from which leakage current of the HV semiconductor element of the high-voltage device can be collected and / or contribute to the parasitic capacitance of the HV semiconductor element. Additional contacts can dissipate a portion of the leakage current and / or fix the potential of the decoupling portion of the parasitic capacitance.

[0037] According to the implementation method, the maximum vertical extension vmax of the first inner region, the second inner region, and the first outer region can be less than the vertical extension v0 of the semiconductor layer.

[0038] The substrate portion can separate the first internal region, the second internal region, the first external region, and the additional doped region from the semiconductor layer and the back surface opposite the front side.

[0039] According to an embodiment, the high-voltage device includes a peripheral region comprising a terminal region and a first outer region, wherein the peripheral region has a radial width w0, and the radial width w0 may be constant along the periphery surrounding the center.

[0040] For example, the external isolation trench structure can laterally surround the semiconductor region of the high-voltage device. The peripheral region extends outward from the central region to the external isolation trench structure. For high-voltage devices with blocking capabilities in the range of 50V to 600V, the radial width w0 can range from 5μm to 100μm. The peripheral region may include additional external regions of other high-voltage semiconductor elements.

[0041] According to the implementation method, the first internal region and the first internal contact structure can form an ohmic contact, and the second internal region and the second internal contact structure can form an ohmic contact.

[0042] The first internal contact structure and the second internal contact structure may be composed of or include doped polysilicon, elemental metal, metal alloy or metal compound.

[0043] According to the implementation, the internal separation structure can laterally separate the first internal region and the second internal region, and / or the external separation structure can laterally separate the first external region and the second external region.

[0044] The internal separation structure may include a pn junction, a doped region having a conductivity type opposite to that of the first and second internal regions, a trench structure comprising an insulating material, or a combination thereof. The external separation structure may include a pn junction, a doped region having a conductivity type opposite to that of the first and second external regions, a trench structure comprising an insulating material, or a combination thereof.

[0045] According to an embodiment, the internal separation structure may include an internal separation region having a conductivity type complementary to that of the first internal region and the second internal region, and / or the external separation structure may include an external separation region, wherein the external separation region and the first external region have complementary conductivity types.

[0046] For example, the internal separation region and / or external separation region may be or include a doped region formed by implanting a dopant and diffusing and activating the implanted dopant. Alternatively, a segment of the substrate portion extending from the first surface into the semiconductor layer between the first internal region and the second internal region and / or between the first external region and the second external region may form an internal separation structure or an external separation structure.

[0047] According to an embodiment, the internal separation structure may include an internal separation trench structure extending from a first surface into a semiconductor layer including a first internal region and a second internal region, and / or the external separation structure may include an external separation trench structure extending from the first surface into a semiconductor layer.

[0048] The internal and / or external separation trench structures can be or include thermally grown shallow trench oxides or field oxides, or trenches containing trench fillers. The trench fillers can include homogeneous insulating fillers or insulating liners, and filler materials different from the insulating liner material. The maximum vertical extension v2 of the internal separation trench structure is less than the vertical extension v0 of the semiconductor layer.

[0049] According to the implementation, the terminal area may further include an idle area or a second extension area, wherein the second extension area is formed between the second inner area and the second outer area, and wherein the extension separation structure laterally separates the first extension area and the second extension area or the first extension area and the idle area.

[0050] The extended separation structure may include a pn junction, an extended separation region with a conductivity type opposite to the first extended region, an extended separation trench comprising an insulating material, or a combination thereof. The extended separation region may be or include a doped region formed by implanting a dopant and diffusing and activating the implanted dopant. Alternatively, a segment of the substrate portion extending from the central region through the terminal region between the first and second extended regions may form an extended separation region. The extended insulating structure extends from the first surface into the semiconductor layer. In the lateral direction, the extended insulating structure extends from the central region through the terminal region between the first and second extended regions. The extended separation trench may be or include thermally grown shallow trench oxide, field oxide, or a trench containing trench filler. The trench filler may include a homogeneous insulating filler or an insulating liner and a filler material different from the insulating liner material. The maximum vertical extension v2 of the extended separation trench may be less than the vertical extension v0 of the semiconductor layer.

[0051] The extended separation trench and the internal separation trench structure can be directly adjacent to each other and can have the same width and vertical extension, so that the extended separation trench and the internal separation trench structure form a continuous straight line structure.

[0052] According to an embodiment, the high-voltage device may include an insulator frame that laterally surrounds a first element region, the first element region including a first inner region, a first extension region, and a first outer region.

[0053] The insulator frame can be a rectangular frame including an internal separation structure and an extended separation structure. The internal separation structure can include two parallel first insulator trenches extending laterally into a central region, and a second insulator trench connecting the two parallel first insulator trenches in the central region. The extended separation structure can include two parallel insulator trenches, each extending from an external isolation trench structure to an end face of one of the first and second insulator trenches. The extended separation structure and the internal separation structure can have the same width and length, and can be directly adjacent portions of a straight insulator structure.

[0054] According to the implementation, the central area may be stadium-shaped and include a rectangular segment and two conical segments on opposite sides of the rectangular segment, wherein a first inner area may be formed in the rectangular segment and a second inner area may be formed in at least one of the conical segments.

[0055] The two conical segments can be semicircular segments forming a semicircle, with a diameter equal to the width of the rectangular segment. The semiconductor portions of one, two, three, or more functional devices can be formed solely within the rectangular segment. The shape of the semicircular segment can be approximated by straight orthogonal line segments forming a step.

[0056] According to an embodiment, the semicircular segment may include a semiconductor portion of a parasitic device, wherein an idle region may be formed in two portions of a terminal region extending radially outward from the two semicircular segments of the central region.

[0057] The semi-circular section may contain only the semiconductor portion of the parasitic device, and may not contain the semiconductor portion of the device in use.

[0058] According to an embodiment, the first inner region has a first conductivity type, and the first outer region may have a complementary second conductivity type that is opposite to the first conductivity type.

[0059] For example, the first conductivity type is n-conductivity. The first and second inner regions are n-conducting, and the first and second outer regions (if applicable) are p-conducting. The first extended region is either n-conducting (lightly n-doped) with a lower net dopant concentration than the first inner region, or p-conducting (lightly p-doped) with a lower net dopant concentration than the first outer region. The first inner region forms the cathode of a functional diode (e.g., a bootstrap diode or desaturation diode for a gate driver circuit), and the first outer region forms the anode of the functional diode. The second inner region forms the cathode of an accessible parasitic diode, and the second outer region forms the anode of an accessible parasitic diode.

[0060] According to another example, the first conductivity type is p-conductivity. The first and second inner regions are p-conducting, and the first and second outer regions (if applicable) are n-conducting. The first extended region is either n-conducting with a lower net dopant concentration than the first outer region, or p-conducting with a lower net dopant concentration than the first inner region. The first inner region forms the anode of a functional diode (e.g., a bootstrap diode or desaturation diode for a gate driver circuit), and the first outer region forms the cathode of the functional diode. The second inner region forms the anode of a controllable parasitic diode, and the second outer region forms the cathode of the controllable parasitic diode.

[0061] According to an embodiment, the high-voltage device may include an internal separation structure that radially separates a first internal region and a second internal region.

[0062] For example, the first inner region is stadium-shaped and includes rectangular segments and two semicircular segments, such as semicircles on opposite sides of the rectangular segments. An inner separation structure can form a ring of uniform width around the first inner region. This ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. A second inner region can form another ring of uniform width around the first inner region and the inner separation structure. This additional ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments.

[0063] According to the implementation method, the external separation structure can radially separate the first external region and the second external region.

[0064] The first outer region can form a ring of uniform width around the terminal region. This ring includes two parallel straight line segments and two semicircles connecting the ends of these two parallel straight line segments. The outer separation structure can form a ring of uniform width along the outer edge of the first outer region. This ring includes two parallel straight line segments and two semicircles connecting the ends of these two parallel straight line segments. The second outer region can form another ring of uniform width around the outer separation structure. This additional ring includes two parallel straight line segments and two semicircles connecting the ends of these two parallel straight line segments.

[0065] According to an embodiment, the high-voltage device may further include a first internal source region in direct contact with the first internal region, wherein the first internal source region and the first internal region have complementary conductivity, and wherein a portion of the first internal region laterally separates the first extension region and the first internal source region.

[0066] For example, the first internal source region, the first extension region, and the first external region are p-conductive. The first internal region is n-conductive and forms the body region of a source-embedded p-channel LDMOS. The n-conductive first internal region (body region) laterally separates the p-conductive first extension region and the first internal source region. The first internal source region is formed by dopant implantation and diffusion, and forms a p-conductive well extending from the first surface into the n-conductive first internal region (body region). The first internal region may laterally surround the first internal source region.

[0067] According to an embodiment, the high-voltage device may further include a first external source region in direct contact with the first external region, wherein the first external source region and the first external region have complementary conductivity, and wherein a portion of the first external region laterally separates the first extension region and the first external source region.

[0068] For example, the first external source region, the first extension region, and the first internal region are n-conductive. The first external region is p-conductive and forms the body region of a drain-in-type n-channel LDMOS. The p-conductive first external region (body region) laterally separates the n-conductive first extension region and the first external source region. The first external source region is formed by dopant implantation and diffusion and forms an n-conductive well extending from the first surface into the p-conductive first external region (body region). The first external region may laterally surround the first external source region.

[0069] Figure 1A and Figure 1B A portion of a semiconductor device 500 having a high-voltage device 510 is shown. The semiconductor device 500 may be an HVIC (High Voltage Integrated Circuit), such as a gate driver circuit or a power factor correction circuit. The semiconductor device 500 includes: a low-voltage portion having logic and analog circuitry using a first power supply voltage reference potential; and a high-voltage portion having logic and analog circuitry using a second power supply voltage reference potential, wherein the first and second power supply voltage reference potentials may deviate from each other by greater than 50V, greater than 100V, or greater than 600V. The high-voltage device 510 includes a high-voltage diode that transmits electrical signals and / or power from the low-voltage portion to the high-voltage portion or vice versa.

[0070] The semiconductor region of the high-voltage device 510 is formed in Figure 1BThe semiconductor layer 110 is shown. The semiconductor layer 110 has a first surface 111 on the front side and a second surface 112 opposite to the front side. The first surface 111 and the second surface 112 are formed in two parallel horizontal planes. The normals to these horizontal planes define a vertical direction. The semiconductor layer 110 includes a vertically extending (thickness) uniform monocrystalline silicon layer between the first surface 111 and the second surface 112. Structures including other materials, such as insulating materials, can extend from the first surface 111 into the semiconductor layer 110. The vertical extension v0 of the semiconductor layer 110 can range from 10 μm to 200 μm, for example, from 35 μm to 80 μm.

[0071] Semiconductor layer 110 has a homogeneous background doping. In the example shown, semiconductor layer 110 has a weak p-type (p-) background doping. In semiconductor layer 110, a doped region can be formed by implanting a dopant through the first surface 111 and activating the implanted dopant during a thermal treatment. The remaining portion of semiconductor layer 110 unaffected by the implanted dopant forms a substrate portion 115 having the original background doping of semiconductor layer 110.

[0072] Semiconductor layer 110 is in an SOI (silicon-on-insulator) configuration, wherein insulating layer 120 separates the second surface 112 of semiconductor layer 110 from substrate 130. Semiconductor layer 110 and insulating layer 120 are in direct contact with each other and form a horizontal interface. The vertical extension of insulating layer 120 can be in the range of 2 μm to 40 μm, for example, in the range of 4 μm to 20 μm. Insulating layer 120 can be a homogeneous layer or a stack of layers comprising at least two layers with different compositions and / or structures. For example, insulating layer 120 can include or be a semiconductor oxide layer, such as a silicon oxide layer. Substrate 130 can include a weakly doped single-crystal silicon layer. Semiconductor layer 110, insulating layer 120 and substrate 130 form SOI (silicon-on-insulator) die 100.

[0073] according to Figure 1A The high-voltage device 510 includes a central region 200 and a peripheral region laterally surrounding the central region 220, wherein the peripheral region includes a terminal region 300. An external isolation trench structure 140 laterally surrounds the peripheral region.

[0074] The central region 200 is stadium-shaped and includes a rectangular segment and two semicircular segments on opposite sides of the rectangular segment, wherein the radius w1 of the semicircular segments is half the corresponding side length of the rectangular segment. The radius w1 can range from 1 μm to 50 μm. The peripheral region laterally surrounds the central region 200 in the radial direction with a constant radial width w0. The radial width w0 can range from 5 μm to 100 μm. The external isolation trench structure 140 extends from the first surface 111 through the semiconductor layer 110 to the second surface 112, and laterally surrounds the peripheral region at a uniform distance from the central region 200 along its entire perimeter.

[0075] The central region 200 includes a first inner region 210 and a second inner region 220. An internal separation structure 215 laterally separates the first inner region 210 and the second inner region 220 from each other. In the illustrated embodiment, the internal separation structure 215 includes an internal separation region 216 having a conductivity type opposite to that of the first inner region 210 and the second inner region 220. The maximum vertical extension vmax of the first inner region 210 and the second inner region 220 is less than the vertical extension v0 of the semiconductor layer 110.

[0076] The termination region 300 includes a transition region for potential and is capable of blocking relatively high voltages greater than 50V, 100V, or 600V applied between the first inner region 210 and the first outer region 410. In the illustrated example, the termination region 300 includes a first extension region 310, a first outer region 410, and an idle region 390.

[0077] A first outer region 410 is formed along an outer isolation trench structure 140. A first extension region 310 extends radially from a first inner region 210 to a first outer region 410. The first extension region 310 is significantly shallower than both the first inner region 210 and the first outer region 410. The first extension region 310 forms a vertical pn junction with the substrate portion 115, a lateral unipolar junction with the first inner region 210, and a lateral pn junction with the first outer region 410. In the illustrated embodiment, the first extension region 310 is in direct contact with the first surface 111. In other examples, a RESURF layer having a conductivity type opposite to that of the first extension region 310 is formed between the first surface 111 and the first extension region 310.

[0078] Beyond the first extension region 310 and the first outer region 410, an idle region 390 extends from the central region 200 to the outer isolation trench structure 140. In the illustrated example, a portion of the base portion 115 forms the idle region 390, wherein the base portion and the first extension region 310 form two lateral pn junctions. Each of these lateral pn junctions forms an extended separation structure 315. The base portion 115 and the first outer region 410 form two lateral unipolar junctions.

[0079] Figure 1B A first internal region 210, a second internal region 220, a first extension region 310, a first external region 410, and a second external region 420 are shown extending from a first surface 111 into a semiconductor layer 110. A substrate portion 115 is formed between the first internal region 210, the second internal region 220, the first extension region, the first external region 410, and the second external region 420 located on a first side and the second surface 112 located on the other side.

[0080] An interlayer dielectric 150 is formed on the first surface 111. A contact structure extends to the first surface 111 through an opening in the interlayer dielectric 150, wherein a first internal contact structure 211 and a first internal region 210 form a low-resistance ohmic contact, a second internal contact structure 221 and a second internal region 220 form a low-resistance ohmic contact, and a first external contact structure 411 and a first external region 410 form a low-resistance ohmic contact.

[0081] The n+-doped first internal region 210, the n-doped first extended region 310, and the p+-doped first external region 410 form a high-voltage diode 512, wherein the n+-doped first internal region 210 forms the cathode, and the p+-doped first external region 410 forms the anode. The high-voltage diode 512 can be used as a bootstrap diode or a desaturation diode. The leakage current generated in the idle region 390 is dissipated via the second internal contact structure 221 and the first external contact structure 411, and does not significantly affect the performance of the high-voltage diode 512. The lateral separation between the first internal region 210 and the second internal region 220 reduces the parasitic capacitance of the high-voltage diode 512.

[0082] exist Figure 1C and Figure 1D In the high-voltage device 510 shown, the peripheral region between the central region 200 and the external isolation trench structure 140 further includes a second external region 420 having the same conductivity type as the first external region 410. The second external region 420 is formed to be in direct contact with the external isolation trench structure 140. A second external contact structure 421 extends through an opening in the interlayer dielectric 150 to the first surface 111. The second external contact structure 421 and the second external region 420 form a low-resistance ohmic contact.

[0083] The internal separation structure 215 includes three straight internal separation trench structures 217 extending from the first surface 111 into the semiconductor layer 110. A first internal separation trench structure 217 extends along the horizontal longitudinal axis of the central region 200. A second internal separation trench structure 217 extends radially from a first end of the first separation trench structure. A third internal separation trench structure 217 extends radially from a second end of the first separation trench structure. The vertical extension v2 of the internal separation trench structure 217 is greater than the maximum vertical extension vmax of the first internal region 210 and the second internal region 220.

[0084] The external separation structure 415 includes two external separation trench structures 417 extending from the first surface 111 into the semiconductor layer 110. Each external separation trench structure 417 laterally separates the first external region 410 from the idle region 390. The extended separation structure 315 includes two extended insulator structures 317 extending from the first surface 111 into the semiconductor layer 110. The extended insulator structures 317 extend radially from the central region 200 to the external separation trench structure 417 between the first extended region 310 and the idle region 390. Each internal separation trench structure 217, each extended insulator structure 317, and each external separation trench structure 417 are segments of a linear, continuous separation trench extending radially from the interior of the central region 210 to the external isolation trench structure 140. In the illustrated embodiment, the separation trench is a trench containing a trench filler, wherein the trench filler comprises or is composed of a homogeneous insulating filler.

[0085] The leakage current generated in the idle region 390 is dissipated through the second internal contact structure 221 and the second external contact structure 421, and does not affect the performance of the high-voltage diode 512. The lateral separation between the first internal region 210 and the second internal region, as well as the lateral separation between the segment of the terminal region with the first extension region 310 and the idle region 390, reduces parasitic capacitance.

[0086] Figure 2A , Figure 2B and Figure 2CThe high-voltage device 510 shown includes a high-voltage diode 512, which has two segments 512-1 and 512-2 formed symmetrically with respect to the horizontal longitudinal axis of the central region 200. A shared first inner region 210 is formed in a rectangular segment of the central region 200. A second inner region 220 includes a separated portion in a semi-circular segment of the central region 200. A first extension region 310 includes two separated portions on opposite sides of the first inner region 210. A first outer region 410 includes two separated portions on opposite sides of the central region 200. An idle region 390 includes two separated portions in a semi-circular segment of the peripheral region. A second outer region 420 includes two separated portions located on opposite sides of the central region 200 along an outer isolation trench structure 140 and laterally contacting the two portions of the idle region 390.

[0087] Two parallel linear separation trenches laterally separate the two portions of the first inner region 210 and the second inner region 220, laterally separate the region having the first extension region 310 from the idle region 390, and laterally separate the two portions of the first outer region 410 from the idle region 390. A single first inner contact structure 211 and the first inner region 210 form an ohmic contact. Each of the two first outer contact structures 411 forms an ohmic contact with one of the two portions of the first outer region 410. Each of the two second inner contact structures 221 forms an ohmic contact with one of the two portions of the second inner region 220.

[0088] exist Figure 3A and Figure 3B In the middle, the high-voltage device 510 includes an LDMOS 514 having two segments 514-1 and 514-2, which are formed symmetrically with respect to the horizontal longitudinal axis of the central region 200. A first inner region 210 is formed in a rectangular segment of the central region 200. A second inner region 220 includes two separate portions in a semi-circular segment of the central region 200.

[0089] The LDMOS 514 is an n-channel FET with an in-drain configuration. A first internal region 210 forms an n+-doped drain region. Two portions of a first extension region 310 form symmetrical n-doped drain extensions. Two portions of a first external region 410 form p-doped body regions. Additionally, each of the two portions of the external source region 412 is formed as a well extending from the first surface 111 into one of the two portions of the first external region 410 (body region).

[0090] On the first surface 111, a gate dielectric is formed above the portion of the first external region 410 located between the two portions of the external source region 412 and the two portions of the first extension region 310. A gate electrode 155 is formed on the gate dielectric. The gate electrode 155 is electrically connected to the gate terminal G. A first internal contact structure 211 is electrically connected to the drain terminal D. Each of the two first external contact structures 411 forms an ohmic contact with a portion of the external source region 412 and a portion of the first external region 410 (body region) and is electrically connected to the source terminal S.

[0091] Figure 4A and Figure 4B A high-voltage device 510 is shown, comprising two independent LDMOS transistors 514 formed symmetrically with respect to the horizontal longitudinal axis of a central region 200. A first internal region 210 of the first LDMOS 514 is formed in a first portion of a rectangular segment of the central region 200. A third internal region 230 of the second LDMOS 514 is formed in a second portion of the rectangular segment of the central region 200. The second internal region 220 includes two portions in a semi-circular segment of the central region 200, and a third portion extending from the first segment to the second segment of the semi-circular segment between the first internal region 210 and the third internal region 230. A first internal contact structure 211 and the first internal region 210 form an ohmic contact. The first internal contact structure 211 is electrically connected to a first drain terminal D1. A third internal contact structure 231 and the third internal region 230 form an ohmic contact. The third internal contact structure 231 is electrically connected to a second drain terminal D2.

[0092] A first external region 410 of the LDMOS 514 is formed radially along a portion of the external isolation trench structure 140 in the first internal region 210. A first extension region 310 extends radially from the first internal region 210 to the first external region 410. A first external source region 412 of the first LDMOS 514 extends from the first surface 111 into the first external region 410. A first external contact structure 411 forms an ohmic contact with the first external source region 412 and the first external region 410 (body region) and is electrically connected to the first source terminal S1 of the first LDMOS 514. On the first surface 111, a gate dielectric is formed over the portion of the first external region 410 between the first external source region 412 and the first extension region 310. A gate electrode 155 is formed on the gate dielectric. The gate electrode 155 is electrically connected to the first gate terminal G1 of the first LDMOS 514.

[0093] The third external region 430 of the second LDMOS 514 is formed radially in the third internal region 230 along a portion of the external isolation trench structure 140. A third extension region 330 extends radially from the third internal region 230 to the third external region 430. The third external source region 432 of the second LDMOS 514 extends from the first surface 111 into the third external region 430. A third external contact structure 431 forms an ohmic contact with the third external source region 432 and the third external region 430 (body region) and is electrically connected to the second source terminal S2 of the second LDMOS 514. On the first surface 111, a gate dielectric is formed above the portion of the third external region 430 between the third external source region 432 and the third extension region 330. A gate electrode 155 is formed on the gate dielectric. The gate electrode 155 is electrically connected to the second gate terminal G2 of the second LDMOS 514.

[0094] A first separation trench structure having three linear segments 217, 317, and 417, and a portion of an external isolation trench structure 140, form a first closed frame surrounding a first inner region 210, a region having a first extension region 310, and a first outer region 410. A second separation trench structure having three linear segments 217, 317, and 417, and a portion of an external isolation trench structure 140, form a second closed frame surrounding a third inner region 230, a region having a third extension region 330, and a third outer region 430. The separation trenches may be formed as shallow trench separators, with a vertical extension greater than the vertical extension of the inner regions 210, 220, and 230.

[0095] Figure 4C Two second internal contact structures 221-1 and 221-2 are shown that form ohmic contacts with the second internal region 220 in two semi-circular segments of the second internal region 220. The idle region 390 includes a second extension region 320, which may have the same conductivity type and dopant dose as the first extension region 310.

[0096] Figure 5 The high-voltage device 510 shown includes three independent LDMOS 514s. The first of the high-voltage FETs 514 is coupled with... Figure 4A and Figure 4B The first LDMOS 514 in the process is formed in a similar manner. The second and third can be formed by connecting them along radial lines. Figure 4A and Figure 4B The second LDMOS 514 is split in two to provide third and fourth internal regions 230, 240, third and fourth extended regions 330, 340, third and fourth external regions 430, 440, and third and fourth external source regions 432, 442.

[0097] exist Figures 6A to 6CIn the high-voltage device 510, a p-channel LDMOS 514 with two segments 514-1 and 514-2 is formed symmetrically with respect to the horizontal longitudinal axis of the central region 200. A first inner region 210 is formed in a rectangular segment of the central region 200. A second inner region 220 includes two separate portions in a semi-circular segment of the central region 200.

[0098] The LDMOS 514 has a source-in-place configuration. A first internal region 210 forms an n-doped body region. Each of the two portions of the internal source region 212 is formed as a well extending from the first surface 111 into the first internal region 210 (body region). A central n+ doped contact region 213 extends from the first surface 111 into the first internal region 210. Two portions of the first extension region 310 form symmetrical p-drain extensions. Two portions of the first external region 410 form p+ doped drain regions.

[0099] On the first surface 111, a gate dielectric is formed above the portion of the first internal region 210 located between the two portions of the internal source region 212 and the two portions of the first extension region 310. A gate electrode 155 is formed on the gate dielectric. The gate electrode 155 is electrically connected to the gate terminal G. A first internal contact structure 211 forms an ohmic contact with the two portions of the internal source region 212 and the body contact region 213, and is electrically connected to the source terminal S. Each of the two first external contact structures 411 forms an ohmic contact with a portion of the first external region 410 and is electrically connected to the drain terminal D of the LDMOS 514.

[0100] Figure 7A and Figure 7B A high-voltage device 510 is shown with an internal separation structure 215 having a radially separated first internal region 210 and a second internal region 220.

[0101] The first inner region 210 is stadium-shaped and includes a rectangular segment and two semicircular segments, such as semicircles on opposite sides of the rectangular segment. An inner separation structure 215 forms a ring of uniform width around the first inner region 210. This ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. A second inner region 220 forms another ring of uniform width around the first inner region 210 and the inner separation structure 215. This additional ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. The inner separation structure 215 may be a doped region or part of a substrate portion 115 with a conductivity type opposite to that of the first inner region 210 and the second inner region 220.

[0102] The peripheral region between the second inner region 220 and the outer isolation trench structure 140 includes a first extension region 310 and a first outer region 410 consisting of two parts. The first extension region 310 completely surrounds the second inner region 220. The first outer region 410 includes two separate portions formed to directly contact the straight section of the outer isolation trench structure 140, and is formed symmetrically with respect to the horizontal longitudinal axis of the high-voltage device 510.

[0103] In the illustrated embodiment, the first inner region 210 and the second inner region 220 are n+ doped, the first extended region 310 is n- doped, and both portions of the first outer region 410 are p+ doped. The first inner contact structure 211 and the first inner region 210 form an ohmic contact. The first inner contact structure 211 is electrically connected to the cathode terminal K. The second inner contact structure 221, consisting of two parts, and the second inner region 220 form an ohmic contact. The two portions of the second inner contact structure 221 are electrically connected to the shielded cathode terminal KS. The two portions of the first outer contact structure 411 form an ohmic contact with each of the two portions of the first outer region 410. The two portions of the first outer contact structure 411 are electrically connected to the anode terminal A.

[0104] Figure 8A and Figure 8B A high-voltage device 510 is shown with an external separation structure 415 having a radially separated first external region 410 and a second external region 420.

[0105] The central region 200 includes a first inner region 210. In the illustrated example, the first inner region 210 forms the central region 200. The terminal region between the central region 200 having the first inner region 210 and the outer isolation trench structure 140 includes a first extension region 310, wherein the first extension region 310 completely surrounds the first inner region 210. The terminal region also includes a first outer region 410, a second outer region 420, and an outer separation structure 415 radially separating the first outer region 410 and the second outer region 420.

[0106] A first outer region 410 forms a ring of uniform width around a first extension region 310. This ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. An outer separation structure 415 forms a ring of uniform width along the outer edge of the first outer region 410. This ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. A second outer region 420 forms another ring of uniform width around the outer separation structure 415 and directly adjoins the outer isolation trench structure 140. This additional ring includes two parallel straight segments and two semicircles connecting the ends of these two parallel straight segments. The outer separation structure 415 may be a doped region with a conductivity type opposite to that of the first outer region 410 and the second outer region 420.

[0107] In the illustrated embodiment, the first outer region 410 and the second outer region 420 are n+ doped, the first extended region 310 is p- doped, and the inner region 210 is p+ doped. A first internal contact structure 211 and the first inner region 210 form an ohmic contact. The first internal contact structure 211 is electrically connected to the anode terminal A. A first outer contact structure 411 and the first outer region 410 form an ohmic contact. The first outer contact structure 411 is electrically connected to the shielded cathode terminal KS. A second outer contact structure 421 and the second outer region 420 form an ohmic contact. The second outer contact structure 421 is electrically connected to the cathode terminal K.

[0108] Figure 7A / Figure 7B and Figure 8A / Figure 8B Each of the high-voltage devices 510 includes a high-voltage main diode having an anode terminal A and a cathode terminal K, and a high-voltage shielding diode having an anode terminal A and a cathode terminal KS.

[0109] The presence of a high-voltage shielding diode can reduce the leakage current of the high-voltage main diode by an order of magnitude.

[0110] Figure 9 A circuit diagram showing a portion of a bootstrap circuit for an HVIC is shown, which will... Figure 7A / Figure 7B or Figure 8A / Figure 8B The high-voltage main diode 516 and the high-voltage shielding diode 518 described herein are used as bootstrap diodes.

[0111] The common anode of the high-voltage main diode 516 and the high-voltage shielding diode 518 is connected to the positive power supply potential of the low-voltage section of the HVIC. The bootstrap capacitor 519 in the high-voltage section of the HVIC is electrically connected between the switching node S and the cathode of the high-voltage main diode 516. The anode of the low-voltage diode 517 is electrically connected to the switching node S. The cathode of the low-voltage diode 517 is electrically connected to the cathode of the high-voltage shielding diode 518.

[0112] When the switching node is connected to a low potential, the high-voltage main diode 512 provides charging current to the bootstrap capacitor 519. When the switching node S is connected to a high potential, such as 600V, the high-voltage main diode 516 blocks. The high-voltage shielding diode 518 reduces leakage current in the high-voltage device, of which the high-voltage main diode 512 is a part. The low-voltage diode 517 is adapted to block approximately 20V and blocks the high-voltage shielding diode 518 during the bootstrap charging time.

[0113] Figure 10Half of a symmetrical high-voltage device 510 with a centrally separated cathode and a common peripheral anode region is shown. An internal separation structure 215 radially separates a first internal region 210 and a second internal region 220. The first internal region 210 forms the cathode of the high-voltage main diode. The second internal region 220 forms the cathode of the high-voltage shielding diode. A field plate 180 is formed in the terminal region above the first extension region 310.

[0114] Figure 11 The time plot shows the time plot with high voltage main diode 518 and high voltage shielding diode 518. Figure 7A / Figure 7B The changes in blocking voltage 701 and leakage current 711 after the high-voltage device changes from forward conduction mode to blocking mode are shown. Line 702 shows the change in blocking voltage of a comparative example with a homogeneous central region 200 but without the internal separation structure 215, and line 712 shows the change in leakage current of this comparative example. Dividing the central region into two separate internal regions improves the switching speed and reduces the leakage current by about one-third.

[0115] Figure 12 A semiconductor device 500 configured as a gate driver circuit is shown. The gate driver circuit includes a high-side portion 620 configured to drive the gate of a high-side switch 922 of a half-bridge and a low-side portion 610 configured to drive the gate of a low-side switch 921 of the half-bridge. The semiconductor device 500 includes a high-side power supply circuit 621 to obtain a positive power supply voltage VB (high-side supply potential VB) for the high-side portion 620, wherein a bootstrap diode 660 charges a bootstrap capacitor from an external power supply voltage VCC. The positive power supply voltage VB for the high-side portion 620 is referenced to a high-side reference potential VS, which corresponds to the potential of the switching nodes of the half-bridge 920.

[0116] A high-side desaturation detection circuit 622 is connected to the power supply potential VA of the half-bridge 920, detects the desaturation of the high-side switch 922 of the half-bridge 920, and outputs a high-side desaturation signal indicating whether a desaturation condition exists. A high-side receiver circuit 623 receives a differential gate control signal from two field-effect transistors (e.g., an n-channel LDMOS 514 as described above) and outputs a single-ended high-side gate control signal. A logic circuit 624 in the high-side portion 620 receives the high-side desaturation signal and the high-side gate control signal. If the high-side desaturation signal does not indicate a desaturation condition, the logic circuit 624 in the high-side portion 620 outputs a second gate drive signal GOut2 in response to the high-side gate control signal. A high-side driver stage 625 can drive the second gate drive signal GOut2.

[0117] The logic circuit 624 in the high-side section also outputs a differential high-side data signal. As described above, the two p-channel LDMOS 514s transmit the differential high-side data signal from the high-side section 620 to the low-side receiver circuit 613 in the low-side section 610.

[0118] The low-side portion 610 of the gate drive circuit includes a low-side power supply circuit 611 to obtain a positive power supply voltage VDD for the low-side portion 610. The positive power supply voltage VDD for the low-side portion 610 is referenced to a first reference potential VSS.

[0119] A low-side desaturation detection circuit 612 is connected to the output node of the half-bridge 920, detects the desaturation of the low-side switch 921, and outputs a low-side desaturation signal indicating the presence of a desaturation condition. A low-side receiver circuit 613 receives differential low-side data signals from two p-channel LDMOS transistors 514 and outputs a single-ended low-side data signal. Logic circuitry 614 in the low-side portion 610 receives the low-side data signal, the low-side desaturation signal, and the low-side gate control signal from an external source such as the processor 990. If neither the low-side desaturation signal nor the low-side data signal indicates a desaturation condition, logic circuitry 614 in the low-side portion 610 outputs a first gate drive signal GOut 1 in response to the low-side gate control signal. A low-side driver stage 615 drives the first gate drive signal GOut 1.

[0120] The logic circuit 614 in the low-side section 610 also outputs a differential gate control signal. Two n-channel LDMOS field-effect transistors 514 transmit the differential gate control signal from the low-side section 610 to the high-side section 620. An inductive load 930 is electrically connected between the switching nodes of the two half-bridges 920.

[0121] The LDMOS 514 with any configuration of this embodiment improves signal transmission between the low-side portion 610 and the high-side portion 620, and can improve the performance of the half-bridge 920 by allowing higher switching frequencies.

[0122] While specific examples have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be used instead of the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, the invention is limited only by the claims and their equivalents.

[0123] It should be noted that semiconductor devices, including their preferred embodiments as outlined in this document, can be used independently or in combination with other semiconductor devices disclosed herein. Furthermore, the features outlined in the context of semiconductor devices also apply to the corresponding methods, and vice versa. Moreover, all aspects of the methods and devices outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0124] It should be noted that the specification and accompanying drawings only illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, although not explicitly described or shown herein, which embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing the principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to cover their equivalents.

Claims

1. A semiconductor device (500) comprising a high-voltage device (510), said high-voltage device comprising: A central area (200), the central area including a first internal area (210); A terminal region (300) that laterally surrounds the central region (200) and includes a first extension region (310); A first outer region (410), wherein the first extension region (310) is formed between the first inner region (210) and the first outer region (410), and A lightly doped substrate portion (115) and the first extended region (310) form a semiconductor junction; The central region (200) further includes a second inner region (220), the first inner region (210) and the second inner region (220) are laterally separated and connected to different inner contact structures (211, 221), and / or the high voltage device (510) further includes a second outer region (420), the first outer region (410) and the second outer region (420) are laterally separated and connected to different outer contact structures (411, 421).

2. The semiconductor device according to claim 1, in, The maximum vertical extension (vmax) of the first inner region (210), the second inner region (220) and the first outer region (410) is less than the vertical extension (v0) of the semiconductor layer (110) of the semiconductor device.

3. The semiconductor device according to any one of the preceding claims, in, The high-voltage device (510) has a radial width (w0) in its peripheral region, which includes the terminal region (300) and at least the first outer region (410), and the radial width (w0) is constant along the periphery surrounding the central region (200).

4. The semiconductor device according to any one of the preceding claims, in, The first internal region (210) and the first internal contact structure (211) form an ohmic contact, and wherein the second internal region (220) and the second internal contact structure (221) form an ohmic contact.

5. The semiconductor device according to any one of the preceding claims, further comprising: An internal separation structure (215) that laterally separates the first internal region (210) and the second internal region (220) and / or an external separation structure (415) that laterally separates the first external region (410) and the second external region (420).

6. The semiconductor device according to the preceding claims, in, The internal separation structure (215) includes an internal separation region (216) having a conductivity type complementary to that of the first internal region (210) and the second internal region (220), and / or the external separation structure (415) includes an external separation region (416) having a conductivity type complementary to that of the first external region (410).

7. The semiconductor device according to claim 5, in, The internal separation structure (215) includes an internal separation trench structure (217) extending from a first surface (111) of a semiconductor layer (110) including the first internal region (210) and the second internal region (220) into the semiconductor layer (110), and / or the external separation structure (415) includes an external separation trench structure (417) extending from the first surface (111) into the semiconductor layer (110).

8. The semiconductor device according to any one of claims 6 and 7, in, The terminal area further includes an idle area (390) or a second extension area (320), wherein the second extension area (320) is formed between the second inner area (220) and the second outer area (420), and wherein the extension separation structure (315) laterally separates the first extension area (310) and the second extension area (320) or the first extension area (310) and the idle area (390).

9. The semiconductor device according to any one of the preceding claims, comprising: An insulator frame that laterally surrounds a first element region including the first inner region (210), the first extension region (310), and the first outer region (410).

10. The semiconductor device according to any one of the preceding claims, in, The central area (200) is stadium-shaped and includes a rectangular section and two semicircular sections on opposite sides of the rectangular section, wherein the first inner area (210) is formed in the rectangular section and the second inner area (220) is formed in at least one of the semicircular sections.

11. The semiconductor device according to the preceding claims, in, The semicircular segment includes the semiconductor portion of the parasitic device, and wherein an idle region (390) is formed in two portions of the terminal region (300) extending radially outward from the two semicircular segments of the central region (200).

12. The semiconductor device according to any one of the preceding claims, in, The first inner region (210) has a first conductivity type, and the first outer region (410) has a complementary second conductivity type that is opposite to the first conductivity type.

13. The semiconductor device according to the preceding claims, comprising: An internal separation structure (215) radially separates the first internal region (210) and the second internal region (220).

14. The semiconductor device of claim 12, comprising: An external separation structure (415) radially separates the first external region (410) and the second external region (420).

15. The semiconductor device according to any one of claims 1 to 12, further comprising: A first internal source region (212) in direct contact with the first internal region (210), wherein the first internal source region (212) and the first internal region (210) have complementary conductivity, and wherein a portion of the first internal region (210) laterally separates the first extension region (310) and the first internal source region (212).

16. The semiconductor device according to any one of claims 1 to 12, further comprising: A first external source region (412) in direct contact with the first external region (410), wherein the first external source region (412) and the first external region (410) have complementary conductivity, and wherein a portion of the first external region (410) laterally separates the first extension region (310) and the first external source region (412).

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