Planar split gate VDMOSFET and manufacturing method thereof

Abstract

The invention relates to a planar split-gate VDMOSFET and a manufacturing method thereof. The planar split-gate VDMOSFET comprises a drain electrode region, a gate electrode region, a gate electrode region and a gate electrode region, the drift region is located on the drain region; the drain electrode is positioned on one surface, deviating from the drift region, of the drain region; a JFET region on the drift region; the body regions are located on the drift region and on the two sides of the JFET region; the source region is located on the body region and on the two sides of the JFET region; the contact region has the second conduction type and is located on the outer side of the body region, and the bottom of the contact region is deeper than that of the body region; a split gate electrode separated from the middle, the separated region being located directly above the JFET region; and a source electrode on the source region and the contact region and in direct contact with the source region and the contact region. The gate-drain capacitance is reduced, the switching power consumption of the device is reduced, and the high-frequency performance of the device is improved. On the premise that the specific on-resistance is not affected, the breakdown voltage of the device is improved, and the long-term reliability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a planar split-gate VDMOSFET, and also to a method for manufacturing a planar split-gate VDMOSFET. Background Technology

[0002] Planar-gate VDMOSFETs (vertical double-diffused metal oxide semiconductor field-effect transistors) using third-generation semiconductor materials as substrates offer advantages over traditional Si-based planar-gate VDMOSFETs, including wider bandgap, higher thermal conductivity, lower critical breakdown electric field, and faster electron saturation drift velocity. These advantages make them more suitable for high-temperature, high-voltage, high-frequency, and high-power applications. However, the large gate-drain capacitance and specific on-resistance of planar-gate VDMOSFETs still result in high power consumption during high-power operation, limiting their high-frequency applications. Planar split-gate VDMOSFETs, with their split gate, reduce the gate-drain overlap area and decrease the gate-drain capacitance, resulting in better high-frequency characteristics. However, their long-term reliability is lower under high-voltage operating conditions. Summary of the Invention

[0003] Therefore, it is necessary to provide a planar split-gate VDMOSFET with good long-term reliability under high-voltage operating conditions and its manufacturing method.

[0004] A planar split-gate VDMOSFET includes: a drain region having a first conductivity type; a drift region having a first conductivity type located on the drain region; a drain electrode located on the side of the drain region away from the drift region; a JFET region having a first conductivity type located on the drift region; a body region having a second conductivity type located on the drift region and on both sides of the JFET region; the first conductivity type and the second conductivity type are opposite conductivity types; a source region having a first conductivity type located on the body region and on both sides of the JFET region; a contact region having a second conductivity type located outside the body region, and the bottom of the contact region is deeper than the bottom of the body region, the outside of the body region being the side of the body region away from the JFET region; a split gate electrode separated in the middle, the separating region being located directly above the JFET region; and a source electrode located on the source region and the contact region, in direct contact with the source region and the contact region.

[0005] The aforementioned planar split-gate VDMOSFET has a contact region that is deeper at the bottom than the body region. Therefore, the contact region and drift region form a deeper PN junction than the body-drift region junction. When a high voltage is applied to the drain, the peak electric field shifts to the bottom of the contact region, away from the split-gate electrode corner above the JFET region. This distances the device from the electric field breakdown weakness at the split-gate electrode corner above the JFET region, resulting in higher breakdown voltage and improved long-term reliability under high-voltage operating conditions.

[0006] In one embodiment, the bottom of the contact area is 0.5 to 2 micrometers deeper than the bottom of the body area.

[0007] In one embodiment, the contact area is formed by etching a trench on the outside of the body region and implanting ions of a second conductivity type on the sides and bottom of the trench.

[0008] In one embodiment, the contact region is formed by high-energy ion implantation.

[0009] In one embodiment, the drift region is formed by multiple epitaxy processes, and the contact region is formed by implanting ions of a second conductivity type after each epitaxy process, followed by heat treatment to allow the implanted ions of the second conductivity type to diffuse.

[0010] In one embodiment, a channel region located between the source region and the JFET region is further included, the channel region having a second conductivity type.

[0011] In one embodiment, a dielectric layer covering the split gate electrode is further included, with the source electrode covering the dielectric layer.

[0012] In one embodiment, the bottom and a portion of the sides of the contact region are in direct contact with the drift region, a portion of the sides of the contact region are in direct contact with the body region, and a portion of the sides of the contact region are in direct contact with the source region.

[0013] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0014] In one embodiment, the drain region and drift region are made of silicon carbide or gallium nitride.

[0015] In one embodiment, the doping concentration of the JFET region is greater than the doping concentration of the drift region.

[0016] In one embodiment, the doping concentration of the drain region is greater than that of the JFET region.

[0017] In one embodiment, the doping concentration of the source region is greater than the doping concentration of the JFET region.

[0018] In one embodiment, the doping concentration of the contact region is greater than that of the body region.

[0019] In one embodiment, the doping concentration of the contact region is greater than that of the channel region.

[0020] A method for manufacturing a planar split-gate VDMOSFET includes: obtaining a wafer on a substrate of a first conductivity type having a first conductivity type layer formed thereon; the doping concentration of the substrate being greater than the doping concentration of the first conductivity type layer; forming a JFET region, a body region, a source region, and a contact region in the first conductivity type layer; the JFET region and the source region having a first conductivity type, the body region and the contact region having a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; the body region being formed on both sides of the JFET region, the source region being formed on the body region and on both sides of the JFET region, the contact region being located outside the body region, and the bottom of the contact region being deeper than the bottom of the body region, the outside of the body region being the side of the body region away from the JFET region; forming a split gate electrode on the first conductivity type layer; the split gate electrode being separated from the middle, the separating region being located directly above the JFET region; forming a source electrode on the source region and the contact region that is in direct contact with the source region and the contact region; and forming a drain electrode on the side of the substrate away from the first conductivity type layer.

[0021] The aforementioned method for manufacturing planar split-gate VDMOSFETs involves setting the contact region to be deeper at the bottom than the body region. This results in a PN junction between the contact and drift regions that is deeper than the body-drift junction. When a high voltage is applied to the drain, the peak electric field shifts to the bottom of the contact region, away from the split-gate electrode corner above the JFET region. This distances the device from the electric field breakdown weakness at the split-gate electrode corner above the JFET region, giving it higher breakdown voltage and improving its long-term reliability under high-voltage operating conditions.

[0022] In one embodiment, the step of forming the JFET region, body region, source region, and contact region in the first conductivity type layer includes: etching the first conductivity type layer to form a trench; and implanting second conductivity type ions on the sides and bottom of the trench to form the contact region.

[0023] In one embodiment, the step of forming the JFET region, body region, source region, and contact region in the outer first conductivity type layer includes: step one, implanting second conductivity type ions into the first conductivity type layer to form a second conductivity type region; step two, forming another epitaxial layer on the wafer; step three, implanting second conductivity type ions into the epitaxial layer to form a second conductivity type region; repeating steps two and three to form multiple layers of second conductivity type regions, and then using heat treatment to diffuse and connect the second conductivity type regions into one piece to form the contact region. Attached Figure Description

[0024] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0025] Figure 1 This is a schematic cross-sectional view of an exemplary planar split-gate VDMOSFET using a third-generation semiconductor material as a substrate.

[0026] Figure 2 This is a cross-sectional view of a planar split-gate VDMOSFET in one embodiment of this application.

[0027] Figure 3 yes Figure 2 A schematic diagram of the region where the electric field intensity peak of the structure shown occurs.

[0028] Figure 4 yes Figure 2 The drift region resistance model of the VDMOSFET during forward conduction is shown.

[0029] Figure 5 This is a cross-sectional view of a planar split-gate VDMOSFET in another embodiment of this application.

[0030] Figure 6 This is a schematic diagram of the contact area 8 formed in one embodiment of this application.

[0031] Figure 7 This is a flowchart of a method for manufacturing a planar split-gate VDMOSFET according to an embodiment of this application. Detailed Implementation

[0032] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0038] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0039] Figure 1 This is a schematic cross-sectional view of an exemplary planar split-gate VDMOSFET using a third-generation semiconductor material as a substrate, including a drain region 1, a drift region 2, a body region 3, a JFET region 4, a source region 5, a channel region 6, a contact region 8, a gate dielectric layer 9, a split gate electrode 10, an interlayer isolation dielectric 11, a source electrode 12, and a drain electrode 13. When a high voltage is applied to the drain electrode 13, the peak electric field intensity appears at the corner of the split gate electrode above the JFET region 4, i.e. Figure 1The arrow points to the location where the body region 3 and drift region 2 form a PN junction. When a high voltage is applied to the drain electrode 13, the depletion layer formed by this PN junction clamps off the JFET region 4. The curvature of the split gate electrode corner above the JFET region 4 is relatively large, causing the electric field to concentrate and increase in intensity at that location. If this large electric field intensity is maintained for a long time, it will cause electrons to tunnel into the gate dielectric layer 9 and cause damage, reducing the device's breakdown voltage and long-term reliability.

[0040] This application proposes a low-loss (switching power consumption) planar split-gate VDMOSFET. Figure 2 This is a cross-sectional view of a planar split-gate VDMOSFET in one embodiment of this application, including: drain region 1, drift region 2, body region 3, JFET region 4, source region 5, contact region 8, split gate electrode 10, source electrode 12, and drain electrode 13.

[0041] Drain region 1 has the first conductivity type. Figure 2 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. Drift region 2 has the first conductivity type and is located on drain region 1. Drain electrode 13 is located on the bottom surface of drain region 1, i.e., the side of drain region 1 facing away from drift region 2. JFET region 4 has the first conductivity type and is located on drift region 2. Body region 3 has the second conductivity type and is located on drift region 2, on both sides of JFET region 4. Source region 5 has the first conductivity type and is located on body region 3, on both sides of JFET region 4. Contact region 8 has the second conductivity type and is located outside body region 3 (i.e., the side of body region 3 away from JFET region 4). The bottom of contact region 8 is deeper than the bottom of body region 3, i.e., the bottom of contact region 8 extends into drift region 2 to a position deeper than the bottom of body region 3. In one embodiment of this application, the doping concentration of contact region 8 is greater than the doping concentration of body region 3. A split gate electrode 10 is located on the source region 5, and the split gate electrode 10 is separated in the middle, with the separating region located directly above the JFET region 4. The source electrode 12 is located on the source region 5 and the contact region 8, and is in direct contact with both the source region 5 and the contact region 8. In one embodiment of this application, the doping concentrations have the following relationship: source region 5 > JFET region 4 > drift region 2, drain region 1 > JFET region 4 > drift region 2.

[0042] In the aforementioned planar split-gate VDMOSFET, the contact region 8 is set to be deeper at the bottom than the body region 3. Therefore, the contact region 8 and the drift region 2 form a PN junction that is deeper than the sum of the body region 3 and the drift region 2. When a high voltage is applied to the drain, the peak electric field intensity shifts to the bottom of the contact region 8, i.e. Figure 3The location indicated by the middle arrow is far from the split gate electrode corner above JFET region 4, meaning it's far from this weak point in the electric field breakdown. This results in higher breakdown voltage and improved long-term reliability under high-voltage operating conditions. The depletion layer formed by the PN junction of contact region 8 and drift region 2 pinches off JFET region 4 compared to... Figure 1 The device shown has a deeper depletion layer, which can further enhance the pinch-off effect of the depletion layer, reduce the electric field concentration at the corner of the split gate electrode, reduce the electric field strength at that location, and improve the breakdown voltage and long-term reliability of the device. Figure 4 yes Figure 2 The diagram shows the drift region resistance model of a VDMOSFET during forward conduction. The filled slashes in the figure represent the current propagation path from the bottom of JFET region 4 to the bottom of drift region 2 during forward conduction. Based on the drift region resistance distribution characteristics of the VDMOSFET, during forward conduction, the depth of contact region 8 and the resulting depletion layer do not affect the original current path and therefore do not affect the specific on-resistance of the device until a certain value is reached. Therefore, the planar split-gate VDMOSFET of this embodiment can improve the breakdown voltage and long-term reliability of the device while maintaining a constant specific on-resistance.

[0043] The difference between the bottom depth of contact region 8 and the bottom depth of body region 3 is denoted as d. To achieve better results, the value of d needs to be reasonably controlled. If d is too small, when a high voltage is applied to the drain electrode 13, the peak electric field intensity cannot be transferred to the bottom of contact region 8 and will remain above the split gate electrode corner of JFET region 4, i.e., close to the weak point of electric field breakdown. Furthermore, when a high voltage is applied to drain electrode 13, the effect of the depletion layer formed by contact region 8 in enhancing the pinch-off effect of the P-type body region depletion layer is weak, and it cannot sufficiently reduce the electric field concentration at the split gate electrode corner, where the electric field intensity is also large, failing to improve the breakdown voltage and long-term reliability of the device. On the other hand, if d is too large, when the device is forward-biased, the P+ contact region and the depletion layer it forms will affect the original current path, affecting the specific on-resistance of the device. In one embodiment of this application, the bottom of contact region 8 is 0.5 to 2 micrometers deeper than the bottom of body region 3.

[0044] In one embodiment of this application, Figure 2 The contact region 8 shown is formed by etching trench 7 on the outside of the body region 3 (etching the epitaxial layer where the drift region 2 is located), and implanting ions of a second conductivity type on the sides and bottom of the trench 7. By first etching the trench 7 and then implanting to form the contact region 8, a contact region 8 with a bottom depth greater than that of the body region 3 can be formed without using high implantation energy.

[0045] exist Figure 2In the illustrated embodiment, the planar split-gate VDMOSFET further includes a channel region 6 located between the source region 5 and the JFET region 4. The channel region 6 has a second conductivity type and is located on the body region 3. In one embodiment of this application, the doping concentration of the contact region 8 is greater than the doping concentration of the channel region 6.

[0046] In one embodiment of this application, the planar split-gate VDMOSFET further includes a dielectric layer covering the split-gate electrode 10, and the source electrode 12 covers the dielectric layer. Figure 2 In the illustrated embodiment, the dielectric layer includes a gate dielectric layer 9 beneath the split gate electrode 10 and an interlayer isolation dielectric 11 covering the split gate electrode 10. In one embodiment of this application, the gate dielectric layer 9 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 9 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment of this application, the interlayer isolation dielectric 11 may be a dielectric material such as silicon dioxide or silicon nitride.

[0047] In one embodiment of this application, the materials of the split gate electrode 10, the source electrode 12, and the drain electrode 13 can be polysilicon, metal, or alloy.

[0048] In one embodiment of this application, the materials of the drain region 1 and the drift region 2 can be third-generation semiconductor materials such as silicon carbide and gallium nitride.

[0049] exist Figure 2 In the illustrated embodiment, the inner edge of the split gate electrode 10 extends above the JFET region 4, meaning that the orthographic projection of the split gate electrode 10 onto the plane containing the upper surface of the JFET region 4 overlaps with a portion of the JFET region 4. The outer edge of the split gate electrode 10 extends above the source region 5, meaning that the orthographic projection of the split gate electrode 10 onto the plane containing the upper surface of the source region 5 overlaps with a portion of the source region.

[0050] In one embodiment of this application, the bottom and part of the side of the contact area 8 are in direct contact with the drift area 2, part of the side of the contact area 8 is in direct contact with the body area 3, and part of the side of the contact area 8 is in direct contact with the source area 5.

[0051] In one embodiment of this application, the contact region 8 is heavily doped to form an ohmic contact with the source electrode 12, thereby reducing the contact resistance. Furthermore, the heavily doped contact region 8 can reduce the resistance of the second conductive region, and when a high voltage is applied to the drain electrode 13, it can suppress the abnormal turn-on of the parasitic bipolar transistor.

[0052] In one embodiment of this application, the contact region 8 may have a heavily doped surface that contacts the source electrode 12, while the lower part of the contact region 8 may have a medium doping concentration, meaning that the doping concentration of the upper surface and the remaining part of the contact region 8 varies.

[0053] In one embodiment of this application, the drain region 1 is an N+ substrate, the drift region 2 is an N- region, the body region 3 is a P-type region, the JFET region 4 is an N-type region, the source region 5 is an N+ region, the channel region 6 is a P-type region, and the contact region 8 is a P+ region.

[0054] Figure 5 This is a cross-sectional view of a planar split-gate VDMOSFET in another embodiment of this application, including: drain region 1, drift region 2, body region 3, JFET region 4, source region 5, channel region 6, contact region 8, dielectric layer, split gate electrode 10, source electrode 12, and drain electrode 13. Figure 5 The illustrated embodiments and Figure 2 The main difference in the illustrated embodiment is that the contact region 8 is not formed by etching to form a trench 7 and then implanting ions of the second conductivity type; that is, no trench 7 is formed. Accordingly, Figure 2 The source electrode 12, which was filled in the middle trench 7, was replaced by a solid contact area 8.

[0055] In one embodiment of this application, Figure 5 The contact region 8 shown is formed by high-energy ion implantation.

[0056] In another embodiment of this application, Figure 5 The contact area 8 shown is through Figure 6 The drift region 2 shown is formed by multiple epitaxy and multiple implantation of ions of the second conductivity type. Specifically, the formation of the drift region 2 includes multiple epitaxy of N-type semiconductor material, and after each epitaxy, implantation of ions of the second conductivity type is performed in the film layer formed by the epitaxy, thereby forming a second conductivity type region in the film layer formed by each epitaxy. Subsequently, these second conductivity type regions are diffused and connected into a single sheet by heat treatment (annealing) to form the contact region 8.

[0057] Based on all the above embodiments, the planar split-gate VDMOSFET of this application, without affecting the specific on-resistance of the device, makes the electric field breakdown point far away from the corner of the split gate electrode, and can further enhance the pinch-off effect of the depletion layer in the body region 3, reduce the electric field intensity at the corner of the split gate electrode, and achieve multiple effects such as low switching loss, small leakage current at the corner of the split gate electrode, and large breakdown voltage.

[0058] This application provides a method for manufacturing a planar split-gate VDMOSFET. Figure 7This is a flowchart of a method for manufacturing a planar split-gate VDMOSFET according to an embodiment of this application, including the following steps:

[0059] S710, Obtain a wafer on which a first conductivity type layer is formed on a substrate.

[0060] In one embodiment of this application, the substrate is a third-generation semiconductor material having a first conductivity type, such as silicon carbide, gallium nitride, etc. The first conductivity type layer can be formed epitaxially. The substrate subsequently serves as the drain region 1 of the device, and the first conductivity type layer subsequently serves as the drift region 2 of the device.

[0061] S720 forms a JFET region, a body region, a source region, and a contact region in the first conductivity type layer.

[0062] JFET region 4 and source region 5 have a first conductivity type, while body region 3 and contact region 8 have a second conductivity type, both of which can be formed by ion implantation. Body region 3 is formed on both sides of JFET region 4, source region 5 is formed on body region 3 and on both sides of JFET region 4, and contact region 8 is located outside body region 3 (i.e., the side of body region 3 away from JFET region 4), and the bottom of contact region 8 is deeper than the bottom of body region 3.

[0063] S730, a split gate electrode is formed on the first conductivity type layer.

[0064] In one embodiment of this application, a gate dielectric layer 9 is first formed on a first conductivity type layer, and then a split gate electrode 10 is formed on the gate dielectric layer 9. The split gate electrode 10 is separated in the middle, and the separation region is located directly above the JFET region 4.

[0065] S740 forms a source electrode on the source region and the contact region.

[0066] The source electrode 12 is in direct contact with the source region 5 and the contact region 8.

[0067] S750 forms a drain electrode on the back side of the substrate.

[0068] In the above-described method for manufacturing a planar split-gate VDMOSFET, the contact region 8 is positioned such that its bottom is deeper than the body region 3. Therefore, the contact region 8 and the drift region 2 form a PN junction that is deeper than the sum of the body region 3 and the drift region 2. When a high voltage is applied to the drain, the peak electric field intensity shifts to the bottom of the contact region 8. Figure 3 The location indicated by the middle arrow is far from the corner of the split gate electrode above region 4 of the JFET, which is far from the weak point of electric field breakdown at the corner of the split gate electrode above region 4 of the JFET. This makes the device have higher withstand voltage and improves the breakdown voltage of the device, thus having better long-term device reliability under the working environment of high voltage applied to the drain.

[0069] In one embodiment of this application, step S720, forming the contact area 8, involves first etching a first conductivity type layer to form a trench 7, and then implanting second conductivity type ions into the sides and bottom of the trench 7 to form the contact area 8.

[0070] In one embodiment of this application, step S720, forming the contact area 8, specifically includes:

[0071] Step 1: Inject ions of the second conductivity type into the first conductivity type layer to form a second conductivity type region.

[0072] Step two: Form another epitaxial layer on the wafer.

[0073] Step 3: Implant ions of the second conductivity type into the epitaxial layer to form a region of the second conductivity type.

[0074] Repeat steps two and three to form multiple layers of second conductivity type regions. Then, through heat treatment, each second conductivity type region diffuses and connects into one piece to form contact region 8.

[0075] In one embodiment of this application, the contact region 8 can also be formed by high-energy ion implantation.

[0076] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0077] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A planar split-gate VDMOSFET, characterized in that, include: The drain region has the first conductivity type; A drift region, having a first conductivity type, is located on the drain region; The drain electrode is located on the side of the drain region that is opposite to the drift region. The JFET region, having a first conductivity type, is located on the drift region; The body region, having a second conductivity type, is located on the drift region and on both sides of the JFET region; the first conductivity type and the second conductivity type are opposite conductivity types; The source region, having a first conductivity type, is located on the body region and on both sides of the JFET region; A contact region having a second conductivity type is located outside the body region, and the bottom of the contact region is deeper than the bottom of the body region. The outer side of the body region is the side of the body region away from the JFET region. The split gate electrode is separated from the middle, with the split region located directly above the JFET region; The source electrode is located on the source region and the contact region and is in direct contact with the source region and the contact region.

2. The planar split-gate VDMOSFET according to claim 1, characterized in that, The bottom of the contact area is 0.5 to 2 micrometers deeper than the bottom of the body area.

3. The planar split-gate VDMOSFET according to claim 1 or 2, characterized in that, The contact area is formed by etching a trench on the outside of the body region and implanting ions of a second conductivity type on the sides and bottom of the trench.

4. The planar split-gate VDMOSFET according to claim 1 or 2, characterized in that, The contact area is formed by high-energy ion implantation.

5. The planar split-gate VDMOSFET according to claim 1 or 2, characterized in that, The drift region is formed through multiple epitaxy processes, and the contact region is formed by implanting ions of a second conductivity type after each epitaxy process, followed by heat treatment to allow the implanted ions of the second conductivity type to diffuse.

6. The planar split-gate VDMOSFET according to claim 1 or 2, characterized in that, It also includes a channel region located between the source region and the JFET region, the channel region having a second conductivity type.

7. The planar split-gate VDMOSFET according to claim 1 or 2, characterized in that, The bottom and part of the side of the contact area are in direct contact with the drift region, part of the side of the contact area is in direct contact with the body region, and part of the side of the contact area is in direct contact with the source region.

8. A method for manufacturing a planar split-gate VDMOSFET, comprising: Obtain a wafer on a substrate of the first conductivity type having a first conductivity type layer formed thereon; The doping concentration of the substrate is greater than that of the first conductivity type layer; A JFET region, a body region, a source region, and a contact region are formed in the first conductivity type layer; the JFET region and the source region have a first conductivity type, and the body region and the contact region have a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; the body region is formed on both sides of the JFET region, the source region is formed on the body region and on both sides of the JFET region, the contact region is located outside the body region, and the bottom of the contact region is deeper than the bottom of the body region, and the outside of the body region is the side of the body region away from the JFET region; A split gate electrode is formed on the first conductivity type layer; the split gate electrode is separated from the middle, and the separating region is located directly above the JFET region; A source electrode is formed on the source region and the contact region, which is in direct contact with the source region and the contact region; A drain electrode is formed on the side of the substrate opposite to the first conductivity type layer.

9. The method for manufacturing a planar split-gate VDMOSFET according to claim 8, characterized in that, The step of forming the JFET region, body region, source region, and contact region in the first conductivity type layer includes: The first conductivity type layer is etched to form trenches; A second type of conductive ions are injected into the sides and bottom of the trench to form the contact area.

10. The method for manufacturing a planar split-gate VDMOSFET according to claim 8, characterized in that, The step of forming the JFET region, body region, source region, and contact region in the outer first conductivity type layer includes: Step 1: Inject ions of the second conductivity type into the first conductivity type layer to form a second conductivity type region; Step two: Form another epitaxial layer on the wafer; Step 3: Implant ions of the second conductivity type into the epitaxial layer to form a region of the second conductivity type; Repeat steps two and three to form multiple layers of second conductive type regions, and then use heat treatment to diffuse and connect the second conductive type regions into one piece to form the contact area.

Images