Semiconductor device and method for manufacturing semiconductor device
By adjusting the connection method of the trench electrodes in the two-layer structure of the semiconductor substrate, the problem of increased switching loss was solved, achieving higher reliability and stability and reducing switching loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-09
- Publication Date
- 2026-03-27
AI Technical Summary
In existing semiconductor devices with two trench electrodes, the collector-gate capacitance (Cgc) is relatively small, which leads to a smaller ratio of Cgc to emitter-gate capacitance (Cge) (Cgc/Cge). This increases the gate resistance of the semiconductor device, and the recovery dv/dt during turn-on is set to a predetermined value, resulting in increased turn-on losses.
The semiconductor substrate employs a two-layer structure, including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a third semiconductor layer. First and second trench electrodes are provided, covered with an insulating film to form upper and lower electrodes. A tip is formed between the upper and lower electrodes through a spacer insulating film. The lower electrode is connected to the gate potential, and the upper electrode is connected to the emitter potential. The Cgc/Cge ratio is adjusted to reduce turn-on loss.
By adjusting the Cgc/Cge ratio, turn-on losses were reduced, the reliability of the semiconductor device was improved, and the device's durability and the stability of the electric field distribution were enhanced.
Smart Images
Figure CN121751697A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device having a two-layer trench electrode. BACKGROUND
[0002] Recently, as disclosed in Patent Literature 1 Figure 4 , a semiconductor device having a two-layer trench electrode having an upper layer trench electrode on an upper side and a lower layer trench electrode on a lower side in a thickness direction of a semiconductor substrate, and a one-layer trench electrode having a one-layer trench electrode is disclosed.
[0003] In Patent Literature 1, the lower electrode of the two-layer trench electrode is not a gate potential, but is given a source potential, and functions as a field plate electrode. In addition, the trench electrode of the one-layer trench electrode is given a source potential.
[0004] Patent Literature 1: Japanese Patent Application Publication No. 2024-1723
[0005] In the semiconductor device described above, all of the lower electrodes and the trench electrode of the one-layer trench electrode are connected to the source potential, so the collector-gate capacitance (Cgc) is small, and the ratio of Cgc to the emitter-gate capacitance (Cge) (Cgc / Cge) is small, the gate resistance of the semiconductor element is increased, and in a case where the recovery dv / dt at the time of turn-on is set to a predetermined value, there is a problem that the turn-on loss increases. SUMMARY
[0006] The present disclosure is made to solve the above-described problems, and aims to provide a semiconductor device capable of suppressing an increase in turn-on loss and improving reliability in a semiconductor device having a two-layer trench electrode.
[0007] The semiconductor device of the present disclosure includes a semiconductor substrate having at least a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided to an upper layer portion of the second semiconductor layer; a first trench electrode and a second trench electrode provided to an inside of a trench that penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in a thickness direction and reaches the first semiconductor layer; an interlayer insulating film covering the first trench electrode and the second trench electrode; a first main electrode in contact with the third semiconductor layer; and a second main electrode provided on a side opposite to the first main electrode in the thickness direction of the semiconductor substrate, the first trench electrode has a two-layer structure including a lower electrode provided to a lower side of the second main electrode side, an upper electrode provided to an upper side of the first main electrode side, a first trench insulating film covering an inner surface of the trench, and a partition wall insulating film provided between the lower electrode and the upper electrode, a portion of the upper electrode corresponding to an upper side of the lower electrode is a recessed portion, a side wall of the recessed portion is a pointed portion protruding toward a bottom portion of the trench, the partition wall insulating film is provided to cover the recessed portion and the pointed portion, the second trench electrode has a second trench insulating film covering an inner surface of the trench, a trench electrode filled in the trench covered by the second trench insulating film, and a visible portion embedded in an upper region of the second trench insulating film, the upper electrode is connected to a potential of the first main electrode, and the lower electrode and the trench electrode are connected to a gate potential.
[0008] According to the semiconductor device of the present disclosure, it is possible to obtain a semiconductor device in which an increase in on-state loss is suppressed and reliability is improved in a semiconductor device having a trench electrode with a two-layer structure. BRIEF DESCRIPTION OF DRAWINGS
[0009] Figure 1 FIG. 1 is a plan view schematically showing an upper surface structure of a semiconductor device of Embodiment 1 of the present disclosure.
[0010] Figure 2 FIG. 4 is a plan view of a partial region in an active region.
[0011] Figure 3 FIG. 5 is a cross-sectional view of a partial region in an active region.
[0012] Figure 4 FIG. 6 is a graph showing thicknesses of each portion in a two-layer trench electrode and a one-layer trench electrode.
[0013] Figure 5 FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device of Embodiment 1 of the present disclosure.
[0014] Figure 6 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0015] Figure 7 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0016] Figure 8 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0017] Figure 9 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0018] Figure 10 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0019] Figure 11 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0020] Figure 12 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0021] Figure 13 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0022] Figure 14 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0023] Figure 15 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0024] Figure 16 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0025] Figure 17 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0026] Figure 18 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0027] Figure 19 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0028] Figure 20 FIG. 1A is a cross-sectional view showing a manufacturing step of a semiconductor device according to Embodiment 1 of the present disclosure.
[0029] Figure 21 is a sectional view of a partial region in the active region.
[0030] Figure 22 is a sectional view of a partial region in the active region.
[0031] Figure 23 is a sectional view of a partial region in the active region.
[0032] Figure 24 is a sectional view showing the structure of a semiconductor device according to Embodiment 3 of the present disclosure.
[0033] Figure 25 is a sectional view showing the structure of a semiconductor device according to Embodiment 4 of the present disclosure.
[0034] Figure 26 is a plan view schematically showing the upper surface structure of a semiconductor device according to Embodiment 5 of the present disclosure.
[0035] Figure 27 is a plan view of a partial region in the active region.
[0036] Figure 28 is a sectional view of a partial region in the active region.
[0037] BRIEF DESCRIPTION OF DRAWINGS + 1...gate wire; 4...dicing line; 5...terminal region; 6, 206...n － type base layer; 9, 209...n type drift layer; 10, 18, 210, 218...trench insulating film; 14, 214, 314...upper electrode; 15, 215...tip; 16, 216...visible part; 17, 217...trench electrode; 19, 219...lower electrode; 20, 220, 319...barrier insulating film; 30, 230...two-layer trench electrode; 40, 240...one-layer trench electrode; 250...IGBT region; 260...diode region; 300...semiconductor substrate; 301...first main surface; 302...second main surface; 303, 304, 320...insulating film; 350...photoresist. DETAILED DESCRIPTION
[0038] ABSTRACT
[0039] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the drawings are schematic views, and the sizes and the relative positions of the images illustrated in different drawings are not necessarily accurately represented. Also, in the following description, the same reference numerals are used for the same components, and the names and functions thereof are also the same. Thus, detailed description thereof will be omitted.
[0040] In addition, in the following description, terms indicating specific positions and directions such as "upper", "lower", "side", "bottom", "surface", and "back" are used at times, but these terms are used for the sake of easy understanding of the contents of the embodiments, and are not related to the directions at the time of actual implementation. In addition, hereinafter, "outer side" is a direction toward the outer periphery of the semiconductor device, and "inner side" is a direction opposite to the "outer side".
[0041] In addition, in the following description, as for the conduction type of impurities, n-type is generally defined as "first conduction type", and p-type is defined as "second conduction type", but the opposite definition can also be used.
[0042] In addition, n － type indicates a concentration of impurities lower than that of n + type indicates a concentration of impurities higher than that of n － type indicates a concentration of impurities lower than that of p + type indicates a concentration of impurities higher than that of p
[0043] <Embodiment 1>
[0044] <Device Structure>
[0045] Figure 1 is a plan view schematically showing the upper surface structure of an insulated gate bipolar transistor (IGBT) 100 of Embodiment 1 of the present disclosure as a whole. Figure 1 The IGBT 100 shown has a quadrangular shape, and most of it is configured with a plurality of minimum unit structures (IGBT cells) of the IGBT, which are called "cells", and an active region AR through which a main current flows. The outer side of the active region AR becomes a termination region 5. A plurality of trench electrodes (not shown) are provided in parallel at intervals in the active region AR. In addition, the plurality of trench electrodes are connected to a gate wiring 3 provided in the active region AR, and the gate wiring 3 is connected to a gate pad 2. A dicing line 4 is provided on the outer side of the termination region 5. In addition, the shapes and the arrangement of the gate wiring 3 and the gate pad 2 are not limited to Figure 1 .
[0046] In Figure 2 , the Figure 1A top view of the active region AR, which is surrounded by a dashed line. Figure 2 This is a partial top view omitting the upper structures such as the emitter electrode in the active region AR.
[0047] like Figure 2 As shown, two striped trench electrodes 30 (first trench electrode) and one trench electrode 40 (second trench electrode) are disposed parallel to each other in the length direction in the active region AR. The two trench electrodes 30 and the one trench electrode 40 are configured to extend in a direction intersecting the extension direction of the gate wiring 3 disposed in the central portion of the active region AR (left-right direction in the paper). However, the extension direction of the two trench electrodes 30 and the one trench electrode 40 is not limited to this; the vertical direction in the paper can also be used as the extension direction.
[0048] exist Figure 3 The middle shows Figure 2 A sectional view taken at line AA. (See example) Figure 3 As shown, the IGBT100 has an n-shaped structure made of a semiconductor substrate. － Type-shifting layer 9 (first semiconductor layer). － The n-type drift layer 9 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with a concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 15 / cm 3 Semiconductor substrates in Figure 3 The middle is from n + The range from the p-type source layer 6 to the p-type collector layer 12. Figure 3 Lieutenant General n + The upper end of the p-type source layer 6 on the paper is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 12 on the paper is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the outer surface side of the IGBT100, and the second main surface of the semiconductor substrate is the main surface on the back side side of the IGBT100.
[0049] like Figure 3 As shown, in n － The first main surface of the drift layer 9 is provided with a concentration ratio of n-type impurities to n － Type drift layer 9 high n + Type 8 carrier accumulation layer. + The n-type carrier accumulation layer 8 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0 × 10⁻⁶. 13 / cm 3 ~1.0×10 17 / cm 3 By setting n +The n-type carrier accumulation layer 8 can reduce the conduction loss when current flows in the IGBT 100, but can also not be provided. + The n-type carrier accumulation layer 8 can reduce the conduction loss when current flows in the IGBT 100, but can also not be provided. + The n-type carrier accumulation layer 8 can reduce the conduction loss when current flows in the IGBT 100, but can also not be provided. － The n-type drift layer 9 and the p-type base layer 7 are collectively referred to as a drift layer.
[0050] The n-type source layer 6 is provided on the first main surface side of the n-type carrier accumulation layer 8. + A p-type base layer 7 (second semiconductor layer) is provided on the first main surface side of the n-type carrier accumulation layer 8. The p-type base layer 7 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 12 / cm 3 ~ 1.0 x 10 19 / cm 3 The p-type base layer 7 is in contact with the trench insulating film 10 (first trench insulating film) of the two-layer trench electrode 30 and the trench insulating film 18 (second trench insulating film) of the one-layer trench electrode 40.
[0051] An n-type source layer 6 (third semiconductor layer) is provided on the first main surface side of the p-type base layer 7 in a manner in contact with the trench insulating films 10 and 18. + The n-type source layer 6 is provided on the first main surface side of the p-type base layer 7 in a manner in contact with the trench insulating films 10 and 18. + The n-type source layer 6 constitutes the first main surface of the semiconductor substrate. + The n-type source layer 6 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0 x 10 17 / cm 3 ~ 1.0 x 10 20 / cm 3 .
[0052] In addition, an n-type impurity layer 12 having a higher concentration of n-type impurities than the n-type drift layer 9 is provided on the second main surface side of the n-type source layer 6. － The n-type impurity layer 12 is provided on the second main surface side of the n-type source layer 6 in a manner in contact with the trench insulating film 18. － The n-type impurity layer 12 is provided on the second main surface side of the n-type source layer 6 in a manner in contact with the trench insulating film 18. + The n-type impurity layer 12 is provided on the second main surface side of the n-type source layer 6 in a manner in contact with the trench insulating film 18. + The n-type buffer layer 11 is provided to suppress the penetration of a depletion layer extending from the p-type base layer 7 toward the second main surface side when the IGBT 100 is in an off state. + The n-type buffer layer 11 can be formed by implanting, for example, phosphorus (P) or protons (H + ) or by implanting both phosphorus (P) and protons (H + ). 12 The n-type buffer layer 11 has a concentration of n-type impurities of 1.0 x 10 3 / cm 18 ~ 1.0 x 10 3 .
[0053] In addition, a p-type buffer layer 13 is provided on the second main surface side of the n-type buffer layer 11.+ type collector layer 12. That is, in the n － type drift layer 9 and the second main surface, a p + type collector layer 12 is provided. The p + type collector layer 12 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 16 / cm 3 ~ 1.0 x 10 20 / cm 3 .
[0054] The two-layer trench electrode 30 is provided in a trench formed in such a manner that the p-type base layer 7 is penetrated from the first main surface of the semiconductor substrate and the n － type drift layer 9 is reached. That is, the two-layer trench electrode 30 has the trench insulating film 10 on the bottom and the side wall, that is, the inner surface of the trench, the lower electrode 19 is provided on the lower side of the trench surrounded by the trench insulating film 10, and the upper electrode 14 is provided on the upper portion of the lower electrode 19. The lower electrode 19 and the upper electrode 14 are insulated by the partition insulating film 20, the upper electrode 14 is connected to the emitter potential, and the lower electrode 19 is connected to the gate potential.
[0055] The portion corresponding to the upper portion of the lower electrode 19 of the upper electrode 14 becomes a recess, and the side wall of the recess becomes a sharp portion 15 projecting toward the bottom of the trench. The partition insulating film 20 is provided so as to cover the inside of the recess and the sharp portion 15.
[0056] The one-layer trench electrode 40 is provided in a trench formed in such a manner that the p-type base layer 7 is penetrated from the first main surface of the semiconductor substrate and the n － type drift layer 9 is reached. That is, the one-layer trench electrode 40 has the trench insulating film 18 on the bottom and the side wall, that is, the inner surface of the trench, the trench electrode 17 reaching the first main surface from the bottom of the trench, and the visible member 16 composed of an electric conductor is buried in the upper region of the trench insulating film 18 of the side wall.
[0057] The trench insulating film 18 of the one-layer trench electrode 40 contacts the p-type base layer 7 and the n + type source layer 6. When the gate drive voltage is applied to the trench electrode 17, a channel is formed in the p-type base layer 7 in contact with the trench insulating film 18.
[0058] Here, the trench insulating films 10, 18, and the partition insulating film 20 are composed of, for example, a silicon oxide film. The upper electrode 14, the lower electrode 19, the trench electrode 17, and the visible member 16 are composed of, for example, any one of polycrystal silicon, amorphous silicon, and metal. In addition, the trench refers to an opening provided in the semiconductor substrate, but sometimes refers to a structure formed in the opening.
[0059] In addition, as Figure 3As shown, an interlayer insulating film IS is provided on the two-layer trench electrode 30 and the one-layer trench electrode 40, and an emitter electrode 1 (first main electrode) is provided on the first main surface of the semiconductor substrate including the interlayer insulating film IS. In addition, a collector 13 (second main electrode) is provided on the second main surface of the semiconductor substrate on the side opposite to the side on which the emitter electrode 1 is provided in the thickness direction.
[0060] The emitter electrode 1 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be an electrode composed of a plated film of a plurality of layers formed by electroless plating or electroplating on an electrode formed of an aluminum alloy.
[0061] The collector 13 can also be composed of an aluminum alloy or an aluminum alloy and a plated film, like the emitter electrode 1. In addition, the collector 13 can have a different structure from the emitter electrode 1. The collector 13 is in ohmic contact with the p-type collector layer 12 and is electrically connected to the p-type collector layer 12.
[0062] Figure 4 is a view showing the length in the horizontal direction, i.e., the thickness of each part in the two-layer trench electrode 30 and the one-layer trench electrode 40. In Figure 4 In the two-layer trench electrode 30, the thickness of the trench insulating film 10 between the trench side wall and the tip 15 is set to X1, the thickness of the tip 15 is set to X2, and the thickness of the partition wall insulating film 20 between the tip 15 and the lower layer electrode 19 is set to X3. In the one-layer trench electrode 40, the thickness of the trench insulating film 18 between the trench side wall and the visible member 16 is set to X11, the thickness of the visible member 16 is set to X12, and the thickness of the trench insulating film 18 between the visible member 16 and the trench electrode 17 is set to X13. The relationship between the thicknesses is X1 = X11, X2 = X12, and X3 = X13.
[0063] Using the above relationship, the thicknesses X1, X2, and X3 of the two-layer trench electrode 30 are managed, whereby the tip 15 having excellent durability can be formed, and the reliability of the gate of the IGBT 100 can be improved.
[0064] That is, when the IGBT 100 is turned off, a negative bias is applied to the gate-emitter. In this case, holes are concentrated in the vicinity of the emitter electrode 1. If an electric field caused by the negative bias and the holes is applied to the emitter electrode 1, and in particular, if the interval, i.e., the thickness X3, between the tip 15 formed in the upper layer electrode 14 and the lower layer electrode 19 is narrow, the electric field is concentrated in the tip 15. As described above, the electric field strength concentrated in the tip 15 depends on the thickness X3 of the partition wall insulating film 20 between the tip 15 and the lower layer electrode 19, and thus the reliability of the IGBT 100 can be improved by managing the deviation caused by the manufacturing process.
[0065] As described in the manufacturing method below, the thickness X12 of the visible component 16 near the first main surface embedded in the trench insulating film 18 is visible from the upper surface of the wafer during the manufacturing process. Therefore, according to the relationship X2 = X12, the thickness X3 of the partition insulating film 20 between the tip 15 and the lower electrode 19 can be managed, thereby improving the reliability of the IGBT 100.
[0066] In addition, in the IGBT100, the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, which can increase the Cgc / Cge ratio and reduce turn-on losses.
[0067] Furthermore, if the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, the electric field near the tip 15 of the upper electrode 14 near the mesa becomes high when disconnected. However, by managing the thickness X12 of the visible part 16 embedded in the trench electrode 40 and the thickness X2 of the insulating film 20 between the tip 15 and the lower electrode 19, the durability against damage to the tip 15 can be improved, and the reliability of the IGBT 100 can be improved.
[0068] <Manufacturing Method>
[0069] Next, the manufacturing process will be shown sequentially. Figures 5-18 The manufacturing method of IGBT100 will be described below. Furthermore, only the manufacturing methods of the two-layer trench electrode 30 and the one-layer trench electrode 40 will be shown below. The manufacturing methods of other parts besides the two-layer trench electrode 30 and the one-layer trench electrode 40 can be known methods, and therefore will be omitted from the description.
[0070] First, prepare an n-type semiconductor substrate 300. Figure 5 In the process shown, in the region of the semiconductor substrate 300 in which two layers of trench electrodes 30 and one layer of trench electrodes 40 are formed, a trench TR is formed extending from the first main surface 301 of the semiconductor substrate 300 to a predetermined depth along the paper depth direction.
[0071] Next, in Figure 6 In the process shown, an insulating film 303 (first insulating film) is formed in the region (first region) in which two layers of trench electrodes 30 are formed in such a way as to cover the inner surface of the trench TR, and an insulating film 304 (second insulating film) is formed in the region (second region) in which one layer of trench electrodes 40 is formed.
[0072] Next, in Figure 7In the illustrated process, the conductive body CD is embedded in the trench TR via the insulating films 303 and 304, the lower electrode 319 is formed in the region where the two-layered trench electrode 30 is formed, and the trench electrode 317 is formed in the region where the one-layered trench electrode 40 is formed. As the conductive body CD, for example, polysilicon, amorphous silicon, and metal can be used.
[0073] Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317. Figure 8 In the illustrated process, the conductive body CD formed on the first main face 301 is retracted by etching, for example, to expose the upper surfaces of the insulating films 303 and 304.
[0074] Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317. Figure 9 Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317.
[0075] Figure 10 Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317.
[0076] Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317. Figure 11 Figure 12 In the illustrated process, the conductive body CD formed on the first main face 301 is retracted by etching, for example, to expose the upper surfaces of the insulating films 303 and 304.
[0077] Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317. Figure 13 That is, in the retracted insulating films 303 and 304 shown by the arrows in FIG. 6, most of the insulating films 320 and 330 are not formed, and the insulating films 320 and 330 are formed on the trench side wall, the upper end of the lower electrode 319, and the upper end of the trench electrode 317, so that, as shown in FIG. 7, the gap GP for embedding the pointed portion 315 and the visible member 316 is formed.
[0078] Figure 13 Figure 14
[0079] Next, in the region where the two-layered trench electrode 30 is formed, the insulating film 320 (third insulating film) is formed on the upper part of the trench side wall and the lower electrode 319, and in the region where the one-layered trench electrode 40 is formed, the insulating film 330 (fourth insulating film) is formed on the upper part of the trench side wall and the trench electrode 317. Figure 15 In the process shown, a conductor CD is embedded in the trench TR in which insulating films 320 and 330 are formed, an upper electrode 314 including a tip 315 is formed in the region where two layers of trench electrodes 30 are formed, and a visible component 316 is embedded in the region where one layer of trench electrodes 40 is formed.
[0080] Next, in Figure 16 In the process shown, the conductor CD and the insulating film 320 and 330 formed above the first main surface 301 are moved back to the height of the first main surface 301.
[0081] Next, in Figure 17 In the process shown, a trench electrode 40 is observed from the first main surface 301 side to obtain the positional relationship between the trench electrode 317, the visible component 316 and the insulating film 304, and to infer the width and shape of the tip 315 at the lower part of the upper electrode 314 formed on the two trench electrodes 30 for management.
[0082] Given that the estimated width and shape of the tip 315 are within the design range, Figure 18 In the process shown, an insulating film 340 is formed on the upper part of the two trench electrodes 30 and the one trench electrode 40 as an interlayer insulating film. The two trench electrodes 30 and the one trench electrode 40 can be obtained through the above process, and the width and shape of the tip 315 of the two trench electrodes 30 can be managed by using the visible part 316 of the one trench electrode 40.
[0083] <Variation Example 1>
[0084] Figure 19 This is a cross-sectional view showing the structure of IGBT 101 in Modified Example 1 of Embodiment 1, and is related to... Figure 1 The diagram corresponds to the sectional view of the portion of the active region AR enclosed by the dashed line at line AA of 50.
[0085] exist Figure 3 In the IGBT 100 of Embodiment 1 shown, there is a structure in which two trench electrodes 30 and one trench electrode 40 are disposed in the active region AR, but Figure 19 The IGBT101 shown has two trench electrodes 70 in addition to two trench electrodes 30 and one trench electrode 40.
[0086] The structure of the two-layer trench electrode 70 is basically the same as that of the two-layer trench electrode 30. A lower electrode 19 is disposed on the lower side of the trench surrounded by the trench insulating film 10, and an upper electrode 24 is disposed on the upper part of the lower electrode 19. The lower electrode 19 and the upper electrode 24 are insulated from each other by the partition insulating film 20. The only difference between the two-layer trench electrode 70 and the two-layer trench electrode 30 is that the upper electrode 24 is connected to the gate potential.
[0087] The portion of the upper electrode 24 corresponding to the upper portion of the lower electrode 19 becomes a recess, and the side wall of the recess becomes a sharp portion 25 that protrudes toward the bottom of the trench. The partition wall insulating film 20 is provided so as to cover the inside of the recess and the sharp portion 25.
[0088] In addition, in Figure 19 Examples in which the same number of two-layered trench electrodes 30, one-layered trench electrodes 40, and two-layered trench electrodes 70 are provided are shown in FIG. 1, but the number is not limited thereto, and any one of them can be increased or any one of them can be decreased as the total number in the active region AR.
[0089] By providing the two-layered trench electrode 70 that connects the upper electrode 24 and the gate potential, it is possible to adjust the number of the lower electrode 19 connected to the emitter potential as with the two-layered trench electrode 30, and adjust the ratio of Cgc / Cge to a desired value. That is, the more the electrodes connected to the emitter potential, the more Cge decreases, and thus by adjusting the number of the electrodes connected to the emitter potential, it is possible to adjust Cge and adjust the ratio of Cgc / Cge.
[0090] Here, since the two-layered trench electrode 30 and the two-layered trench electrode 70 are used for adjustment of the ratio of Cgc / Cge, they can be referred to as a first adjustment trench electrode and a second adjustment trench electrode, respectively.
[0091] <Modified Example 2>
[0092] In Figure 3 In the IGBT 100 of Embodiment 1 shown in FIG. 1, the potential of the visible member 16 buried in the upper region of the trench insulating film 18 of the one-layered trench electrode 40 is not limited, but the visible member 16 can be connected to any one of the gate potential and the emitter potential, or can be a floating potential. The visible member 16 does not function as an electrode for waterproofing, and is used only for management of the width and shape of the sharp portion 15 of the two-layered trench electrode 30. Thus, by not limiting the potential of the visible member 16, the degree of freedom in design is increased.
[0093] <Embodiment 2>
[0094] Figure 20 is a diagram illustrating a semiconductor device of Embodiment 2, and shows a planar shape of a partial region 60 surrounded by a dashed line in the active region AR of Figure 1 Figure 20 is a partial plan view that omits the upper structure of the emitter electrode and the like in the vicinity of the gate wire 3, and is a plan view of a wire lead-out region.
[0095] The wiring lead-out area is the area where the lower electrode 19 of the two trench electrodes 30 is connected to the gate potential, and the lower electrode 19 is exposed at the end of the two trench electrodes 30.
[0096] Will Figure 20 The sectional view at the BB line is shown in Figure 21 The sectional view at the CC line is shown in Figure 22 The sectional view at the DD line is shown in Figure 23 .
[0097] like Figure 21 as well as Figure 22 As shown, the two trench electrodes 30 have the same structure as the single trench electrode 40 at their ends. The lower electrode 19 extends upward in a manner that contacts the interlayer insulating film IS and is electrically connected to the gate wiring 3 disposed on the interlayer insulating film IS via the contact hole 62.
[0098] In addition, such as Figure 23 As shown, the portion of the two-layer trench electrode 30 outside the end is constructed as two-layer trench electrode 30. The upper electrode 14 is in contact with the interlayer insulating film IS and is electrically connected to the emitter wiring 64 disposed on the interlayer insulating film IS via the contact hole 63.
[0099] In addition, such as Figure 21 As shown, a p-type terminal well region 61 is provided on the terminal region 5 side, which is located on the outer side of the end of the two-layer trench electrode 30.
[0100] Thus, in the wiring lead-out area, the ends of the two trench electrodes 30 have the same structure as the single trench electrode 40, therefore... Figure 22 As shown, the width and shape of the tips 15 of the two trench electrodes 30 can be managed using the visible component 16 of the trench electrode 40.
[0101] <Implementation Method 3>
[0102] Figure 24 This is a diagram illustrating the semiconductor device of Embodiment 3, and it is Figure 1 A cross-sectional view taken at the EE line of a portion 80 of the active region AR, enclosed by a dashed line. The portion 80 is the terminal region 5 on the outer side of the active region AR. A trench electrode 81 formed in the terminal region has the same structure as the trench electrode 40. A trench insulating film 88 is provided at the bottom and sidewalls, i.e., the inner surface, of the trench. A trench electrode 89 extends from the bottom of the trench to the first main surface. A visible component 82 made of a conductor is embedded in the upper region of the trench insulating film 88 on the sidewalls. Therefore, the width and shape of the tips 15 of the two trench electrodes 30 can be managed using the visible component 82.
[0103] Additionally, a p-type terminal well region 61 is provided on the outer side of the trench electrode 81, and an interlayer insulating film IS is provided on the p-type terminal well region 61. Although no structures are shown on the area where the trench electrode 81 is provided, an emitter electrode or an interlayer insulating film can be provided there. The width and shape of the tips 15 of the two trench electrodes 30 are managed using the visible component 82, thus allowing any potential to be applied, including a floating potential.
[0104] <Implementation Method 4>
[0105] Figure 25 This is a diagram illustrating the semiconductor device of Embodiment 4, and it is formed with... Figure 1 A sectional view of the portion of the area enclosed by dashed lines in region 90 of the cutting line 4, taken at line FF. (See also...) Figure 25 As shown, a trench electrode 91 is formed in a portion of region 90. The trench electrode 91 has the same structure as the trench electrode 40, with a trench insulating film 98 on the bottom and sidewalls (inner surface) of the trench, and a trench electrode 99 extending from the bottom of the trench to the first main surface. A visible component 92 made of a conductor is embedded in the upper region of the trench insulating film 98 on the sidewalls. Therefore, the width and shape of the tips 15 of the two trench electrodes 30 can be managed using the visible component 92.
[0106] <Implementation Method 5>
[0107] Figure 26 This is a top view schematically showing the overall upper surface structure of the RC-IGBT (Reverse Conducting IGBT) 200 according to Embodiment 2 of this disclosure. The RC-IGBT 200 includes an IGBT region 250 and a diode region 260 within a semiconductor substrate.
[0108] Multiple diode regions 260 are arranged side-by-side both vertically and horizontally within the RC-IGBT 200, and each diode region 260 is surrounded by an IGBT region 250. That is, multiple diode regions 260 are arranged in an island-like configuration within the IGBT region 250. Furthermore, the diode regions 260 are not limited to... Figure 26 The quantity.
[0109] RC-IGBT200 and Figure 1Similarly, in the IGBT 100 shown, the outer side of the active region AR is a termination region 205. Multiple trench electrodes (not shown) are arranged side-by-side at intervals within the active region AR. These trench electrodes are connected to gate wiring 203 disposed within the active region AR, and the gate wiring 203 is connected to gate pads 202. A cleaving line 204 is provided on the outer side of the termination region 205. Furthermore, the shape and arrangement of the gate wiring 203 and the gate pads 202 are not limited to... Figure 26 .
[0110] Will Figure 26 The top-view shape of the portion of region 51 enclosed by dashed lines in the active region AR is shown in... Figure 27 . Figure 27 This is a partial top view omitting the upper structure of the active region AR, including the emitter electrode, etc.
[0111] exist Figure 27 The active region AR shown has two layers of trench electrodes 230 and one layer of trench electrodes 240 arranged in parallel stripes. The two layers of trench electrodes 230 and the one layer of trench electrodes 240 are arranged parallel to each other along the left-right direction of the arrangement of the plurality of diode regions 260 on the paper. However, the extension direction of the two layers of trench electrodes 230 and the one layer of trench electrodes 240 is not limited to this, and the vertical direction on the paper can also be used as the extension direction.
[0112] Will Figure 27 The sectional view at the GG line in the middle is shown in Figure 28 .like Figure 28 As shown, the IGBT region 250 of the RC-IGBT200 has an n-shaped structure formed by a semiconductor substrate. － Type drift layer 209 (first semiconductor layer). － Type drift layer 209 and IGBT100 n － The drift layer 9 is the same.
[0113] Semiconductor substrate in Figure 28 The middle is from n + The range from the p-type source layer 206 to the p-type collector layer 212. Figure 28 In the middle, n + The upper end of the p-type source layer 206 on the paper is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 212 on the paper is called the second main surface of the semiconductor substrate.
[0114] like Figure 28 As shown, in n － The first main surface of the drift layer 209 is provided with a concentration ratio of n-type impurities to n － Type drift layer 209 high n + Type 208 carrier accumulation layer. +The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0115] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0116] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0117] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0118] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. － The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. － The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0119] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0120] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. Figure 28 The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0121] The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. Figure 28 The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100. + The p-type source layer 206 (third semiconductor layer) is provided on the first main surface side of the n-type drift layer 209 in contact with the trench insulating film 210. The p-type source layer 206 is the same as the n-type source layer 6 of the IGBT 100.
[0122] The p-type anode layer 221 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, with a p-type impurity concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3 n + The n-type cathode layer 222 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, with an n-type impurity concentration of 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 21 / cm 3 .
[0123] Two trench electrodes 230 are disposed on the p-type base layer 207 extending from the first main surface of the semiconductor substrate and reaching the n-type base layer 207. － The trench is formed in a manner similar to a drift layer 209. Specifically, two trench electrodes 230 have trench insulating films 210 on the bottom and sidewalls (inner surfaces) of the trench. A lower electrode 219 is disposed on the lower side of the trench surrounded by the trench insulating film 210, and an upper electrode 214 is disposed above the lower electrode 219. The lower electrode 219 and the upper electrode 214 are insulated from each other by a partition insulating film 220. The upper electrode 214 is connected to the emitter potential, and the lower electrode 219 is connected to the gate potential.
[0124] The portion above the upper electrode 214 and the lower electrode 219 is a recess, and the sidewall of the recess is a pointed portion 215 protruding toward the bottom of the trench. The partition insulating film 220 is configured to cover the recess and the pointed portion 15.
[0125] A trench electrode 240 is disposed on the p-type base layer 207 extending from the first main surface of the semiconductor substrate and reaching the n-type base layer 207. － The trench is formed in a manner similar to a drift layer 209. That is, a trench electrode 240 has a trench insulating film 218 on the bottom and sidewalls of the trench, i.e., the inner surface, and has a trench electrode 217 extending from the bottom of the trench to the first main surface. A visible component 216 made of a conductor is embedded in the upper region of the trench insulating film 218 on the sidewall.
[0126] The two-layer trench electrode 230 and the one-layer trench electrode 240 are the same as the two-layer trench electrode 30 and the one-layer trench electrode 40 of the IGBT100.
[0127] In addition, such as Figure 28As shown, an interlayer insulating film IS is provided on the two-layer trench electrode 230 and the one-layer trench electrode 240, and an emitter electrode 201 (first main electrode) is provided on the first main surface of the semiconductor substrate including the interlayer insulating film IS. In addition, a collector electrode 213 (second main electrode) that also functions as a cathode electrode is provided on the second main surface of the semiconductor substrate on the side opposite to the side on which the emitter electrode 201 is provided in the thickness direction.
[0128] Since the visible part 216 of the one-layer trench electrode 240 and the tip part 215 of the two-layer trench electrode 230 are formed of the same part, the formation conditions are the same, and the width and shape of the tip part 215 of the two-layer trench electrode 230 are managed by using the visible part 216, so that the durability against damage of the tip part 215 can be improved, and the reliability of the RC-IGBT 200 can be improved.
[0129] In addition, the present disclosure can freely combine each embodiment, appropriately omit, and deform each embodiment within the scope of the disclosure.
[0130] The above-described disclosure of the present disclosure is collectively described as a postscript.
[0131] (A postscript 1) A semiconductor device, wherein:
[0132] a semiconductor substrate having at least a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided to an upper layer portion of the second semiconductor layer;
[0133] a first trench electrode and a second trench electrode provided inside a trench that penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in a thickness direction and reaches the first semiconductor layer;
[0134] an interlayer insulating film covering the first trench electrode and the second trench electrode;
[0135] a first main electrode in contact with the third semiconductor layer; and
[0136] a second main electrode provided on the side opposite to the first main electrode in the thickness direction of the semiconductor substrate,
[0137] the first trench electrode is formed in a two-layer structure, having:
[0138] a lower electrode provided on the lower side on the side of the second main electrode;
[0139] an upper electrode provided on the upper side on the side of the first main electrode;
[0140] A first trench insulating film covers the inner surface of the trench; and
[0141] A partition insulating film is disposed between the lower electrode and the upper electrode.
[0142] The portion of the upper electrode corresponding to the upper portion of the lower electrode is a recess, and the sidewall of the recess is a pointed portion protruding toward the bottom of the trench.
[0143] The insulating film of the partition wall is configured to cover the inside of the recess and the tip.
[0144] The second trench electrode has:
[0145] A second trench insulating film covers the inner surface of the trench;
[0146] A trench electrode, which fills the trench covered by the second trench insulating film; and
[0147] A visible component, which is embedded in the upper region of the second trench insulating film.
[0148] The upper electrode is electrically connected to the first main electrode.
[0149] The lower electrode and the trench electrode are connected to the gate potential.
[0150] (Note 2) A semiconductor device, comprising:
[0151] A semiconductor substrate includes a first region and a second region. The first region includes at least: a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, a third semiconductor layer of a first conductivity type disposed on an upper portion of the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type disposed on a side of the first semiconductor layer opposite to the third semiconductor layer in the thickness direction. The second region includes at least: the first semiconductor layer, the second semiconductor layer, a fifth semiconductor layer of a first conductivity type disposed on an upper portion of the third semiconductor layer, and a sixth semiconductor layer of a second conductivity type disposed on a side of the first semiconductor layer opposite to the fifth semiconductor layer in the thickness direction.
[0152] A first trench electrode is disposed inside a first trench that penetrates the third semiconductor layer and the second semiconductor layer in the thickness direction and reaches the first semiconductor layer.
[0153] The second trench electrode is disposed inside the second trench that penetrates the second region and the second semiconductor layer in the thickness direction and reaches the first semiconductor layer.
[0154] An interlayer insulating film covers the first trench electrode and the second trench electrode;
[0155] A first main electrode, which is in contact with the third semiconductor layer and the fifth semiconductor layer; and
[0156] The second main electrode is disposed on the side opposite to the first main electrode in the thickness direction of the semiconductor substrate.
[0157] The first trench electrode forms a two-layer structure, having:
[0158] The lower electrode is disposed on the side below the side that becomes the second main electrode;
[0159] The upper electrode is disposed on the upper side that becomes the first main electrode side;
[0160] A first trench insulating film, which covers the inner surface of the first trench; and
[0161] A partition insulating film is disposed between the lower electrode and the upper electrode.
[0162] The portion of the upper electrode corresponding to the upper portion of the lower electrode is a recess, and the sidewall of the recess is a pointed portion protruding toward the bottom of the trench.
[0163] The insulating film of the partition wall is configured to cover the inside of the recess and the tip.
[0164] The second trench electrode has:
[0165] A second trench insulating film covers the inner surface of the second trench;
[0166] A trench electrode, which fills the trench covered by the second trench insulating film; and
[0167] A visible component, which is embedded in the upper region of the second trench insulating film.
[0168] The upper electrode is electrically connected to the first main electrode.
[0169] The lower electrode and the trench electrode are connected to the gate potential.
[0170] (Note 3) The semiconductor device according to Note 1 or 2, wherein,
[0171] The thickness of the first trench insulating film between the sidewall of the trench and the tip of the first trench electrode is set to X1.
[0172] The thickness of the tip is set to X2.
[0173] The thickness of the insulating film between the tip and the lower electrode is set to X3.
[0174] The thickness of the second trench insulating film between the sidewall of the trench of the second trench electrode and the visible component is set to X11.
[0175] The thickness of the visible component is set to X12.
[0176] When the thickness of the second trench insulating film between the visible component and the trench electrode is set to X13,
[0177] They have the relationships X1 = X11, X2 = X12, and X3 = X13.
[0178] (Note 4) In the semiconductor device according to Note 3, wherein,
[0179] The first trench electrode includes:
[0180] The first adjustment trench electrode, wherein the upper electrode is potential-connected to the first main electrode and the lower electrode is potential-connected to the gate electrode; and
[0181] The upper electrode and the lower electrode are connected to the second adjustment trench electrode of the gate potential.
[0182] (Note 5) In the semiconductor device according to Note 3, wherein,
[0183] The visible component is connected to any one of the potentials of the first main electrode, the gate potential, and the floating potential.
[0184] (Note 6) In the semiconductor device according to Note 4 or 5, wherein,
[0185] The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow.
[0186] The first trench electrode has the same structural portion as the second trench electrode at its end in the longitudinal direction.
[0187] The lower electrode is connected to the trench electrode of the structure and is electrically connected to the gate wiring disposed along the outer periphery of the active region via the trench electrode.
[0188] (Note 7) The semiconductor device according to Note 4 or 5, wherein,
[0189] The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow.
[0190] The second trench electrode is also disposed in the terminal region outside the active region.
[0191] (Note 8) The semiconductor device according to Note 4 or 5, wherein,
[0192] The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow.
[0193] The second trench electrode is also disposed at the outermost cleavage line of the active region.
[0194] (Note 9) The semiconductor device according to any one of Notes 1 to 8, wherein,
[0195] The visible component and the upper electrode are made of the same conductor.
[0196] (Note 10) A method for manufacturing a semiconductor device, comprising the following steps:
[0197] a. The process of forming a first trench and a second trench extending from the main surface of a semiconductor substrate to a specified depth;
[0198] b. The process of forming a first insulating film on the inner surface of the first trench and forming a second insulating film on the inner surface of the second trench;
[0199] c. The process of embedding a conductor through the first insulating film and the second insulating film, forming a lower electrode in the first trench, and forming a trench electrode in the second trench;
[0200] d. The process of removing the conductor on the main surface that is above the first insulating film and the second insulating film;
[0201] e. The process of selectively forming a resist mask in a manner that covers the second trench;
[0202] f. The etching process is performed by using the resist mask as an etching mask, so that the lower electrode is retracted into the first trench and the trench electrode is left in place.
[0203] g. A process of removing the first insulating film and the second insulating film by etching, after removing the resist mask, such that the upper ends of the first insulating film and the second insulating film are lower than the upper ends of the lower electrode and the trench electrode.
[0204] h. The process of forming a third insulating film on the sidewall of the first trench and the upper part of the lower electrode, and forming a fourth insulating film on the trench sidewall of the second trench and the upper part of the trench electrode.
[0205] i. The process of embedding the conductor in the first trench and the second trench in the state where the third insulating film and the fourth insulating film are formed, forming an upper electrode including a tip in the first trench, and embedding a visible component in the second trench.
[0206] j. The process of removing the conductor, the third insulating film, and the fourth insulating film from the main surface;
[0207] k. A process of observing the trench electrode from the main surface side, obtaining the positional relationship between the trench electrode, the visible component, and the second insulating film, and inferring the width and shape of the tip of the first trench for management purposes; and
[0208] l. A process of forming an interlayer insulating film on the upper part of the first trench and the second trench, provided that the estimated width and shape of the tip are within the design range.
Claims
1. A semiconductor device, characterized in that, have: A semiconductor substrate having at least a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of a first conductivity type disposed on an upper portion of the second semiconductor layer; The first trench electrode and the second trench electrode are disposed inside the trench that penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in the thickness direction and reaches the first semiconductor layer. An interlayer insulating film covers the first trench electrode and the second trench electrode; The first main electrode is in contact with the third semiconductor layer; as well as The second main electrode is disposed on the side opposite to the first main electrode in the thickness direction of the semiconductor substrate. The first trench electrode forms a two-layer structure, having: The lower electrode is disposed on the side below the side that becomes the second main electrode; The upper electrode is disposed on the upper side that becomes the first main electrode side; A first trench insulating film covers the inner surface of the trench; as well as A partition insulating film is disposed between the lower electrode and the upper electrode. The portion of the upper electrode corresponding to the upper portion of the lower electrode is a recess, and the sidewall of the recess is a pointed portion protruding toward the bottom of the trench. The insulating film of the partition wall is configured to cover the inside of the recess and the tip. The second trench electrode has: A second trench insulating film covers the inner surface of the trench; A trench electrode that fills the trench covered by the second trench insulating film; as well as A visible component, which is embedded in the upper region of the second trench insulating film. The upper electrode is electrically connected to the first main electrode. The lower electrode and the trench electrode are connected to the gate potential.
2. A semiconductor device, characterized in that, have: A semiconductor substrate includes a first region and a second region. The first region includes at least: a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, a third semiconductor layer of a first conductivity type disposed on an upper portion of the second semiconductor layer, and a fourth semiconductor layer of a second conductivity type disposed on a side of the first semiconductor layer opposite to the third semiconductor layer in the thickness direction. The second region includes at least: the first semiconductor layer, the second semiconductor layer, a fifth semiconductor layer of a first conductivity type disposed on an upper portion of the third semiconductor layer, and a sixth semiconductor layer of a second conductivity type disposed on a side of the first semiconductor layer opposite to the fifth semiconductor layer in the thickness direction. A first trench electrode is disposed inside a first trench that penetrates the third semiconductor layer and the second semiconductor layer in the thickness direction and reaches the first semiconductor layer. The second trench electrode is disposed inside the second trench that penetrates the second region and the second semiconductor layer in the thickness direction and reaches the first semiconductor layer. An interlayer insulating film covers the first trench electrode and the second trench electrode; The first main electrode is in contact with the third semiconductor layer and the fifth semiconductor layer; as well as The second main electrode is disposed on the side opposite to the first main electrode in the thickness direction of the semiconductor substrate. The first trench electrode forms a two-layer structure, having: The lower electrode is disposed on the side below the side that becomes the second main electrode; The upper electrode is disposed on the upper side that becomes the first main electrode side; A first trench insulating film covers the inner surface of the first trench; as well as A partition insulating film is disposed between the lower electrode and the upper electrode. The portion of the upper electrode corresponding to the upper portion of the lower electrode is a recess, and the sidewall of the recess is a pointed portion protruding toward the bottom of the trench. The insulating film of the partition wall is configured to cover the inside of the recess and the tip. The second trench electrode has: A second trench insulating film covers the inner surface of the second trench; A trench electrode that fills the trench covered by the second trench insulating film; as well as A visible component, which is embedded in the upper region of the second trench insulating film. The upper electrode is electrically connected to the first main electrode. The lower electrode and the trench electrode are connected to the gate potential.
3. The semiconductor device according to claim 1 or 2, characterized in that, The thickness of the first trench insulating film between the sidewall of the trench and the tip of the first trench electrode is set to X1. The thickness of the tip is set to X2. The thickness of the insulating film between the tip and the lower electrode is set to X3. The thickness of the second trench insulating film between the sidewall of the trench of the second trench electrode and the visible component is set to X11. The thickness of the visible component is set to X12. When the thickness of the second trench insulating film between the visible component and the trench electrode is set to X13, They have the relationships X1 = X11, X2 = X12, and X3 = X13.
4. The semiconductor device according to claim 3, characterized in that, The first trench electrode includes: The first adjustment trench electrode, wherein the upper electrode is potential-connected to the first main electrode and the lower electrode is potential-connected to the gate electrode; and The upper electrode and the lower electrode are connected to the second adjustment trench electrode of the gate potential.
5. The semiconductor device according to claim 3, characterized in that, The visible component is connected to any one of the potentials of the first main electrode, the gate potential, and the floating potential.
6. The semiconductor device according to claim 4 or 5, characterized in that, The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow. The first trench electrode has the same structural portion as the second trench electrode at its end in the longitudinal direction. The lower electrode is connected to the trench electrode of the structure and is electrically connected to the gate wiring disposed along the outer periphery of the active region via the trench electrode.
7. The semiconductor device according to claim 4 or 5, characterized in that, The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow. The second trench electrode is also disposed in the terminal region outside the active region.
8. The semiconductor device according to claim 4 or 5, characterized in that, The first trench electrode and the second trench electrode are arranged at intervals between each other in a parallel manner along their length in the active region for the main current to flow. The second trench electrode is also disposed at the outermost cleavage line of the active region.
9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The visible component and the upper electrode are made of the same conductor.
10. A method for manufacturing a semiconductor device, characterized in that, It includes the following processes: a. The process of forming a first trench and a second trench extending from the main surface of a semiconductor substrate to a specified depth; b. The process of forming a first insulating film on the inner surface of the first trench and forming a second insulating film on the inner surface of the second trench; c. The process of embedding a conductor through the first insulating film and the second insulating film, forming a lower electrode in the first trench, and forming a trench electrode in the second trench; d. The process of removing the conductor on the main surface that is above the first insulating film and the second insulating film; e. The process of selectively forming a resist mask in a manner that covers the second trench; f. The etching process is performed by using the resist mask as an etching mask, so that the lower electrode is retracted into the first trench and the trench electrode is left in place. g. A process of removing the first insulating film and the second insulating film by etching, after removing the resist mask, such that the upper ends of the first insulating film and the second insulating film are lower than the upper ends of the lower electrode and the trench electrode. h. The process of forming a third insulating film on the sidewall of the first trench and the upper part of the lower electrode, and forming a fourth insulating film on the trench sidewall of the second trench and the upper part of the trench electrode. i. The process of embedding the conductor in the first trench and the second trench in the state where the third insulating film and the fourth insulating film are formed, forming an upper electrode including a tip in the first trench, and embedding a visible component in the second trench. j. The process of removing the conductor, the third insulating film, and the fourth insulating film from the main surface; k. A process of observing the trench electrode from the main surface side, obtaining the positional relationship between the trench electrode, the visible component, and the second insulating film, and inferring the width and shape of the tip of the first trench for management purposes; as well as l. The process of forming an interlayer insulating film on the upper part of the first trench and the second trench, provided that the estimated width and shape of the tip are within the design range.
Citation Information
Patent Citations
Semiconductor device and method of manufacturing the same
JP2024001723A