Semiconductor device
By adjusting the insulating film thickness and electrode position relationship of the semiconductor device, the problem of balancing gate charge and saturation current in the two-stage active trench structure was solved, thereby improving the current conduction performance of the semiconductor device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2026-03-27
AI Technical Summary
In the prior art, the two-stage active trench structure cannot maintain the saturation current while reducing the gate charge, resulting in a decrease in the performance of the semiconductor device.
By adjusting the structure of the semiconductor device, the thickness of the lower insulating film is made greater than that of the upper insulating film, and specific length and area conditions are met. At the same time, the lower end position of the upper electrode is controlled to reduce the gate charge and suppress the decrease of saturation current.
This achieves the goal of maintaining or increasing saturation current while reducing gate charge, thereby enhancing the current conduction capability of semiconductor devices.
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Figure CN121751698A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to semiconductor devices. Background Technology
[0002] For semiconductor devices having upper and lower electrodes that are mutually insulated within a trench, a structure has been proposed in which the lower insulating film that contacts the side portion of the lower electrode is thicker than the upper insulating film that contacts the side portion of the upper electrode (e.g., Patent Document 1). According to such a structure, the switching losses of the semiconductor device can be suppressed by reducing the gate charge while suppressing the influence of the channel on the threshold voltage characteristics.
[0003] Patent Document 1: Japanese Patent No. 7061954
[0004] However, in a two-stage active trench structure, if the thickness of the lower-stage insulating film is increased to reduce the gate charge (Qg), the carrier concentration in the accumulation layer at the trench sidewalls decreases, thus reducing the saturation current (Isat). Therefore, in a two-stage active trench structure, there is a challenge of simultaneously reducing the gate charge (Qg) and maintaining the saturation current (Isat). Summary of the Invention
[0005] Therefore, this disclosure is made in view of the aforementioned problems, and its object is to provide a technique that can suppress the decrease of saturation current while reducing the amount of gate charge.
[0006] The semiconductor device disclosed herein comprises: a semiconductor substrate having a first main surface, and a drift layer of a first conductivity type, a carrier accumulation layer of the first conductivity type with an impurity concentration higher than that of the drift layer, and a base layer of a second conductivity type sequentially disposed toward the first main surface; and a two-stage active trench structure disposed on the first main surface side of the semiconductor substrate, the two-stage active trench structure comprising: a lower insulating film disposed at the lower part of a trench extending from the first main surface through the base layer and the carrier accumulation layer to the drift layer; a lower electrode disposed on the lower insulating film and electrically connected to a gate electrode; an upper insulating film disposed at the upper part of the trench; and an upper electrode disposed on the upper insulating film, electrically connected to the gate electrode, and disposed within the trench and connected to the upper electrode. The lower electrode is insulated, and the thickness of the lower insulating film that contacts the side of the lower electrode is greater than the thickness of the upper insulating film that contacts the side of the upper electrode. It satisfies at least one of the following conditions: (a) the length of the portion of the upper electrode that protrudes downward from the base layer is less than the length of the lower electrode in the vertical direction; (b) the length of the upper electrode in the vertical direction is less than the length of the lower electrode in the vertical direction; and (c) the cross-sectional area of the upper electrode in the unit region is less than the cross-sectional area of the lower electrode in the unit region. The lower end of the upper electrode is located below the lower end of the base layer and above the position where the cumulative value of the impurity concentration in the vertical direction of the carrier accumulation layer is half.
[0007] According to this disclosure, satisfying at least one of conditions (a), (b), and (c), the lower end of the upper electrode is located above a position where the cumulative impurity concentration in the vertical direction of the carrier accumulation layer is half. With this structure, it is possible to suppress the decrease in saturation current while reducing the gate charge. Attached Figure Description
[0008] Figure 1 This is a top view showing the structure of the semiconductor device according to Embodiment 1.
[0009] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.
[0010] Figure 3 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.
[0011] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.
[0012] Figure 5This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 1.
[0013] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device involved in Modification Example 1.
[0014] Figure 7 This is a cross-sectional view showing the structure of the semiconductor device involved in Modification Example 2.
[0015] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device involved in Variation Example 4.
[0016] Figure 9 This is a cross-sectional view showing the structure of the semiconductor device involved in Variation Example 4.
[0017] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device involved in Variation Example 4.
[0018] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 2.
[0019] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 4.
[0020] Figure 13 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 5.
[0021] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device involved in Embodiment 6.
[0022] Explanation of reference numerals in the attached figures
[0023] 1...Emitter electrode; 3...Upper electrode; 4...Upper insulating film; 6...Lower electrode; 7...Lower insulating film; 8...Trench; 9...Drift layer; 14...Base layer; 15...Carrier accumulation layer; 16...Gate electrode; 17...Two-stage active trench structure; 18...Dummy active trench structure; 19...Cellular region; 22...Insulating component; 23...Recessed active trench structure. Detailed Implementation
[0024] The embodiments will now be described with reference to the accompanying drawings. The features described in the following embodiments are illustrative, and not all features are essential. Furthermore, in the following description, the same or similar reference numerals are used to denote the same components in multiple embodiments, and the different components will be described primarily. Additionally, in the following description, specific positions and directions such as "upper," "lower," "left," "right," "front," or "back" do not necessarily need to correspond to the actual positions and directions in the implementation. Furthermore, a higher concentration in one part than other parts may mean, for example, that the average concentration of that part is higher than the average concentration of the other parts. Conversely, a lower concentration in one part than other parts may mean, for example, that the average concentration of that part is lower than the average concentration of the other parts. Furthermore, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may also be p-type and the second conductivity type n-type.
[0025] <Implementation Method 1>
[0026] Figure 1 This is a top view showing the structure of the semiconductor substrate included in the semiconductor device according to Embodiment 1. Figure 1 In the semiconductor substrate, a cell region 19 on which semiconductor elements are disposed is defined, a terminal region 20 surrounding the cell region 19, and an outer peripheral region 21 surrounding the terminal region 20.
[0027] Semiconductor substrates can be made of conventional semiconductor wafers or epitaxial growth layers. Furthermore, semiconductor substrates can be made of conventional silicon (Si) or wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. When the semiconductor substrate is made of a wide-bandgap semiconductor, stable operation of the semiconductor device under high temperatures and high voltages, as well as high-speed switching of the semiconductor device, are possible.
[0028] Figures 2-5This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 1, specifically a cross-sectional view showing the structure of the unit region 19 where the semiconductor element is disposed. Hereinafter, the structure of an IGBT (Insulated Gate Bipolar Transistor) as the semiconductor element will be described as an example, but it is not limited to this. The semiconductor element can be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an RC-IGBT (Reverse Conducting IGBT) having an IGBT region where an IGBT is disposed and a diode region where an SBD (Schottky Barrier Diode) and a PND (PN junction diode) are disposed.
[0029] like Figure 2 As shown, the semiconductor substrate includes n － Type 9 drift layer, n-type carrier accumulation layer, p-type base layer, n ＋ The semiconductor substrate has a source layer 2 of type n, a buffer layer 10 of type n, and a collector layer 11 of type p. The semiconductor substrate has a first main surface corresponding to the upper end of the source layer 2 and a second main surface corresponding to the lower end of the collector layer 11.
[0030] Next, the layers of the semiconductor substrate will be described. A carrier accumulation layer 15 with a higher n-type impurity concentration than the drift layer 9 is provided on the first main surface side of the drift layer 9. A base layer 14 is provided on the first main surface side of the carrier accumulation layer 15. A source layer 2 with a higher n-type impurity concentration than the carrier accumulation layer 15 is provided on the first main surface side of the base layer 14.
[0031] Thus, in the semiconductor substrate according to Embodiment 1, a drift layer 9, a carrier accumulation layer 15, a base layer 14, and a source layer 2 are sequentially disposed toward the first main surface. On the other hand, in the semiconductor substrate, a drift layer 9, a buffer layer 10, and a collector layer 11 are sequentially disposed toward the second main surface. Each layer of the semiconductor substrate is selectively formed, for example, by mask formation and ion implantation.
[0032] The semiconductor device not only has a semiconductor substrate, but also has a two-stage active trench structure 17, an interlayer insulating film 13, an emitter electrode 1, and a collector electrode 12.
[0033] The two-stage active trench structure 17 includes a lower insulating film 7, a lower electrode 6, a boundary insulating film 5, an upper insulating film 4, and an upper electrode 3, and is disposed on the first main surface side of the semiconductor substrate.
[0034] The lower insulating film 7 is disposed at the lower part of the trench 8 that extends from the first main surface of the semiconductor substrate through the source layer 2, the base layer 14, and the carrier accumulation layer 15 to the drift layer 9. The lower electrode 6 is disposed on the lower insulating film 7, and as shown in the figure. Figure 3 It is electrically connected to the gate electrode 16. Furthermore, although not shown, the gate electrode 16 is disposed on the semiconductor substrate in the same manner as the emitter electrode 1, and corresponds to the gate pad to which the gate potential is applied from the outside.
[0035] Figure 2 The boundary insulating film 5 is disposed on the upper part of the lower electrode 6. The upper insulating film 4 is disposed on the upper part of the trench 8. The lower insulating film 7, the boundary insulating film 5, and the upper insulating film 4 are formed, for example, by thermal oxidation and CVD (Chemical Vapor Deposition). The upper electrode 3 is disposed on the upper insulating film 4 and is insulated from the lower electrode 6 within the trench 8 by the boundary insulating film 5. The lower end of the upper electrode 3 is located below the lower end of the base layer 14. Additionally, as... Figure 3 As shown, the upper electrode 3 is electrically connected to the gate electrode 16.
[0036] Figure 2 An interlayer insulating film 13 is disposed on the upper electrode 3. The emitter electrode 1 is configured to cover the source layer 2 and the interlayer insulating film 13, is electrically connected to the source layer 2, and is insulated from the upper electrode 3 through the interlayer insulating film 13. The collector electrode 12 is configured to cover the collector layer 11 and is electrically connected to the collector layer 11.
[0037] like Figure 4 As shown, the thickness (Lb) of the lower insulating film 7 that contacts the side of the lower electrode 6 is thicker than the thickness (La) of the upper insulating film 4 that contacts the side of the upper electrode 3. In addition, the condition (a) is satisfied that the length (T2) of the portion of the upper electrode 3 that protrudes downward from the base layer 14 is less than the vertical length (T1) of the lower electrode 6.
[0038] Here, the gate charge (Qg) is directly proportional to the surface area of the insulating film and inversely proportional to its thickness. Therefore, according to the semiconductor device of Embodiment 1 configured as described above, the total length (T1) and length (T2) are the same as in Embodiment 1, and the gate charge (Qg) can be reduced compared to a structure where the length (T2) is greater than the length (T1). On the other hand, in a semiconductor device with a thick lower insulating film 7 (Lb), the carrier concentration in the n-type accumulation layer such as the carrier accumulation layer 15 at the sidewall of the trench 8 is reduced, thus reducing the carrier concentration at the interface of the trench 8 and decreasing the saturation current (Isat).
[0039] Therefore, such as Figure 5 As shown, in this embodiment 1, the lower end of the upper electrode 3 is configured to be located above the position (CS1) where the cumulative value of the impurity concentration in the carrier accumulation layer 15 in the vertical direction is half. Here, in a typical two-stage active trench structure 17, the electric field increases at the boundary between the thin upper insulating film 4 and the thick lower insulating film 7. In this embodiment 1, since the lower end of the upper electrode 3 is located above the position (CS1), the boundary where the electric field increases is located near the base layer 14. Therefore, the electric field in the mesa area (i.e., the portion between adjacent trenches 8) near the trench (i.e., near the base layer 14) can be increased, and the field plate effect of the trench 8 can be weakened.
[0040] The current I injected from the channel is expressed as I = qnμE, which is approximately proportional to the electric field E near the channel. Therefore, by increasing the electric field near the channel, the drift current increases, and thus, according to the semiconductor device according to Embodiment 1, the decrease in saturation current (Isat) caused by increasing the thickness (Lb) of the lower insulating film 7 can be suppressed.
[0041] Furthermore, the thickness of the lower insulating film 7, which contacts the bottom of the lower electrode 6 rather than its side, is preferably thicker than the thickness (La) of the upper insulating film 4, which contacts the side of the upper electrode 3. With this structure, the electric field is less likely to concentrate at the bottom of the two-stage active trench structure 17, thereby increasing the electric field on the mesa near the trench. As a result, the decrease in saturation current (Isat) caused by increasing the thickness (Lb) of the lower insulating film 7 can be further suppressed.
[0042] <Summary of Implementation Method 1>
[0043] According to the semiconductor device of this embodiment 1 as described above, the thickness (Lb) of the lower insulating film 7 that contacts the side of the lower electrode 6 is thicker than the thickness (La) of the upper insulating film 4 that contacts the side of the upper electrode 3. The length (T2) of the portion of the upper electrode 3 that protrudes downward from the base layer 14 is less than the vertical length (T1) of the lower electrode 6. The lower end of the upper electrode 3 is located above a position where the cumulative value of the impurity concentration in the vertical direction of the carrier accumulation layer 15 is half (CS1). With this structure, it is possible to suppress the decrease in saturation current (Isat) while reducing the gate charge (Qg).
[0044] <Variation Example 1>
[0045] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device involved in Modification Example 1. In Embodiment 1, the condition (a) is satisfied that the length (T2) of the portion of the upper electrode 3 protruding downward from the base layer 14 is less than the vertical length (T1) of the lower electrode 6. In this Modification Example 1, condition (a) is not satisfied, but rather... Figure 6 In this way, the condition (b) is met that the vertical length (T3) of the upper electrode 3 is less than the vertical length (T1) of the lower electrode 6.
[0046] As described above, the gate charge (Qg) is directly proportional to the surface area of the insulating film and inversely proportional to its thickness. Therefore, in the semiconductor device according to this modified example 1, the total length (T1) and length (T3) are the same as in this modified example 1. Compared to a structure where the length (T3) is greater than the length (T1), the gate charge (Qg) can be reduced. Apart from this, the structure of modified example 1 is the same as that of embodiment 1. Therefore, according to the structure of this modified example 1, the reduction of the saturation current (Isat) can be suppressed while suppressing the gate charge (Qg).
[0047] <Variation Example 2>
[0048] Figure 7 This is a cross-sectional view showing the structure of the semiconductor device involved in Modification 2. In this Modification 2, conditions (a) and (b) are not satisfied, but rather... Figure 7 In this way, the condition (c) is satisfied that the cross-sectional area (S2) of the upper electrode 3 in unit region 19 is smaller than the cross-sectional area (S1) of the lower electrode 6 in unit region 19.
[0049] As described above, the gate charge (Qg) is directly proportional to the surface area of the insulating film and inversely proportional to its thickness. Therefore, in the semiconductor device according to this modified example 2, the total cross-sectional area (S1) and cross-sectional area (S2) are the same as in this modified example 2. Compared to a structure where the cross-sectional area (S2) is larger than the cross-sectional area (S1), the gate charge (Qg) can be reduced. Apart from this, the structure of modified example 2 is the same as that of embodiment 1. Therefore, according to the structure of this modified example 2, the reduction of the gate charge (Qg) can be reduced while suppressing the decrease of the saturation current (Isat).
[0050] In summary, it is sufficient to satisfy at least one of the conditions (a) of Embodiment 1, (b) of Modification 1, and (c) of Modification 2. Furthermore, in this specification, for example, at least one of A, B, C, ..., and Z means any combination of all combinations formed by extracting one or more from the group of A, B, C, ..., and Z.
[0051] <Variation Example 3>
[0052] exist Figure 5 In this configuration, the peak position (CS2) of the impurity concentration in the carrier accumulation layer 15 is located above the position (CS1) where the cumulative value of the impurity concentration in the vertical direction of the carrier accumulation layer 15 is half. In this case, the lower end of the upper electrode 3 can also be located above the peak position (CS2). With this structure, the electric field on the mesa near the channel can be further increased, the drift current can be further increased, and thus the decrease in saturation current (Isat) can be further suppressed.
[0053] In addition, Figure 5 In this configuration, the center position (CS3) of the carrier accumulation layer 15 in the vertical direction is located below the position (CS1) where the cumulative impurity concentration in the vertical direction of the carrier accumulation layer 15 is half that of the center position (CS1). However, depending on the distribution of the impurity concentration, the center position (CS3) may sometimes be located above the center position (CS1). In this case, the lower end of the upper electrode 3 may also be located above the center position (CS3). With this structure, the electric field on the mesa near the channel can be further increased, the drift current can be further increased, and thus the decrease in saturation current (Isat) can be further suppressed.
[0054] <Variation Example 4>
[0055] Figures 8-10 This is a cross-sectional view showing the structure of the semiconductor device involved in Variation Example 4. For example... Figure 8 In that case, the bottom of the upper electrode 3 can also have a recessed portion in the center. Additionally, as... Figure 9In that case, the upper part of the lower electrode 6 can also have a protrusion with a central portion. Additionally, as... Figure 10 That way, it can also be used to target Figure 9 The structure positions the upper end of the lower electrode 6 above the lower end of the upper electrode 3.
[0056] Furthermore, following Embodiment 2, we will describe a structure that has been appropriately modified from the structure of Embodiment 1. However, in Embodiments 1 to 4, modifications following Embodiment 2 may also be performed.
[0057] <Implementation Method 2>
[0058] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. Figure 11 Therefore, in this embodiment 2, not only are two-stage active trench structures 17 provided on the first main surface side of the semiconductor substrate, but also a dummy active trench structure 18 is provided. The dummy active trench structure 18 is a structure corresponding to the two-stage active trench structures 17, that is, the same structure as the two-stage active trench structures 17. However, in the dummy active trench structure 18, the emitter electrode 1 is electrically connected to the upper electrode 3 instead of the gate electrode 16.
[0059] In the upper part of the dummy active trench structure 18 constructed in this way, no capacitance is substantially generated. Therefore, according to the semiconductor device according to Embodiment 2, the gate charge (Qg) can be further reduced.
[0060] <Implementation Method 3>
[0061] In this embodiment 3, at least one of the above conditions (a) to (c) and the following formula (1) are satisfied.
[0062] A×Cgc1>(A+D)×Cgc2・・・(1)
[0063] Where A is the number of two-stage active trench structures 17 in cross-sectional observation, and D is the number of dummy active trench structures 18 in cross-sectional observation. Cgc1 is the capacitance per unit length of the upper insulating film 4 that contacts the side portion of the portion protruding downward from the base layer 14 in the upper electrode 3, and Cgc2 is the capacitance per unit length of the lower insulating film 7 that contacts the side portion of the lower electrode 6. When equation (1) is modified, equation (2) can be obtained.
[0064] Y<100×(1-1 / (Lb / La))・・・(2)
[0065] Y [%] is the ratio of the number of dummy active trench structures 18 to the number of two-stage active trench structures 17 and dummy active trench structures 18 during cross-sectional observation, i.e., the sparsity, expressed as Y = 100 × D / (A + D). For example, when A = 1 and A + D = N, it is expressed as Y = 100 × (N - 1) / N. Similar to Embodiment 1, La is the thickness of the upper insulating film 4 that contacts the side of the upper electrode 3, and Lb is the thickness of the lower insulating film 7 that contacts the side of the lower electrode 6.
[0066] In this embodiment 3, since at least one of the above conditions (a) to (c) and equation (2) (i.e. equation (1)) are satisfied, the capacitance (Cgc) of the semiconductor device can be reduced, and as a result, the gate charge (Qg) can be reduced.
[0067] <Implementation Method 4>
[0068] Figure 12 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 4. Figure 12 Thus, in this embodiment 4, the groove 8 has a conical shape that tapers towards the bottom.
[0069] Furthermore, the cone angle of the sidewall with the cone-shaped portion in the groove 8 relative to the horizontal direction is preferably 89 degrees or less, more preferably 87 degrees or less, and even more preferably 85 degrees or less. Additionally, the depth of the groove 8 is preferably 3 μm or more, more preferably 4 μm or more, and even more preferably 5 μm or more.
[0070] According to the semiconductor device of this embodiment 4, the cross-sectional area of the lower insulating film 7 can be reduced, thereby further reducing the gate charge (Qg).
[0071] <Implementation Method 5>
[0072] Figure 13 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 5. For example... Figure 13 Therefore, in this embodiment 5, not only is a two-stage active trench structure 17 provided on the first main surface side of the semiconductor substrate, but a recessed active trench structure 23 is also provided. The recessed active trench structure 23 is a structure corresponding to the two-stage active trench structure 17, that is, the same structure as the two-stage active trench structure 17. However, the recessed active trench structure 23 includes an insulating member 22 as an insulating member, which replaces the upper electrode 3.
[0073] The insulating component 22 can be made of the same material as the upper insulating film 4, or it can be made of the same material as the interlayer insulating film 13. In structures with the same materials, the manufacturing process can be simplified and the manufacturing cost can be reduced.
[0074] Furthermore, the insulating component 22 can be a thermally oxidized film formed by thermal oxidation or a CVD film formed by CVD. Since thermally oxidized films have superior electrical properties compared to CVD films, gate characteristics can be improved when the insulating component 22 is a thermally oxidized film. On the other hand, the impurity concentration of CVD films is generally higher than that of thermally oxidized films, and manufacturing costs can be reduced. Alternatively, for example, if the upper insulating film 4 or the lower insulating film 7 is a thermally oxidized film with excellent electrical properties, the insulating component 22 can also be a CVD film. The impurity concentration of the insulating component 22 can also be higher than that of the upper insulating film 4 or the lower insulating film 7.
[0075] As described in Implementation Method 2 Figure 11 In the dummy active trench structure 18, a capacitance (Cge) is generated between the lower electrode 6 connected to the gate electrode 16 and the upper electrode 3 connected to the emitter electrode 1, which contributes to the increase of the gate charge (Qg). In contrast, the recessed active trench structure 23 of this embodiment can further reduce the gate charge (Qg) because it can reduce the capacitance (Cge).
[0076] <Implementation Method 6>
[0077] Figure 14 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 6. For example... Figure 14 Thus, in this embodiment 6, the upper insulating film 4 that contacts the side of the upper electrode 3 includes a first portion that contacts the base layer 14 and a second portion that does not contact the base layer 14. Moreover, the thickness (Lc) of the second portion is thicker than the thickness (La) of the first portion. With this structure, the capacitance of the second portion of the upper insulating film 4 can be reduced, and therefore the gate charge (Qg) can be further reduced.
[0078] Furthermore, in this English disclosure, 'a' and 'an' mean more than one. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used with the same meaning.
[0079] Furthermore, the various embodiments (and their variations) can be freely combined, or appropriately modified, omitted, or adapted.
[0080] The various forms disclosed herein will be recorded hereafter as appendices.
[0081] (Note 1) A semiconductor device, wherein,
[0082] The aforementioned semiconductor device includes:
[0083] A semiconductor substrate has a first main surface, and a drift layer of a first conductivity type, a carrier accumulation layer of the first conductivity type with a higher impurity concentration than the drift layer, and a base layer of a second conductivity type are sequentially disposed facing the first main surface; and
[0084] A two-stage active trench structure is disposed on the first main surface side of the aforementioned semiconductor substrate.
[0085] The aforementioned two-stage active trench structure includes:
[0086] The lower insulating film is disposed in the lower part of the trench that extends from the first main surface through the base layer and the carrier accumulation layer and reaches the drift layer;
[0087] The lower electrode is disposed on the aforementioned lower insulating film and is electrically connected to the gate electrode;
[0088] An upper insulating film is disposed on the upper part of the aforementioned trench; and
[0089] The upper electrode is disposed on the upper insulating film, electrically connected to the gate electrode, and insulated from the lower electrode within the trench.
[0090] The thickness of the lower insulating film that contacts the side portion of the lower electrode is greater than the thickness of the upper insulating film that contacts the side portion of the upper electrode.
[0091] The following conditions must be met: (a) the length of the portion of the upper electrode that protrudes downward from the base layer is less than the length of the lower electrode in the vertical direction; (b) the length of the upper electrode in the vertical direction is less than the length of the lower electrode in the vertical direction; and (c) the cross-sectional area of the upper electrode in the unit region is less than the cross-sectional area of the lower electrode in the unit region.
[0092] The lower end of the aforementioned upper electrode is located below the lower end of the aforementioned base layer, and above the position where the cumulative value of the aforementioned impurity concentration in the aforementioned carrier accumulation layer in the aforementioned vertical direction is half.
[0093] (Note 2) In the semiconductor device according to Note 1, wherein,
[0094] The lower end of the aforementioned upper electrode is located above the position of the peak value of the impurity concentration in the aforementioned carrier accumulation layer.
[0095] (Note 3) The semiconductor device according to Note 1, wherein,
[0096] The lower end of the aforementioned upper electrode is located above the center position in the vertical direction of the aforementioned carrier accumulation layer.
[0097] (Appendix 4) The semiconductor device according to any one of Appendices 1 to 3, wherein,
[0098] It also has a dummy active trench structure, which is a structure corresponding to the two-stage active trench structure mentioned above, wherein the emitter electrode replaces the gate electrode and is electrically connected to the upper electrode of the dummy active trench structure.
[0099] (Appendix 5) The semiconductor device according to any one of Appendices 1 to 4, wherein,
[0100] The aforementioned groove has a conical shape that tapers at the end as it faces downwards.
[0101] (Note 6) The semiconductor device according to Note 4, wherein,
[0102] When the number of the above-mentioned dummy active trench structures in cross-sectional observation is set to the ratio of the number of the above-mentioned two-level active trench structures and the number of the above-mentioned dummy active trench structures, i.e., the sparsity rate is set to Y [%], the thickness of the above-mentioned upper insulating film is set to La, and the thickness of the above-mentioned lower insulating film is set to Lb, Y < 100 × (1 - 1 / (Lb / La)).
[0103] (Note 7) The semiconductor device according to any one of Notes 1 to 6, wherein,
[0104] It also has a recessed active trench structure, which corresponds to the structure of the two-stage active trench structure mentioned above, wherein an insulating component is included instead of the upper electrode.
[0105] (Appendix 8) The semiconductor device according to any one of Appendices 1 to 7, wherein,
[0106] The upper insulating film that contacts the side portion of the upper electrode includes:
[0107] Part 1, in contact with the aforementioned base layer; and
[0108] Part 2 does not contact the base layer mentioned above and is thicker than Part 1.
Claims
1. A semiconductor device, wherein, The semiconductor device includes: A semiconductor substrate has a first main surface, and a drift layer of a first conductivity type, a carrier accumulation layer of the first conductivity type with an impurity concentration higher than that of the drift layer, and a base layer of a second conductivity type are sequentially disposed facing the first main surface. and A two-stage active trench structure is disposed on the first main surface side of the semiconductor substrate. The two-stage active trench structure includes: The lower insulating film is disposed in the lower part of the trench that extends from the first main surface through the base layer and the carrier accumulation layer and reaches the drift layer; The lower electrode is disposed on the lower insulating film and is electrically connected to the gate electrode; An upper insulating film is disposed on the upper part of the trench; and The upper electrode is disposed on the upper insulating film, electrically connected to the gate electrode, and insulated from the lower electrode within the trench. The thickness of the lower insulating film that contacts the side portion of the lower electrode is greater than the thickness of the upper insulating film that contacts the side portion of the upper electrode. The following conditions must be met: (a) the length of the portion of the upper electrode protruding downwards from the base layer is less than the vertical length of the lower electrode; (b) the vertical length of the upper electrode is less than the vertical length of the lower electrode; and (c) the cross-sectional area of the upper electrode in the unit region is less than the cross-sectional area of the lower electrode in the unit region. The lower end of the upper electrode is located below the lower end of the base layer and above the position where the cumulative value of the impurity concentration in the carrier accumulation layer in the vertical direction is half.
2. The semiconductor device according to claim 1, wherein, The lower end of the upper electrode is located above the peak value of the impurity concentration in the carrier accumulation layer.
3. The semiconductor device according to claim 1, wherein, The lower end of the upper electrode is located above the center position of the carrier accumulation layer in the vertical direction.
4. The semiconductor device according to any one of claims 1 to 3, wherein, It also has a dummy active trench structure, which is a structure corresponding to the two-stage active trench structure, wherein the emitter electrode replaces the gate electrode and is electrically connected to the upper electrode of the dummy active trench structure.
5. The semiconductor device according to any one of claims 1 to 4, wherein, The groove has a tapered shape that tapers at the end as it faces downwards.
6. The semiconductor device according to claim 4, wherein, When the number of the dummy active trench structures in the cross-sectional observation is set to the ratio of the number of the two-stage active trench structures and the number of the dummy active trench structures, i.e., the sparsity is set to Y [%), the thickness of the upper insulating film is set to La, and the thickness of the lower insulating film is set to Lb, Y < 100 × (1 - 1 / (Lb / La)).
7. The semiconductor device according to any one of claims 1 to 6, wherein, It also has a recessed active trench structure, which is a structure corresponding to the two-stage active trench structure, wherein an insulating component is included instead of the upper electrode.
8. The semiconductor device according to any one of claims 1 to 7, wherein, The upper insulating film that contacts the side portion of the upper electrode includes: Part 1, in contact with the base layer; and The second part does not contact the base layer and is thicker than the first part.