MOS device and preparation method thereof

Abstract

The invention relates to the field of semiconductors, and provides an MOS device and a preparation method thereof, and the MOS device comprises a substrate; the epitaxial layer is located on the substrate and has a first doping type; the plurality of base regions are arranged in the epitaxial layer at intervals and have a second doping type; the source electrode is positioned on one side of the base region deviating from the substrate; the JFET region is located between adjacent base regions in the epitaxial layer; the grid electrode is located on the side, away from the substrate, of the JFET region; a well region in contact with the source electrode, a source region and a laminated conductive structure are arranged in the base region, the source region is located on the side, close to the JFET region, of the well region and is spaced from the edge of the base region, the well region has a second doping type, the source region has a first doping type, the laminated conductive structure comprises a first metal layer and a second metal layer, the first metal layer is in contact with the well region and the source region, and the second metal layer is in contact with the second metal layer. The surface, close to the substrate, of the second metal layer is closer to the substrate than the surfaces, close to the substrate, of the well region and the source region, and the second metal layer is located on the side, close to the substrate, of the first metal layer and is an ohmic metal layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOS device and a method for fabricating the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are key power electronic components widely used in various high-voltage and high-power applications, including but not limited to new energy vehicles and photovoltaic inverter systems. MOSFETs utilize the properties of semiconductor materials to control the flow of charge carriers between the source and drain by applying an external voltage, thereby realizing the switching function in a circuit.

[0003] Silicon carbide (SiC), as an outstanding representative of third-generation semiconductor materials, has gained widespread attention in the field of power electronics due to its excellent physical and electronic properties. SiC's wide bandgap, high breakdown electric field strength, high thermal conductivity, and high saturated electron drift velocity make it a good choice for manufacturing high-performance MOSFETs.

[0004] In SiC-based MOSFETs, device structure design has a significant impact on performance, including current control, thermal management, and reliability. In particular, reducing the on-resistance of the MOSFET is crucial for high-frequency and high-power applications.

[0005] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide a MOS device and its fabrication method to solve the problem of high on-resistance in existing MOS devices.

[0007] To achieve the above objectives, according to one aspect of this application, a MOS device is provided, comprising: a substrate; an epitaxial layer disposed on the substrate and having a first doping type; a plurality of base regions disposed at intervals within the epitaxial layer and having a second doping type opposite to the first doping type; a source electrode disposed on the side of the base regions away from the substrate; a JFET region located between adjacent base regions within the epitaxial layer; and a gate electrode disposed on the side of the JFET region away from the substrate; wherein, a well region, a source region, and a stacked conductive structure are disposed within the base regions respectively in contact with the source electrode, the source region is located on the side of the well region near the JFET region and is spaced from the edge of the base region, the well region has the second doping type, the source region has the first doping type, the stacked conductive structure includes a first metal layer and a second metal layer, the first metal layer is in contact with the well region and the source region respectively, and the surface of the first metal layer near the substrate is closer to the substrate than the surfaces of the well region and the source region near the substrate, the second metal layer is located on the side of the first metal layer near the substrate, and the second metal layer is an ohmic metal layer.

[0008] In some embodiments of this application, the stacked conductive structure further includes at least one of the following: a first barrier layer disposed on the side of the first metal layer facing away from the substrate; a second barrier layer disposed on the side of the second metal layer facing away from the substrate; wherein the first barrier layer and the second barrier layer are conductive metal nitrides.

[0009] In some embodiments of this application, the stacked conductive structure further includes an adhesion layer located between the first metal layer and the second barrier layer, and the adhesion layer is conductive.

[0010] In some embodiments of this application, the conductivity of the first metal layer is higher than that of the second metal layer.

[0011] In some embodiments of this application, the material of the first metal layer includes at least one of tungsten and aluminum, and the material of the second metal layer includes titanium.

[0012] In some embodiments of this application, the materials of the first barrier layer, the second barrier layer, and the adhesive layer all include titanium compounds.

[0013] In some embodiments of this application, the material of the adhesive layer includes a titanium-tungsten alloy.

[0014] In some embodiments of this application, the ratio of the depth of the stacked conductive structure to the width of the stacked conductive structure in the arrangement direction of the well region and the source region is 2:1 to 5:1.

[0015] In some embodiments of this application, the thickness of the first metal layer is greater than the thickness of the second metal layer.

[0016] According to another aspect of this application, a method for fabricating a MOS device is provided for fabricating the MOS device in any of the above embodiments. The method includes: forming an epitaxial layer having a first doping type on a substrate; forming a plurality of base regions in the epitaxial layer, the plurality of base regions being spaced apart, and each base region having a second doping type opposite to the first doping type; forming a well region having the second doping type in the base regions; forming a source region having the first doping type in the base regions, the source region being spaced apart from the edge of the base region; and forming a JFET region between adjacent base regions, the JFET region being located in the source region away from the well region. The base region is formed in a trench, during which a portion of the well region and a portion of the source region are removed. A stacked conductive structure is formed in the trench, the stacked conductive structure including a first metal layer and a second metal layer. The first metal layer is in contact with the well region and the source region, and the surface of the first metal layer near the substrate is closer to the substrate than the surfaces of the well region and the source region near the substrate. The second metal layer is located on the side of the first metal layer near the substrate, and the second metal layer is an ohmic metal layer. A source is formed on the side of the base region away from the substrate, and a gate is formed on the side of the JFET region away from the substrate.

[0017] The beneficial effects of this application are as follows:

[0018] This application relates to the field of semiconductor technology and provides a MOS device and its fabrication method. The MOS device includes: a substrate; an epitaxial layer disposed on the substrate and having a first doping type; a plurality of base regions disposed at intervals within the epitaxial layer and having a second doping type opposite to the first doping type; a source electrode disposed on the side of the base regions away from the substrate; a JFET region located between adjacent base regions within the epitaxial layer; and a gate electrode disposed on the side of the JFET region away from the substrate. Each base region has a well region, a source region, and a stacked conductive structure respectively in contact with the source electrode. The source region is located on the side of the well region near the JFET region and is spaced from the edge of the base region. The well region has a second doping type, and the source region has a first doping type. The stacked conductive structure includes a first metal layer and a second metal layer. The first metal layer is in contact with the well region and the source region respectively, and the surface of the first metal layer near the substrate is closer to the substrate than the surfaces of the well region and the source region near the substrate. The second metal layer is located on the side of the first metal layer near the substrate and is an ohmic metal layer. The first metal layer contacts both the well and source regions, and its surface is closer to the substrate than the well and source regions. Extending into the base region, this first metal layer provides a vertical current path for carrier transport, reducing the lateral current flow distance, decreasing base region resistance, optimizing current distribution within the base region, reducing the risk of local overload, and improving device stability and reliability under high current conditions. The second metal layer, an ohmic metal layer extending into the base region, forms a low-impedance ohmic contact with the epitaxial semiconductor material, significantly reducing base region resistance and improving device conduction performance. Furthermore, the extended conductive structure into the base region reduces base region current density, preventing parasitic diode turn-on caused by high current density, thus enhancing the device's latch-up resistance. Additionally, the extended conductive structure into the base region provides more heat dissipation area compared to conventional structures, conducting heat from the device interior to the surface, reducing operating temperature, and extending lifespan. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with corresponding figures in the accompanying drawings. These illustrative descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings are not proportionally limited. To more clearly illustrate the technical solutions in the embodiments of this application or in conventional technology, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0020] Figure 1 This is a schematic diagram of the structure of a MOS device according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the structure of a first stacked conductive structure provided according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of a second stacked conductive structure provided according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a third stacked conductive structure provided according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the fourth stacked conductive structure provided according to an embodiment of this application;

[0025] Figure 6 This is a schematic diagram of the fifth stacked conductive structure provided according to an embodiment of this application;

[0026] Figure 7 This is a schematic flowchart of a method for fabricating a MOS device according to an embodiment of this application;

[0027] Figures 8 to 15 This is a schematic diagram of the fabrication process of a MOS device provided according to an embodiment of this application.

[0028] The above figures include the following reference numerals:

[0029] 1. Substrate; 2. Epitaxial layer; 3. Base region; 41. Source; 42. Gate; 43. Drain; 44. Gate oxide layer; 45. Gate active layer; 46. Gate dielectric layer; 5. JFET region; 6. Well region; 7. Source region; 8. Stacked conductive structure; 81. First metal layer; 82. Second metal layer; 83. First barrier layer; 84. Second barrier layer; 85. Adhesion layer. Detailed Implementation

[0030] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0031] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] When a component "includes" another component, unless otherwise stated, other components are not excluded, and may be further included. Furthermore, when a component such as a layer, film, region, or plate is said to be "on / located" on another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or there can be another component present in between. Additionally, when a component such as a layer, film, region, or plate is "directly located" on another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it indicates that no other components are located in between.

[0033] The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists, A and B exist simultaneously, or B exists. Additionally, the character " / " in this text generally indicates that the preceding and following related objects have an "or" relationship.

[0034] The terms "first," "second," etc., are used to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. It should be understood that such terms can be used interchangeably where appropriate to describe embodiments of this application.

[0035] When an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element. Furthermore, in the specification and claims, terms such as "mounted," "connected," "joined," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0036] The orientations or positional relationships indicated by terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "up," "down," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application. Furthermore, in the accompanying drawings corresponding to the embodiments of this application, the thickness and area of ​​the layers are enlarged for better understanding and ease of description.

[0037] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0038] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0039] Figure 1 This is a schematic diagram of the structure of a MOS device according to an embodiment of this application, as shown below. Figure 1 As shown, the MOS device includes: a substrate 1, an epitaxial layer 2, multiple base regions 3, a source 41, a JFET region 5, a gate 42, a well region 6, a source region 7, and a stacked conductive structure 8.

[0040] Substrate 1 serves as the basic support structure for the device, providing the growth interface for epitaxial layer 2 and other functional regions. Epitaxial layer 2 bears the main breakdown voltage and acts as the drift region of the device, controlling the concentration and movement of charge carriers. Epitaxial layer 2 is disposed on substrate 1, and its doping type is the same as that of substrate 1; that is, both substrate 1 and epitaxial layer 2 have the first doping type. Both substrate 1 and epitaxial layer 2 can be made of silicon carbide (SiC), which has excellent thermal stability and electrical insulation properties, enabling the device to withstand high-power, high-temperature operating conditions.

[0041] Multiple base regions 3 are spaced apart within the epitaxial layer 2 and have a second doping type opposite to the first doping type. For example, the first doping type can be N-type doping and the second doping type can be P-type doping, or the first doping type can be P-type doping and the second doping type can be N-type doping. In this application, an example of N-type doping as the first doping type and P-type doping as the second doping type will be used for illustration.

[0042] The source 41 is located on the side of the base region 3 away from the substrate 1. The source 41 is the injection point for electrons or holes and is used to control the conduction state of the device.

[0043] The junction field-effect transistor (JFET) region, namely JFET region 5, is located between adjacent base regions 3 within the epitaxial layer 2. Under the action of the gate voltage 42, JFET region 5 can form a controllable current path, similar to a field-effect transistor.

[0044] The gate 42 is located on the side of the JFET region 5 away from the substrate 1. The gate 42 can form an electric field by applying a voltage, control the carrier distribution in the JFET region 5, and realize the switching control of the current of the MOS device.

[0045] The base region 3 contains a well region 6, a source region 7, and a stacked conductive structure 8. The source region 7 is located on the side of the well region 6 near the JFET region 5 and is spaced from the edge of the base region 3. The well region 6, the source region 7, and the stacked conductive structure 8 are in contact with the source electrode 41. The region in the base region 3 between the source region 7 and the JFET region 5 can be used to form a channel to transport carriers. The well region 6 has a second doping type and can be used to isolate the source electrode 41 and the drain electrode 43 to prevent short circuits and maintain the stability of the device. The source region 7 has a first doping type and can be used to inject or extract carriers into the channel region of the MOS device.

[0046] Figure 2 This is a schematic diagram of a multilayer conductive structure 8 provided according to an embodiment of this application, with reference to... Figure 1 and Figure 2 The stacked conductive structure 8 includes a first metal layer 81 and a second metal layer 82. The first metal layer 81 is in contact with the well region 6 and the source region 7, respectively. The surface of the first metal layer 81 near the substrate 1 is closer to the substrate 1 than the surfaces of the well region 6 and the source region 7 near the substrate 1. The second metal layer 82 is located on the side of the first metal layer 81 near the substrate 1, and the second metal layer 82 is an ohmic metal layer.

[0047] It should be understood that the aforementioned first metal layer 81 contacting the well region 6 and the source region 7 respectively means that one side of the sidewall of the first metal layer 81 is in contact with the well region 6, and the opposite side is in contact with the source region 7. The surface of the first metal layer 81 near the substrate 1 is closer to the substrate 1 than the surfaces of the well region 6 and the source region 7 near the substrate 1, meaning that the first metal layer 81 extends into the base region 3. The second metal layer 82 is located on the side of the first metal layer 81 near the substrate 1, therefore the second metal layer 82 is located in the base region 3 and is in contact with the base region 3.

[0048] In this embodiment, the first metal layer 81 contacts the well region 6 and the source region 7, respectively, and its surface is closer to the substrate 1 than the well region 6 and the source region 7. Extending into the interior of the base region 3, the first metal layer 81 provides a vertical current path for carrier transport, thereby reducing the lateral current flow distance, decreasing the resistance of the base region 3, optimizing the current distribution within the base region 3, reducing the risk of local overload, and improving the stability and reliability of the device under high current conditions. The second metal layer 82 is an ohmic metal layer that extends into the interior of the base region 3, forming a low-impedance ohmic contact with the semiconductor material of the epitaxial layer 2, significantly reducing the resistance of the base region 3 and improving the device's conduction performance. Furthermore, the extension of the stacked conductive structure 8 into the interior of the base region 3 reduces the current density in the base region 3, preventing parasitic diode turn-on caused by high current density, thus enhancing the device's anti-latch-up capability. In addition, the extension of the stacked conductive structure 8 into the interior of the base region 3 provides additional heat dissipation area compared to conventional structures, conducting heat from the device interior to the surface, reducing the device's operating temperature, and extending its lifespan.

[0049] In some embodiments of this application, the conductivity of the first metal layer 81 is higher than that of the second metal layer 82. The high conductivity of the first metal layer 81 can significantly improve the electrical performance of the MOS device, reduce power consumption, optimize speed performance, and enhance the high-temperature reliability and heat dissipation capability of the device.

[0050] In some embodiments of this application, the thickness of the first metal layer 81 is greater than the thickness of the second metal layer 82. This helps to reduce resistance and improve current transmission efficiency. Furthermore, the thicker first metal layer 81 can withstand a larger current, preventing overheating or material burnout under high load conditions. The thinner second metal layer 82, on the other hand, helps to reduce costs.

[0051] In some embodiments of this application, the material of the first metal layer 81 may include at least one of tungsten (W) and aluminum (Al). W has a high melting point and high electrical conductivity, and using W to form the first metal layer 81 can give it excellent thermal stability, enabling it to maintain structural stability at high temperatures and effectively carry large currents, reducing energy consumption and heat generation during current transmission, and improving device efficiency and thermal management performance. Al is a low-cost metal material that is easy to process and form, suitable for mass production, helping to reduce manufacturing costs and improve production efficiency. At the same time, Al has good electrical conductivity, meeting most current transmission requirements. Using either W or Al can ensure that the first metal layer 81 has good conductivity and reliability. By adjusting the ratio of tungsten to aluminum in the first metal layer 81, performance and cost can be balanced according to specific needs.

[0052] In some embodiments of this application, the material of the second metal layer 82 may include at least one of titanium (Ti) and nickel (Ni). Ti and Ni have good electrical conductivity and can serve as efficient current transport media. During heat treatment, they can react with SiC in the base region 3 to form an intermetallic compound. Such a compound has low resistance characteristics, which can significantly reduce contact resistance and provide excellent ohmic contact.

[0053] Figure 3 This is a schematic diagram of another stacked conductive structure 8 provided according to an embodiment of this application, with reference to... Figure 1 and Figure 3 In some embodiments of this application, the stacked conductive structure 8 further includes a first barrier layer 83. The first barrier layer 83 is disposed on the side of the first metal layer 81 facing away from the substrate 1, and the first barrier layer 83 is a conductive metal nitride. For example, the first barrier layer 83 is titanium nitride (TiN). In the embodiments of this application, metal nitrides such as TiN have high chemical stability, which can effectively prevent the source metal 41 from diffusing into the lower layer and affecting the performance of the first metal layer 81, thus extending the lifespan of the device. It also has excellent thermal stability, maintaining structural stability even under high-temperature operating conditions, and is not prone to oxidation or other chemical changes, thereby improving the reliability of the device.

[0054] Figure 4 This is a schematic diagram of another stacked conductive structure 8 provided according to an embodiment of this application, with reference to... Figure 1 and Figure 4 In some embodiments of this application, the stacked conductive structure 8 further includes a second barrier layer 84 disposed on the side of the second metal layer 82 facing away from the substrate 1, and the second barrier layer 84 is a conductive metal nitride. Similar to the provision of the first barrier layer 83, the provision of the second barrier layer 84 in this embodiment can effectively prevent the first metal layer 81 or other films disposed above the second metal layer 82 from diffusing downwards and affecting the performance of the second metal layer 82, thereby improving the independence of each layer material in the stacked conductive structure 8, extending the device's lifespan, and enhancing its reliability.

[0055] Figure 5 This is a schematic diagram of another stacked conductive structure 8 provided according to an embodiment of this application, with reference to... Figure 1 and Figure 5 In some embodiments of this application, the stacked conductive structure 8 may simultaneously include the first barrier layer 83 and the second barrier layer 84 described above. Both the first barrier layer 83 and the second barrier layer 84 are conductive metal nitrides. Firstly, this maintains the independence and functionality of each layer material in the stacked conductive structure 8, further improving the reliability of the device, while ensuring that the stacked conductive structure 8 has good conductivity.

[0056] Both the first barrier layer 83 and the second barrier layer 84 can be made of TiN, which can further enhance their adhesion strength with adjacent film layers, especially with the first metal layer 81. Specifically, TiN and W have similar crystal structures (both face-centered cubic structures) and small lattice mismatch, which allows TiN to be epitaxially or quasi-epitaxially grown on the W surface, forming a coherent or semi-coherent tight interface with very high bonding energy. During the deposition process, the initial Ti (the precursor for depositing TiN) may undergo slight interdiffusion with the W surface, forming a very strong W-Ti mixed bond. Therefore, the TiN-W interface is a combination of strong chemical bonding and structural matching, and is exceptionally strong.

[0057] Because Ti has a high chemical affinity for Al, during the post-deposition annealing process, Ti atoms on the TiN surface react with Al to form an intermetallic compound TiA. This reaction creates a compositionally gradual transition layer at the interface (from TiN to TiA). Then to Al), and TiA It can also combine well with Al, even without forming a large amount of TiA. In this case, there is also a strong interaction force between Al atoms and N and Ti atoms on the TiN surface.

[0058] As can be seen, the first metal layer 81 is made of W or Al, or a combination of both, and the first barrier layer 83 and the second barrier layer 84 are made of TiN. This not only prevents diffusion between different film layers, but also improves the bonding strength between the film layers, thereby further improving the stability of the device.

[0059] Figure 6 This is a schematic diagram of another stacked conductive structure 8 provided according to an embodiment of this application, with reference to... Figure 1 and Figure 6 In some embodiments of this application, the stacked conductive structure 8 further includes an adhesion layer 85, which is located between the first metal layer 81 and the second barrier layer 84, and the adhesion layer 85 is conductive. The adhesion layer 85 can improve the adhesion between the first metal layer 81 and the second barrier layer 84, preventing delamination caused by stress during processing or thermal cycling after long-term use. The adhesion layer 85 is typically selected from materials that have good reactivity with both the first metal layer 81 and the second barrier layer 84. In some embodiments of this application, the material of the adhesion layer 85 includes a titanium-tungsten alloy (TiW), which can not only form good contact with the first metal layer 81 (W / Al) but also bond tightly with the second barrier layer 84 (TiN), thereby improving the material compatibility and stability of the entire stacked structure.

[0060] In some embodiments of this application, the ratio of the depth of the stacked conductive structure 8 to its width in the arrangement direction of the well region 6 and the source region 7 is 2:1 to 5:1, exemplarily 2:1, 2.5:1, 3:1, 4:1, 5:1, etc. The aforementioned aspect ratio of the stacked conductive structure 8 indicates a larger depth and a smaller width. By increasing the depth while maintaining a relatively small width, more vertical current paths can be provided, reducing the lateral flow distance of current through the high-resistivity base region, thereby reducing the overall device resistance, improving conductivity, and reducing power consumption. Setting the aspect ratio of the stacked conductive structure 8 within the aforementioned range avoids the difficulty in reducing contact resistance due to an excessively small aspect ratio, while also avoiding excessive processing difficulty due to an excessively large aspect ratio. In other words, the aforementioned aspect ratio effectively balances device performance and processing difficulty.

[0061] Taking a specific embodiment of this application as an example, the stacked conductive structure 8 includes a second metal layer 82, a second barrier layer 84, an adhesion layer 85, a first metal layer 81, and a first barrier layer 83 stacked sequentially. The second metal layer 82 includes Ti, the second barrier layer 84 includes TiN, the adhesion layer 85 includes TiW, the first metal layer 81 includes Al and W, and the first barrier layer 83 includes TiN. Compared with conventional MOS devices without the above-mentioned stacked conductive structure 8, the MOS device in this embodiment can reduce the base region resistance by 50% to 80%, increase the latch-up trigger current density by more than 50%, reduce the device junction temperature by 15% to 25%, and increase the device lifetime by more than 3 times under high temperature and high humidity operating conditions. The conductivity and reliability of the device are significantly improved.

[0062] Based on the same concept, embodiments of this application also provide a method for fabricating a MOS device, which can be used to fabricate any of the MOS devices described above. Figure 7 This is a schematic flowchart illustrating a method for fabricating a MOS device according to an embodiment of this application, as shown below. Figure 7 As shown, the fabrication method of the MOS device includes the following steps S1 to S8:

[0063] Step S1: Form an epitaxial layer 2 having a first doping type on the substrate 1. Exemplarily, after completing step S1, an epitaxial layer 2 is formed as shown... Figure 8 In the structure shown, in this step, the substrate 1 has the same first doping type as the epitaxial layer 2, for example, N-type doping. The resistivity of the substrate 1 can be 0.02 ± 20% Ω·cm. The epitaxial layer 2 is formed by epitaxial growth technology, and a drift region can be formed in the epitaxial layer 2 to serve as the main breakdown layer of the device. The doping concentration of the epitaxial layer 2 is 1E+15~1E1+16 cm⁻¹. -3The thickness is set according to product requirements. For example, in a MOS device with a withstand voltage requirement of 1200V, the thickness of its epitaxial layer 2 is 9~11μm, and in a MOS device with a withstand voltage requirement of 650V, the thickness of its epitaxial layer 2 is 5~7μm.

[0064] Step S2: A plurality of base regions 3 are formed within the epitaxial layer 2, the plurality of base regions 3 being spaced apart, and the base regions 3 having a second doping type opposite to the first doping type. For example, after completing step S2, a layer is formed as shown... Figure 9 The structure shown is formed by ion implantation into the epitaxial layer 2. The implanted element is a second type of dopant, which is the opposite of the first type of dopant, such as p-type aluminum (Al). The implantation dose is 1E+17±50%cm. -3 The injection depth is 0.7~0.8μm.

[0065] Step S3: Form a well region 6 with a second doping type within the base region 3. Exemplarily, after completing step S3, a well region 6 is formed as shown... Figure 10 The structure shown is formed by ion implantation into the base region 3. The implanted element is a second-type dopant, such as p-type aluminum (Al). The doping concentration of the well region 6 is greater than that of the base region 3, and its implantation dose is 1E+19±50%cm³. -3 The injection depth is 0.2~0.3μm.

[0066] Step S4: A source region 7 with a first doping type is formed within the base region 3, and the source region 7 is spaced from the edge of the base region 3. Exemplarily, after completing step S4, a structure is formed as shown... Figure 11 The structure shown is formed by ion implantation into the base region 3. The implanted element is a first-type dopant, such as an N-type dopant, with an implantation dose of 1E+19~1E+20 cm⁻¹. -3 The injection depth is 0.2~0.3μm. The edges of the source region 7 and the base region 3 are spaced apart. When the MOS device is working, the space between the source region 7 and the base region 3 can serve as a channel for carrier transport, and the channel width is 0.3~0.6μm.

[0067] Step S5: A JFET region 5 is formed between adjacent base regions 3. The JFET region 5 is located on the side of the source region 7 away from the well region 6. Exemplarily, after completing step S5, a structure is formed as shown... Figure 12 The structure shown is formed by ion implantation into the region between adjacent base regions 3 in the epitaxial layer 2. The implanted element is a first doping type element, such as an N-type dopant, and the implantation dose is 1E+18±50%cm. -3 The implantation depth is 0.8~0.9μm, and the implanted elements are activated by annealing after implantation.

[0068] Step S6: Form a trench in the base region 3, removing part of the well region 6 and part of the source region 7 during trench formation. For example, the trench is formed by an etching process with an etching depth of 0.4~1.2μm, a trench width of 0.1~0.3μm, and a trench aspect ratio of 2:1 to 5:1.

[0069] Step S7: Form a multilayer conductive structure 8 in the trench. Exemplarily, the multilayer conductive structure 8 includes multiple film layers, each of which may be formed sequentially by physical vapor deposition (PVD) processes, including but not limited to those formed by physical vapor deposition.

[0070] Step S8: A source electrode 41 is formed on the side of the base region 3 opposite to the substrate 1, and a gate electrode 42 is formed on the side of the JFET region 5 opposite to the substrate 1. Exemplarily, the source electrode 41 and the gate electrode 42 are formed by a process of depositing electrode material and then patterning.

[0071] After the step of forming JFET region 5 (i.e., step S5) and before the step of forming JFET region 5 (i.e., step S6), the fabrication method in this embodiment may further include sequentially forming a gate oxide layer 44, a gate active layer 45, and a gate dielectric layer 46 on the side of JFET region 5 facing away from substrate 1. Exemplarily, after completing the above steps, a layer is formed as shown... Figure 13 In the structure shown, the gate oxide layer 44 is made of an insulating material, such as silicon dioxide (SiO2), and is grown using thermal oxidation or chemical vapor deposition (CVD) processes, with a thickness of 300–800 Å. The gate active layer 45 is made of a semiconductor material, such as polysilicon, and is grown using CVD processes, with a thickness of 2000–8000 Å. After growing the entire gate oxide layer 44 and gate active layer 45, the desired pattern can be formed through an etching process. The gate dielectric layer 46 is made of an insulating dielectric material, such as SiO2, and is formed by deposition followed by etching, with a thickness of 600–1000 nm. The gate dielectric layer 46 covers the gate oxide layer and the gate active layer 45, and can protect them in subsequent steps. Figure 13 The structure shown, after completing step S6, forms the following... Figure 14 The structure shown, after completing step S7, forms the following... Figure 15 The structure shown.

[0072] In some embodiments, step S7 described above includes sequentially forming a second metal layer 82 and a first metal layer 81 in the trench to form a... Figure 2 The stacked conductive structure 8 shown; in some other embodiments, step S7 above includes sequentially forming a second metal layer 82, a first metal layer 81, and a first barrier layer 83 in the trench to form a structure as shown. Figure 3 The stacked conductive structure 8 shown; in some other embodiments, step S7 above includes sequentially forming a second metal layer 82, a second barrier layer 84, and a first metal layer 81 in the trench to form Figure 4 The structure shown; in some other embodiments, step S7 above includes sequentially forming a second metal layer 82, a second barrier layer 84, a first metal layer 81, and a first barrier layer 83 in the trench to form Figure 5 The structure shown; in some other embodiments, step S7 above includes sequentially forming a second metal layer 82, a second barrier layer 84, an adhesion layer 85, a first metal layer 81, and a first barrier layer 83 in the trench to form Figure 6 The structure shown is as follows. In this structure, the first metal layer 81 is in contact with the well region 6 and the source region 7, and the surface of the first metal layer 81 near the substrate 1 is closer to the substrate 1 than the surfaces of the well region 6 and the source region 7 near the substrate 1. The second metal layer 82 is located on the side of the first metal layer 81 near the substrate 1, and the second metal layer 82 is an ohmic metal layer.

[0073] For example, the material of the first metal layer 81 is at least one of W and Al, and it is formed by PVD process, sputtering process or electroplating process, and its thickness can be 0.3~1.0 μm.

[0074] For example, the material of the second metal layer 82 is an ohmic metal, such as Ti or Ni, formed by PVD or sputtering processes, and its thickness can be 10~30 nm. After the formation of the second metal layer 82, high-temperature annealing can form compounds such as TiSi or TiC to promote the contact reaction between the second metal layer 82 and the epitaxial layer 2, form an ohmic contact, and reduce the contact resistance.

[0075] For example, the material of the first barrier layer 83 is including but not limited to TiN, and is formed by sputtering or CVD processes, with a thickness of 20~50nm.

[0076] For example, the material of the second barrier layer 84 is at least one of conductive metal nitrides, including but not limited to TiN or TaN, and is formed by sputtering or CVD processes, with a thickness of 20-50 nm.

[0077] For example, the material of the adhesion layer 85 is including but not limited to TiW, formed by sputtering or CVD processes, and its thickness is 50~100nm.

[0078] In step S8 above, the gate dielectric layer 46 can be slotted first to expose the gate active layer 45, and then the gate 42 can be formed in the slot so that it contacts the gate active layer 45. This step can also include forming a drain 43 on the side of the substrate 1 away from the epitaxial layer 2. Before forming the drain 43, an ohmic metal layer can be formed first to reduce the contact resistance on the drain 43 side.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A MOS device, characterized in that, include: Substrate; An epitaxial layer is disposed on the substrate and has a first doping type; Multiple base regions are spaced apart within the epitaxial layer and have a second doping type opposite to the first doping type; The source electrode is disposed on the side of the base region opposite to the substrate; The JFET region is located between adjacent base regions within the epitaxial layer; The gate is disposed on the side of the JFET region opposite to the substrate; The base region contains a well region, a source region, and a stacked conductive structure that are in contact with the source electrode. The source region is located on the side of the well region near the JFET region and is spaced from the edge of the base region. The well region has the second doping type, and the source region has the first doping type. The stacked conductive structure includes a first metal layer and a second metal layer. The first metal layer is in contact with the well region and the source region, respectively. The surface of the first metal layer near the substrate is closer to the substrate than the surfaces of the well region and the source region near the substrate. The second metal layer is located on the side of the first metal layer near the substrate and is an ohmic metal layer.

2. The MOS device according to claim 1, characterized in that, The stacked conductive structure further includes at least one of the following: A first barrier layer is disposed on the side of the first metal layer opposite to the substrate; A second barrier layer is disposed on the side of the second metal layer opposite to the substrate; The first barrier layer and the second barrier layer are conductive metal nitrides.

3. The MOS device according to claim 2, characterized in that, The stacked conductive structure further includes: An adhesive layer is located between the first metal layer and the second barrier layer, and the adhesive layer is conductive.

4. The MOS device according to claim 1, characterized in that, The conductivity of the first metal layer is higher than that of the second metal layer.

5. The MOS device according to claim 3, characterized in that, The material of the first metal layer includes at least one of tungsten and aluminum, and the material of the second metal layer includes titanium.

6. The MOS device according to claim 5, wherein the materials of the first barrier layer, the second barrier layer, and the adhesion layer all include titanium compounds.

7. The MOS device according to claim 6, characterized in that, The material of the adhesion layer includes a titanium-tungsten alloy.

8. The MOS device according to any one of claims 1 to 7, characterized in that, The ratio of the depth of the stacked conductive structure to the width of the stacked conductive structure in the arrangement direction of the well region and the source region is 2:1 to 5:

1.

9. The MOS device according to any one of claims 1 to 7, characterized in that, The thickness of the first metal layer is greater than the thickness of the second metal layer.

10. A method for fabricating a MOS device, used to fabricate the MOS device according to any one of claims 1 to 9, characterized in that, The preparation method includes: An epitaxial layer having a first doping type is formed on the substrate; Multiple base regions are formed within the epitaxial layer, the multiple base regions are spaced apart, and the base regions have a second doping type opposite to the first doping type; A well region having the second doping type is formed within the base region; A source region having the first doping type is formed within the base region, and the source region is spaced from the edge of the base region; A JFET region is formed between adjacent base regions, the JFET region being located on the side of the source region away from the well region; A trench is formed within the base region, and a portion of the well region and a portion of the source region are removed during the formation of the trench. A stacked conductive structure is formed in the trench. The stacked conductive structure includes a first metal layer and a second metal layer. The first metal layer is in contact with the well region and the source region. The surface of the first metal layer near the substrate is closer to the substrate than the surfaces of the well region and the source region near the substrate. The second metal layer is located on the side of the first metal layer near the substrate and is an ohmic metal layer. A source is formed on the side of the base region opposite to the substrate, and a gate is formed on the side of the JFET region opposite to the substrate.

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