Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate; the epitaxial layer is located on the surface of one side of the substrate; the first doped region is located in the epitaxial layer, and the doping type of the first doped region is different from that of the epitaxial layer; the second doped region is located in the first doped region, and the doping type of the second doped region is different from that of the first doped region; the quantum well structure is located in the second doped region, the surface, away from the substrate, of the quantum well structure is not overlapped with the surface, away from the substrate, of the second doped region, and the surface, close to the substrate, of the quantum well structure is not overlapped with the surface, close to the substrate, of the second doped region; the quantum well structure comprises an alternating structure, the alternating structure comprises a first layer and a second layer which are sequentially and alternately stacked and are made of different materials, the material of the first layer comprises a wide-band-gap semiconductor material, and the material of the second layer comprises silicon carbide. The MOS device solves the problem that in the prior art, a parasitic triode in an MOS device is easy to conduct, so that the reliability of the device is low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a semiconductor device. BACKGROUND

[0002] Silicon-based IGBT dominates the high-voltage and high-current scene, but silicon-based IGBT cannot withstand high-frequency working conditions and has high power consumption, etc., while SiC has the characteristics of high voltage and high temperature resistance, so that it can cover the voltage resistance level of silicon-based IGBT with a simpler MOSFET device, while avoiding the shortcomings of high energy consumption. Compared with silicon-based IGBT of the same specification, the energy loss of silicon carbide-based MOSFET is reduced by 66% in the same environment, mainly due to a significant reduction in switching loss. In the new energy vehicle industry, SiC can be used for inverters, vehicle chargers and fast charging piles for driving and controlling motors. In photovoltaic power generation, the leading enterprises of photovoltaic inverters have replaced silicon devices with SiC power devices.

[0003] In the N+ source region structure of the traditional SiC MOS, the parasitic transistor composed of the N+ source region, the P-base body region and the epitaxial layer has high emitter injection efficiency due to the high doping of the N+ source region, which is easy to cause the parasitic transistor to be turned on, reduce the UIS capability of the device and affect the reliability of the device. SUMMARY

[0004] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to solve the problem that the parasitic transistor in the MOS device is easy to be turned on, resulting in low reliability of the device in the prior art.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on one side surface of the substrate; a first doped region located in the epitaxial layer, the doping type of the first doped region being different from the doping type of the epitaxial layer; a second doped region located in the first doped region, the doping type of the second doped region being different from the doping type of the first doped region; a quantum well structure located in the second doped region, a surface of the quantum well structure away from the substrate not overlapping a surface of the second doped region away from the substrate, and a surface of the quantum well structure close to the substrate not overlapping a surface of the second doped region close to the substrate; the quantum well structure comprises an alternating structure, the alternating structure comprises a first layer and a second layer which are alternately and sequentially stacked along a first direction, the material of the first layer comprises a wide bandgap semiconductor material, the material of the second layer comprises silicon carbide, the material of the first layer is different from the material of the second layer, and the first direction is parallel to the thickness direction of the substrate.

[0006] Optionally, the second doped region comprises: a first sub-doped region located on a surface of the quantum well structure away from the substrate, the surface of the first sub-doped region away from the substrate is flush with the surface of the second doped region away from the substrate; a second sub-doped region, the quantum well structure is located in the second sub-doped region, the second sub-doped region is located on a side of the first sub-doped region close to the substrate, the surface of the second sub-doped region close to the substrate is flush with the surface of the second doped region close to the substrate, the surface of the second sub-doped region away from the substrate is flush with the surface of the quantum well structure away from the substrate, the doping concentration of the first sub-doped region is different from the doping concentration of the second sub-doped region.

[0007] Optionally, the quantum well structure comprises a plurality of the alternating structures stacked along the first direction, and the number of the alternating structures is 5-10.

[0008] Optionally, the thickness of the quantum well structure is 5-50 nm.

[0009] Optionally, the thickness of the first layer is equal to the thickness of the second layer.

[0010] Optionally, the doping concentration of the first sub-doped region is greater than the doping concentration of the second sub-doped region, and the doping concentration of the second sub-doped region is 1.0e18 cm -3 -5.0e18 cm -3 .

[0011] Optionally, the doping depth of the first sub-doped region is 0.08-0.12 μm.

[0012] Optionally, the wide bandgap semiconductor material comprises at least one of gallium nitride, gallium oxide and diamond.

[0013] Optionally, the semiconductor structure further comprises: a third doped region located in the first doped region and on a side of the second doped region, the sidewall of the third doped region is in contact with the sidewall of the second doped region, the doping type of the third doped region is the same as the doping type of the first doped region, and the doping concentration of the third doped region is greater than the doping concentration of the first doped region; a gate structure located on a part of the surface of the epitaxial layer away from the substrate, on the surface of the first doped region away from the substrate, and on a part of the surface of the second doped region away from the substrate; an interlayer dielectric layer covering the gate structure; a first electrode located on a part of the surface of the second doped region away from the substrate and on the surface of the third doped region away from the substrate, the interlayer dielectric layer is located between the first electrode and the gate structure; and a second electrode located on the surface of the substrate away from the epitaxial layer.

[0014] According to another aspect of this application, a semiconductor device is provided, comprising: any of the semiconductor structures described herein.

[0015] The semiconductor structure using the technical solution of this application includes a stacked substrate and an epitaxial layer, and further includes a first doped region in the epitaxial layer, a second doped region in the first doped region, and a quantum well structure in the second doped region. The first doped region has a different doping type than the epitaxial layer and the second doped region. The surface of the quantum well structure does not overlap with the surface of the second doped region. The quantum well structure includes an alternating structure, which comprises a first layer and a second layer of different materials stacked alternately. The material of the first layer includes a wide-bandgap semiconductor material, and the material of the second layer includes silicon carbide. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in MOS devices in the prior art, this application introduces a quantum well structure in the second doped region. The quantum well structure consists of an alternating first layer including a wide-bandgap material and a second layer including SiC, forming an artificial quantum well. By utilizing the quantum confinement effect within the quantum well, the behavior of charge carriers can be effectively controlled. Especially in SiC MOS devices, this structure can enhance hole recombination, reduce the base transport efficiency of parasitic transistors, thereby improving the device's resistance to uncontrolled oscillation (UIS) and improving the device's reliability and performance. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown.

[0018] The above figures include the following reference numerals:

[0019] 10. Substrate; 11. Epitaxial layer; 12. First doped region; 13. Second doped region; 14. Quantum well structure; 15. Alternating structure; 151. First layer; 152. Second layer; 131. First sub-doped region; 132. Second sub-doped region; 16. Third doped region; 17. Gate structure; 18. Interlayer dielectric layer; 19. First electrode; 20. Second electrode; 171. Gate oxide layer; 172. Gate; 21. JFET region. Detailed Implementation

[0020] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0021] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0024] As described in the background section, in the prior art, parasitic transistors in MOS devices are prone to conduction, resulting in low device reliability. To solve the above problems, embodiments of this application provide a semiconductor structure and a semiconductor device.

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] This application provides a semiconductor structure, such as... Figure 1 As shown, it includes:

[0027] Substrate 10;

[0028] Specifically, the resistivity of the substrate can be 0.02 ± 20% Ωcm, and the doping concentration of the substrate can be 1E+15~1E+16cm. -3 .

[0029] Epitaxial layer 11 is located on one side surface of the substrate 10;

[0030] Specifically, the doping type of the epitaxial layer is the same as that of the substrate. The doping type of the epitaxial layer can be N-type or P-type, and this application does not impose a specific limitation on this. In the embodiments of this application, the doping type of the epitaxial layer is N-type.

[0031] The first doped region 12 is located in the epitaxial layer 11, and the doping type of the first doped region 12 is different from the doping type of the epitaxial layer 11.

[0032] The second doped region 13 is located in the first doped region 12, and the doping type of the second doped region 13 is different from that of the first doped region 12.

[0033] The quantum well structure 14 is located in the second doped region 13. The surface of the quantum well structure 14 away from the substrate 10 does not overlap with the surface of the second doped region 13 away from the substrate 10, and the surface of the quantum well structure 14 close to the substrate 10 does not overlap with the surface of the second doped region 13 close to the substrate 10.

[0034] The quantum well structure 14 includes an alternating structure 15, which includes a first layer 151 and a second layer 152 that are alternately stacked along a first direction. The material of the first layer 151 includes a wide bandgap semiconductor material, and the material of the second layer 152 includes silicon carbide. The materials of the first layer 151 and the second layer 152 are different. The first direction is parallel to the thickness direction of the substrate 10.

[0035] Specifically, in the alternating structure, the first layer can be closer to the upper surface of the epitaxial layer, or the second layer can be closer to the upper surface of the epitaxial layer. This application does not impose any specific restrictions on this.

[0036] In the above embodiments, the semiconductor structure includes a stacked substrate and an epitaxial layer, and further includes a first doped region in the epitaxial layer, a second doped region in the first doped region, and a quantum well structure in the second doped region. The first doped region has a different doping type than the epitaxial layer and the second doped region. The surface of the quantum well structure does not overlap with the surface of the second doped region. The quantum well structure includes an alternating structure, which comprises a first layer and a second layer of different materials stacked alternately. The material of the first layer includes a wide-bandgap semiconductor material, and the material of the second layer includes silicon carbide. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in MOS devices in the prior art, this application introduces a quantum well structure in the second doped region. The quantum well structure consists of an alternating first layer including a wide-bandgap material and a second layer including SiC, forming an artificial quantum well. By utilizing the quantum confinement effect in the quantum well, the behavior of charge carriers can be effectively controlled. Especially in SiC MOS devices, this structure can enhance hole recombination, reduce the base transport efficiency of parasitic transistors, thereby improving the device's resistance to UIS and improving the device's reliability and performance.

[0037] Specifically, the semiconductor structure of this application is a MOS structure.

[0038] In one alternative, such as Figure 1 As shown, the second doped region 13 includes: a first sub-doped region 131, located on the surface of the quantum well structure 14 away from the substrate 10, the surface of the first sub-doped region 131 away from the substrate 10 being flush with the surface of the second doped region 13 away from the substrate 10; and a second sub-doped region 132, in which the quantum well structure 14 is located, the second sub-doped region 132 being located on the side of the first sub-doped region 131 close to the substrate 10, the surface of the second sub-doped region 132 close to the substrate 10 being flush with the surface of the second doped region 13 close to the substrate 10, and the surface of the second sub-doped region 132 away from the substrate 10 being flush with the surface of the quantum well structure 14 away from the substrate 10. The doping concentration of the first sub-doped region 131 is different from that of the second sub-doped region 132. In this embodiment, the second doped region is subdivided into a first sub-doped region and a second sub-doped region, forming a unique layered structure. The first sub-doped region is located above the quantum well structure, while the second sub-doped region is located below the first sub-doped region. The quantum well structure is embedded in the second sub-doped region. This construction further ensures that the quantum well structure can effectively collect charge carriers while preventing them from flowing excessively to the emitter, thereby further disrupting the operating conditions of the parasitic transistor. By precisely controlling the position and doping concentration of each sub-doped region, the device's resistance to UIS can be further improved, enhancing its stability and reliability under high voltage, high current, and high frequency operation.

[0039] In another alternative, such as Figure 1 As shown, the quantum well structure 14 includes multiple alternating structures 15 stacked along the first direction. The number of alternating structures is 5-10. In this embodiment, by introducing multiple alternating structures, the quantum confinement effect can be used to more precisely control the movement and recombination of charge carriers. This superlattice structure provides additional potential energy barriers for charge carriers, requiring higher energy for holes to cross the barrier, thereby reducing hole mobility and injection efficiency. With 5 to 10 alternating layers, this specific number of cycles in the quantum well structure can more precisely control charge carrier behavior, ensuring that recombination occurs at an appropriate level. This avoids device performance degradation caused by excessively high base region transport efficiency, while also preventing excessive suppression that could affect charge carrier transport under normal operating conditions.

[0040] According to some exemplary embodiments of this application, the thickness of the quantum well structure described above is 5nm-50nm. In this embodiment, the quantum well within this thickness range can further precisely control the confinement of holes, thereby enhancing the recombination efficiency of charge carriers and further reducing the base transport efficiency of parasitic transistors. This helps to maximize the UIS capability of the device without increasing device complexity or manufacturing cost, and improve the reliability and efficiency of the device in high-frequency, high-voltage, and high-current applications.

[0041] In other embodiments, the thickness of the first layer is equal to the thickness of the second layer. In this embodiment, maintaining consistent thicknesses for both materials helps to create a more uniform carrier distribution within the quantum well, improving the stability and consistency of the device.

[0042] According to some other exemplary embodiments of this application, the doping concentration of the first sub-doped region is greater than the doping concentration of the second sub-doped region, wherein the doping concentration of the second sub-doped region is 1.0e18cm. -3 -5.0e18cm -3 In this embodiment, the highly doped first sub-doped region can provide a low-resistance ohmic contact, ensuring good conductivity between the source region and the electrode, while the low-doped second sub-doped region is adjacent to the quantum well structure, which helps to control carrier injection between the source region and the first doped region, avoids the activation of parasitic transistors, and thus improves the device's UIS capability.

[0043] In some alternative embodiments of this application, the doping depth of the first sub-doped region is 0.08 μm-0.12 μm. In this embodiment, the depth of the first sub-doped region directly affects the connection resistance between the source and the semiconductor substrate. An appropriate depth can reduce this parasitic resistance, thereby reducing the energy loss of the device and improving the switching speed and efficiency.

[0044] According to some other exemplary embodiments of this application, the wide bandgap semiconductor material described above includes at least one of the following: gallium nitride, gallium oxide, and diamond. In this embodiment, different wide bandgap semiconductor materials have different band structures and physical properties. For example, gallium nitride (GaN) has a higher electron mobility than SiC, gallium oxide (GaO) has an extremely high breakdown field strength, while diamond has excellent thermal conductivity and chemical stability. Selecting the material most suitable for the application requirements as part of the quantum well can optimize the overall performance of the device, such as improving switching speed, reducing thermal resistance, or enhancing voltage withstand capability.

[0045] In practical applications, those skilled in the art can flexibly select suitable wide-bandgap materials according to actual needs, and this application does not impose specific limitations in this regard. In the embodiments of this application, the wide-bandgap semiconductor material includes gallium nitride.

[0046] In other embodiments, such as Figure 1 As shown, the semiconductor structure further includes: a third doped region 16 located in the first doped region 12 and on one side of the second doped region 13, the sidewall of the third doped region 16 being in contact with the sidewall of the second doped region 13, the doping type of the third doped region 16 being the same as that of the first doped region 12, and the doping concentration of the third doped region 16 being greater than that of the first doped region 12; a gate structure 17 located on the portion of the epitaxial layer 11 away from the substrate 10, the portion of the first doped region 12 away from the substrate 10, and the portion of the second doped region 13 away from the substrate 10; an interlayer dielectric layer 18 covering the gate structure 17; a first electrode 19 located on the portion of the second doped region 13 away from the substrate 10 and the portion of the third doped region 16 away from the substrate 10, the interlayer dielectric layer 18 being located between the first electrode 19 and the gate structure 17; and a second electrode 20 located on the surface of the substrate 10 away from the epitaxial layer 11. In this embodiment, two electrodes are used for current input and output, and the gate structure is used to control the current switching. The presence of the interlayer dielectric layer isolates the gate structure and the electrodes, avoiding short circuits.

[0047] Specifically, the first electrode serves as the source electrode of the device, and the second electrode serves as the drain electrode of the device.

[0048] Specifically, such as Figure 1 As shown, the gate structure 17 includes a gate oxide layer 171 and a gate 172. The gate oxide layer 171 is located on a portion of the epitaxial layer 11 away from the substrate 10, on a portion of the first doped region 12 away from the substrate 10, and on a portion of the second doped region 13 away from the substrate 10. The gate 172 is located on a portion of the gate oxide layer 171 away from the substrate 10.

[0049] Specifically, such as Figure 1 As shown, in the second direction, there are two first doped regions 12, and the two first doped regions 12 are spaced apart; the semiconductor structure also includes a JFET region 21 located between the two first doped regions 12, and a third doped region 16 located on the side of the second doped region 13 away from the JFET region 21, and the second direction is perpendicular to the thickness direction of the substrate 10.

[0050] Specifically, the process steps of the semiconductor structure fabrication method of this application include: 1) First, an EPI layer is grown on an N+ type SiC substrate (with a resistivity of 0.02±20%Ω cm) as a drift region (i.e., epitaxial layer) to serve as the main breakdown layer. The doping concentration of the epitaxial layer is 1E+15cm. -3 ~1E+16cm -3 The thickness is set according to product requirements (e.g., the EPI layer thickness of a 1200V MOS is 9~11μm, and the EPI layer thickness of a 650V MOS is 5~7μm); 2) Grow the P+ layer (i.e., the third doped region), with Al as the implanted element and an implantation dose of 1E+19±50%cm. -3 3) Growth of a P-base layer (i.e., the first doped region), with Al as the implanted element and an implantation dose of 1E+17±50%cm⁻¹. -3 4) The implantation depth is 0.7 μm to 0.9 μm; 5) An N-source region layer is grown, which is generated by implantation or epitaxy. The main body of the source region is N-type (i.e., the second sub-doped region) with a concentration of 1.0e18 cm⁻¹. -3 -5.0e18cm -3 A 5-50 nm thick quantum well structure is embedded within it, achieved by alternating growth of extremely thin SiC (the second layer) and another wide-bandgap material (the first layer, such as GaN). The quantum well has 5-10 cycles, with consistent thicknesses for SiC and GaN within a single cycle. This quantum well structure realizes the potential well through a superlattice. The top layer is a 0.08-0.12 μm N+ contact layer (the first sub-doped region) with a doping concentration of 1.0e20 cm⁻¹. -3 The bottom is an N-region (i.e., the second sub-doped region) in contact with the P-base layer; a quantum well structure is introduced into the source region to control the carriers through the quantum confinement effect. The confinement of holes by the quantum well enhances recombination and reduces the base transport efficiency of the parasitic transistor. This quantum well structure reduces the peak collector current of the parasitic transistor under UIS stress, and significantly enhances the UIS capability; 5) Grow the JFET region, with the implanted element being N element, and its implantation dose being 1E+18±50%cm -36) The implantation depth is 0.8~0.9μm, and the activation of the implanted region and the active region layer are completed and etched; 7) The gate oxide layer is grown with a thickness of 300-800A, and then the polysilicon gate layer (i.e., the gate) is grown with a thickness of 2000-8000A, and the excess gate oxide layer and polysilicon gate layer are etched away; 8) The interlayer dielectric layer is deposited and the excess interlayer dielectric layer is etched away. The material can be SiO2 or other dielectric materials with a thickness of 600-1000nm; 9) The source electrode (i.e., the first electrode) and the back drain electrode (i.e., the second electrode) are generated in sequence.

[0051] In summary, this application introduces a quantum well structure in the source region and modulates the charge carriers through the quantum confinement effect. The quantum well is formed by alternating the growth of extremely thin SiC and another wide-bandgap material (such as gallium nitride). The beneficial effect is that the confinement effect of the quantum well on holes enhances recombination and further reduces the base region transport efficiency of the parasitic transistor.

[0052] This application also provides a semiconductor device, including any of the above-described semiconductor structures.

[0053] Specifically, the semiconductor device in this application may be a SiC MOS device.

[0054] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0056] The semiconductor structure of this application includes a stacked substrate and an epitaxial layer, a first doped region in the epitaxial layer, a second doped region in the first doped region, and a quantum well structure in the second doped region. The first doped region has a different doping type than the epitaxial layer and the second doped region. The surface of the quantum well structure does not overlap with the surface of the second doped region. The quantum well structure includes an alternating structure, comprising a first layer and a second layer of different materials stacked alternately. The first layer is made of a wide-bandgap semiconductor material, and the second layer is made of silicon carbide. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in MOS devices in the prior art, this application introduces a quantum well structure in the second doped region. The quantum well structure consists of an alternating first layer of a wide-bandgap material and a second layer of SiC, forming an artificial quantum well. By utilizing the quantum confinement effect within the quantum well, the behavior of charge carriers can be effectively controlled. Especially in SiC MOS devices, this structure can enhance hole recombination, reduce the base transport efficiency of parasitic transistors, thereby improving the device's resistance to uncontrolled oscillation (UIS) and improving the device's reliability and performance.

[0057] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An epitaxial layer is located on one side surface of the substrate; A first doped region is located in the epitaxial layer, and the doping type of the first doped region is different from the doping type of the epitaxial layer. The second doped region is located within the first doped region, and the doping type of the second doped region is different from that of the first doped region; A quantum well structure is located in the second doped region, wherein the surface of the quantum well structure away from the substrate does not overlap with the surface of the second doped region away from the substrate, and the surface of the quantum well structure close to the substrate does not overlap with the surface of the second doped region close to the substrate; The quantum well structure includes an alternating structure, which includes a first layer and a second layer stacked alternately along a first direction. The material of the first layer includes a wide-bandgap semiconductor material, and the material of the second layer includes silicon carbide. The materials of the first layer and the second layer are different. The first direction is parallel to the thickness direction of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The second doped region includes: The first sub-doped region is located on the surface of the quantum well structure away from the substrate, and the surface of the first sub-doped region away from the substrate is flush with the surface of the second doped region away from the substrate; The second sub-doped region, wherein the quantum well structure is located in the second sub-doped region, the second sub-doped region is located on the side of the first sub-doped region closer to the substrate, the surface of the second sub-doped region closer to the substrate is flush with the surface of the second sub-doped region closer to the substrate, the surface of the second sub-doped region farther from the substrate is flush with the surface of the quantum well structure farther from the substrate, and the doping concentration of the first sub-doped region is different from the doping concentration of the second sub-doped region.

3. The semiconductor structure according to claim 1, characterized in that, The quantum well structure includes a plurality of alternating structures stacked along the first direction, the number of which is 5-10.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The thickness of the quantum well structure is 5nm-50nm.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The thickness of the first layer is equal to the thickness of the second layer.

6. The semiconductor structure according to claim 2, characterized in that, The doping concentration of the first sub-doped region is greater than that of the second sub-doped region, and the doping concentration of the second sub-doped region is 1.0e18cm. -3 -5.0e18cm -3 .

7. The semiconductor structure according to claim 2, characterized in that, The doping depth of the first sub-doped region is 0.08μm-0.12μm.

8. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The wide bandgap semiconductor material includes at least one of the following: gallium nitride, gallium oxide, and diamond.

9. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The semiconductor structure also includes: The third doped region is located within the first doped region and on one side of the second doped region. The sidewall of the third doped region is in contact with the sidewall of the second doped region. The doping type of the third doped region is the same as that of the first doped region. The doping concentration of the third doped region is greater than that of the first doped region. A gate structure is located on a portion of the epitaxial layer away from the substrate, on a portion of the first doped region away from the substrate, and on a portion of the second doped region away from the substrate. An interlayer dielectric layer covers the gate structure; The first electrode is located on the portion of the second doped region away from the substrate and on the portion of the third doped region away from the substrate, and the interlayer dielectric layer is located between the first electrode and the gate structure; The second electrode is located on the surface of the substrate away from the epitaxial layer.

10. A semiconductor device, characterized in that, include: The semiconductor structure according to any one of claims 1 to 9.

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