Semiconductor device and electronic equipment
By introducing a P+ shielding layer and a shielded gate structure into the trench gate MOSFET, the problems of single-event gate penetration and parasitic NPN transistors in SiC field-effect transistors in the space radiation environment are solved, achieving high reliability and withstand voltage capability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-27
AI Technical Summary
SiC field-effect transistors are susceptible to high-energy particle bombardment in the space radiation environment, leading to single-event gate breakdown and single-event burn-out. They are also prone to turning on parasitic NPN transistors, affecting device performance and reliability.
Introducing a P+ shielding layer and a shielding gate structure into a trench gate MOSFET, by setting two trench gates in the source region and connecting the P+ shielding layer to the source electrode, ionized holes are extracted, hole accumulation and parasitic NPN transistor turn-on are avoided, and single-event protection performance is enhanced.
It effectively avoids the influence of strong electric fields on the gate oxide layer, prevents device breakdown, enhances single-event immunity and stability, reduces parasitic NPN transistor turn-on, and improves device reliability and withstand voltage.
Smart Images
Figure CN121751704A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology
[0002] With the rapid development of deep space exploration and aerospace technology, power semiconductor devices are facing the dual demands of high voltage withstand capability and miniaturization. Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses excellent properties such as wide bandgap, high thermochemical stability, strong radiation resistance, high breakdown field strength, and high electron saturation velocity, providing key material support for building high-efficiency, high-reliability, and environmentally adaptable power electronic systems.
[0003] However, SiC field-effect transistors (MOSFETs) operating in the radiation environment of space are still susceptible to bombardment by high-energy particles (especially heavy ions), leading to severe failure phenomena such as single-event gate breakdown (SEGR) and single-event burn-out (SEB), resulting in device performance degradation or even permanent damage. In trench-gate MOSFETs, SEGR mainly occurs in the gate oxide region at the bottom of the trench, while SEB often originates in localized locations where the electric field is highly concentrated in the bulk region. The degree of damage is influenced by multiple parameters, including drain bias and the linear energy transfer (LET) value of incident ions.
[0004] In addition, parasitic NPN transistors are an inherent structural defect inside MOSFETs. It is necessary to avoid turning on parasitic NPN transistors in MOSFETs, because their conduction will cause a series of serious problems, affecting the normal operation and reliability of the device.
[0005] Therefore, those skilled in the art urgently need to systematically improve the structure of trench gate MOSFETs to avoid the activation of parasitic NPN transistors and ensure their single-event protection performance in strong radiation environments. Summary of the Invention
[0006] In view of this, embodiments of the present disclosure provide a semiconductor device and an electronic device for preventing the parasitic NPN transistor from turning on and for improving the single-event protection performance of trench gate MOSFETs in strong radiation environments.
[0007] This disclosure provides a semiconductor device and electronic device, the specific solution of which is as follows: On one hand, this disclosure provides a semiconductor device including an N+ substrate and an N- drift layer located on one side of the N+ substrate. A P+ shielding layer and two current diffusion layers are disposed on the side of the N- drift layer away from the N+ substrate. The P+ shielding layer is located between the two current diffusion layers. The arrangement direction of the P+ shielding layer and the current diffusion layers is a first direction, which is parallel to the N+ substrate. It also includes: a P-type well layer located on the side of the current diffusion layer away from the N+ substrate, and a P+ region and an N+ region located on the side of the P-type well layer away from the N+ substrate; the P+ region and the N+ region are arranged along the first direction, and the N+ region is close to the P+ shielding layer, and the top surfaces of the P+ region, the N+ region and the P+ shielding layer away from the N+ substrate are flush; The P+ shielding layer includes two first grooves spaced apart along the first direction. Each first groove contains a gate electrode. A first dielectric layer is disposed between each gate electrode and the bottom and sidewall of the corresponding first groove. The first dielectric layer is in contact with the current diffusion layer, the P-type well layer, and the sidewall of the N+ region. It also includes: two isolation layers spaced apart and located in each of the first grooves on the side of the gate electrode away from the N+ substrate, each of the isolation layers also covering a portion of the N+ region and a portion of the P+ shielding layer around the first groove; It also includes: a source electrode located on the side of the P+ region, the N+ region, the isolation layer and the P+ shielding layer away from the N+ substrate, and a drain electrode located on the side of the N+ substrate away from the N- drift layer.
[0008] In some embodiments, in the semiconductor device provided in the present disclosure, the distance between the bottom surface of the P+ shielding layer near the N+ substrate and the N+ substrate is smaller than the distance between the bottom surface of the P-type well layer near the N+ substrate and the N+ substrate.
[0009] In some embodiments, in the semiconductor device provided in this disclosure, the P+ shielding layer and the source electrode are in an ohmic contact.
[0010] In some embodiments, in the semiconductor device provided in the present disclosure, each of the first grooves further includes: a shielding gate located between the gate electrode and the first dielectric layer, and a second dielectric layer located between the shielding gate and the gate electrode; the shielding gate is coupled to a fixed potential.
[0011] In some embodiments, in the semiconductor device provided in the present disclosure, the material of the shielding gate is the same as the material of the source electrode, and the shielding gate and the source electrode are electrically connected.
[0012] In some embodiments, in the semiconductor device provided in the present disclosure, the first groove has a through-hole that exposes the shielding gate, the orthographic projection of the through-hole on the N+ substrate does not overlap with the orthographic projection of the gate electrode on the N+ substrate, and the source electrode fills the through-hole and is electrically connected to the shielding gate.
[0013] In some embodiments, in the semiconductor device provided in the present disclosure, the extending direction of the shielding gate is a second direction, the second direction is parallel to the N+ substrate, and the second direction is perpendicular to the first direction; The shielding gate is divided into a first shielding gate and a second shielding gate along the second direction. The orthogonal projections of the gate electrode and the second dielectric layer on the N+ substrate both cover the orthogonal projection of the first shielding gate on the N+ substrate. The orthogonal projection of the isolation layer on the N+ substrate covers the orthogonal projections of the first shielding gate and part of the second shielding gate on the N+ substrate. The isolation layer is connected to the second dielectric layer. The source electrode fills the through-hole and is electrically connected to the second shielding gate.
[0014] In some embodiments, in the semiconductor device provided in the present disclosure, the P+ shielding layer further includes at least one second groove disposed between the two first grooves, and the source electrode fills the second groove.
[0015] In some embodiments, in the semiconductor device provided in the present disclosure, the material of the gate electrode includes highly doped polycrystalline silicon.
[0016] On the other hand, embodiments of this disclosure also provide an electronic device, including any of the semiconductor devices described above in embodiments of this disclosure.
[0017] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device and electronic device, in which each set of current diffusion layer, P-type well layer, P+ region, and N+ region constitutes the source region of the device. By setting two trench gates in the two source regions, and forming P+ shielding layers at the bottom of the two trench gates and between them, it can be ensured that the P+ shielding layer is connected to the source electrode on the shortest path. The P+ shielding layer can extract ionized holes that move upward and accumulate under the action of electric field to the source electrode. On the one hand, it avoids a large number of holes accumulating under the first dielectric layer (i.e., gate oxide layer) and degrading the performance of the gate oxide layer, providing strong protection for the gate electrode and its trench region, effectively avoiding the impact of strong electric field accumulation on the gate oxide layer, avoiding premature breakdown of the device, and enhancing the single-particle gate breakdown and single-particle burn-off resistance of the device; on the other hand, it reduces the hole concentration entering the P-type well layer, avoids the turn-on of parasitic NPN transistors, and improves the stability and reliability of the device. Attached Figure Description
[0018] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure; Figure 2 for Figure 1 A schematic diagram of a partial cross-sectional structure extending along the second direction Y; Figure 3 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure; Figure 4 For this disclosure Figure 1 The diagram shows the electric field distribution of the semiconductor device under reverse bias. Figure 5 for Figure 1 The diagram shows a structural schematic of a semiconductor device during its fabrication process. Figure 6 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 7 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 8 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 9 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 10 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 11 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Figure 12 for Figure 1 The diagram shows another structural schematic of a semiconductor device during its fabrication process. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0020] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0021] In the following description, when a component or layer is referred to as "on" or "connected to" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. When a component or layer is referred to as "located on one side of" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as "directly on" or "directly connected to" another component or layer, there are no intermediate components or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.
[0022] This disclosure provides a semiconductor device, such as... Figure 1 As shown, it includes an N+ substrate 1 and an N- drift layer 2 located on one side of the N+ substrate 1. A P+ shielding layer 3 and two current diffusion layers 4 are disposed on the side of the N- drift layer 2 away from the N+ substrate 1. The P+ shielding layer 3 is located between the two current diffusion layers 4. The arrangement direction of the P+ shielding layer 3 and the current diffusion layers 4 is a first direction X, which is parallel to the N+ substrate 1. It also includes: a P-type well layer 5 located on the side of the current diffusion layer 4 away from the N+ substrate 1, and a P+ region 6 and an N+ region 7 located on the side of the P-type well layer 5 away from the N+ substrate 1; the P+ region 6 and the N+ region 7 are arranged along the first direction X, and the N+ region 7 is close to the P+ shielding layer 3, and the top surfaces of the P+ region 6, the N+ region 7 and the P+ shielding layer 3 away from the N+ substrate 1 are flush. The P+ shielding layer 3 includes two first grooves U1 spaced apart along the first direction X. Each first groove U1 is provided with a gate electrode 8. A first dielectric layer 9 is provided between each gate electrode 8 and the bottom and sidewall of the corresponding first groove U1. The first dielectric layer 9 is in contact with the side of the current diffusion layer 4, the P-type well layer 5 and the N+ region 7. It also includes: two isolation layers 10 that are spaced apart and located in each first groove U1 on the side away from the N+ substrate 1, and each isolation layer 10 also covers part of the N+ region 7 and part of the P+ shielding layer 3 around the first groove U1; It also includes: a source electrode 11 located on the side of P+ region 6, N+ region 7, isolation layer 10 and P+ shielding layer 3 away from N+ substrate 1, and a drain electrode 12 located on the side of N+ substrate 1 away from N- drift layer 2.
[0023] Specifically, such as Figure 1As shown, the N+ substrate 1 serves as the base and main conductive support region of the device, forming an ohmic contact with the drain electrode 12 below, thereby ensuring smooth current conduction. The N-drift layer 2 serves as the main withstand voltage region of the device. Within this layer, a P+ shielding layer 3 is formed through ion implantation, and then a groove structure is etched within the P+ shielding layer 3 to embed the gate electrode 8 and control the conduction of the channel. The current diffusion layer 4 plays a role in current diffusion and current equalization, making the current distribution in the conduction state more uniform, significantly reducing the peak current density in the channel region and the N-drift layer 2, thereby reducing the on-resistance of the device.
[0024] In the semiconductor device provided in this embodiment, each group of current diffusion layer, P-type well layer, P+ region, and N+ region constitutes the source region of the device. By setting two trench gates in the two source regions, and forming P+ shielding layers at the bottom of the two trench gates and between them, it can be ensured that the P+ shielding layer is connected to the source electrode on the shortest path. The P+ shielding layer can extract ionized holes that move upward and accumulate under the action of electric field to the source electrode. On the one hand, it avoids a large number of holes accumulating under the first dielectric layer (i.e., gate oxide layer) and degrading the performance of the gate oxide layer, providing strong protection for the gate electrode and its trench region, effectively avoiding the influence of strong electric field accumulation on the gate oxide layer, avoiding premature breakdown of the device, and enhancing the single-particle gate breakdown and single-particle burn-off resistance of the device; on the other hand, it reduces the hole concentration entering the P-type well layer, avoids the turn-on of parasitic NPN transistors, and improves the stability and reliability of the device.
[0025] Specifically, such as Figure 1 As shown, the P+ shielding layer 3, the current diffusion layer 4, the P-type well layer 5, the P+ region 6, and the N+ region 7 can all be formed by selected area ion implantation on the side of the N-drift layer 2 away from the N+ substrate 1.
[0026] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, the distance d1 between the bottom surface of the P+ shielding layer 3 and the N+ substrate 1 is smaller than the distance d2 between the bottom surface of the P-type well layer 5 and the N+ substrate 1. This makes the P+ shielding layer 3 deeper than the P-type well layer 5, ensuring that holes drifting upwards from the depths of the N-drift layer 2 preferentially enter the source electrode 11 via the P+ shielding layer 3, reducing the number of holes entering the P-type well layer 5, and further suppressing the turn-on of parasitic NPN transistors.
[0027] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1As shown, the P+ shielding layer 3 and the source electrode 11 are preferably in an ohmic contact. Specifically, the P+ shielding layer 3 is achieved by a one-step or multi-step masking ion implantation process in the N-drift layer 2, and then the gate electrode metal and gate oxide layer deposited on it are etched away and connected to the source electrode 11 to achieve an ohmic contact.
[0028] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, a Schottky contact can also be used between the P+ shielding layer 3 and the source electrode 11 to prevent the body diode from turning on.
[0029] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, each first groove U1 further includes: a shielding gate 13 located between the gate electrode 8 and the first dielectric layer 9, and a second dielectric layer 14 located between the shielding gate 13 and the gate electrode 8; the shielding gate 13 is coupled to a fixed potential. By forming a control channel within the first groove U1 using the gate electrode 8 and the shielding gate 13, with one shielding gate 13 correspondingly positioned below one gate electrode 8, the shielding gate 13 is used to share the electric field in the high-voltage region of the drain electrode 12, preventing electric field spikes at the bottom of the groove, improving the device's withstand voltage capability, and thus enhancing the device's single-event gate breakdown and single-event burn-out resistance. Furthermore, the shielding gate 13, located between the gate electrode 8 and the drain electrode 12, physically isolates the direct coupling between the gate electrode 8 and the drain electrode 12, reducing the device's gate-drain capacitance. Moreover, under actual operating conditions, the conduction and turn-off characteristics of the device can be optimized by adjusting the potential difference between the gate electrode 8 and the source electrode 11, improving switching speed and operating efficiency. By optimizing the electric field distribution of the gate electrode, the gate structure helps reduce the failure rate of the device under extreme operating environments such as high temperature and high pressure, thereby extending the device's lifespan.
[0030] Therefore, this disclosure provides strong protection for the gate electrode and its recessed region by setting two recessed gates and simultaneously introducing a shielded gate structure and a P+ shielding layer structure. This effectively avoids the impact of strong electric field accumulation on the gate oxide layer, prevents premature breakdown of the device, and enhances the device's single-event gate breakdown and single-event burn-out resistance. Furthermore, the deeper P+ shielding layer compared to the P-type well layer allows holes to preferentially enter the source electrode via the P+ shielding layer, reducing the number of holes entering the P-type well layer, suppressing the turn-on of parasitic NPN transistors, and improving device reliability.
[0031] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, the material of the shielding gate 13 is the same as that of the source electrode 11, and the shielding gate 13 and the source electrode 11 are electrically connected. For example, the source electrode 11 is made of one or more materials such as doped polysilicon or metal.
[0032] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 As shown, the shielding gate 13 extends in the second direction Y (i.e., perpendicular to the screen direction, represented by a dot). The second direction Y is parallel to the N+ substrate 1, and the second direction Y is perpendicular to the first direction X, as shown. Figure 2 As shown, Figure 2 for Figure 1 A partial cross-sectional view of the structure extending along the second direction Y shows that the first groove U1 has a through-hole H exposing the shielding gate 13. The orthographic projection of the through-hole H on the N+ substrate 1 does not overlap with the orthographic projection of the gate electrode 8 on the N+ substrate 1. The source electrode 11 fills the through-hole H and is electrically connected to the shielding gate 13, that is, the source electrode 11 directly fills the through-hole H and is connected to the deeply buried shielding gate 13. Specifically, there can be multiple through-holes H.
[0033] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 2 As shown, the shielding gate 13 is divided into a first shielding gate 131 and a second shielding gate 132 along the second direction Y. The orthogonal projections of the gate electrode 8 and the second dielectric layer 14 on the N+ substrate 1 both cover the orthogonal projection of the first shielding gate 131 on the N+ substrate 1. The orthogonal projection of the isolation layer 10 on the N+ substrate 1 covers the orthogonal projections of the first shielding gate 131 and part of the second shielding gate 132 on the N+ substrate 1. The isolation layer 10 is connected to the second dielectric layer 14. That is, the length of the gate electrode 8 along the second direction Y is less than the length of the shielding gate 13 along the second direction Y. The first dielectric layer 9, the second dielectric layer 14 and the isolation layer 10 wrap around the gate electrode 8 and cover part of the first shielding gate 131 and the second shielding gate 132, so as to expose part of the second shielding gate 132 that is longer than the gate electrode 8. In this way, the source electrode 11 fills the via H and is electrically connected to the exposed second shielding gate 132 to realize the fixed potential of the shielding gate 13, which is used to share the electric field of the high voltage region of the drain electrode 12, avoid the electric field peak at the bottom of the groove, and improve the withstand voltage capability of the device.
[0034] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 3 As shown, Figure 3 The structure shown is Figure 1 They are basically the same, the difference is: Figure 3 The P+ shielding layer 3 also includes at least one second groove U2 disposed between the two first grooves U1. In this embodiment, taking the disposal of one second groove U2 as an example, the source electrode 11 fills the second groove U2. By slotting the P+ shielding layer 3 between the grooves and filling it with the metal of the source electrode 11, the distance from the bottom region of the P+ shielding layer 3 to the source electrode 11 can be reduced, which is beneficial for extracting holes to the source electrode 11.
[0035] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 3 As shown, the material of the gate electrode 8 preferably includes highly doped polycrystalline silicon, but it is not limited to this. For example, the material of the gate electrode 8 can also be a metal.
[0036] In some embodiments, the materials of the first dielectric layer 9, the second dielectric layer 14, and the isolation layer 10 may be SiO2, HfO2, Al2O3, Si3N4, etc.
[0037] In some embodiments, the current diffusion layer 4 is an N-type doped layer, and the doping concentration of the current diffusion layer 4 can be between the doping concentration of the N-type drift layer 2 and the doping concentration of the N+ region 7.
[0038] In some embodiments, in the semiconductor device provided in the present disclosure, the drain electrode may be made of one or more materials such as doped polycrystalline silicon or metal.
[0039] In some embodiments, the N+ substrate in this disclosure can be made of materials such as single-crystal silicon, silicon carbide, or gallium nitride. That is, the semiconductor device provided in the embodiments of this disclosure can be fabricated based on semiconductor materials such as single-crystal silicon, silicon carbide, or gallium nitride through processes such as epitaxy and ion implantation.
[0040] like Figure 4 As shown, Figure 4 For this disclosure Figure 1 The schematic diagram of the electric field distribution of the semiconductor device under reverse bias shows that a strong electric field is distributed at the bottom edge of the P+ shielding layer 3 and the sidewall of the first dielectric layer 9 around the shielding gate 13. This completely avoids the influence of the strong electric field on the gate electrode 8 and the surrounding first dielectric layer 9, enhancing the device's resistance to single-particle gate breakdown and single-particle burn-out. Therefore, this disclosure significantly improves the withstand voltage performance while maintaining low on-resistance, solves the reliability problem of the gate oxide layer caused by electric field concentration at the corner of the groove, and achieves a comprehensive optimization effect of uniform current distribution, high breakdown voltage, low conduction loss, and strong device stability. It is particularly suitable for scenarios such as electric vehicle drive modules, photovoltaic inverters, and high-frequency industrial power supplies.
[0041] It should be noted that the thickness of each layer, the type of doped ions, and the concentration of ions in the semiconductor device provided in the embodiments of this disclosure can be designed as needed, and this disclosure does not limit them.
[0042] It should be noted that the semiconductor devices provided in the embodiments of this disclosure are not limited to MOSFETs, but can also be applied to radiation-hardened diodes, insulated-gate bipolar transistors and other device structures. Structures with internal structures similar to those described in this disclosure and with the same purpose are all within the scope of protection of this disclosure.
[0043] To better understand the structure of the semiconductor device provided in the embodiments of this disclosure, this disclosure uses... Figure 1 Taking the semiconductor device shown as an example, the fabrication process of the semiconductor device will be explained in detail.
[0044] In some embodiments, Figure 1 The fabrication process of the semiconductor device shown may specifically include the following steps: (1) such as Figure 5 As shown, an N- drift layer 2 is epitaxially grown on one side of the N+ substrate 1.
[0045] (2) such as Figure 6 As shown, a current diffusion layer 4, a P+ shielding layer 3, a P-type well layer 5, a P+ region 6, and an N+ region 7 are formed by mask-based selective ion implantation on the side of the N-drift layer 2 away from the N+ substrate 1.
[0046] (3) such as Figure 7 As shown, the P+ shielding layer 3 is selectively etched to form the first groove U1, and the first dielectric layer 9 is formed at the bottom and sidewalls of the first groove U1 by thermal oxidation or deposition.
[0047] (4) such as Figure 8 As shown, a shielding grid 13 is formed in the first groove U1 by deposition and etching processes.
[0048] (5) such as Figure 9 As shown, a second dielectric layer 14 is deposited above the shielding grid 13 within the first groove U1.
[0049] (6) For example Figure 10 As shown, a gate electrode 8 is formed on the second dielectric layer 14 by deposition and etching processes. The material of the gate electrode 8 is preferably highly doped polycrystalline silicon.
[0050] (7) For example Figure 11 As shown, the deposition covers two isolation layers 10, namely the first groove U1, part of the N+ region 7, and part of the P+ shielding layer 3.
[0051] (8) such as Figure 12 As shown, a source electrode 11 covering the P+ region 6, N+ region 7, isolation layer 10 and P+ shielding layer 3 is formed by sputtering and other methods.
[0052] (9) For example Figure 1 As shown, a drain electrode 12 is formed on the side of the N+ substrate 1 away from the N- drift layer 2 by methods such as sputtering.
[0053] Through the above steps (1)-(9), a process is formed. Figure 1 The semiconductor device shown.
[0054] It needs to be clarified that yes, Figure 3The method for fabricating the semiconductor device shown is similar to Figure 1 The preparation methods shown are basically the same, except that: in step (3) above, when selective etching is performed on the P+ shielding layer 3 to form the first groove U1, the second groove U2 is formed at the same time; in step (8) above, when the source electrode 11 is formed, the source electrode 11 fills the second groove U2.
[0055] It should be noted that in the above-described fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.
[0056] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.
[0057] In some embodiments, the electronic devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the electronic devices provided in this disclosure may include other structures besides semiconductor devices. For example, when the electronic device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the electronic device is a mixer, it may also include structures such as input ports and output ports.
[0058] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0059] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.
Claims
1. A semiconductor device, characterized in that, It includes an N+ substrate and an N- drift layer located on one side of the N+ substrate. A P+ shielding layer and two current diffusion layers are disposed on the side of the N- drift layer away from the N+ substrate. The P+ shielding layer is located between the two current diffusion layers. The arrangement direction of the P+ shielding layer and the current diffusion layer is a first direction, which is parallel to the N+ substrate. It also includes: a P-type well layer located on the side of the current diffusion layer away from the N+ substrate, and a P+ region and an N+ region located on the side of the P-type well layer away from the N+ substrate; the P+ region and the N+ region are arranged along the first direction, and the N+ region is close to the P+ shielding layer, and the top surfaces of the P+ region, the N+ region and the P+ shielding layer away from the N+ substrate are flush; The P+ shielding layer includes two first grooves spaced apart along the first direction. Each first groove contains a gate electrode. A first dielectric layer is disposed between each gate electrode and the bottom and sidewall of the corresponding first groove. The first dielectric layer is in contact with the current diffusion layer, the P-type well layer, and the sidewall of the N+ region. It also includes: two isolation layers spaced apart and located in each of the first grooves on the side of the gate electrode away from the N+ substrate, each of the isolation layers also covering a portion of the N+ region and a portion of the P+ shielding layer around the first groove; It also includes: a source electrode located on the side of the P+ region, the N+ region, the isolation layer and the P+ shielding layer away from the N+ substrate, and a drain electrode located on the side of the N+ substrate away from the N- drift layer.
2. The semiconductor device as claimed in claim 1, characterized in that, The distance between the bottom surface of the P+ shielding layer near the N+ substrate and the N+ substrate is less than the distance between the bottom surface of the P-type well layer near the N+ substrate and the N+ substrate.
3. The semiconductor device as described in claim 1, characterized in that, The P+ shielding layer and the source electrode are in an ohmic contact.
4. The semiconductor device as claimed in claim 1, characterized in that, Each of the first grooves further includes: a shielding gate located between the gate electrode and the first dielectric layer, and a second dielectric layer located between the shielding gate and the gate electrode; the shielding gate is coupled to a fixed potential.
5. The semiconductor device as described in claim 4, characterized in that, The shielding grid is made of the same material as the source electrode, and the shielding grid and the source electrode are electrically connected.
6. The semiconductor device as claimed in claim 5, characterized in that, The first groove has a through hole that exposes the shielding gate. The orthographic projection of the through hole on the N+ substrate does not overlap with the orthographic projection of the gate electrode on the N+ substrate. The source electrode fills the through hole and is electrically connected to the shielding gate.
7. The semiconductor device as claimed in claim 6, characterized in that, The shielding gate extends in a second direction, which is parallel to the N+ substrate and perpendicular to the first direction. The shielding gate is divided into a first shielding gate and a second shielding gate along the second direction. The orthogonal projections of the gate electrode and the second dielectric layer on the N+ substrate both cover the orthogonal projection of the first shielding gate on the N+ substrate. The orthogonal projection of the isolation layer on the N+ substrate covers the orthogonal projections of the first shielding gate and part of the second shielding gate on the N+ substrate. The isolation layer is connected to the second dielectric layer. The source electrode fills the through-hole and is electrically connected to the second shielding gate.
8. The semiconductor device according to any one of claims 1-7, characterized in that, The P+ shielding layer further includes at least one second groove disposed between the two first grooves, and the source electrode fills the second groove.
9. The semiconductor device according to any one of claims 1-7, characterized in that, The gate electrode is made of highly doped polycrystalline silicon.
10. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1-9.