Silicon carbide semiconductor device and preparation method thereof

Abstract

The invention provides a silicon carbide semiconductor device and a preparation method thereof, and the silicon carbide semiconductor device comprises the components of a substrate which is provided with a first groove on one side surface; the first source region is located in the substrate at the bottom of the first groove; the second source region is positioned in the substrate on two sides of the first groove; the trench gate structure is located in the first trench and is in contact with the first source region; the plane gate structure is positioned on the substrate on two sides of the first groove and is in contact with the second source region; the interlayer dielectric layer is located in the first groove and further located on the side face of the groove gate structure, the surface, away from the substrate, of the groove gate structure, the side face of the plane gate structure and the surface, away from the substrate, of the plane gate structure; the source electrode is located in the first groove, on part of the surface of the second source region, on the surface, away from the substrate, of the interlayer dielectric layer and on the side wall of the interlayer dielectric layer and makes contact with the first source region. The on-resistance of the device can be reduced at least.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a silicon carbide semiconductor device and a method for fabricating the same. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor, is a new generation of power semiconductor material. Due to its unique physical properties, it exhibits significant advantages in high-voltage, high-temperature, and high-frequency applications, gradually becoming a core direction for replacing traditional silicon-based power devices. Silicon carbide has a bandgap (3.2 eV) three times that of silicon (1.1 eV), a breakdown field strength (3 MV / cm) ten times that of silicon, and a thermal conductivity (4.9 W / cm·K) three times that of silicon. These characteristics allow it to withstand higher operating voltages (>1200V), higher switching frequencies (MHz level), and higher junction temperatures (>200℃), significantly reducing system heat dissipation requirements. For example, at the same 1200V voltage level, silicon carbide devices with the same resistance specifications have losses more than 50% lower than silicon-based IGBTs, and their volume is reduced to less than 1 / 5, making them suitable for high power density designs.

[0003] However, current silicon carbide MOSFETs still suffer from high on-resistance, which increases their conduction losses and limits their further development. Summary of the Invention

[0004] The main objective of this application is to provide a silicon carbide semiconductor device and its fabrication method to solve the problem of high on-resistance in existing silicon carbide semiconductor devices.

[0005] To achieve the above objectives, according to one aspect of this application, a silicon carbide semiconductor device is provided, comprising: a substrate having a first trench on one side surface of the substrate; a first source region located in the substrate at the bottom of the first trench; a second source region located in the substrate on both sides of the first trench; a trench gate structure located in the first trench and in contact with the first source region; a planar gate structure located on the substrate on both sides of the first trench and in contact with the second source region; an interlayer dielectric layer located in the first trench, and also located on the side surface of the trench gate structure, the surface of the trench gate structure away from the substrate, the side surface of the planar gate structure, and the surface of the planar gate structure away from the substrate; and a source located in the first trench, on a portion of the surface of the second source region, on the surface of the interlayer dielectric layer away from the substrate, and on a sidewall, and in contact with the first source region.

[0006] Optionally, the width of the first trench increases along the direction from the bottom of the first trench to the opening of the first trench, and the angle between the sidewall of the first trench and the surface of the substrate on both sides of the first trench is 70~85°.

[0007] Optionally, the first source region includes: a first body region located in the substrate at the bottom of the first trench, the first body region having a first doping type; a first doped region located in the first body region, the first doped region being a region formed by ion implantation of a portion of the surface of the first body region near the trench gate structure, the first doped region having a second doping type; and a second doped region located in the first body region, located on the side of the first doped region away from the trench gate structure and in contact with the first doped region, the second doped region having the first doping type and a doping concentration greater than that of the first body region; wherein the trench gate structure is in contact with both the first body region and the first doped region, and the source electrode is in contact with both the first doped region and the second doped region.

[0008] Optionally, the silicon carbide semiconductor device further includes: a second trench located at the bottom of the first trench, the second trench extending through the first doped region to the second doped region, and the source electrode also located in the second trench.

[0009] Optionally, the first source region satisfies at least one of the following: the junction depth of the first body region is 0.8~1.2μm; the junction depth of the first doped region is 0.1~0.2μm; the junction depth of the second doped region is 0.1~0.15μm; and the distance between the sidewall of the first body region and the sidewall of the first doped region located on the same side is 0.3~0.4μm.

[0010] Optionally, the trench gate structure includes: a first oxide layer located on a portion of the surface of the first body region near the interlayer dielectric layer, a portion of the surface of the first doped region near the interlayer dielectric layer, and a sidewall of the first trench; and a first gate located on the surface of the first oxide layer away from the first body region and the first doped region, wherein the thickness of the first gate is less than the depth of the first trench.

[0011] Optionally, the interlayer dielectric layer includes: a first dielectric layer located in the first trench, in contact with the surface of the first gate away from the sidewall of the first trench, the sidewall of the first oxide layer located between the first gate and the first doped region, and the source electrode, wherein the thickness of the first dielectric layer is greater than the thickness of the first gate and less than or equal to the depth of the first trench; and a second dielectric layer located between the first oxide layer and the first dielectric layer, on the sidewall of the planar gate structure, and on the surface of the planar gate structure away from the substrate, wherein the first dielectric layer and the second dielectric layer are made of different materials.

[0012] Optionally, the second source region includes: a second body region located in the substrate on both sides of the first trench, wherein the surface of the second body region near the source electrode overlaps with a portion of the surface of the substrate, and has a first doping type; a third doped region located in the second body region, wherein the third doped region is a region formed by ion implantation of a portion of the surface of the second body region near the source electrode, and the third doped region has a second doping type; and a fourth doped region located in the second body region, located on the side of the third doped region away from the first trench and in contact with the third doped region, wherein the fourth doped region is a region formed by ion implantation of a portion of the surface of the second body region near the source electrode, and the fourth doped region has the first doping type and a doping concentration greater than that of the second body region; wherein the planar gate structure is in contact with the third doped region, the second body region, and the substrate, respectively, and the source electrode is in contact with the third doped region and the fourth doped region, respectively.

[0013] According to another aspect of this application, a method for fabricating the silicon carbide semiconductor device is provided, comprising: providing an initial device, the initial device including an initial substrate and a first trench located in the initial substrate; forming a first source region in the initial substrate at the bottom of the first trench, forming second source regions in the initial substrate on both sides of the first trench, and forming a sacrificial structure in the first trench that contacts the first source region, the remaining initial substrate forming a substrate; forming a trench gate structure in the remaining first trench that contacts a portion of the surface of the first source region, and forming a planar gate structure on the surface of the substrate that contacts a portion of the surface of the second source region. A first initial dielectric layer is formed, located on the outer wall of the sacrificial structure, the trench gate structure, the planar gate structure, the exposed surfaces of the first source region and the second source region; at least a portion of the first initial dielectric layer and the sacrificial structure is removed to form a third trench in the remaining first trench, exposing a portion of the first source region and a portion of the second source region, the remaining first initial dielectric layer forming an interlayer dielectric layer, and a source electrode is formed in the third trench, on the exposed surface of the second source region, and on the exposed surface of the interlayer dielectric layer, the source electrode located in the third trench contacting the first source region.

[0014] Optionally, the initial device further includes a first mask layer and a second mask layer, wherein the first mask layer is located on the initial substrates on both sides of the first trench, and the second mask layer is located on the exposed surface of the first trench and the exposed surface of the first mask layer. A first source region is formed in the initial substrate at the bottom of the first trench, a second source region is formed in the initial substrates on both sides of the first trench, and a sacrificial structure in the first trench in contact with the first source region is formed, including: forming a third mask layer at least on a portion of the second mask layer's surface away from the sidewall of the first trench. Using the third mask layer as a mask, ion implantation of the initial substrate at the bottom of the first trench is performed using a first doping type to form a first initial body region. A fourth mask layer is formed at least on the surfaces of the second and third mask layers away from the sidewalls of the first trench. Using the fourth mask layer as a mask, ion implantation of the first initial body region is performed using a second doping type to form a first initial doped region within the first initial body region. A fifth mask layer is formed on the sidewall of the fourth mask layer. Using the fifth mask layer as a mask, the remaining bottom of the first trench is etched to penetrate... A fourth trench is formed by penetrating the first initial doped region to reach the first initial body region, and a first type of ion implantation is performed on the initial substrate at the bottom of the fourth trench to form a second doped region located in the first initial body region and in contact with the first initial doped region. The remaining first initial body region forms a first body region, the remaining first initial doped region forms a first doped region, and the first body region, the first doped region, and the second doped region form the first source region. An oxide material is filled in the fourth trench, and the exposed surface of the initial device filled with the oxide material is planarized until a portion of the first mask layer is removed. Ion implantation is performed on the initial substrate, using at least the remaining first mask layer as a mask, to form a second source region in the initial substrate. The remaining initial substrate forms the substrate. The remaining first mask layer, the remaining second mask layer, the remaining third mask layer, the remaining fourth mask layer, and the remaining fifth mask layer are removed, exposing the surfaces of the first source region, the second source region, the substrate, and the remaining oxide material. The remaining oxide material forms the sacrificial structure.

[0015] By applying the technical solution of this application, a first trench is formed on one side surface of the substrate. This first trench not only provides space for forming additional channels, but also eliminates the JFET region in the device, avoiding the influence of the JFET effect on the device. By forming a first source region and a second source region at the bottom and sides of the first trench respectively, and combining the trench gate structure and the planar gate structure, two independent conductive channels are successfully integrated in the device, realizing the three-dimensional layout of the device channels. This structure greatly improves the channel density of the device, allowing more channels to be accommodated in the same chip area, thereby improving the total current carrying capacity and power handling capacity of the device, and effectively reducing the on-resistance and on-loss of the device. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic diagram of the structure of a silicon carbide semiconductor device according to an embodiment of this application is shown;

[0018] Figure 2 It shows Figure 1 A schematic diagram of the current path of a silicon carbide semiconductor device during forward operation;

[0019] Figure 3 It shows Figure 2 A schematic diagram of the current path in a silicon carbide semiconductor device under reverse freewheeling.

[0020] Figure 4 A schematic flowchart of a method for fabricating a silicon carbide semiconductor device according to an embodiment of this application is shown;

[0021] Figures 5 to 21 A schematic diagram of the structure obtained after each process step of the method for fabricating a silicon carbide semiconductor device according to an embodiment of this application is shown.

[0022] The accompanying drawings include the following reference numerals:

[0023] 10. Substrate; 11. First trench; 12. First source region; 121. First body region; 122. First doped region; 123. Second doped region; 13. Second source region; 131. Second body region; 132. Third doped region; 133. Fourth doped region; 14. Trench gate structure; 141. First oxide layer; 142. First gate; 15. Planar gate structure; 151. Second oxide layer; 152. Second gate; 16. 17. Source electrode; 18. Second trench; 19. First dielectric layer; 20. Second dielectric layer; 21. Intermediate substrate; 22. Fourth photoresist layer; 23. First mask layer; 24. First sub-mask layer; 25. Second sub-mask layer; 26. Third sub-mask layer; 27. Initial substrate; 28. Second mask layer; 29. ​​Fourth sub-mask layer; 20. Fifth sub-mask layer; 21. First initial mask layer; 22. First photoresist layer Layer; 27, Sixth Trench; 28, Third Mask Layer; 29, First Initial Body Region; 30, Second Initial Mask Layer; 31, Seventh Trench; 32, Fourth Mask Layer; 33, First Initial Doped Region; 34, Eighth Trench; 35, Fifth Mask Layer; 351, Sixth Sub-Mask Layer; 352, Seventh Sub-Mask Layer; 36, Fourth Trench; 37, First Intermediate Mask Layer; 38, Initial Sacrificial Structure; 39, Fourth Intermediate Mask Layer; 40. Fifth intermediate mask layer; 41. Sixth intermediate mask layer; 42. Seventh intermediate mask layer; 43. Sixth mask layer; 44. Second initial body region; 45. Seventh mask layer; 46. Third initial doped region; 47. Eighth mask layer; 48. Second photoresist layer; 49. Eighth intermediate mask layer; 50. Sacrificial structure; 51. Initial gate oxide layer; 52. Polysilicon layer; 53. Third photoresist layer; 54. Second initial dielectric layer. Detailed Implementation

[0024] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0028] As described in the background section, existing technologies suffer from high on-resistance in silicon carbide semiconductor devices. To address this issue, embodiments of this application provide a silicon carbide semiconductor device and its fabrication method.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] This application provides a silicon carbide semiconductor device. Figure 1 A schematic diagram of the structure of a silicon carbide semiconductor device according to an embodiment of this application is shown as an example. Figure 1 As shown, the silicon carbide semiconductor device includes:

[0031] A substrate 10, wherein a first groove 11 is provided on one side surface of the substrate 10;

[0032] Optionally, the substrate 10 may include a SiC substrate and a SiC epitaxial layer located on the SiC substrate, wherein the first trench 11 may be located in the SiC epitaxial layer, the SiC substrate is used to provide mechanical support, and the SiC epitaxial layer serves as the active layer of the device. Optionally, the substrate 10 may also be composed of a SiC epitaxial layer.

[0033] The first source region 12 is located in the substrate 10 at the bottom of the first trench 11;

[0034] Specifically, the first source region 12 is formed in the SiC epitaxial layer at the bottom of the first trench 11.

[0035] The second source region 13 is located in the substrate 10 on both sides of the first trench 11;

[0036] Specifically, the second source region 13 is formed in the SiC epitaxial layer on both sides of the first trench 11.

[0037] The trench gate structure 14 is located in the first trench 11 and is in contact with the first source region 12;

[0038] Specifically, the trench gate structure 14 fills the first trench 11 and contacts the first source region 12. When a voltage is applied to the trench gate structure 14, a channel is formed between the first source region 12 and the corresponding drain region. The current in the channel is controlled by the trench gate structure 14.

[0039] The planar gate structure 15 is located on the substrate 10 on both sides of the first trench 11 and is in contact with the second source region 13;

[0040] Specifically, the planar gate structure 15 is located on the SiC epitaxial layer on both sides of the first trench 11 and is in contact with the second source region 13. When a voltage is applied to the planar gate structure 15, another channel is formed between the second source region 13 and the corresponding drain region. The current of this channel is controlled by the planar gate structure 15.

[0041] An interlayer dielectric layer is located in the first trench 11, and also on the side of the trench gate structure, on the surface of the trench gate structure away from the substrate 10, on the side of the planar gate structure, and on the surface of the planar gate structure away from the substrate 10.

[0042] Specifically, the interlayer dielectric layer is used to separate the planar gate structure and the source 16, ensuring electrical isolation between the gate and the source and providing good insulation performance.

[0043] The source electrode 16 is located in the first trench 11, on a portion of the surface of the second source region 13, on the surface of the interlayer dielectric layer away from the substrate 10, and on the sidewall, and is in contact with the first source region 12.

[0044] Specifically, the source electrode 16 forms good electrical contact with the first source region 12 and the second source region 13, respectively. Optionally, the contact surface between the source electrode 16 and the first source region 12, and the contact surface between the source electrode 16 and the second source region 13, can be ohmic contacts, respectively.

[0045] In the embodiments described above, a first trench is formed on one side surface of the substrate. This first trench provides space for forming additional channels and eliminates the JFET region in the device, avoiding the influence of the JFET effect on the device. By forming a first source region and a second source region at the bottom and sides of the first trench respectively, and combining the trench gate structure and the planar gate structure, two independent conductive channels are successfully integrated in the device, realizing a three-dimensional layout of the device channels. This structure greatly improves the channel density of the device, allowing more channels to be accommodated in the same chip area, thereby improving the total current carrying capacity and power handling capacity of the device, and effectively reducing the on-resistance and on-loss of the device.

[0046] In some embodiments, the source electrode 16 located in the first trench 11 can be a columnar structure or a cuboid structure, such as a cuboid or a cube.

[0047] In practical applications, those skilled in the art can flexibly set the shape of the first groove 11 according to actual design needs, for example, forming a hole-shaped groove, a square groove, or a trapezoidal groove, etc.

[0048] According to one alternative of this application, such as Figure 1 As shown, along the direction from the bottom of the first trench 11 to the opening of the first trench 11, the width of the first trench 11 gradually increases, and the angle between the sidewall of the first trench 11 and the surfaces of the substrate 10 on both sides of the first trench 11 is 70~85°. That is, in the thickness profile of the silicon carbide semiconductor device, the first trench 11 is inverted trapezoidal, and the apex angle of the inverted trapezoid is maintained in the range of 70~85°. Traditional planar silicon carbide MOSFETs suffer from the JFET effect, where the presence of a fixed potential barrier increases on-resistance and reduces efficiency. This embodiment eliminates this effect by introducing an inverted trapezoidal groove in the JFET region, resulting in lower on-resistance for the same size device. The sidewalls of the inverted trapezoidal groove form a 70°~85° tilt angle with the substrate surface. This tilt angle prevents excessive electric field concentration at the trench's sharp corners, avoiding excessively high electric field strength on the gate oxide layer. This helps improve the electric field distribution, reducing the risk of gate oxide damage and threshold voltage drift, thus improving device reliability. Furthermore, the gradually widening and tilt angle design of the inverted trapezoidal groove allows for a more uniform current path distribution, preventing current from concentrating in small areas and optimizing the current path. In addition, the uniform current distribution also facilitates heat dissipation, as heat is distributed more evenly rather than concentrated at a single point, improving the device's thermal stability.

[0049] In another exemplary embodiment, such as Figure 1As shown, the first source region 12 includes: a first body region 121 located in the substrate 10 at the bottom of the first trench 11, the first body region 121 having a first doping type; a first doped region 122 located in the first body region 121, the first doped region 122 being a region formed by ion implantation of a portion of the surface of the first body region 121 near the trench gate structure 14, the first doped region 122 having a second doping type; and a second doped region 123 located in the first body region 121, on the side of the first doped region 122 away from the trench gate structure 14, and in contact with the first doped region 122, the second doped region 123 having the first doping type and a doping concentration greater than that of the first body region 121, the second doped region 123 also being a region formed by ion implantation of the first body region 121; wherein, the trench gate structure 14 is in contact with the first body region 121 and the first doped region 122 respectively, and the source electrode 16 is in contact with the first doped region 122 and the second doped region 123 respectively.

[0050] In the embodiment described, the first body region 121 serves as the functional implementation region and forms the basis for the channel. It responds to the gate control voltage, regulates the opening and closing of the channel, and controls the current path of the device. The first body region 121 helps the device withstand high voltage and simultaneously provides electric field protection for the gate oxide, improving the device's reliability. The first doped region 122 serves as the device's source. When the device is turned on, the first doped region 122, as the source, injects charge carriers into the channel, forming the device's forward conduction path. The second doped region 123 further enhances the ohmic contact with the source metal 16, ensuring low impedance of the current path and increasing the contact area with the second doped region 123. This increases the area of ​​reverse current flow from the source metal 16, improving the device's reverse current capability. Furthermore, in reverse recovery or short-circuit states, the second doped region 123 can act as an additional freewheeling channel, helping charge carriers to be released rapidly, reducing stored charge, thereby reducing reverse recovery losses and improving the device's durability. The first body region 121, the first doped region 122, and the second doped region 123 work together through the short-circuit connection of the source metal 16 to jointly realize the core function of the trench gate structure 14 MOS transistor to safely and efficiently conduct large current and withstand high voltage under gate control.

[0051] Furthermore, the current path of a silicon carbide semiconductor device under forward operation is as follows: Figure 2 The arrow-marked lines indicate the current path of a silicon carbide semiconductor device under reverse freewheeling conditions. Figure 3 The markings indicated by the arrows, such as Figure 2 The forward continuous flow path shown and Figure 3As shown in the reverse freewheeling path, the source 16 of this application extends into the bottom of the groove and contacts the second doped region 123, forming a freewheeling channel during reverse recovery or short-circuit overshoot. When the device is overcurrent, this structure provides nearly twice the current path of a conventional planar gate MOS. When the device is operating in the forward direction, this structure can also serve as a current-conducting channel for the MOS at the bottom of the groove. Regardless of whether the device is in forward or reverse operation, the current density within the device is more uniform.

[0052] Furthermore, such as Figure 1 As shown, the silicon carbide semiconductor device further includes a second trench 17 located at the bottom of the first trench 11. The second trench 17 extends through the first doped region 122 to the second doped region 123, and the source 16 is also located in the second trench 17. In this embodiment, by additionally forming a second trench 17 at the bottom of the first trench 11, the source 16 metal can penetrate deep into the SiC substrate, forming a vertical contact with the first doped region 122 on the sidewall of the second trench 17 and the second doped region 123 at the bottom of the second trench 17. This increases the contact area with the second doped region 123, thereby increasing the area through which the source 16 metal flows during reverse current flow, improving the reverse current flow capability of the device, and reducing conduction losses. In conventional planar MOSFETs, current is mainly collected and distributed through the lateral contact of the source 16. However, in the embodiment of this application, the source 16 metal is connected to the first doped region 122 through a vertical hole. The contact between 22 and the second doped region 123 means that current can be collected and distributed through multiple vertical paths. This not only increases the current path but also makes the current distribution more uniform, avoiding hot spots caused by current concentration, thereby improving the thermal stability and reliability of the device. Traditional lateral contact may also cause parasitic resistance and capacitance, which will adversely affect the switching performance of the device. However, the vertical contact method of this application reduces these parasitic effects and is conducive to improving the switching speed and efficiency of the device. The design of vertical hole contact can simplify the planar layout of the device and realize the three-dimensional structure of the internal structure of the device, thereby increasing the channel density without increasing the chip area.

[0053] In another exemplary embodiment, such as Figure 1 As shown, the second doped region 123 can be located in the first body region 121 and contact the first doped region 122 along a first direction, which is perpendicular to the thickness direction of the silicon carbide semiconductor device. In this embodiment, the source metal 16 is in lateral contact with the first doped region 122 and the second doped region 123, and the silicon carbide semiconductor device may not have the second trench 17.

[0054] In one exemplary embodiment, the junction depth of the first body region 121 is 0.8~1.2μm. For example, the junction depth of the first body region 121 can be 0.8μm, 0.9μm, 1.0μm, 1.1μm, or 1.2μm, etc. A deeper junction depth of the first body region 121 will affect the breakdown voltage, while a shallower junction depth will affect the normal operation of the MOS at the bottom of the first trench 11. Controlling the junction depth of the first body region 121 between 0.8μm and 1.2μm can balance the relationship between these two factors, thereby ensuring optimal device performance.

[0055] In another exemplary embodiment, the junction depth of the first doped region 122 is 0.1~0.2μm, for example, 0.1μm, 0.12μm, 0.15μm, 0.17μm, 0.19μm, or 0.2μm. The junction depth of the first doped region 122 directly determines the depth of contact with the channel. A junction depth of 0.1~0.2μm ensures sufficient overlap between the region and the channel, thereby forming a low-impedance channel and reducing channel resistance, while also avoiding the problem of breakdown voltage reduction caused by excessive junction depth leading to breakdown electric field penetration.

[0056] In another exemplary embodiment, the junction depth of the second doped region 123 is 0.1~0.15μm. For example, the junction depth of the second doped region 123 can be 0.1μm, 0.11μm, 0.12μm, 0.13μm, 0.14μm, or 0.15μm. A junction depth greater than or equal to 0.1μm ensures sufficient contact area between the second doped region 123 and the source metal 16, avoiding insufficient contact resistance that could affect the overall device efficiency. Furthermore, a junction depth less than or equal to 0.15μm prevents excessively large junction depths from affecting the device's breakdown voltage.

[0057] In another exemplary embodiment, the distance between the sidewall of the first body region 121 and the sidewall of the first doped region 122 on the same side is 0.3~0.4μm. For example, the distance between the sidewall of the first body region 121 and the sidewall of the first doped region 122 on the same side can be 0.3μm, 0.35μm, or 0.4μm, etc. This distance is the MOS channel length at the bottom of the first trench 11. The selection of the channel length needs to find a balance between reducing the on-resistance and maintaining the breakdown voltage. An excessively long channel will increase the on-resistance, while an excessively short channel may cause a decrease in the breakdown voltage. A channel length of 0.3~0.4μm reduces the on-resistance while still maintaining sufficient breakdown voltage to adapt to high-voltage applications.

[0058] Optionally, such as Figure 1As shown, the trench gate structure 14 includes: a first oxide layer 141 located on a portion of the surface of the first body region 121 near the interlayer dielectric layer, a portion of the surface of the first doped region 122 near the interlayer dielectric layer, and a sidewall of the first trench 11; and a first gate 142 located on the surface of the first oxide layer 141 away from the first body region 121 and the first doped region 122, wherein the thickness of the first gate 142 is less than the depth of the first trench 11. The design of the first gate 142 being less than the depth of the first trench 11 ensures that the gate can effectively control the opening and closing of the bottom channel of the first trench 11, providing more precise gate drive, which helps to reduce on-resistance.

[0059] In the aforementioned embodiment, by controlling the thickness and position of the first gate 142, the electric field distribution is effectively adjusted, thereby reducing the gate oxide layer stress under high-voltage operating conditions and avoiding premature gate oxide decay and threshold voltage instability caused by excessively high electric field strength. Simultaneously, the first oxide layer 141 provides necessary insulation protection.

[0060] Specifically, the thickness of the first gate 142 and the depth of the first trench 11 refer to the thickness / depth in the thickness direction of the silicon carbide semiconductor device, respectively. The projection of the first gate 142 onto the substrate 10 overlaps with the first body region 121 and the first doped region 122, respectively.

[0061] According to some other embodiments of this application, such as Figure 1 As shown, the interlayer dielectric layer includes: a first dielectric layer 18, located in the first trench 11, in contact with the surface of the first gate 142 away from the sidewall of the first trench 11, the sidewall of the first oxide layer 141 located between the first gate 142 and the first doped region 122, and the source 16, respectively. The thickness of the first dielectric layer 18 is greater than the thickness of the first gate 142 and less than or equal to the depth of the first trench 11; a second dielectric layer 19, located between the first oxide layer 141 and the first dielectric layer 18, on the sidewall of the planar gate structure 15, and on the surface of the planar gate structure 15 away from the substrate 10. The first dielectric layer 18 and the second dielectric layer 19 are made of different materials.

[0062] In this embodiment, the interlayer dielectric layer includes a first dielectric layer 18 and a second dielectric layer 19. The first dielectric layer 18 is located inside the first trench 11 and is in contact with the sidewall of the first gate 142, the sidewall of the first oxide layer 141, and the source 16. Its thickness is designed to be greater than the thickness of the first gate 142 but not exceeding the depth of the first trench 11, ensuring that the first dielectric layer 18 can effectively isolate the first gate 142 and the source 16 and provide the necessary insulation performance. The second dielectric layer 19 is distributed between the first oxide layer 141 and the first dielectric layer 18, on the side of the planar gate structure 15, and on the surface away from the substrate, ensuring that the second dielectric layer 19 can effectively isolate the second gate 152 (i.e., the gate of the planar gate structure 15) and the source 16 and provide the necessary insulation performance.

[0063] Specifically, the surface of the second dielectric layer 19 away from the substrate 10 can be planar. Achieving planarization of the upper surface of the device through the second dielectric layer 19 facilitates subsequent device fabrication processes.

[0064] For example, the material of the first dielectric layer 18 may include silicon nitride, and the material of the second dielectric layer 19 may include silicon oxide.

[0065] Furthermore, the first dielectric layer 18 can be a nitrided layer, and the second dielectric layer 19 can be an oxide layer.

[0066] In other alternative embodiments, such as Figure 1 As shown, the second source region 13 includes: a second body region 131, located in the substrate 10 on both sides of the first trench 11, wherein the surface of the second body region 131 near the source electrode 16 overlaps with a portion of the surface of the substrate 10, and has a first doping type; a third doped region 132, located in the second body region 131, wherein the third doped region 132 is a region formed by ion implantation of a portion of the surface of the second body region 131 near the source electrode 16, and the third doped region 132 has a second doping type; and a fourth doped region 133, located in the second body region 131, located in the... The third doped region 132 is located away from the first trench 11 and is in contact with the third doped region 132. The fourth doped region 133 is a region formed by ion implantation of a portion of the surface of the second body region 131 near the source electrode 16. The fourth doped region 133 has the first doping type and the doping concentration is greater than that of the second body region 131. The planar gate structure 15 is in contact with the third doped region 132, the second body region 131 and the substrate 10, respectively. The source electrode 16 is in contact with the third doped region 132 and the fourth doped region 133, respectively.

[0067] In the described embodiment, the second body region 131 forms a conductive channel and a PN junction with the SiC epitaxial layer, suppressing parasitic transistor effects. The low doping concentration of the second body region 131 is beneficial for the device to withstand high voltages because it prevents electric field punch-through from causing premature device breakdown. The third doped region 132 provides a low-impedance current path, contacting the source 16 metal to ensure that current flows quickly and efficiently during forward conduction. During device conduction, the third doped region 132 can rapidly inject a large number of charge carriers into the channel, forming a current conduction path for the device. The fourth doped region 133 contacts the third doped region 132. In reverse recovery or short-circuit conditions, the fourth doped region 133 can serve as an additional freewheeling channel, assisting in the rapid extraction and re-injection of charge carriers, reducing reverse recovery time, and thus reducing reverse recovery losses. This application, through the combined design of the second body region 131, the third doped region 132, and the fourth doped region 133, achieves efficient current switching, stable voltage withstand, and optimized thermal management.

[0068] In some embodiments, such as Figure 1 As shown, the planar gate structure 15 includes: a second oxide layer 151 located on a portion of the surface of the substrate 10 on both sides of the first trench 11, a portion of the surface of the second body region 131, and a portion of the surface of the third doped region 132; and a second gate 152 located on a portion of the surface of the second oxide layer 151 away from the substrate 10, wherein the projection of the second gate 152 on the substrate 10 overlaps with the second body region 131 and the third doped region 132, respectively.

[0069] Optionally, the second oxide layer 151 may contact the first oxide layer 141, that is, the second oxide layer 151 may extend to the opening edge of the first trench 11, thereby connecting with the first oxide layer 141. The first oxide layer 141 and the second oxide layer 151 may be formed simultaneously.

[0070] In some other embodiments, the substrate 10 has a second doping type, and the silicon carbide semiconductor device of this application further includes a drain electrode located on the surface of the substrate 10 away from the source electrode 16.

[0071] In some exemplary embodiments of this application, the materials of the first oxide layer 141 and the second oxide layer 151 may be silicon oxide. The materials of the first gate 142 and the second gate 152 may be polysilicon. The materials of the source 16 and the drain may be independently selected from at least one of nickel, aluminum, copper, silver, and gold.

[0072] For example, such as Figure 1As shown, the substrate 10 can be an N-type substrate, the first body region 121 and the second body region 131 can be P-type doped regions, the first doped region 122 and the third doped region 132 can be N+ type doped regions, and the second doped region 123 and the fourth doped region 133 can be P+ doped regions.

[0073] This application also provides a method for fabricating the silicon carbide semiconductor device described above. Figure 4 This is a flowchart of the method for fabricating a silicon carbide semiconductor device according to an embodiment of this application. Figures 5 to 21 A schematic diagram of the structure obtained after each process step of this preparation method is shown as an example. Figures 4 to 21 As shown, the method includes the following steps:

[0074] Step S201, providing an initial device, the initial device including an initial substrate and a first trench located in the initial substrate;

[0075] Step S202: A first source region is formed in the initial substrate at the bottom of the first trench, a second source region is formed in the initial substrate on both sides of the first trench, and a sacrificial structure in contact with the first source region is formed in the first trench, with the remaining initial substrate forming a substrate;

[0076] Optionally, the sacrificial structure may be a columnar structure or a cuboid structure extending along the depth direction of the first trench.

[0077] Step S203: A trench gate structure in contact with a portion of the surface of the first source region is formed in the remaining first trench; a planar gate structure in contact with a portion of the surface of the second source region is formed on the surface of the substrate; and a first initial dielectric layer is formed, the first initial dielectric layer being located on the outer wall of the sacrificial structure, the trench gate structure, the planar gate structure, and the exposed surfaces of the first and second source regions.

[0078] Step S204: At least a portion of the first initial dielectric layer and the sacrificial structure are removed to form a third trench in the remaining first trench, exposing a portion of the first source region and a portion of the second source region. The remaining first initial dielectric layer forms an interlayer dielectric layer, and a source electrode is formed in the third trench, on the exposed surface of the second source region, and on the exposed surface of the interlayer dielectric layer. The source electrode located in the third trench is in contact with the first source region.

[0079] This embodiment first provides an initial substrate and a first trench therein; then, a first source region and a second source region are formed in the initial substrate, and a sacrificial structure is formed in the first trench; subsequently, a trench gate structure is formed in the first trench, a planar gate structure is formed on the substrate, and a first initial dielectric layer covers the trench gate structure and the planar gate structure; finally, at least through a removal step, a third trench is formed in the first trench, exposing the first and second source regions, and the remaining first initial dielectric layer forms an interlayer dielectric layer; finally, a source electrode is formed in the third trench and on the exposed surfaces of the interlayer dielectric layer, the first source region, and the second source region, resulting in final carbonization. This silicon semiconductor device features a first trench that provides space for forming additional channels and eliminates the JFET region, thus avoiding the JFET effect. By forming a first source region at the bottom and a second source region on both sides of the first trench, and combining trench gate structure and planar gate structure, two independent conductive channels are successfully integrated into the device, achieving a three-dimensional layout of the device channels. This structure greatly improves the channel density of the device, allowing more channels to be accommodated within the same chip area, thereby improving the device's total current carrying capacity and power handling capacity, and effectively reducing the device's on-resistance and conduction loss.

[0080] In the specific implementation process, such as Figure 5 and Figure 6 As shown, the initial device further includes a first mask layer 22 and a second mask layer 24. The first mask layer 22 is located on the initial substrate 23 on both sides of the first trench 11, and the second mask layer 24 is located on the exposed surface of the first trench 11 and the exposed surface of the first mask layer 22. Providing an initial device may include: Figure 5 As shown, an intermediate substrate 20 is provided; a first oxide layer, a first nitride layer, and a second oxide layer are sequentially stacked on one side surface of the intermediate substrate 20. The first oxide layer can be formed by thermal oxidation and has a thickness of 200-500 angstroms; the first nitride layer can be formed by deposition and has a thickness of 1000-2000 angstroms; the second oxide layer can be formed by deposition and has a thickness of 14000-18000 angstroms. Figure 5As shown, a fourth photoresist layer 21 is formed on the surface of the second oxide layer away from the first nitride layer. The pattern opening of the fourth photoresist layer 21 is 1.5~2μm. Using the fourth photoresist layer 21 as a mask, the second oxide layer, the first nitride layer, and the first oxide layer are etched sequentially to expose a portion of the surface of the intermediate substrate 20. The etched second oxide layer forms a third sub-mask layer 223, the etched first nitride layer forms a second sub-mask layer 222, and the etched first oxide layer forms a first sub-mask layer 221, resulting in the first mask layer 22. The exposed intermediate substrate 20 is then etched. The etching depth is controlled to be 2~4μm to form the first trench 11. The angle between the sidewall of the first trench 11 and the surface of the intermediate substrate 20 is 70°~85°. The remaining intermediate substrate 20 forms the initial substrate 23. A third oxide layer with a thickness of 200~500 angstroms is formed on the surface of the initial substrate 23 and in the first trench 11 to obtain a fourth sub-mask layer 241. Then, a second nitride layer with a thickness of 3000~3500 angstroms is formed to cover the exposed surface of the third oxide layer to obtain a fifth sub-mask layer 242. The fourth sub-mask layer 241 and the fifth sub-mask layer 242 constitute the second mask layer 24.

[0081] In the embodiment described, the thickness of each sub-mask layer in the first mask layer 22 depends on the etching selectivity ratio of the photoresist to the oxide and nitride layers. The higher the etching selectivity ratio, the thinner the total thickness of the first mask layer 22 can be. The pattern opening of the fourth photoresist layer 21 determines the width of the first trench 11, which can be adjusted according to process capabilities and design. The depth of the first trench 11 can be adjusted according to process capabilities and design. The trench should not be too deep, as this will easily lower the breakdown voltage. Maintaining a certain tilt angle (i.e., 70°~85°) between the sidewalls and the horizontal plane can reduce the impact of subsequent high-energy ion implantation on the concentration near the trench sidewalls.

[0082] Based on this, step S201: forming a first source region 12 in the initial substrate 23 at the bottom of the first trench 11, forming a second source region 13 in the initial substrate 23 on both sides of the first trench 11, and forming a sacrificial structure 50 in the first trench 11 that contacts the first source region 12, including:

[0083] Step S2021: As Figure 8 As shown, a third mask layer 28 is formed on at least a portion of the surface of the second mask layer 24 away from the sidewall of the first trench, and the initial substrate 23 at the bottom of the first trench is implanted with ions of a first doping type using the third mask layer 28 as a mask to form a first initial body region 29.

[0084] Optionally, the first trench 11 covering the second mask layer 24 is a fifth trench, and a third mask layer 28 is formed at least on the surface of the second mask layer 24 away from the sidewall of the first trench 11, including: Figures 6 to 8 As shown, a first initial mask layer 25 is formed on the exposed surface of the second mask layer 24, resulting in the following: Figure 6 The structure shown has the following characteristics: the surface of the first initial mask layer 25 away from the initial substrate 23 is planar; a first photoresist layer 26 is formed on a portion of the surface of the first initial mask layer 25 away from the initial substrate 23, the pattern opening width of the first photoresist layer 26 being smaller than the bottom width of the first trench 11; using the first photoresist layer 26 as a mask, a portion of the first initial mask layer 25 is removed by wet etching to form an inverted trapezoidal sixth trench 27, resulting in the structure shown. Figure 7 The structure shown has a bottom width of the sixth trench 27 that is smaller than the bottom width of the first trench 11. Dry etching is performed on the structure with the sixth trench 27 to remove part of the remaining first initial mask layer 25 until the second mask layer 24 located in the fifth trench is exposed. The first photoresist layer 26 is removed, and dry etching is performed on the remaining first initial mask layer 25 until the second mask layer 24 on the initial substrate 23 on both sides of the fifth trench is exposed. The remaining first initial mask layer 25 forms the third mask layer 28, which is formed in the fifth trench. The third mask layer 28 covers the middle of the sidewall of the fifth trench, resulting in the structure shown. Figure 8 The structure shown.

[0085] In the embodiment, the pattern opening size of the first photoresist layer 26 is smaller than the bottom width of the first trench 11 to avoid the subsequent wet etching spreading causing the etched opening to be wider than the opening of the fifth trench. Utilizing the isotropic characteristics of wet etching, the inverted trapezoidal sixth trench 27 is formed, followed by dry etching to completely remove the first initial mask layer 25 in the exposed area until the surface of the bottom second mask layer 24 is etched. Then, the first photoresist layer 26 is removed, and dry etching is continued to etch the exposed first initial mask layer 25 on the device surface until the top first initial mask layer 25 is etched away, leaving only two mask pillars on the sidewall of the fifth trench. These two mask pillars cover part of the middle of the sidewall of the fifth trench, providing sidewall protection for the subsequent ion implantation process and preventing the epitaxial doping concentration of the sidewall of the fifth trench from being affected.

[0086] For example, the pattern opening width of the first photoresist layer 26 can be 1~1.5μm. The first initial mask layer 25 fills the first trench 11 and is 1~2μm higher than the upper surface of the second mask layer 24 on the initial substrate 23, ensuring effective coverage of the second mask layer 24 while avoiding material waste during the fabrication process.

[0087] Optionally, such as Figure 8 As shown, using the third mask layer 28 as a mask, ion implantation of the initial substrate 23 at the bottom of the first trench 11 is performed using a first doping type to form a first initial body region 29. This includes: using the third mask layer 28 as a mask, performing AI ion implantation on the initial substrate 23, controlling the ion implantation depth to be 0.8~1.2μm, to obtain the first initial body region 29 located in the initial substrate 23. This range ensures that the first initial body region 29 is not too deep, which would affect the breakdown voltage, nor too shallow, which would affect the normal operation of the subsequent MOS at the bottom of the first trench 11.

[0088] Step S2022: As Figure 10 As shown, a fourth mask layer 32 is formed on at least the surface of the second mask layer and the third mask layer 28 away from the sidewall of the first trench 11, and the first initial body region 29 is implanted with ions of the second doping type using the fourth mask layer 32 as a mask to form a first initial doped region 33 in the first initial body region 29.

[0089] Figure 9 This example illustrates a scenario where the fourth mask layer 32 is formed using the same material as the third mask layer 28. Exemplarily, both the fourth mask layer 32 and the third mask layer 28 can be silicon oxide mask layers.

[0090] Optionally, such as Figures 8 to 10 As shown, a fourth mask layer 32 is formed at least on the surfaces of the second mask layer 24 and the third mask layer 28 away from the sidewalls of the first trench 11, including: Figure 8 and Figure 9 As shown, a second initial mask layer 30 with a thickness of 0.2~0.4μm is deposited on the exposed surfaces of the second mask layer 24 and the third mask layer 28 (i.e., on the surface of the second mask layer 24 in the fifth trench and on both sides of the fifth trench), and the filled fifth trench forms a seventh trench 31; as Figure 9 and Figure 10As shown, the structure after the formation of the second initial mask layer 30 is subjected to dry etching to expose the bottom of the seventh trench 31 to the second mask layer 24, and the second initial mask layer 30 on the second mask layer 24 on both sides of the seventh trench 31 is removed. The remaining second initial mask layer 30 forms the fourth mask layer 32, and the remaining seventh trench 31 forms the eighth trench 34.

[0091] In the embodiment, by etching the second initial mask layer 30, only the second initial mask layer 30 located on both sides inside the fifth trench is retained to obtain the fourth mask layer 32, and the position and width of the ion implantation region are restricted by the fourth mask layer 32.

[0092] For example, the fourth mask layer 32 may be a silicon oxide mask layer.

[0093] Optionally, such as Figure 10 As shown, using the fourth mask layer 32 as a mask, ion implantation of the first initial body region 29 with a second doping type is performed to form a first initial doped region 33 in the first initial body region 29. This includes: using the fourth mask layer 32 as a mask, performing ion implantation on the first initial body region 29, controlling the implantation depth to be 0.1~0.2μm, to obtain the first initial doped region 33. The left and right sides of the first initial doped region 33 do not overlap with the left and right sides of the first initial body region 29, and the distance between their left sides is 0.3~0.4μm, and the distance between their right sides is 0.3~0.4μm. The area where the two sides do not overlap is the channel region, and these two distances are the channel length.

[0094] Step S2023: As Figure 11 As shown, a fifth mask layer 35 is formed on the sidewall of the fourth mask layer 32. Using the fifth mask layer 35 as a mask, the bottom of the remaining first trench 11 is etched to penetrate the first initial doped region 33 and reach the first initial body region 29 to form a fourth trench 36. The initial substrate 23 at the bottom of the fourth trench 36 is implanted with ions of the first type to form a second doped region 123 located in the first initial body region 29 and in contact with the first initial doped region 33. The remaining first initial body region 29 forms a first body region 121, and the remaining first initial doped region 33 forms a first doped region 122. The first body region 121, the first doped region 122, and the second doped region 123 form the first source region 12.

[0095] Optionally, a fifth mask layer 35 is formed on the sidewall of the fourth mask layer 32. Using the fifth mask layer 35 as a mask, the bottom of the remaining first trench 11 is etched to penetrate the first initial doped region 33 and reach the first initial body region 29, forming a fourth trench 36. This includes: sequentially stacking a third initial mask layer and a fourth initial mask layer on the exposed surfaces of the fourth mask layer 32 and the second mask layer 24 (i.e., in the eighth trench 34 and on the surface of the second mask layer 24 away from the initial substrate 23). The thickness of the third initial mask layer is 0.1~0.2μm, and the thickness of the fourth initial mask layer is 0.1~0.2μm. The remaining eighth trench 34 forms a ninth trench. Dry etching is performed on the structure with the ninth trench to remove the second mask layers on both sides of the ninth trench. The fourth initial mask layer on 24, the third mask layer 28 on the second mask layer 24 on both sides of the ninth trench, a portion of the fourth initial mask layer at the bottom of the ninth trench, and a portion of the third initial mask layer in the ninth trench are etched away, exposing a portion of the second mask layer 24 at the bottom of the ninth trench. The remaining third initial mask layer and the fourth initial mask layer form the fifth mask layer 35. Using the fifth mask layer 35 as a mask, a self-aligned process is used to etch the exposed second mask layer 24 at the bottom of the ninth trench, exposing a portion of the initial substrate 23. The exposed initial substrate 23 is etched to form a second trench 17 located in the initial substrate 23. The depth of the second trench 17 is 0.3~0.4μm, and the entire trench forms the fourth trench 36.

[0096] Specifically, the second trench 17 should not be too deep to prevent it from penetrating the first initial body region 29 at the bottom of the trench. A first type of ion implantation is performed on the initial substrate 23 at the bottom of the fourth trench 36 to form a second doped region 123 located in the first initial body region 29 and in contact with the first initial doped region 33. This includes: vertical ion implantation on the initial substrate 23 at the bottom of the fourth trench 36, and ion implantation at an angle of approximately 7° to the vertical direction, with an implantation depth of 0.1~0.15 μm. The ion implantation width around the second trench 17 is controlled at 0.03~0.05 μm to ensure that the formed second doped region 123 is not too large, thus avoiding affecting the breakdown voltage while effectively reducing the internal resistance of the first body region 121, thereby allowing the device to utilize a body diode for freewheeling.

[0097] Optionally, such as Figure 11As shown, the fourth initial mask layer can be a nitride layer, and the third initial mask layer can be an oxide layer. The fifth mask layer 35 includes a stacked sixth sub-mask layer 351 (i.e., the remaining third initial mask layer) and a seventh sub-mask layer 352 (i.e., the remaining fourth initial mask layer).

[0098] It should be noted that, since the third mask layer 28 and the second initial mask layer 30 in this embodiment are film layers formed using the same material, and the third mask layer 28, the fourth mask layer 32 and the sixth sub-mask layer 351 are film layers formed using the same material, therefore... Figures 9 to 11 The boundaries between these film layers are defined by dashed lines.

[0099] Step S2024: As Figures 11 to 14 As shown, the fourth trench 36 is filled with an oxide material, the exposed surface of the initial device filled with the oxide material is planarized until a portion of the first mask layer 22 is removed, and the initial substrate 23 is ion implanted with at least the remaining first mask layer 22 as a mask to form the second source region 13 in the initial substrate 23, and the remaining initial substrate 23 forms the substrate 10;

[0100] Optionally, the first mask layer 22 includes a stacked first sub-mask layer 221, a second sub-mask layer 222, and a third sub-mask layer 223, and the second mask layer 24 includes a stacked fourth sub-mask layer 241 and a fifth sub-mask layer 242. Filling the fourth trench 36 with an oxide material includes: covering the exposed surface of the device in which the fourth trench 36 is formed with the oxide material, such that the oxide material fills the fourth trench 36 and covers the upper surface of the second mask layer 24; planarizing the device filled with the oxide material until the second sub-mask layer 223 is reached. 22 is exposed, or until part of the second sub-mask layer 222 is removed, such that the thickness of the remaining first mask layer 22 is 1000~2000 angstroms. The remaining first mask layer 22 forms the first intermediate mask layer 37, the remaining oxide material forms the initial sacrificial structure 38, the remaining fourth sub-mask layer 241 forms the fourth intermediate mask layer 39, the remaining fifth sub-mask layer 242 forms the fifth intermediate mask layer 40, the remaining sixth sub-mask layer 351 forms the sixth intermediate mask layer 41, and the remaining seventh sub-mask layer 352 forms the seventh intermediate mask layer 42, as shown. Figure 12As shown, the seventh intermediate mask layer 42 is located on the upper half of the outer wall of the initial sacrificial structure 38, the sixth intermediate mask layer 41 is located on the upper half of the outer wall of the seventh intermediate mask layer 42, the fifth intermediate mask layer 40 is located on the outer wall and bottom of the sixth intermediate mask layer 41 and contacts the lower half of the outer wall of the seventh intermediate mask layer 42, and the fourth intermediate mask layer 39 is located on the outer wall and bottom of the fifth intermediate mask layer 40 and contacts a portion of the sidewall of the initial sacrificial structure 38.

[0101] Optionally, at least the remaining first mask layer 22 is used as a mask to perform ion implantation on the initial substrate 23 to form the second source region 13 in the initial substrate 23, and the remaining initial substrate 23 forms the substrate 10, including: forming a fifth initial mask layer on the planarized device surface, the thickness of the fifth initial mask layer being 1~2 μm; removing a portion of the fifth initial mask layer by photolithography, thereby exposing a portion of the second sub-mask layer 222. Figure 12 In this process, the first intermediate mask layer 37 includes a first sub-mask layer 221 and a second sub-mask layer 222 stacked on the initial substrate 23, and the remaining fifth initial mask layer forms a sixth mask layer 43; the structure with the sixth mask layer 43 is subjected to AI ion implantation to an implantation depth of 0.8~1.2 μm to form a second initial body region 44 in the initial substrate 23, resulting in... Figure 12 The structure shown; a seventh mask layer 45 is formed on a portion of the exposed surface of the second sub-mask layer 222, the seventh mask layer 45 being in contact with the sixth mask layer 43, and the thickness of the seventh mask layer 45 being 0.2~0.4 μm; ion implantation is performed on the device with the seventh mask layer 45 formed, such that the implantation depth is 0.15~0.2 μm, to form a third initial doped region 46 in the second initial body region 44, resulting in the structure shown. Figure 13 The structure shown; as Figure 14 As shown, an eighth mask layer 47 is formed on a portion of the exposed surface of the second sub-mask layer 222. The eighth mask layer 47 is in contact with the seventh mask layer 45, and the thickness of the eighth mask layer 47 is 0.2~0.4 μm. Al ion implantation is performed on the device with the eighth mask layer 47 to an implantation depth of 0.6~0.8 μm to form a fourth doped region 133 extending from the third initial doped region 46 into the second initial body region 44. The remaining second initial body region 44 forms the second body region 131, and the remaining third initial doped region 46 forms the third doped region 132. The second body region 131, the third doped region 132, and the third doped region 132 constitute the second source region 13, and the remaining initial substrate 23 forms the substrate 10.

[0102] For example, the fifth mask layer 35 can be a nitrided layer, and the sixth mask layer 43 and the seventh mask layer 45 can be oxide layers, respectively.

[0103] It should be noted that, since the seventh mask layer 45 and the eighth mask layer 47 described in this embodiment are film layers formed using the same material, therefore... Figure 14 The boundary between the two is defined by a dashed line.

[0104] Step S2025: Remove the remaining first mask layer 22, the remaining second mask layer 24, the remaining third mask layer 28, the remaining fourth mask layer 32 and the remaining fifth mask layer 35, so that the surfaces of the first source region 12, the second source region 13, the substrate 10 and the remaining oxide material are exposed, and the remaining oxide material forms the sacrificial structure 50.

[0105] Optionally, the remaining first mask layer 22, the remaining second mask layer 24, the remaining third mask layer 28, the remaining fourth mask layer 32, and the remaining fifth mask layer 35 are removed, exposing the surfaces of the first source region 12, the second source region 13, the substrate 10, and the remaining oxide material. The remaining oxide material forms the sacrificial structure 50, including: Figure 14 As shown, a second photoresist layer 48 is formed on the portion of the fifth mask layer 35 away from the substrate 10. Along the thickness direction of the device, the second photoresist layer 48 covers the initial sacrificial structure 38, and the center point of the second photoresist layer 48 is located on the extended line of the centerline of the initial sacrificial structure 38. Figure 15 As shown, the eighth mask layer 47 and the seventh mask layer 45 are removed by etching with hydrochloric acid; as Figure 16 As shown, using the second photoresist layer 48 as a mask, phosphoric acid is used to etch the second sub-mask layer 222 and the sixth mask layer 43 to remove a portion of the sixth mask layer 43. The remaining sixth mask layer 43 at least covers the upper surface of the seventh intermediate mask layer 42, and the fifth intermediate mask layer 40 is etched away, exposing a portion of the sidewalls of the seventh intermediate mask layer 42 and the sixth intermediate mask layer 41. The remaining sixth mask layer 43 forms the eighth intermediate mask layer 49. Figure 17 As shown, hydrochloric acid etching is used to remove the first sub-mask layer 221, the sixth intermediate mask layer 41, and the fourth intermediate mask layer 39, exposing the surface of the substrate 10, a portion of the bottom of the first trench 11, the seventh intermediate mask layer 42, and a portion of the initial sacrificial structure 38; as Figure 18As shown, the second photoresist layer 48 is removed, and the seventh intermediate mask layer 42 and the eighth intermediate mask layer 49 are removed by phosphoric acid etching, exposing the initial sacrificial structure 38; removing part of the initial sacrificial structure 38 yields the sacrificial structure 50, whose upper surface is flush with the surface of the substrate 10. Figure 18 As shown, the sacrificial structure 50 is located in the first trench 11 and the second trench 17, and the surface of the substrate 10, part of the bottom and sidewalls of the first trench 11 are exposed.

[0106] For example, the width of the second photoresist layer 48 can be 0.6~0.8μm;

[0107] Optionally, after obtaining the second source region 13 and before forming the sacrificial structure 50, the method further includes: annealing the device with the second source region 13 formed thereon at an annealing temperature greater than 1700°C for 25-30 minutes to activate the first source region 12 and the second source region 13.

[0108] In other embodiments, a trench gate structure is formed in the remaining first trench 11 to contact a portion of the surface of the first source region 12; a planar gate structure is formed on the surface of the substrate 10 to contact a portion of the surface of the second source region 13; and a first initial dielectric layer is formed, the first initial dielectric layer being located on the outer wall of the sacrificial structure 50, the trench gate structure, the planar gate structure, and the exposed surfaces of the first source region 12 and the second source region 13, including: Figure 18 and Figure 19 As shown, a first dielectric layer 18 is formed on the exposed sidewall of the sacrificial structure 50, and the bottom of the first dielectric layer 18 covers a portion of the surface of the third doped region 132; as Figure 19 As shown, an initial gate oxide layer 51 is formed on the bottom and sidewalls of the remaining first trench 11 and on the surface of the substrate 10. The thickness of the initial gate oxide layer 51 can be 300-400 angstroms. Figure 19 and Figure 20 As shown, a polysilicon layer 52 is formed on the exposed surface of the initial gate oxide layer 51, the exposed surface of the first dielectric layer 18, and the exposed surface of the sacrificial structure 50. The polysilicon layer 52 fills the first trench, and the upper surface of the polysilicon layer 52 is planar. The thickness of the polysilicon layer 52 can be 1000~2000 angstroms. A third photoresist layer 53 is formed on the portion of the polysilicon layer 52 away from the substrate 10. In the thickness direction of the device, the third photoresist layer 53 overlaps with a portion of the second body region 131, a portion of the third doped region 132, and a portion of the substrate 10, respectively. Figure 20 and Figure 21 As shown, using the third photoresist layer 53 as a mask, the polysilicon layer 52 is etched to obtain a first gate 142 and a second gate 152. The first gate 142 is located on the initial gate oxide layer 51 in the first trench 11, and its thickness can be 0.4~0.5μm. The second gate 152 is located on the initial gate oxide layer 51 on both sides of the first trench 11, and its width can be 0.8~1μm. In the thickness direction of the device, the first gate 142 overlaps with the first body region 121 and the first doped region 122 respectively, but does not overlap with the second doped region 123; the second gate 152 overlaps with the second body region 131 and the third doped region 132 respectively, but does not overlap with the fourth doped region 133. One end of the second gate 152 is located at the corner of the first trench 11. Figure 21 As shown, a second initial dielectric layer 54 is formed on the exposed surface of the device on which the first gate 142 and the second gate 152 are formed, and the second initial dielectric layer 54 and the first dielectric layer 18 form the first initial dielectric layer.

[0109] At least a portion of the first initial dielectric layer and the sacrificial structure 50 are removed to form a third trench in the remaining first trench 11, exposing a portion of the first source region 12 and a portion of the second source region 13. The remaining first initial dielectric layer forms an interlayer dielectric layer, and a source electrode 16 is formed in the third trench, on the exposed surface of the second source region 13, and on the exposed surface of the interlayer dielectric layer, including: Figure 21 and Figure 1 As shown, the device with the second initial dielectric layer 54 is subjected to photolithography and etching to remove the sacrificial structure 50, a portion of the second initial dielectric layer 54, and a portion of the initial gate oxide layer 51, exposing a portion of the surface of the first doped region 122, a portion of the surface of the second doped region 123, a portion of the surface of the third doped region 132, and a portion of the surface of the fourth doped region 133. The remaining second initial dielectric layer 54 forms the second dielectric layer 19, and the remaining initial gate oxide layer 51 forms the gate oxide layer. The thickness of the second dielectric layer 19 on the gate oxide layer is 4000~6000 angstroms. Metal material is deposited on the exposed surface of the device to form a source electrode 16 that contacts the first doped region 122, the second doped region 123, the third doped region 132, and the fourth doped region 133, respectively. The surface of the source electrode 16 away from the substrate 10 is planar.

[0110] Specifically, such as Figure 1As shown, the gate oxide layer is located both between the first gate 142 and the substrate 10 (corresponding to the first oxide layer 141), forming a trench gate structure 14 with the first gate 142, and between the second gate 152 and the substrate 10 (corresponding to the second oxide layer 151), forming a planar gate structure 15 with the second gate 152. The gate oxide layer extends from the surfaces of the substrate 10 on both sides of the first trench 11 to the bottom surface of the first trench 11, forming a continuous film structure.

[0111] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the silicon carbide semiconductor device fabrication method of this application will be described in detail below with reference to specific embodiments.

[0112] This embodiment relates to a specific method for fabricating a silicon carbide semiconductor device, including the following steps:

[0113] 1) A hard mask (HM) is deposited using an ONO stacking method. The first layer is OX (oxide) deposited thermally, with a thickness of 200-500 angstroms. The second layer is SiN (nitride), with a thickness of 1000-2000 angstroms. The third layer is OX (oxide), formed by deposition, with a thickness of 15000-18000 angstroms. The thickness of the ONO film depends on the etching ratio of the photoresist to the OX and SiN layers; the higher the etching ratio, the thinner the ONO film can be. Photoresist is applied, and the photolithographic CD (Critical Dimension) is 1.5-2 μm. This determines the CD size of the inverted trapezoidal groove (i.e., the first trench), which can be adjusted according to process capabilities and design. The hard mask is then etched, stopping at the SiC epitaxial surface.

[0114] 2) Etch SiC epitaxy to a depth of 2-4 μm. This determines the depth of the inverted trapezoidal trench, which can be adjusted according to process capabilities and design. The trench should not be too deep, as the breakdown voltage may be too low. The sidewalls should maintain a certain tilt angle with the horizontal plane, approximately 70-85°, to reduce the impact of subsequent high-energy ion implantation on the concentration near the trench sidewalls. Deposit an oxide layer OX with a thickness of 200-500 angstroms on the surface, and deposit a nitride layer SiN with a thickness of 3000-3500 angstroms as the dielectric layer for subsequent self-aligned processes. Then, deposit an oxide layer using HDP (High Density Plasma) to fill the trench. The OX surface should be 1-2 μm higher than the SiN surface, only needing to be more than 1 μm higher to ensure coverage of the SiN layer.

[0115] 3) Photolithography: Expose CD 1.0~1.5μm, which is narrower than the inverted trapezoidal groove CD. This avoids the subsequent wet etching expansion causing the etched opening to be wider than the openings on both sides of SiN. Perform a Descum (residual resist removal) process to cure the photoresist. Then perform wet etching on the OX on the surface. Due to the isotropic nature of wet etching, the groove formed by etching is inverted trapezoidal.

[0116] 4) Dry etching is performed on the oxide layer while retaining the photoresist, completely removing the OX in the exposed area until the SiN surface at the bottom of the trench is etched. Then, the photoresist is removed, and dry etching is used to etch the surface oxide layer until the topmost OX is completely etched clean, leaving only two OX pillars on the trench sidewall. The OX pillars cover part of the middle of the sidewall. Al ion implantation is performed to form the P-Well region with an implantation depth of 0.8~1.2μm. It should not be too deep, as this will affect the breakdown voltage, nor should it be too shallow, to avoid affecting the normal operation of the MOS at the bottom of the inverted trapezoidal trench. Because the sidewall is protected by the two OX pillars, the epitaxial doping concentration of the trench sidewall is not affected.

[0117] 5) A self-aligned process is used to deposit an OX layer with a thickness of 0.2~0.4μm to cover the surface SiN layer.

[0118] 6) Dry etching is performed on the surface OX to over-etch the bottom OX to SiN, and N ion implantation is performed to form an N+ region with a depth of 0.1~0.2μm. The length of the non-overlapping position on the left and right sides of the N+ and P- regions is 0.3~0.4μm, which is used as the channel length of the SiC device. This position is the channel region.

[0119] 7) Deposit an oxide layer again, with a thickness of 0.1~0.2μm, and then deposit a SiN layer with a thickness of 0.1~0.2μm. Use dry etching to etch away the SiN and OX layers in the trench using a self-aligned method to expose the SiC surface. Then etch the SiC to create a small trench (i.e., the second trench), 0.3~0.4μm below the SiC surface at the bottom of the trench, for ion implantation on the SiC substrate at the bottom of the inverted trapezoidal trench. Do not implant too deeply to prevent penetration through the bottom P-Well of the inverted trapezoidal trench. Then perform ion implantation at approximately 7° and vertically, implanting Al ions to form a P+ region with an implantation depth of 0.1~0.15μm and a trench width of 0.03~0.05μm on both sides. The formed P+ region should not be too large to avoid affecting the breakdown voltage, while effectively reducing the internal resistance of the P-Well and utilizing the body diode for freewheeling.

[0120] 8) Then, an oxide layer is deposited in the trench using HDP to fill the small trenches, filling the OX surface 1~2μm higher than the SiN surface. Subsequently, the surface SiN layer and OX layer are etched and thinned by CMP (Chemical Mechanical Polishing). The HM (OX+SiN+OX) composite layer is thinned to 1000~2000 angstroms, while a layer of SiN with a thickness of 1~2μm is deposited. Photolithography is then performed to expose the P-Well implantation region, and Al ion implantation is performed to a depth of 0.8~1.2μm to form the P-Well.

[0121] 9) Using a self-aligned method, deposit 0.2~0.4μm thick OX, and then etch back OX to expose the SiN surface to obtain the N+ implantation region. Perform N ion implantation to a depth of 0.15~0.2μm.

[0122] 10) Using a self-aligned method, deposit a 0.2~0.4μm thick OX layer, and then etch back the OX to the exposed SiN surface to obtain the P+ implantation region. Perform Al ion implantation to a depth of 0.6~0.8μm, followed by annealing at >1700℃ for 25~30 minutes to activate the previous implantation. Next, coat with PR resist and expose the area. The remaining photoresist covers the top of the internal OX pillars with a width of 0.6~0.8μm, with the center of the photoresist aligned with the center of the OX pillars. Descum and cure the photoresist.

[0123] 11) First, use hydrochloric acid to over-etch the surface OX. After removing the surface OX, use phosphoric acid to etch the SiN, causing the surface SiN film to narrow into the photoresist on both sides, exposing the OX in the trench. At the same time, the SiN at the top of the OX pillar wraps around the SiN on the OX pillar and the SiN on the sidewalls of the OX pillar. Then, use an appropriate amount of hydrochloric acid to etch the exposed OX, so that the OX outside the SiN on both sides of the OX pillar is completely removed. Since the OX thickness at the bottom of the SiN on both sides of the OX pillar is only 200~500 angstroms, the hydrochloric acid etching window is small. Therefore, the OX etching rate on the SiC surface at the bottom of the trench is low, and the process is relatively controllable. Finally, remove the photoresist and use excess phosphoric acid to etch the SiN wrapped on the OX surface, exposing the OX pillar.

[0124] 12) Next, a SiN layer is deposited on the device surface. The SiN on the top of the OX pillar and other locations is etched away by anisotropic etching using dry etching to remove surface C. Subsequently, a gate oxide layer with a thickness of 300~400 angstroms is formed by oxidation.

[0125] 13) Deposit Poly, then grind it to a surface thickness of 1000~2000 angstroms by CMP, apply PR (photoresist) and perform photolithography, then etch Poly, retaining only a 0.8~1μm wide Poly on the surface and a 0.4~0.5μm thick Poly in the trench. The surface Poly requires one side to cover the N+ region and not to cover the P+ region, and the other side of the Poly is at the corner of the trench.

[0126] 14) Perform ILD (Inter Layer Dielectric) deposition with a thickness of approximately 6000~8000 angstroms, followed by reflow planarization.

[0127] 15) Finally, photolithography and etching processes are performed to etch away the OX pillars in the trench, exposing the internal SiN and the SiC at the bottom of the trench. Contact holes are also etched into the surface ILD, covering P+ and part of N+. The contact holes on the device surface and the ILD on the Poly side are left with a thickness of 4000 to 6000 angstroms. Then, metal sputtering and alloying are performed to complete the final device structure.

[0128] In this embodiment, an inverted trapezoidal trench is introduced into the planar gate MOS, and the source metal is inserted deep into the SiC substrate below the trench through a series of self-aligned processes, shorting it to the P+ at the bottom of the trench. This forms a freewheeling channel during reverse recovery or short-circuit overshoot. During overcurrent, this is equivalent to nearly twice the current path of a traditional planar gate MOS. When the device is operating in the forward direction, it can also serve as a reverse current channel for the MOS at the bottom of the trench. Regardless of the device's operating condition, the current density within the device is more uniform. Furthermore, this embodiment utilizes a SiN layer as the dielectric layer for the self-aligned process, reducing the number of photolithography layers and successfully isolating the source metal layer from the polysilicon layer, thus preventing gate-source short circuits.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A silicon carbide semiconductor device, characterized in that, include: A substrate having a first groove on one side surface; The first source region is located in the substrate at the bottom of the first trench; The second source region is located in the substrate on both sides of the first trench; A trench gate structure is located in the first trench and is in contact with the first source region; A planar gate structure is located on the substrate on both sides of the first trench and is in contact with the second source region; An interlayer dielectric layer is located in the first trench, and also on the side of the trench gate structure, on the surface of the trench gate structure away from the substrate, on the side of the planar gate structure, and on the surface of the planar gate structure away from the substrate; The source electrode is located in the first trench, on a portion of the surface of the second source region, on the surface of the interlayer dielectric layer away from the substrate, and on the sidewall, and is in contact with the first source region.

2. The silicon carbide semiconductor device according to claim 1, characterized in that, Along the direction from the bottom of the first trench to the opening of the first trench, the width of the first trench increases, and the angle between the sidewall of the first trench and the surface of the substrate on both sides of the first trench is 70~85°.

3. The silicon carbide semiconductor device according to claim 1, characterized in that, The first source region includes: A first body region is located in the substrate at the bottom of the first trench, and the first body region has a first doping type; The first doped region is located in the first body region. The first doped region is a region formed by ion implantation of a portion of the surface of the first body region near the trench gate structure. The first doped region has a second doping type. The second doped region is located in the first body region, on the side of the first doped region away from the trench gate structure, and in contact with the first doped region. The second doped region has the first doping type and the doping concentration is greater than that of the first body region. The trench gate structure is in contact with the first body region and the first doped region, respectively, and the source electrode is in contact with the first doped region and the second doped region, respectively.

4. The silicon carbide semiconductor device according to claim 3, characterized in that, The silicon carbide semiconductor device further includes: The second trench is located at the bottom of the first trench and extends through the first doped region to the second doped region. The source electrode is also located in the second trench.

5. The silicon carbide semiconductor device according to claim 3, characterized in that, The first source region satisfies at least one of the following: The junction depth of the first body region is 0.8~1.2μm; The junction depth of the first doped region is 0.1~0.2μm; The junction depth of the second doped region is 0.1~0.15μm; The distance between the sidewall of the first body region and the sidewall of the first doped region, which are located on the same side, is 0.3~0.4μm.

6. The silicon carbide semiconductor device according to claim 3, characterized in that, The trench grid structure includes: The first oxide layer is located on a portion of the surface of the first body region near the interlayer dielectric layer, a portion of the surface of the first doped region near the interlayer dielectric layer, and the sidewall of the first trench. A first gate is located on the surface of the first oxide layer away from the first body region and the first doped region, and the thickness of the first gate is less than the depth of the first trench.

7. The silicon carbide semiconductor device according to claim 6, characterized in that, The interlayer dielectric layer includes: A first dielectric layer is located in the first trench and is in contact with the surface of the first gate away from the sidewall of the first trench, the sidewall of the first oxide layer located between the first gate and the first doped region, and the source electrode, respectively. The thickness of the first dielectric layer is greater than the thickness of the first gate and less than or equal to the depth of the first trench. The second dielectric layer is located between the first oxide layer and the first dielectric layer, on the side of the planar gate structure, and on the surface of the planar gate structure away from the substrate. The first dielectric layer and the second dielectric layer are made of different materials.

8. The silicon carbide semiconductor device according to claim 1, characterized in that, The second source region includes: The second body region is located in the substrate on both sides of the first trench, and the surface of the second body region near the source electrode overlaps with a portion of the surface of the substrate, and has a first doping type; The third doped region is located in the second body region. The third doped region is a region formed by ion implantation of a portion of the surface of the second body region near the source electrode. The third doped region has a second doping type. The fourth doped region is located in the second body region, on the side of the third doped region away from the first trench, and in contact with the third doped region. The fourth doped region is a region formed by ion implantation of a portion of the surface of the second body region near the source electrode. The fourth doped region has the first doping type and the doping concentration is greater than that of the second body region. The planar gate structure is in contact with the third doped region, the second bulk region, and the substrate, respectively, and the source electrode is in contact with the third doped region and the fourth doped region, respectively.

9. A method for fabricating a silicon carbide semiconductor device according to any one of claims 1 to 8, characterized in that, include: An initial device is provided, the initial device comprising an initial substrate and a first trench located in the initial substrate; A first source region is formed in the initial substrate at the bottom of the first trench, a second source region is formed in the initial substrate on both sides of the first trench, and a sacrificial structure in contact with the first source region is formed in the first trench, with the remaining initial substrate forming a substrate; A trench gate structure is formed in the remaining first trench that contacts a portion of the surface of the first source region; a planar gate structure is formed on the surface of the substrate that contacts a portion of the surface of the second source region; and a first initial dielectric layer is formed, the first initial dielectric layer being located on the outer wall of the sacrificial structure, the trench gate structure, the planar gate structure, and the exposed surfaces of the first and second source regions. At least a portion of the first initial dielectric layer and the sacrificial structure are removed to form a third trench in the remaining first trench, exposing a portion of the first source region and a portion of the second source region. The remaining first initial dielectric layer forms an interlayer dielectric layer, and a source electrode is formed in the third trench, on the exposed surface of the second source region, and on the exposed surface of the interlayer dielectric layer. The source electrode located in the third trench is in contact with the first source region.

10. The method according to claim 9, characterized in that, The initial device further includes a first mask layer and a second mask layer, the first mask layer being located on the initial substrates on both sides of the first trench, and the second mask layer being located on the exposed surface of the first trench and the exposed surface of the first mask layer. A first source region is formed in the initial substrate at the bottom of the first trench, a second source region is formed in the initial substrates on both sides of the first trench, and a sacrificial structure in the first trench that contacts the first source region is formed, including: A third mask layer is formed on at least a portion of the surface of the second mask layer away from the sidewall of the first trench, and the third mask layer is used as a mask to perform ion implantation of a first doping type on the initial substrate at the bottom of the first trench to form a first initial body region. A fourth mask layer is formed on at least the surfaces of the second mask layer and the third mask layer away from the sidewalls of the first trench, and the first initial body region is implanted with ions of the second doping type using the fourth mask layer as a mask to form a first initial doped region in the first initial body region. A fifth mask layer is formed on the sidewall of the fourth mask layer. Using the fifth mask layer as a mask, the bottom of the remaining first trench is etched to penetrate the first initial doped region and reach the first initial body region to form a fourth trench. The initial substrate at the bottom of the fourth trench is implanted with ions of the first type to form a second doped region located in the first initial body region and in contact with the first initial doped region. The remaining first initial body region forms a first body region, the remaining first initial doped region forms a first doped region, and the first body region, the first doped region, and the second doped region form the first source region. An oxide material is filled into the fourth trench, and the exposed surface of the initial device filled with the oxide material is planarized until a portion of the first mask layer is removed. Ion implantation is performed on the initial substrate using at least the remaining first mask layer as a mask to form the second source region in the initial substrate, and the remaining initial substrate forms the substrate. The remaining first mask layer, the remaining second mask layer, the remaining third mask layer, the remaining fourth mask layer, and the remaining fifth mask layer are removed, exposing the first source region, the second source region, the surface of the substrate, and the remaining oxide material, with the remaining oxide material forming the sacrificial structure.

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