Method of manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device (100) is presented. The method includes processing the semiconductor body (102) at a first surface (1021) of the semiconductor body (102). Processing the semiconductor body (102) includes forming a wiring region (104) over the first surface (1021). Thereafter, the method further includes forming a field stop region (106) in the semiconductor body. Forming the field stop region (106) includes introducing implant ions including selenium into the semiconductor body (102) through the second surface (1022) of the semiconductor body (102) by an ion implantation process (I2Se). The second surface (1022) is opposite the first surface (1021). The main beam direction (I2Se) of the ion implantation process deviates from the main crystal direction by at most 1 degree, the implanted ions are channelized along the main crystal direction, and the main beam incident angle divergence is at most + / -0.5 degrees. Forming the field stop region (106) further includes electrically activating at least a portion of the selenium by a laser annealing process (LA).

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including forming a field stop region. Background Technology

[0002] The development of next-generation semiconductor devices (e.g., insulated-gate field-effect transistors (IGFETs), such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) or diodes) aims to improve electrical characteristics and reduce costs by shrinking device geometry. While cost reduction is possible through shrinking device geometry, various trade-offs and challenges must be met when increasing device functionality per unit area. For example, improving the electrical characteristics of the field stop region (e.g., regarding reduced thermal leakage current and / or turn-off softness) can be challenging due to process-dependent constraints. Such process-dependent constraints may arise from thermal budget constraints due to process sequences, such as the thermal budget constraints for processing the back side of the semiconductor body when the front-side processing is already complete or partially complete.

[0003] Therefore, there is a need to improve the methods used to manufacture semiconductor devices. Summary of the Invention

[0004] Examples of this disclosure relate to a method of manufacturing a semiconductor device. The method includes processing the semiconductor body at a first surface. Processing the semiconductor body includes forming a wiring region over the first surface. The method further includes forming a field stop region in the semiconductor body. Forming the field stop region includes introducing implanted ions, including selenium, into the semiconductor body through a second surface of the semiconductor body via an ion implantation process. The second surface is opposite to the first surface. The main beam direction of the ion implantation process deviates from the host crystal direction by at most 1 degree, channeling of the implanted ions occurs along the host crystal direction, and the main beam incident angle divergence is at most ±0.5 degrees. Forming the field stop region further includes electrically activating at least a portion of the selenium by a laser annealing process.

[0005] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and when viewing the accompanying drawings. Attached Figure Description

[0006] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which similar reference numerals refer to similar or identical elements. The elements in the drawings are not necessarily drawn to scale relative to each other. Features of the various illustrated examples can be combined unless they are mutually exclusive.

[0007] Figures 1A to 1C It is a cross-sectional view of a semiconductor body used to illustrate the process characteristics of manufacturing semiconductor devices.

[0008] Figures 2 to 5 It is used for diagrams that can be integrated into Figures 1A to 1C The diagram shows a cross-sectional view of the semiconductor body illustrating the process characteristics in the method.

[0009] Figure 6 It is a schematic top view used to illustrate a pattern applied to the surface of a semiconductor body by a multi-pulse laser beam. Detailed Implementation

[0010] In the following detailed description, reference is made to the accompanying drawings, which form part of the detailed description and illustrate specific examples of methods for manufacturing semiconductor devices by way of illustration. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. For example, a feature illustrated or described for one example may be used in combination with other examples to produce yet another example. It is intended that this disclosure include such modifications and variations. The use of specific language to describe the examples should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustrative purposes only. Unless otherwise stated, corresponding elements are designated by the same reference numerals in different drawings.

[0011] Although specific examples have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent embodiments may be substituted for the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

[0012] It should be noted that the methods and devices, including their preferred embodiments as outlined in this document, can be used independently or in combination with other methods and devices disclosed in this document. Furthermore, the features outlined in the context of the device also apply to the corresponding method, and vice versa. Moreover, all aspects of the methods and devices outlined in this document can be combined arbitrarily. In particular, the features of the claims can be combined with each other in any manner.

[0013] The terms “having,” “comprising,” “including,” “containing,” and the like are open-ended and indicate the presence of the stated structure, element, or feature, but do not exclude the presence of additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0014] The range given for physical dimensions includes boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value, such as "at most" and "at least".

[0015] The terms “on” and “above” should not be interpreted as simply meaning “directly on” and “directly above”. Rather, if an element is positioned “on” or “above” another element (e.g., a layer “on” or “above” another layer or a substrate), then additional components (e.g., additional layers) may be positioned between the two elements (e.g., if a layer is “on” or “above” a substrate, then additional layers may be positioned between said layer and said substrate).

[0016] The adjectives “first” and “second” can be used in this document to distinguish features specified by the same terms, such as first modification / second modification or first separation region / second separation region. The adjectives do not preclude the order in which the features were manufactured. Therefore, the first modification can be formed before or after the second modification.

[0017] Examples of this disclosure relate to a method of manufacturing a semiconductor device. The method includes processing the semiconductor body at a first surface. Processing the semiconductor body includes forming a wiring region over the first surface. The method further includes forming a field stop region in the semiconductor body. Forming the field stop region includes introducing implanted ions, including selenium, into the semiconductor body through a second surface of the semiconductor body via an ion implantation process. The second surface is opposite to the first surface. The main beam direction of the ion implantation process deviates from the host crystal direction by at most 1 degree, channeling of the implanted ions occurs along the host crystal direction, and the main beam incident angle divergence is at most ±0.5 degrees. Forming the field stop region further includes electrically activating at least a portion of the selenium by a laser annealing process.

[0018] For example, a semiconductor device can be a die within a semiconductor body. The semiconductor body can be based on various semiconductor materials, such as silicon (Si), silicon-on-insulator (SOI), silicon-sapphire (SOS), silicon-germanium, germanium, gallium arsenide, silicon carbide, gallium nitride, or other compound semiconductor materials. The semiconductor body can be based on a semiconductor substrate, such as a semiconductor wafer, and can include one or more epitaxial layers deposited thereon and / or can be back-side thinned. For example, each semiconductor device or die can be an integrated circuit or a discrete semiconductor device. An integrated circuit or discrete semiconductor device can be or can include power semiconductor devices, such as vertical power semiconductor devices with load current flowing between a first and second surface. For example, dies can be used in sensing solutions and security in automotive, industrial power control, power management, and IoT applications. A die can be or can include a power semiconductor diode, or a power semiconductor IGBT (Insulated Gate Bipolar Transistor), or a reverse-conducting (RC) IGBT, or a power semiconductor transistor such as an IGFET (Insulated Gate Field Effect Transistor, such as a metal-oxide-semiconductor field effect transistor). For example, the power semiconductor device in the die can be configured to conduct currents greater than 1A, 10A, or even 30A. The semiconductor device in the die can be further configured to block voltages between load terminals, such as the voltage between the emitter and collector of an IGBT, the voltage between the cathode and anode of a diode, or the voltage between the drain and source of a MOSFET, in the range of hundreds or up to thousands of volts, such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV, and 10kV.

[0019] Forming a wiring region may include forming one or more (e.g., two, three, four, or even more) wiring levels. Each wiring level may be formed from a single conductive layer or a stack of conductive layers, such as one or more metal layers. For example, the wiring levels may be photolithographically patterned. An interlayer dielectric structure may be formed between the stacked wiring levels. One or more contact plugs or contact lines may be formed in the openings in the interlayer dielectric structure to electrically connect portions of different wiring levels (e.g., metal lines or contact areas) to each other.

[0020] Processing the semiconductor body may further include, for example, at least one doping process for forming doped regions in the semiconductor body at a first surface prior to forming wiring regions. The at least one doping process may include an ion implantation process followed by thermal activation of the dopant, a diffusion process introducing the dopant from a dopant source (e.g., a solid or gas diffusion source) into the semiconductor body, or an in-situ doping process when a semiconductor layer is formed on a semiconductor substrate such as a wafer, for example, through a layer deposition process. Exemplary doping processes may be combined in any manner and may be repeated in any manner, for example, depending on the desired number and distribution of doped regions to be formed in the semiconductor substrate at the first surface. Exemplary doped regions are source and drain regions, or emitter and collector regions, anode and cathode regions, one or more body regions, one or more body contact regions, one or more current diffusion regions, or one or more shielding regions configured to shield the gate dielectric from high electric fields. The process may also include a trench etching process. Trench etching processes can be used to form trenches, such as gate electrode trenches, field electrode trenches, multi-electrode trenches (e.g., combining a gate electrode and a field electrode in one trench), trenches for edge-terminating structures, and contact trenches for providing electrical contact with doped regions in a semiconductor substrate. The process may also include forming one or more insulating layers, one or more conductive layers, or any combination thereof in the trench. Exemplary insulating or conductive layers particularly include gate or field electrodes formed by doped semiconductor layers (e.g., doped polysilicon or metal or metal alloys), oxide layers (e.g., silicate glass, deposited SiO2, thermal SiO2), nitride layers (e.g., Si3N4), high-k dielectric layers, low-k dielectric layers, dielectric spacers, or any combination thereof.

[0021] The field stop region has the same doping type as the drift region of the semiconductor device, such as n-type or p-type. The field stop region is disposed between the drift region and the second surface of the semiconductor body. The field stop region has a higher doping concentration than the drift region and plays a critical role in the operating properties of the semiconductor device. For example, the thickness and concentration of the field stop region affect the switching and breakdown voltage characteristics of the semiconductor device. Forming the field stop region involves channeling ion implantation containing selenium implanted ions to increase the depth of the selenium doping distribution.

[0022] The semiconductor host can have a lattice suitable for channeling ions. Typically, in some crystal orientations of a single-crystal material, open spaces extend directly into the crystal. These open spaces form channels through which ions travel with less interaction with lattice atoms compared to the outside of the channel. The channel guides the ions to some extent, where ions entering such a channel exhibit a deceleration mode different from that of ions entering the semiconductor host from the outside of the channel. The channel orientation is aligned with the host crystal orientation.

[0023] For example, the semiconductor substrate has a silicon-like (Si) diamond cubic lattice. In the case of a diamond cubic lattice, the exposed processed surfaces of the semiconductor substrate (e.g., the first surface) can coincide with the (100) crystal plane, can be tilted relative to the {100} crystal plane by up to ±2 degrees, or can be any other surface suitable for channelization. Therefore, <100> The crystal orientation (which is one of several principal crystal orientations along which channeling occurs) or any other suitable orientation that travels perpendicular to the processed surface and is referred to as the principal crystal orientation.

[0024] The examples of semiconductor device fabrication described in this paper achieve several technical benefits. For example, a deep selenium distribution can be formed for the field stop region. When adjusting the thermal budget for electroactivation of selenium, a diffusion component for extending the depth of the selenium distribution may no longer be required. This is due to the channelization implantation of selenium. Furthermore, a deep selenium doping distribution can achieve a reduction in thermal leakage current and / or an improvement in turn-off softness.

[0025] For example, a laser annealing process can include sweeping a multi-pulse laser beam along a scanning direction on a second surface of the semiconductor substrate. The pulse repetition frequency can be greater than 10 MHz. The multi-pulse laser can be further scanned along the second scanning direction. This allows the multi-pulse laser beam to be swept line by line across the second surface of the semiconductor substrate. Applying a laser annealing process can allow for deep electrical activation of the implanted dopant (e.g., selenium). For example, deep electrical activation can reach depths greater than 1 μm, or greater than 2 μm, or even greater than 5 μm from the second surface.

[0026] For example, a semiconductor device can be a power transistor or a power diode.

[0027] For example, the method may further include: after processing the semiconductor body at the first surface and before the laser annealing process, introducing boron-containing implanted ions into the semiconductor body through a second surface of the semiconductor body via an ion implantation process. The penetration depth of the boron-containing implanted ions is set to be less than the penetration depth of the selenium-containing implanted ions. For example, the ion implantation process for introducing boron-containing implanted ions into the semiconductor body may introduce the implanted ions into the semiconductor body along a direction in which channeling does not occur (i.e., along a non-channeling direction). For example, the ion implantation process for introducing boron-containing implanted ions into the semiconductor body may be a tilted ion implantation process. For example, the laser annealing process may not only electrically activate at least a portion of the selenium in the field stop region, but also electrically activate at least a portion of the boron that can serve as the collector region / back-side emitter region of the IGBT.

[0028] In other words, the laser annealing process used for at least a portion of the electroactivated selenium is also used for at least a portion of the electroactivated boron.

[0029] For example, the method may further include introducing protons into the semiconductor body via an ion implantation process through a second surface of the semiconductor body after treating the semiconductor body at the first surface and before the laser annealing process. This allows the doping concentration distribution of the field stop region to be set using hydrogen-associated donors and selenium. The laser annealing process for at least a portion of the electro-activation of selenium can also be used for at least a portion of the electro-activation of protons (hydrogen-associated donors). In some examples, for example, the protons can be electro-activated via a furnace process.

[0030] For example, the method may further include: after treating the semiconductor body at the first surface, introducing implanted ions, including phosphorus ions, into the semiconductor body through a second surface of the semiconductor body via an ion implantation process. For example, the penetration depth of the implanted ions including phosphorus may be set to be less than the penetration depth of the implanted ions including selenium.

[0031] For example, the laser annealing process used for at least a portion of electroactivated selenium can also be used for at least a portion of electroactivated phosphorus.

[0032] For example, the method may further include, after a laser annealing process for at least a portion of the electro-activated selenium, electro-activating at least a portion of the phosphorus by a second laser annealing process. For example, a combination of a laser annealing process in a sub-melting mode scheme for at least a portion of the electro-activated selenium and a laser annealing process in a molten mode scheme for at least a portion of the electro-activated phosphorus may be applied.

[0033] For example, the method may further include removing at least partially the dielectric layer from the second surface of the semiconductor body before forming the field stop region and after treating the semiconductor body at the first surface. For example, oxides may be removed before introducing implanted ions, including selenium, into the semiconductor body through the second surface of the semiconductor body via an ion implantation process. Oxides may be removed using hydrofluoric acid, HF acid, and / or HF gas. This may allow for increased penetration depth of implanted ions, including selenium, into the semiconductor body.

[0034] For example, the laser annealing process for electroactivated selenium can be a non-melting laser annealing process.

[0035] For example, the method may further include forming an ion implantation mask with mask openings for introducing implanted ions, including selenium, into the semiconductor body through the mask openings.

[0036] For example, the semiconductor body can be a wafer comprising multiple dies, and the multi-pulse laser beam used for at least a portion of the laser annealing process for electrically activating selenium can be applied only to a portion of the surface region of each of the multiple dies. This allows the electrical characteristics to be tuned depending on the lateral position within the die or semiconductor device. For example, this allows the electrical characteristics in the active region of the semiconductor device to be set differently from those at or around the edge of the chip or die.

[0037] For example, the method may further include electrically activating at least a portion of selenium in another portion of a surface region of each of a plurality of dies by an additional or second laser annealing process. This can allow for selenium doping distributions of varying depths, such as those aligned with the structure at a first surface of the die or semiconductor body.

[0038] For example, an ion implantation process for introducing selenium-containing implanted ions into a semiconductor host can include ion implantation energies in the range of 50 keV to 500 keV. The ion implantation process for introducing selenium-containing implanted ions into a semiconductor host can further include energies in the range of 1 x 10⁻⁶ keV. 12 cm -2 Up to 1x10 14 cm -2 Ion implantation dose within the range.

[0039] For example, the multi-pulse laser beam used in the laser annealing process for electrically activated selenium can have a wavelength of 100 μm. 2 Up to 0.1mm 2 The size of the bundle within the range.

[0040] For example, the sweeping speed of a multi-pulse laser beam along the scanning direction on the second surface of a semiconductor substrate can be in the range of 10 m / s to 100 m / s.

[0041] For example, the pulse length of a multi-pulse laser beam can range from 0.5 ns to 10 ns. For example, the multi-pulse laser beam parameters described herein can contribute to the deep electrical activation of selenium introduced by channelized ion implantation.

[0042] For example, sweeping of a multi-pulse laser beam along the scanning direction can be performed line by line, where adjacent lines are offset from each other along a direction perpendicular to the scanning direction by a size smaller than the beam size of the multi-pulse laser beam along the direction perpendicular to the scanning direction. This allows for uniform electroactivation of selenium along the direction perpendicular to the scanning direction.

[0043] For example, sweeping of a multi-pulse laser beam along the scanning direction can be performed line by line, where adjacent lines are offset from each other in a direction perpendicular to the scanning direction by a size greater than the beam size of the multi-pulse laser beam in the direction perpendicular to the scanning direction. This allows for variation in the electrical activation level of selenium in the direction perpendicular to the scanning direction. For example, alternating low / high doped regions can be formed, thereby tuning the back-side or rear-side emitter efficiency of the IGBT.

[0044] For example, the process of implanting dopant ions, including selenium, and activating them via laser annealing can be carried out using a wafer with or without a carrier attached to the wafer. For example, a carrier can be used in the case of thin wafers or back-side thinning wafers.

[0045] It should be noted that the specification and accompanying drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements, although not explicitly described or shown herein, which embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiments outlined in this document are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements and specific examples of the principles, aspects, and embodiments of the invention provided herein are intended to cover their equivalents.

[0046] The specification and accompanying drawings merely illustrate the principles of this disclosure. Furthermore, all examples listed herein are primarily and explicitly intended for illustrative purposes only to aid the reader in understanding the principles of this disclosure and the concepts contributed by the inventor(s) to advance the art. All statements herein listing the principles, aspects, and examples of this disclosure, as well as specific examples thereof, are intended to cover their equivalents.

[0047] Figures 1A to 1C This is a schematic cross-sectional view illustrating exemplary process features of a method for manufacturing a semiconductor device.

[0048] refer to Figure 1A A schematic cross-sectional view shows the semiconductor body 102 being processed at a first surface 1021. Processing the semiconductor body 102 includes forming semiconductor device elements in a portion 1025 of the semiconductor body 102 adjacent to the first surface 102. Processing the semiconductor body 102 further includes forming a wiring region 104 on the first surface 1021.

[0049] refer to Figure 1B A schematic cross-sectional view, in the implementation Figure 1AFollowing the process characteristics illustrated in the figure, a field stop region 106 is formed in the semiconductor body. Forming the field stop region 106 involves introducing implanted ions, including selenium, into the semiconductor body 102 through an ion implantation process I2Se passing through a second surface 1022 of the semiconductor body 102. The second surface 1022 is opposite to the first surface 1021. The main beam direction of the ion implantation process I2Se deviates from the host crystal direction by at most 1 degree, channeling of the implanted ions occurs along the host crystal direction, and the main beam incident angle divergence is at most ±0.5 degrees.

[0050] refer to Figure 1C A schematic cross-sectional view, showing that at least part of the selenium is electrically activated via a laser annealing process (LA).

[0051] It should be understood that the disclosure of multiple actions, processes, operations, steps, or functions in the specification or claims is not to be construed as being in a particular order, unless otherwise expressly or implicitly stated, for example by expressions such as "hereafter," for technical reasons. Therefore, the disclosure of multiple actions or functions will not limit them to a particular order unless such actions or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may include or be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations, or sub-steps. Unless expressly excluded, such sub-actions may be included and such sub-actions are part of the disclosure of the single action.

[0052] refer to Figure 2 A schematic cross-sectional view, after the semiconductor body 102 has been processed at the first surface 1021 and before the laser annealing process LA, i.e. Figure 1A The process features illustrated in the figure are then followed by... Figure 1C Prior to the process features illustrated herein, boron-containing implanted ions are introduced into the semiconductor body 102 via ion implantation process I2B through the second surface 1022 of the semiconductor body 102. (Reference) Figure 1C The laser annealing process (LA) described can be used simultaneously for at least a portion of the electro-activated boron.

[0053] refer to Figure 3 A schematic cross-sectional view, after the semiconductor body 102 has been processed at the first surface 1021 and before the laser annealing process LA, i.e. Figure 1A The process features illustrated in the figure are then followed by... Figure 1C Prior to the process features illustrated herein, phosphorus-containing implanted ions are introduced into the semiconductor body 102 via an ion implantation process (I2P) through the second surface 1022 of the semiconductor body 102. (Reference) Figure 1C The laser annealing process described can be used simultaneously for at least a portion of the electro-activated phosphorus.

[0054] refer to Figure 4 A schematic cross-sectional view, after the semiconductor body 102 has been processed at the first surface 1021 and before the laser annealing process LA, i.e. Figure 1A The process features illustrated in the figure are then followed by... Figure 1C Prior to the process features illustrated herein, proton-containing implanted ions are introduced into the semiconductor body 102 via an ion implantation process, where I₂H⁺ ions penetrate the second surface 1022 of the semiconductor body 102. (Reference) Figure 1C The laser annealing process described can be used simultaneously to electrically activate at least a portion of protons that are hydrogen-related donors.

[0055] like Figure 5 As illustrated in the schematic cross-sectional view, a second laser annealing process LA2 and / or a third laser annealing process LA3 are applied to the second surface 1022. For example, the second laser annealing process LA2 can be performed in... Figure 1C The laser annealing process illustrated in the figure is applied after LA, for example, in the absence of boron and / or phosphorus and / or proton implantation. Figure 1A and Figure 1C In the case of the process features illustrated in the figure, but in Figure 1C Following the process characteristics illustrated in the figure, in this case, the second laser annealing process LA2 at least partially electrically activates boron and / or phosphorus and / or protons as hydrogen-related donors. Similarly, the second laser annealing process LA2 can be performed... Figure 1A The process features illustrated in the figure are then followed by... Figure 1B The process features illustrated in the diagram are applied prior to, for example, in, as shown in Figure 1B The process features illustrated herein are prior to the implantation of boron and / or phosphorus and / or protons. In this case, prior to the channelization implantation of selenium, the second laser annealing process LA2 at least partially electrically activates boron and / or phosphorus and / or protons as hydrogen-related donors. For example, the third layer annealing process LA3 can be applied to the surface area of ​​the second surface 1022 other than the surface area to which the laser annealing process LA has already been applied.

[0056] Figure 6 The schematic top view illustrates an example of applying a multi-pulse laser beam of the laser annealing process LA to electrically activate at least a portion of selenium to only a portion 1025 of the surface region of each of a plurality of dies or semiconductor devices 100. Figure 6The pattern illustrated can be formed by sweeping a multi-pulse laser beam line by line along the scanning direction x1, and i) interrupting the sweeping of the multi-pulse laser beam along the scanning direction x1, and ii) introducing an offset between adjacent lines along a direction x2 perpendicular to the scanning direction x1, the offset being greater than the beam size of the multi-pulse laser beam along direction x2. For example, a third laser annealing process LA3 can be applied to a portion of the surface region outside part 1025. The pattern of at least a portion of the pattern for applying the multi-pulse laser beam of the laser annealing process LA to electro-activate selenium can be deviated from... Figure 6 Examples of patterns, which can be adapted as desired.

[0057] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternatives and / or equivalent embodiments can be used instead of the illustrated and described embodiments without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device (100), the method comprising: The semiconductor body (102) is processed at a first surface (1021) of the semiconductor body (102), wherein processing the semiconductor body (102) includes forming a wiring region (104) on the first surface (1021); and thereafter A field stop region (106) is formed in the semiconductor body (102), wherein the formation of the field stop region (106) includes: Selenium-containing implanted ions are introduced into the semiconductor body (102) through a second surface (1022) of the semiconductor body (102) via an ion implantation process (I2Se), the second surface (1022) being opposite to the first surface (1021), wherein the main beam direction of the ion implantation process (I2Se) deviates from the main crystal direction by at most 1 degree, channelization of the implanted ions occurs along the main crystal direction, and the main beam incident angle divergence is at most ±0.5 degrees; and At least a portion of the selenium is electrically activated by a laser annealing (LA) process.

2. The method according to the preceding claim, wherein the laser annealing process (LA) includes sweeping a multi-pulse laser beam along a scanning direction (x1) on a second surface (1022) of the semiconductor body (102), and the pulse repetition frequency is greater than 10 MHz.

3. The method according to any one of the preceding claims, wherein the semiconductor device (100) is a power transistor or a power diode.

4. The method according to any one of the preceding claims further includes, after processing the semiconductor body (102) at the first surface (1021) and before the laser annealing process (LA), introducing boron-containing implanted ions into the semiconductor body (102) through the second surface (1022) of the semiconductor body (102) by an ion implantation process (I2B), wherein the penetration depth of the boron-containing implanted ions is set to be less than the penetration depth of the selenium-containing implanted ions.

5. The method according to the preceding claim, wherein the laser annealing process (LA) for at least a portion of the electroactivated selenium is also used for at least a portion of the electroactivated boron.

6. The method according to the preceding claim further includes, after treating the semiconductor body (102) at the first surface (1021) and before the laser annealing process (LA), introducing protons into the semiconductor body (102) through the second surface (1022) of the semiconductor body (102) by an ion implantation process (I2H+).

7. The method according to the preceding claim further includes, after treating the semiconductor body (102) at the first surface (1021), introducing implanted ions, including phosphorus ions, into the semiconductor body (102) through the second surface (1022) of the semiconductor body (102) via an ion implantation process (I2P).

8. The method according to the preceding claim, wherein the laser annealing process (LA) for electroactivating selenium is also used for at least a portion of electroactivating phosphorus.

9. The method of claim 7, further comprising, after a laser annealing process (LA) for electroactivating at least a portion of selenium, electroactivating at least a portion of phosphorus by a second laser annealing process (LA2).

10. The method according to any one of the preceding claims further includes, before forming the field stop region (106) and after processing the semiconductor body at the first surface, removing at least partially the dielectric layer from the second surface (1022) of the semiconductor body (102).

11. The method according to any one of the preceding claims, wherein at least a portion of the laser annealing process (LA) for electro-activating selenium is a non-melting laser annealing process.

12. The method according to any one of the preceding claims further includes forming an ion implantation mask having a mask opening for introducing implanted ions, including selenium, into the semiconductor body (102) through the mask opening.

13. The method according to any one of the preceding claims, wherein the semiconductor body (102) is a wafer comprising a plurality of dies, and a multi-pulse laser beam for at least a portion of the laser annealing process (LA) for electrically activating selenium is applied to only a portion (1025) of the surface region of each of the plurality of dies.

14. The method according to the preceding claim, further comprising: At least a portion of the selenium in another part of the surface region of each of the plurality of dies is electrically activated by a third laser annealing process (LA3).

15. The method according to any one of the preceding claims, wherein the ion implantation process (I₂Se) for introducing implanted ions comprising selenium into the semiconductor body (102) includes ion implantation energies in the range of 50 keV to 500 keV and in the range of 1 x 10⁻⁶ keV. 12 cm -2 Up to 1x10 14 cm -2 Ion implantation dose within the range.

16. The method according to any one of the preceding claims, wherein the multi-pulse laser beam for the laser annealing process (LA) of electrically activated selenium has a wavelength ranging from 100 μm. 2 Up to 0.1mm 2 The size of the bundle within the range.

17. The method according to any one of the preceding claims, wherein the sweeping speed of the multi-pulse laser beam along the scanning direction (x1) on the second surface (1022) of the semiconductor body (102) is in the range of 10 m / s to 100 m / s.

18. The method according to any one of the preceding claims, wherein the pulse length of the pulses of the multi-pulse laser beam is in the range of 0.5 ns to 10 ns.

19. The method according to any one of the preceding claims, wherein the multi-pulse laser beam is swept line by line along the scanning direction (x1), wherein adjacent lines are offset from each other along a direction (x2) perpendicular to the scanning direction (x1) by a size smaller than the beam size of the multi-pulse laser beam along the direction (x2) perpendicular to the scanning direction (x1).

20. The method according to any one of claims 1 to 18, wherein the multi-pulse laser beam is swept line by line along the scanning direction (x1), wherein adjacent lines are offset from each other along a direction (x2) perpendicular to the scanning direction (x1) by a size greater than the beam size of the multi-pulse laser beam along the direction perpendicular to the scanning direction (x1).

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