Preparation method of semiconductor device
By nitriding and metal doping the third gate oxide layer in the first region during the fabrication of semiconductor devices, the problem of threshold voltage performance differences in the I/O device region was solved, and the consistency of device voltage was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-27
AI Technical Summary
The threshold voltage performance of the La-doped stacked gate structure in the IO device region is poor. How to adjust the dipole difference between different device regions on the substrate has become an urgent technical problem to be solved.
In the fabrication process of semiconductor devices, the third gate oxide layer of the first region is nitrided to form a nitrided layer, and the second gate oxide layer and the nitrided layer are metal-doped to adjust oxygen vacancies in order to control the drift of the threshold voltage.
By adjusting oxygen vacancies, the threshold voltage difference between the I/O device and the core device regions was improved, thereby enhancing the consistency of the device's voltage performance.
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Figure CN121751736A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor device. BACKGROUND
[0002] With the continuous reduction of the size of semiconductor devices, the thickness of the gate dielectric layer is reduced to below 2nm, in order to improve the gate leakage current, the prior art generally uses high-K dielectric material as the gate oxide layer.
[0003] The high-K of high-K dielectric material is due to the internal dipole structure, which can control the induced oxygen vacancies in the gate stack structure by forming a layer structure that induces a dipole effect, such as in the NMOS gate process, introducing a cover layer La2O3 to increase the number of oxygen vacancies in the high-K dielectric material, thereby causing the threshold voltage of the device to drift. Due to the difference in the number of dipoles between IO devices and core devices, the threshold voltage of the La-doped stacked gate structure in the IO device region often performs poorly, and how to adjust the dipole difference between different device regions on the substrate has become a technical problem to be solved at present.
[0004] It should be noted that the information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY
[0005] The purpose of the present application is to provide a preparation method of semiconductor device to solve the problem of poor threshold voltage performance of IO device.
[0006] To solve the above technical problems, the present application provides a preparation method of semiconductor device, comprising:
[0007] providing a substrate, the substrate comprising a first region and a second region;
[0008] forming a first gate oxide layer, a second gate oxide layer and a third gate oxide layer in sequence on the first region and the second region;
[0009] nitriding the third gate oxide layer in the first region to form a nitride layer;
[0010] metal-doping the second gate oxide layer and the nitride layer;
[0011] forming a gate electrode layer on the second gate oxide layer and the nitride layer.
[0012] Optionally, the thickness of the first gate oxide layer in the first region is less than that in the second region.
[0013] Optionally, the nitriding the third gate oxide layer in the first region comprises:
[0014] forming a mask layer and etching an opening on the first region;
[0015] nitriding the third gate oxide layer exposed through the opening to form the nitride layer;
[0016] removing the remaining mask layer to expose the remaining third gate oxide layer which is not nitrided.
[0017] Optionally, the metal doping the second gate oxide layer and the nitride layer comprises:
[0018] depositing a capping layer on the nitride layer and the third gate oxide layer which is not nitrided, and doping elements in the capping layer into the nitride layer, the third gate oxide layer which is not nitrided and the second gate oxide layer.
[0019] Optionally, the nitriding the third gate oxide layer in the first region comprises:
[0020] nitriding the third gate oxide layer to form a nitride layer;
[0021] removing at least the nitride layer on the second region.
[0022] Optionally, the metal doping the second gate oxide layer and the nitride layer comprises:
[0023] depositing a capping layer on the nitride layer and the second gate oxide layer, and doping elements in the capping layer into the nitride layer and the second gate oxide layer.
[0024] Optionally, the forming the gate electrode layer comprises sequentially depositing a metal base layer, a gate material layer and a capping layer.
[0025] Optionally, after the forming the gate electrode layer, etching is performed to form a first gate structure and a second gate structure in the first region and the second region respectively.
[0026] Optionally, the third gate oxide layer is made of TiO2.
[0027] Optionally, the second gate oxide layer and the nitride layer are doped with La.
[0028] In the method for manufacturing a semiconductor device, a substrate is provided, the substrate comprising a first region and a second region; a first gate oxide layer, a second gate oxide layer and a third gate oxide layer are sequentially formed on the first region and the second region; the third gate oxide layer in the first region is subjected to a nitridation treatment to form a nitrided layer; the second gate oxide layer and the nitrided layer are subjected to a metal doping treatment; and a gate electrode layer is formed on the second gate oxide layer and the nitrided layer. The third gate oxide layer in the first region is subjected to the nitridation treatment before the metal doping treatment, so as to adjust the oxygen vacancies in different regions on the substrate to make the threshold voltage drift in a proper direction. BRIEF DESCRIPTION OF DRAWINGS
[0029] Those skilled in the art will understand that the drawings provided herein are for illustrative purposes and constitute any limitation to the scope of the present application. Among them:
[0030] Figure 1 is a flow chart of an embodiment of the present application for forming a semiconductor device;
[0031] Figure 2 is a structural schematic diagram of an embodiment of the present application after forming a third gate oxide layer;
[0032] Figure 3 is a structural schematic diagram of an embodiment of the present application after forming a mask layer;
[0033] Figure 4 is a structural schematic diagram of an embodiment of the present application for performing a nitridation treatment on a third gate oxide layer;
[0034] Figure 5 is a structural schematic diagram of an embodiment of the present application after forming a cover layer;
[0035] Figure 6 is a structural schematic diagram of an embodiment of the present application after forming a gate electrode layer and etching;
[0036] Figure 7 is a structural schematic diagram of another embodiment of the present application for performing a nitridation treatment on a third gate oxide layer;
[0037] Figure 8 is a structural schematic diagram of another embodiment of the present application after removing the third gate oxide layer after nitridation above the second region;
[0038] Figure 9 is a structural schematic diagram of another embodiment of the present application after forming a cover layer;
[0039] Figure 10 is a structural schematic diagram of another embodiment of the present application after forming a gate electrode layer and etching.
[0040] In the drawings:
[0041] 100, substrate; 101, first region; 102, second region; 103, isolation structure; 200, first gate oxide layer; 300, second gate oxide layer; 400, third gate oxide layer; 500, mask layer; 600, cover layer; 700, nitride layer; 800, gate electrode layer; 801, metal base layer; 802, gate material layer; 803, capping layer. DETAILED DESCRIPTION
[0042] For the purposes of the present application, the objectives, advantages and features thereof are more clearly understood from the following detailed description together with the appended claims and drawings. It is to be understood that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the application, for which reference should be made only to the appended claims. Furthermore, the language used in the specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the application.
[0043] The application is described more fully hereinafter with reference to the accompanying drawings, in which specific embodiments of the application are shown. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on" another element or substrate, it can be directly on the element or substrate or intervening layers can also be present. Such a construction is referred to herein as a "sandwich." Herein, "directly on" means that the first element, which is on the second element, can be in contact with the second element or there can be one or more intermediate elements between the first element and the second element. There can be intermediate elements between the first element and the second element; however, there can also be no intermediate elements between the first element and the second element. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms since such elements are commonly known to have temporal meanings as well. The above-described elements can be replaced by other elements that have similar function.
[0044] In the embodiments of the present application, the terms "first", "second" and the like are used to distinguish between similar objects, but are not necessarily used to describe a particular sequential or chronological order. It should be noted that the technical solutions recorded in the embodiments of the present application can be combined arbitrarily without conflict.
[0045] In particular, reference is made to Figure 1 , Figure 1 A flowchart of a method for manufacturing a semiconductor device is provided. At least the following steps are included:
[0046] Step S01: providing a substrate 100, the substrate 100 comprising a first region 101 and a second region 102;
[0047] Step S02: sequentially forming a first gate oxide layer 200, a second gate oxide layer 300 and a third gate oxide layer 400 on the first region 101 and the second region 102;
[0048] Step S03: Nitride the third gate oxide layer 400 in the first region 101 to form a nitrided layer 700;
[0049] Step S04: Perform metal doping on the second gate oxide layer 300 and the nitride layer 700;
[0050] Step S05: A gate electrode layer 800 is formed on the second gate oxide layer 300 and the nitride layer 700.
[0051] In order to enable those skilled in the art to easily understand the semiconductor device fabrication method in the embodiments of the present invention, the following will further explain the semiconductor device fabrication method proposed in the present invention with reference to the various structural schematic diagrams in the fabrication process.
[0052] Figures 2 to 6 This is a schematic diagram of the structure of the semiconductor device fabrication method provided in one embodiment of the present invention during the fabrication process.
[0053] like Figure 2 As shown, steps S01 and S02 are performed to provide a substrate 100, which serves as the basis for setting the semiconductor structure in this embodiment of the invention, and the substrate 100 is divided into a first region 101 and a second region 102. In one embodiment, the substrate referred to herein may include any type of substrate, typically a semiconductor substrate, such as a bulk single-crystal silicon wafer, a binary compound substrate (e.g., a GaAs silicon wafer), a ternary compound substrate (e.g., an AlGaAs wafer), or a higher-order compound silicon wafer, on which additional insulating or conductive layers may or may not be formed. When a semiconductor substrate is used, it may also include non-semiconductor materials, such as oxides in a half-silicon insulator (SOI), a partially SOI substrate, polycrystalline silicon, insulators, oxides, metals, amorphous silicon, or organic materials. In some embodiments, the substrate 100 may also include multiple wafers or dies stacked together or otherwise bonded together. The first region 101 and the second region 102 are both located in the peripheral region of the semiconductor structure, for example. The first region 101 is, for example, the core device region, and the second region 102 is, for example, the I / O device region. The substrate 100 of the first region 101 and the second region 102 is also provided with a plurality of isolation structures 103. The active area (AA, not shown) is defined by the isolation structure 103. The isolation structure 103 is a shallow trench isolation structure (STI). The isolation structure 103 may include a single layer or multiple layers of dielectric material, for example, silicon oxide or silicon nitride.
[0054] In step S02, a first gate oxide layer 200, a second gate oxide layer 300, and a third gate oxide layer 400 are sequentially formed on the first region 101 and the second region 102. In one embodiment, the thickness of the first gate oxide layer 200 in the first region 101 is less than its thickness in the second region 102. Using a deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), or any combination thereof, a first gate oxide layer 200 of different thicknesses, comprising silicon oxide, is prepared in the first region 101 and the second region 102. Then, the second gate oxide layer 300 and the third gate oxide layer 400 are deposited and covered on the first gate oxide layer 200.
[0055] As an optional embodiment, the second gate oxide layer 300 is a high-k dielectric material, such as hafnium silicate (e.g., Hf). x Si 1-x O y ) or hafnium oxynitrides (such as Hf) x Si 1-x O y N z Other zirconium silicates, aluminosilicates, and lanthanum silicates may be used, but other silicates of zirconium, aluminum, lanthanum, strontium, tantalum, and titanium, and combinations thereof, including but not limited to HfSiO, may also be used. x ZrSiO x LaSiO x YSiO x ScSiO x CeSiO x and HfLaSiO x Furthermore, multimetal oxides (such as barium strontium titanate BST) can also provide high dielectric constant properties. The third gate oxide layer 400 is a metal oxide material and may contain elements selected from the group consisting of: Ti (titanium), Ta (tantalum), La (lanthanum), Ir (iridium), Mo (molybdenum), Ru (ruthenium), W (tungsten), Os (osmium), Nb (niobium), V (vanadium), Ni (nickel), and Re (rhenium), forming an oxygen-containing metal substrate (such as TiO2). For example, the first gate oxide layer 200 is made of silicon oxide, the second gate oxide layer 300 is made of HfSiO4, and the third gate oxide layer 400 is deposited using an atomic layer deposition process. The thickness of the third gate oxide layer 400 is 5 Å, and the material is TiO2.
[0056] In step S03, the nitriding treatment of the third gate oxide layer 400 in the first region 101 includes:
[0057] A mask layer 500 is formed, and an opening is etched in the first region 101;
[0058] The third gate oxide layer 400 exposed through the opening is subjected to nitriding treatment to form a nitrided layer 700;
[0059] Remove the remaining mask layer 500 to expose the remaining unnitrided third gate oxide layer 400.
[0060] Please refer to Figure 3 A mask layer 500 is deposited on the third gate oxide layer 400. Photoresist is then coated onto the mask layer 500 using a coating process. Photolithography is performed to etch an opening located in the first region 101 onto the mask layer 500. The opening range is not less than the range of the formed first gate structure. Please refer to [reference needed]. Figure 4 Nitriding treatment is performed on the exposed portion of the third gate oxide layer 400 through the opening. For example, NH3 gas is used to nitride the third gate oxide layer 400, and N is doped into the TiO2 material third gate oxide layer 400 to form TiON. The void defects are adjusted. After nitriding, the residual mask layer 500 is removed to provide conditions for subsequent processes. The material of the mask layer 500 is silicon nitride, but it is not limited to this.
[0061] In step S04, metal doping of the second gate oxide layer 300 and the nitride layer 700 includes:
[0062] A capping layer 600 is deposited on the nitrided layer 400 and the unnitrided third gate oxide layer 400, and elements in the capping layer 600 are doped into the nitrided layer 700, the unnitrided third gate oxide layer 400 and the second gate oxide layer 300.
[0063] Please refer to Figure 5 A capping layer 600 is deposited on the nitrided layer 700 and the unnitrided third gate oxide layer 400. The capping layer 600 is made of La2O3 and La. y Hf z O x La y Hf z SiO x Y2O3 and La y Y z Hf w SiO x or other materials containing La At least one of the following is used. Next, a high-temperature heat treatment is performed to dope the metal in the capping layer 600 into the second gate oxide layer 300 and the third gate oxide layer 400. More preferably, the capping layer 600 is made of La2O3. The second gate oxide layer 300 and the third gate oxide layer 400 are La-doped. By nitriding the third gate oxide layer 400, which acts as a diffusion barrier for lanthanum dioxide, the threshold voltage Vt of the IO device region / core device region is adjusted, and the threshold voltage Vt conversion characteristics are improved by reducing HfSiON oxygen vacancies through TiO2 / TiON.
[0064] Next, step S05 is performed, where a gate electrode layer 800 is formed on the second gate oxide layer 300 and the nitride layer 700. Forming the gate electrode layer 800 on the second gate oxide layer 300 and the nitride layer 700 includes: sequentially depositing a metal substrate layer 801, a gate material layer 802, and a sealing layer 803. After forming the gate electrode layer 800, etching is performed to form a first gate structure and a second gate structure in the first region 101 and the second region 102, respectively. The metal substrate layer 801 may include, but is not limited to, TiN (titanium nitride), Ru (ruthenium), TaN (tantalum nitride), TaC (tantalum carbide), TiC (titanium carbide), TiON (titanium oxynitride), Re (rhenium), and W (tungsten). The gate material layer 802 may include, but is not limited to, polysilicon. The sealing layer 803 may include, but is not limited to, Ti and TiN.
[0065] After forming the gate electrode layer 800, the stacked film layers are etched using an etching process such as at least one of dry etching or wet etching to form the first gate structure and the second gate structure on the first region 101 and the second region 102, respectively. It should be understood that only the third gate oxide layer 400 in the first region 101 is nitrided, while a portion of the unnitrided third gate oxide layer 700 is retained in the second region 102. Please refer to [reference needed]. Figure 5 The first gate structure includes a stacked first gate oxide layer 200, a second gate oxide layer 300, a third gate oxide layer 400, and a gate electrode layer 800, wherein the third gate oxide layer 400 is nitrided to form a nitrided layer 700; the second gate structure includes a first gate oxide layer 200, a second gate oxide layer 300, the remaining unnitrided third gate oxide layer 400, and a gate electrode layer 800.
[0066] Figures 7 to 10 This is a schematic diagram of the structure of the semiconductor device fabrication method provided in another embodiment of the present invention during the fabrication process.
[0067] like Figure 2As shown, steps S01 and S02 are performed to provide a substrate 100, which is then divided into a first region 101 and a second region 102. The first region 101 is, for example, a core device region, and the second region 102 is, for example, an I / O device region. A first gate oxide layer 200, a second gate oxide layer 300, and a third gate oxide layer 400 are sequentially formed on the first region 101 and the second region 102. The thickness of the first gate oxide layer 200 in the first region 101 is less than its thickness in the second region 102. The structure of the semiconductor device in this embodiment is largely the same as the manufacturing method of the semiconductor device in the previous embodiments; other similarities will not be repeated here.
[0068] In step S03, the nitriding treatment of the third gate oxide layer 400 in the first region 101 includes:
[0069] The third gate oxide layer 400 is nitrided to form a nitrided layer 700;
[0070] At least the nitrided layer 700 on the second region 102 is removed.
[0071] Please refer to Figure 7 The third gate oxide layer 400 on the first region 101 and the second region 102 is nitrided, for example, by using NH3 gas to nitrid the third gate oxide layer 400, doping N into the TiO2 material of the third gate oxide layer 400 to form a nitrided layer 700, preferably TiON. Subsequently, photoresist is formed on the first region 101 and the second region 102, and the photoresist is patterned to form a photoresist pattern covering the first region 101. Then, all nitrided layers 700 outside the area covered by the photoresist pattern are removed, exposing the second gate oxide layer 300 in other areas. Void defects are adjusted, retaining only the structure of the nitrided layer 700 above the first region 101. Figure 8 As shown. It should be understood that, for example, the nitride layer 700 on the isolation structure 103 can be removed together with the nitride layer 700 on the second region 102, or it can be removed separately or together with other processes.
[0072] Please refer to Figure 9 In step S04, metal doping of the second gate oxide layer 300 and the nitride layer 700 includes:
[0073] A capping layer 600 is deposited on the nitride layer 700 and the second gate oxide layer 300, and elements in the capping layer 600 are doped into the nitride layer 700 and the second gate oxide layer 300.
[0074] A capping layer 600 is deposited on the nitride layer 700 and the second gate oxide layer 300, and then subjected to high-temperature heat treatment to dope the metal in the capping layer 600 into the second gate oxide layer 300 and the nitride layer 700. More preferably, the capping layer 600 is made of La2O3. The second gate oxide layer 300 and the nitride layer 700 in the first region 101 are La-doped, and the second gate oxide layer 300 in the second region 102 is also La-doped.
[0075] Next, step S05 is performed to form the gate electrode layer 800. Forming the gate electrode layer 800 on the second gate oxide layer 300 and the nitride layer 700 includes sequentially depositing a metal substrate layer 801, a gate material layer 802, and a capping layer 803. After forming the gate electrode layer 800, etching is performed to form a first gate structure and a second gate structure in the first region 101 and the second region 102, respectively. Please refer to... Figure 10 The first gate structure contains a stacked first gate oxide layer 200, a second gate oxide layer 300, a nitride layer 700 and a gate electrode layer 800, wherein the nitride layer 700 is prepared by nitriding the third gate oxide layer 400; the second gate structure includes only the first gate oxide layer 200, the second gate oxide layer 300 and the gate electrode layer 800.
[0076] In summary, the semiconductor fabrication method provided by this invention includes a substrate comprising a first region and a second region; a first gate oxide layer, a second gate oxide layer, and a third gate oxide layer are sequentially formed on the first region and the second region; the third gate oxide layer in the first region is nitrided to form a nitrided layer; the second gate oxide layer and the nitrided layer are metal-doped; and a gate electrode layer is formed on the second gate oxide layer and the nitrided layer. Before metal doping, the third gate oxide layer in the first region is nitrided to adjust the oxygen vacancies in different regions of the substrate so that the threshold voltage drifts in a suitable direction.
[0077] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.
[0078] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first gate oxide layer, a second gate oxide layer, and a third gate oxide layer are sequentially formed on the first region and the second region; The third gate oxide layer in the first region is nitrided to form a nitrided layer; The second gate oxide layer and the nitride layer are metal-doped; A gate electrode layer is formed on the second gate oxide layer and the nitride layer.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the first gate oxide layer in the first region is less than its thickness in the second region.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The nitriding treatment of the third gate oxide layer in the first region includes: A mask layer is formed, and an opening is etched into the first region; The third gate oxide layer exposed through the opening is nitrided to form the nitrided layer. Remove the remaining mask layer to expose the remaining unnitrided third gate oxide layer.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, Metal doping of the second gate oxide layer and the nitride layer includes: A capping layer is deposited on the nitrided layer and the unnitrided third gate oxide layer, and elements in the capping layer are doped into the nitrided layer, the unnitrided third gate oxide layer and the second gate oxide layer.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The nitriding treatment of the third gate oxide layer in the first region includes: The third gate oxide layer is nitrided to form a nitrided layer; At least the nitrided layer on the second region shall be removed.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, Metal doping of the second gate oxide layer and the nitride layer includes: A capping layer is deposited on the nitride layer and the second gate oxide layer, and elements in the capping layer are doped into the nitride layer and the second gate oxide layer.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, Forming the gate electrode layer involves sequentially depositing a metal substrate layer, a gate material layer, and a capping layer.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After the gate electrode layer is formed, etching is performed to form a first gate structure and a second gate structure in the first region and the second region, respectively.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the third gate oxide layer includes TiO2.
10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second gate oxide layer and the nitride layer are La-doped.