Manufacturing method of semiconductor structure
By controlling the removal of the capping layer and the epitaxial process during MCFET manufacturing, the source/drain defect problem was solved, improving the DC and high-frequency performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2026-03-27
AI Technical Summary
In the manufacturing process of multichannel field-effect transistors (MCFETs), semiconductor materials cannot be epitaxially grown on the surface of the inner spacer layer, resulting in a large number of defects in the source/drain regions, which affects the DC performance of the device.
By forming a capping layer in the opening, controlling the removal and epitaxial processes, the remaining part of the capping layer is gradually removed, and semiconductor materials are epitaxially grown in the opening, thus avoiding the formation of defects in the source/drain regions.
This reduces defects in the source/drain regions, improves the DC performance of the semiconductor structure, and maintains high-frequency performance.
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Figure CN121751737A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for manufacturing a semiconductor structure. Background Technology
[0002] Against the backdrop of integrated circuit miniaturization, the gate control capability of three-gate 3D transistors decreases as device size shrinks.
[0003] In pursuit of higher device performance, related technologies have begun to adopt multi-channel field-effect transistors (MCFETs) with a four-gate structure that have stronger gate control capabilities for the same size. Summary of the Invention
[0004] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising: providing a substrate structure including two adjacent fin portions on a substrate, each fin portion including a stack of alternating first semiconductor layers and second semiconductor layers, the first semiconductor layers having spacer layers at both ends, and an opening between the two fin portions; forming a capping layer in the opening, the capping layer including a first portion covering the bottom of the opening and a second portion covering the sidewalls of the opening; performing a removal process to remove the first portion and a portion of the second portion, wherein the remaining portion of the second portion covers at least a portion of the sidewalls of a portion of the second semiconductor layers in the stack; after the removal process, performing an epitaxial process to epitaxially grow a first semiconductor material at the bottom of the opening; and after the epitaxial process, removing the remaining portion of the second portion and epitaxially growing a second semiconductor material in the opening.
[0005] According to some embodiments of this disclosure, after the removal process, the remaining portion of the second part covers at least a portion of the sidewall of the uppermost second semiconductor layer in the stack.
[0006] According to some embodiments of this disclosure, after the removal process, the remaining portion of the second part covers the sidewall of the uppermost second semiconductor layer in the stack, and also covers at least a portion of the sidewalls of one or more second semiconductor layers other than the uppermost second semiconductor layer.
[0007] According to some embodiments of this disclosure, after the removal process, the remaining portion of the second part covers the sidewalls of all the second semiconductor layers in the stack.
[0008] According to some embodiments of this disclosure, removing the remaining portion of the second portion and epitaxially growing a second semiconductor material in the opening includes multiple repeated processes, each repeated process including: removing a portion of the remaining portion of the second portion such that the bottom of the remaining portion of the second portion moves upward; and epitaxially growing the second semiconductor material in the opening.
[0009] According to some embodiments of this disclosure, the process of removing the remaining portion of the second part and the process of epitaxially growing the second semiconductor material in the opening are performed simultaneously.
[0010] According to some embodiments of this disclosure, in the covering layer formed in the opening, the thickness of the second portion gradually decreases from top to bottom, and the thickness of the first portion is less than or equal to the thickness of the second portion.
[0011] According to some embodiments of this disclosure, during the epitaxial growth of the second semiconductor material in the opening, the rate at which the second semiconductor material is epitaxially grown at the bottom of the opening is controlled to be greater than the rate at which it is epitaxially grown on the sidewall of the opening; and / or during the removal of the remaining portion of the second part, the rate at which the relatively lower portion of the remaining portion of the second part is removed is controlled to be greater than the rate at which the relatively upper portion of the remaining portion of the second part is removed.
[0012] According to some embodiments of this disclosure, the upper surface of the first semiconductor material is not higher than the upper surface of the lowermost first semiconductor layer in the stack; and / or the cover layer includes a dielectric layer.
[0013] According to some embodiments of this disclosure, forming a capping layer in the opening includes: epitaxially growing a third semiconductor material in the opening, the third semiconductor material being different from the first semiconductor material; and forming the capping layer in the opening after epitaxially growing the third semiconductor material.
[0014] According to some embodiments of this disclosure, the upper surface of the third semiconductor material is not higher than the upper surface of the lowermost first semiconductor layer in the stack. Attached Figure Description
[0015] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.
[0016] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:
[0017] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0018] Figures 2-7 This is a schematic diagram of different stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0019] Figures 8-13 This is a schematic diagram of different stages of a method for manufacturing a semiconductor structure according to other embodiments of the present disclosure.
[0020] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation
[0021] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values set forth in these embodiments should be interpreted as exemplary only and not as limiting.
[0022] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.
[0023] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.
[0024] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.
[0025] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0026] In related technologies, during the manufacturing process of MCFETs, after etching the source / drain regions of the superlattice fins, a sacrificial layer in the superlattice is etched inwards, and inner spacer layers are formed on both sides of the sacrificial layer. When the sacrificial layer is subsequently removed and metal material is filled to form the metal gate, the inner spacer layers effectively prevent capacitive parasitic effects between the source / drain regions and the gate, thus improving the high-frequency performance of the device.
[0027] The inventors noted that while introducing an inner spacer layer can reduce capacitance parasitic effects, in this scenario, during the formation of the source / drain regions, semiconductor material cannot be epitaxially grown on the surface of the inner spacer layer. Instead, the semiconductor material can only be epitaxially grown independently from the surface of the substrate and the surfaces of multiple discrete channel layers in the superlattice, each in a different direction. This results in numerous defects in the final source / drain regions. These defects cause significant stress loss from the source / drain regions on the channel layers, leading to a decrease in the device's DC performance.
[0028] In view of this, the present disclosure proposes the following technical solutions, which help to improve the high-frequency performance of semiconductor structures while reducing defects in the source / drain regions, thereby further improving the DC performance of semiconductor structures.
[0029] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0030] Figures 2-7 This is a schematic diagram of different stages of a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0031] Next, combine Figures 1-7 Methods for manufacturing semiconductor structures according to different embodiments of the present disclosure will be described.
[0032] First, such as Figure 1 As shown, in step S10, a substrate structure 10 is provided.
[0033] like Figure 2As shown, the substrate structure 10 includes two adjacent fin portions 200 located on the substrate 100. For example, the two fin portions 200 are arranged along the first direction P1. Each fin portion 200 includes a stack formed by alternately stacking a first semiconductor layer 210 and a second semiconductor layer 220. The two ends of the first semiconductor layer 210 have spacer layers 230, and there is an opening 240 between the two fin portions 200. In some embodiments, the substrate structure 10 includes a plurality of fin portions 200 arranged in the first direction P1, and there is an opening 240 between any two adjacent fin portions 200.
[0034] The first semiconductor layer 210 can be further removed subsequently and can also be referred to as a sacrificial layer. The second semiconductor layer 220 serves as the channel layer of the finally formed transistor device.
[0035] In some embodiments, the first semiconductor layer 210 can be a germanide of silicon, and the second semiconductor layer 220 can be silicon or a germanide of silicon, etc. For example, the first semiconductor layer 210 and the second semiconductor layer 220 can be Si 1-x Ge x and Si 1- y Ge y . As some implementation manners, y < x. As some implementation manners, 0 < x ≤ 1, 0 ≤ y ≤ 0.6.
[0036] It can be understood that the two ends of the first semiconductor layer 210 refer to the two ends of the first semiconductor layer 210 in the first direction P1. The spacer layers 230 at the two ends of the first semiconductor layer 210 can also be referred to as inner spacer layers, which are used to reduce the parasitic capacitance between the source region / drain region and the gate in the finally formed semiconductor structure, thereby weakening the capacitive parasitic effect.
[0037] The opening 240 between two adjacent fin portions 200 is the space between the two fin portions 200. In the substrate structure 10, the opening 240 is defined by the boundaries of any two adjacent fin portions 200 and the substrate 100.
[0038] In some embodiments, as Figure 2 shown, the substrate structure 10 further includes a dummy gate structure 400 located on each fin portion 200. The dummy gate structure 400 includes a dummy gate 410 (the dummy gate 410 includes, for example, polysilicon) and spacer portions 420 at both ends of the dummy gate (the spacer portions 420 include, for example, dielectric materials). There can also be a gate dielectric layer 500 (the gate dielectric layer 500 includes, for example, an oxide layer of silicon) further between the dummy gate structure 400 and the fin portion 200, as Figure 2 shown.
[0039] Referring to Figure 1 and Figure 3In step S20, a covering layer 300 is formed in the opening 240. The covering layer 300 includes a first portion 301 covering the bottom of the opening 240 and a second portion 302 covering the sidewalls of the opening 240.
[0040] The sidewall of opening 240 refers to the sidewall of opening 240 in the direction of the line connecting the two fin portions 200. For example, when there are no other structures on the sidewalls of the two fin portions 200 facing each other, the sidewall of opening 240 refers to the sidewalls of these two fin portions 200. When there are other structures (such as a specific material layer) on the sidewalls of the two fin portions 200 facing each other, the sidewall of opening 240 includes the surface of the other structure and the portion of the sidewalls of the two fin portions 200 exposed (if any) that is not covered by the other structure.
[0041] The bottom of opening 240 refers to the surface of the structure below opening 240. For example, when there is no other structure above the portion of the surface of substrate 100 between the two fin portions 200, the bottom of opening 240 refers to the portion of the surface of substrate 100 between the two fin portions 200. When there is another structure (e.g., a specific material layer) above the portion of the surface of substrate 100 between the two fin portions 200, the bottom of opening 240 includes the surface of that other structure, as well as the portion of the surface of substrate 100 between the two fin portions 200 that is not covered by that other structure (if present).
[0042] In some embodiments, such as Figure 3 As shown, when the substrate structure 10 includes a dummy gate structure 400 located on each fin portion 200, the capping layer 300 may further include a third portion 303 covering the upper surface and sidewalls of the dummy gate structure 400. It should be understood that the third portion 303 of the capping layer 300 covering the upper surface and sidewalls of the dummy gate structure 400 can be removed in subsequent processes (e.g., before forming a metal gate).
[0043] The capping layer 300 is used to block the epitaxial growth of semiconductor materials. In some embodiments, the capping layer 300 includes a dielectric layer. For example, the capping layer 300 includes a silicon oxide (e.g., silicon oxide) layer, a silicon nitride (e.g., silicon nitride) layer, a silicon oxide oxynitride (e.g., silicon oxynitride) layer, an aluminum oxide (e.g., aluminum oxide) layer, etc. In this way, it can effectively prevent the formation of other structures on the covered portion and facilitate subsequent removal.
[0044] refer to Figure 1 and Figure 4 In step S30, a removal process is performed to remove the first portion 301 and a portion of the second portion 302. After the removal process, the remaining portion of the second portion 302 at least covers at least a portion of the sidewall of the second semiconductor layer 220 in the stack.
[0045] For example, after the removal process, the remaining portion of the second portion 302 covers at least a portion of the sidewall of one of the second semiconductor layers 220 in the stack. As another example, after the removal process, the remaining portion of the second portion 302 covers at least a portion of the sidewalls of multiple second semiconductor layers 220 in the stack.
[0046] The remaining portion of the second part 302 is used to block the epitaxial growth of semiconductor material on the surface of the portion of the second semiconductor layer 220 that is exposed and covered by the remaining portion.
[0047] In some embodiments, radical etching (TE), capacitively coupled plasma (CCP) etching, or inductively coupled plasma (ICP) etching may be used to remove the first portion 301 and a portion of the second portion 302.
[0048] refer to Figure 1 and Figure 5 In step 40, after the removal process, an epitaxial process is performed to epitaxially grow a first semiconductor material 201 at the bottom of the opening 240.
[0049] The first semiconductor material 201 is a semiconductor material used in the source / drain region. For example, the first semiconductor material 201 is silicon, silicon germanide (e.g., silicon germanide), or silicon phosphide (silicon phosphide), etc.
[0050] In certain scenarios (e.g., the semiconductor material of the source / drain region is different from the semiconductor material of the substrate 100), the first semiconductor material 201 can also serve as a buffer layer between the semiconductor material (i.e., the second semiconductor material 202, as detailed below) and the substrate 100, thereby reducing defects caused by lattice mismatch between the substrate 100 and the second semiconductor material 202.
[0051] refer to Figure 1 and Figure 7 In step 50, after the epitaxial process, the remaining portion of the second portion 302 is removed and the second semiconductor material 202 is epitaxially grown in the opening 240.
[0052] In some embodiments, radical etching, capacitively coupled plasma etching, or inductively coupled plasma etching may be used to remove the remaining portion of the second part 302.
[0053] Through steps S10-S50, a first semiconductor material 201 and a second semiconductor material 202 are epitaxially grown in the opening 240 to form a source / drain region.
[0054] When at least a portion of the sidewall of the uppermost second semiconductor layer 220 is covered in step S30, semiconductor material cannot be epitaxially grown in the covered portion of the sidewall of the second semiconductor layer 220 when epitaxial growth of semiconductor material is performed in the opening 240 to form the source / drain region. The covered portion of the sidewall of the second semiconductor layer 220 is exposed only in step S50, thus delaying the epitaxial growth of the semiconductor material connecting the channel layer. This reduces the proportion of semiconductor material epitaxially grown on the sidewall of the second semiconductor layer 220 within the entire opening 240.
[0055] By reducing the proportion of semiconductor material epitaxially grown on the sidewalls of the second semiconductor layer 220, the number of defects in the source / drain regions can be reduced, thereby ensuring that the source / drain regions exert more stress on the channel layer and improving the DC performance of the final semiconductor structure.
[0056] In some embodiments, such as Figure 4 As shown, after the removal process in step S30, the remaining portion of the second portion 302 at least covers at least a portion of the sidewall of the uppermost second semiconductor layer 220 in the stack. For example, a portion of the first portion 301 and the second portion 302 connected to the first portion 301 can be removed without additional protection for the portion of the second portion 302 near the bottom, which facilitates process implementation.
[0057] In some implementations, the remainder of the second portion 302 covers a portion of the sidewall of the uppermost second semiconductor layer 220 in the stack. In other implementations, the remainder of the second portion 302 covers the entire sidewall of the uppermost second semiconductor layer 220 in the stack.
[0058] In some embodiments, such as Figure 4 As shown, after the removal process in step S30, the remaining portion of the second part 302, in addition to covering the sidewalls of the uppermost second semiconductor layer 220, can also cover at least a portion of the sidewalls of one or more other second semiconductor layers 220. In this way, during the epitaxial growth of the first semiconductor material 201 at the bottom of the opening 240, it is possible to prevent the epitaxial growth of the first semiconductor material 201 on the sidewalls of more second semiconductor layers 220, thereby minimizing the number of defects in the source / drain regions and further improving the DC performance of the final semiconductor structure.
[0059] In some embodiments, such as Figure 4As shown, the remaining portion of the second part 302 covers the sidewall of the uppermost second semiconductor layer 220 in the stack, and also continuously covers at least a portion of the second semiconductor layer 220 adjacent to the uppermost second semiconductor layer 220 (i.e., the second second semiconductor layer 220 from top to bottom). Thus, without requiring additional control during the removal of the second part 302, the epitaxial growth of the first semiconductor material 201 on the sidewalls of the second semiconductor layer 220 can be prevented during the epitaxial growth process at the bottom of the opening 240, thereby minimizing the number of defects in the source / drain regions and further improving the DC performance of the final semiconductor structure.
[0060] In some embodiments, such as Figure 4 As shown, after the removal process in step S30, the remaining portion of the second part 302 covers the sidewalls of all the second semiconductor layers 220 in the stack. In this case, only the bottom of the opening 240 is exposed as the epitaxial growth site. For example, if there are three second semiconductor layers 220 in the stack, the remaining portion of the second part 302 covers the sidewalls of each second semiconductor layer 220. In this way, during the epitaxial growth of the first semiconductor material 201 at the bottom of the opening 240, the first semiconductor material 201 is not epitaxially grown on the sidewalls of all the second semiconductor layers 220, thereby minimizing the number of defects in the source / drain regions and further improving the DC performance of the final semiconductor structure.
[0061] As some implementation methods, such Figure 4 As shown, the remaining portion of the second part 302 may also cover a portion of the spacer layer 230 at the end of the lowest first semiconductor layer 210 in the stack, to prevent the epitaxial growth of the first semiconductor material 201 on the sidewalls of all the second semiconductor layers 220.
[0062] As some further implementation methods, such as Figure 4 As shown, a portion of the second part 302 can be removed from the bottom up, ensuring that the bottom boundary of the remaining portion of the second part 302 is not higher than the upper surface of the lowermost first semiconductor layer 210 in the stack.
[0063] In some embodiments, such as Figure 5 As shown, in step S40, the upper surface of the first semiconductor material 201 epitaxially grown is not higher than the upper surface of the lowermost first semiconductor layer 210 in the stack.
[0064] In the above embodiments, the time for epitaxial growth of the first semiconductor material 201 can be reduced. When the remaining portion of the second part 302 does not cover all the sidewalls of the second semiconductor layer 220 in the stack, excessive first semiconductor material 201 can be epitaxially grown on the surface of the uncovered portion of the sidewall of the second semiconductor layer 220 in the stack, which helps to further reduce defects in the source / drain region and further improve the DC performance of the final semiconductor structure.
[0065] In some embodiments, in step S50, removing the remaining portion of the second portion 302 and epitaxially growing the second semiconductor material 202 in the opening 240 includes multiple repeated processes. Each repeated process includes: removing a portion of the remaining portion of the second portion 302 such that the bottom of the remaining portion of the second portion 302 moves upward; and epitaxially growing the second semiconductor material 202 in the opening 240.
[0066] Figure 5 , Figure 6 and Figure 7 The illustration schematically depicts a scenario where the remaining portion of the second part 302 is removed through two processes, and a second semiconductor material 202 is epitaxially grown in the opening 240. Figure 5 Based on this, through the first process, a portion of the remaining part of the second part 302 was removed and a portion of the second semiconductor material 202 was epitaxially grown, such as... Figure 6 As shown. Through a second process, all remaining portions of the second part 302 are removed, and another portion of the second semiconductor material 202 is epitaxially grown, so that the second semiconductor material 202 fills the opening 240, as shown. Figure 7 As shown.
[0067] Decomposing step S50 into multiple processes facilitates the execution of the entire process flow. For example, the sidewalls of the second semiconductor layer 220 can be gradually exposed, followed by epitaxial growth of the second semiconductor material 202, which helps to further reduce defects in the source / drain regions and further improve the DC performance of the final semiconductor structure.
[0068] As one implementation method, in each process, a portion of the remaining part of the second portion 302 can be removed first, and then a portion of the second semiconductor material 202 can be epitaxially grown in the opening 240. In this way, the second semiconductor material 202 can be epitaxially grown without altering the remaining portion of the second portion 302, which helps control the amount of the second semiconductor material 202 to be epitaxially grown and reduces the complexity of the process flow. For example, the upper surface of the second semiconductor material 202 can be made no higher than the bottom of the remaining portion of the second portion 302, thereby avoiding a situation where a portion of the remaining portion of the second portion 302 is surrounded by the sidewalls of the opening 240 and the second semiconductor material 202, making removal inconvenient.
[0069] As a further implementation, in each process except the last one, the bottom of the remaining portion of the second part 302 can be moved up to the lower surface of the sidewall of a certain second semiconductor layer 220 in the stack, and then a portion of the second semiconductor material 202 can be epitaxially grown in the opening 240 so that the upper surface of the second semiconductor material 202 is flush with the bottom of the remaining portion of the second part 302. In this way, it can be ensured that a certain second semiconductor layer 220 is completely covered in the current process, and the epitaxial growth of the second semiconductor material 202 in two directions can be carried out simultaneously in the next process at the lower surface of the sidewall of the second semiconductor layer 220 (i.e., the epitaxial growth of the second semiconductor material 202 at the lower surface of the sidewall of the second semiconductor layer 220 is delayed to the maximum extent), further reducing defects in the epitaxially grown semiconductor material.
[0070] As another implementation, in at least one of the multiple processes (e.g., in each process), a portion of the remaining part of the second portion 302 can be removed first, and then, before that portion of the remaining part of the second portion 302 is completely removed, a portion of the second semiconductor material 202 can be epitaxially grown in the opening 240. That is, the removal of a portion of the remaining part of the second portion 302 and the epitaxial growth of the second semiconductor material 202 in the opening 240 overlap in time. This can improve the execution efficiency of the process.
[0071] As another implementation, in at least one process, a portion of the remaining portion of the second part 302 may be removed first, followed by epitaxial growth of a portion of the second semiconductor material 202 in the opening 240; in at least another process, a portion of the remaining portion of the second part 302 may be removed first, followed by epitaxial growth of a portion of the second semiconductor material 202 in the opening 240 before that portion of the remaining portion of the second part 302 is completely removed.
[0072] In other embodiments, in step S50, the process of removing the remaining portion of the second portion 302 and the process of epitaxially growing the second semiconductor material 202 in the opening 240 are performed simultaneously. This improves the efficiency of step S50.
[0073] Synchronous execution means that there is at least a period of time during which the process of removing the remaining part of the second part 302 and the process of epitaxially growing the second semiconductor material 202 in the opening 240 are carried out simultaneously, that is, the two overlap in time.
[0074] As one implementation, the epitaxial growth of the second semiconductor material 202 in the opening 240 can begin simultaneously with the removal of the remaining portion of the second part 302. This maximizes the efficiency of step S50.
[0075] As another implementation, the remaining portion of the second part 302 can be removed first, and then, before the remaining portion of the second part 302 is completely removed, a portion of the second semiconductor material 202 can be epitaxially grown in the opening 240. This reduces the complexity of the process.
[0076] As a further implementation of the above-mentioned implementations, the rate at which the bottom height of the remaining portion of the second part 302 rises is equal to the rate at which the upper surface height of the second semiconductor material 202 epitaxially grown from the bottom of the opening 240 rises, so as to balance the efficiency and quality of epitaxial growth.
[0077] In some embodiments, in step S20, in the covering layer 300 formed in the opening 240, the thickness of the second portion 302 gradually decreases from top to bottom, and the thickness of the first portion 301 is less than or equal to the thickness of the second portion 302, such as... Figure 3 As shown.
[0078] In the above embodiments, by forming a capping layer 300 with a sidewall thickness that gradually decreases from top to bottom and has the smallest bottom thickness (e.g., through the step effect in thin film deposition), the execution difficulty of steps S30 and S50 can be effectively reduced. For example, isotropic etching (e.g., free radical etching) can be used to remove the bottom portions of the first portion 301 and the second portion 302 separately, and to move the bottom of the second portion 302 upwards, without other means.
[0079] In other embodiments, in step S20, the thickness of each portion of the covering layer 300 formed in the opening 240 is the same.
[0080] In some embodiments, during the epitaxial growth of the second semiconductor material 202 in the opening 240 in step S50, the rate of epitaxial growth of the second semiconductor material 202 at the bottom of the opening 240 is controlled to be greater than the rate of epitaxial growth at the sidewalls of the opening 240. This effectively reduces the amount of second semiconductor material 202 epitaxially grown from the sidewalls of the second semiconductor layer 220, thereby reducing defects.
[0081] As some implementation methods, an accelerator that accelerates the epitaxial growth of the second semiconductor material 202 can be applied to the bottom of the opening 240, and an inhibitor that suppresses the epitaxial growth of the second semiconductor material 202 can be applied to the sidewall of the opening 240.
[0082] In some embodiments, during the removal of the remaining portion of the second portion 302 in step S50, the rate of removing the lower portion of the remaining portion of the second portion 302 is controlled to be greater than the rate of removing the upper portion of the remaining portion of the second portion 302. This allows the bottom of the remaining portion of the second portion 302 to gradually move upwards.
[0083] The boundaries between the relatively lower and relatively upper portions can be set according to requirements. For example, a threshold height can be set such that the portion of the remaining portion of the second part 302 below the threshold height is removed at a rate greater than the portion of the remaining portion of the second part 302 above the threshold height.
[0084] As some implementation methods, capacitively coupled plasma etching or inductively coupled plasma etching can be used to remove the remaining portion of the second part 302. For example, by controlling (e.g., controlling the applied bias voltage) to make the plasma density in the relatively lower space of the opening 240 greater than the plasma density in the relatively upper space of the opening 240, the relatively lower portion of the remaining portion of the second part 302 can be removed at a faster rate.
[0085] Figures 8-13 Based on Figure 2 The schematic diagram shown illustrates different stages of a method for manufacturing a semiconductor structure according to other embodiments of the present disclosure, with substrate structure 10 as an example.
[0086] and Figures 2-7 Compared to the illustrated embodiment, in a method for manufacturing a semiconductor structure according to other embodiments of this disclosure, step S20 of forming a capping layer 300 in the opening 240 includes: epitaxially growing a third semiconductor material 203 in the opening 240, wherein the third semiconductor material 203 is different from the first semiconductor material 201, such as... Figure 8 As shown; and a capping layer 300 is formed in the opening 240 after the epitaxial growth of the third semiconductor material 203, as... Figure 9 As shown.
[0087] In some embodiments, the third semiconductor material 203 epitaxially grown on the sidewalls of the opening 240 (i.e., the sidewalls of each of the second semiconductor layers 220) can be separated from each other and from the third semiconductor material 203 epitaxially grown at the bottom of the opening 240, specifically as follows: Figure 8 As shown. In this way, the amount of epitaxially grown third semiconductor material is not excessive, avoiding contact between the separated third semiconductor materials 203 and the formation of defects at the contact points.
[0088] In other embodiments, the third semiconductor material 203 epitaxially grown on the sidewalls of the opening 240 (i.e., the sidewalls of each of the second semiconductor layers 220) can be connected to each other to form a film and connected to the third semiconductor material 203 epitaxially grown at the bottom of the opening 240 to form a film.
[0089] In the above manufacturing method, the states corresponding to steps S10, S20, S30, S40, and S50 can be referred to respectively. Figure 2 , Figures 8-9 , Figure 10 , Figure 11 and Figures 12-13 For relevant descriptions, please refer to the above text. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figures 6-7 The description will not be repeated here.
[0090] The third semiconductor material 203 can serve as a buffer layer between the substrate 100 and the first semiconductor material 201 (for example, the lattice size of the third semiconductor material 203 is located between the lattice size of the first semiconductor material 201 and the lattice size of the material of the substrate 100), thereby reducing defects in the source / drain regions caused by lattice mismatch between the substrate 100 and the first semiconductor material 201.
[0091] In some embodiments, the first semiconductor material 201 may be the same as the second semiconductor material 202, that is, the third semiconductor material 203 may serve as a buffer layer.
[0092] In other embodiments, the first semiconductor material 201 may be different from the second semiconductor material 202, so that the first semiconductor material 201 serves as a buffer layer between the third semiconductor material 203 and the second semiconductor material 202, thereby further reducing defects caused by lattice mismatch.
[0093] In some embodiments, the upper surface of the third semiconductor material 203 is not higher than the upper surface of the lowermost first semiconductor layer 210 in the stack. In this way, excessive epitaxial growth of the third semiconductor material 203 on the sidewalls of the opening 240 can be avoided, and the probability of the third semiconductor materials 203 epitaxially grown on the sidewalls of the respective second semiconductor layers 220 contacting each other and forming defects at the contact points can be reduced, which helps to further improve the DC performance of the semiconductor structure.
[0094] In some embodiments, where the substrate structure 10 includes a dummy gate structure 400 located on each fin portion 200, the method of manufacturing the semiconductor structure further includes: removing the dummy gate 410 and all of the first semiconductor layers 210 in the stack to form a space, and filling the space where the dummy gate 410 and the first semiconductor layers 210 were originally located with a metal material to form a metal gate. Thus, a semiconductor structure with fewer defects in the source / drain regions is ultimately formed.
[0095] In this embodiment of the disclosure, the semiconductor structure may be an MCFET or a semiconductor device including an MCFET.
[0096] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.
[0097] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, comprising: A substrate structure is provided, the substrate structure including two adjacent fin portions located on a substrate, each fin portion including a stack of alternating first semiconductor layers and second semiconductor layers, the first semiconductor layers having spacer layers at both ends, and an opening between the two fin portions; A covering layer is formed in the opening, the covering layer comprising a first portion covering the bottom of the opening and a second portion covering the sidewalls of the opening; A removal process is performed to remove the first portion and a portion of the second portion, wherein the remaining portion of the second portion at least covers at least a portion of the sidewall of a portion of the second semiconductor layer in the stack; Following the removal process, an epitaxial process is performed to epitaxially grow a first semiconductor material at the bottom of the opening; and After the epitaxial process, the remaining portion of the second part is removed and a second semiconductor material is epitaxially grown in the opening.
2. The method according to claim 1, wherein, After the removal process, the remaining portion of the second part covers at least a portion of the sidewall of the uppermost second semiconductor layer in the stack.
3. The method according to claim 2, wherein, After the removal process, the remaining portion of the second part covers the sidewall of the uppermost second semiconductor layer in the stack, and also covers at least a portion of the sidewalls of one or more second semiconductor layers other than the uppermost second semiconductor layer.
4. The method according to claim 3, wherein, After the removal process, the remaining portion of the second part covers the sidewalls of all the second semiconductor layers in the stack.
5. The method according to claim 1, wherein, Removing the remaining portion of the second part and epitaxially growing a second semiconductor material in the opening includes multiple repeated processes, each repeated process including: Remove a portion of the remaining part of the second part so that the bottom of the remaining part of the second part moves upward; and The second semiconductor material is epitaxially grown in the opening.
6. The method according to claim 1, wherein, The process of removing the remaining portion of the second part and the process of epitaxially growing the second semiconductor material in the opening are performed simultaneously.
7. The method according to any one of claims 1-6, wherein, In the covering layer formed in the opening, the thickness of the second portion gradually decreases from top to bottom, and the thickness of the first portion is less than or equal to the thickness of the second portion.
8. The method according to any one of claims 1-6, wherein, During the epitaxial growth of the second semiconductor material in the opening, the rate at which the second semiconductor material is epitaxially grown at the bottom of the opening is controlled to be greater than the rate at which it is epitaxially grown on the sidewall of the opening. and / or During the process of removing the remaining portion of the second part, the rate of removing the lower part of the remaining portion of the second part is controlled to be greater than the rate of removing the upper part of the remaining portion of the second part.
9. The method according to any one of claims 1-6, wherein, The upper surface of the first semiconductor material is not higher than the upper surface of the lowermost first semiconductor layer in the stack; and / or The cover layer includes a dielectric layer.
10. The method according to any one of claims 1-6, wherein, Forming a covering layer in the opening includes: A third semiconductor material, different from the first semiconductor material, is epitaxially grown in the opening; and The capping layer is formed in the opening after the epitaxial growth of the third semiconductor material.