Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device may include a stacked structure including: a bulk semiconductor pattern including a first well region; a sacrificial film on an upper surface of the bulk semiconductor pattern; and a semiconductor film on an upper surface of the sacrificial film. The semiconductor device may further include a device isolation pattern at a side of the stack structure; and a backside wiring structure on a lower surface of the bulk semiconductor pattern and a lower surface of the device isolation pattern, in which the stack structure further includes a first doped region extending across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film, and connected to the first well region, and in which the first doped region is connected to the semiconductor film. The first doped region is spaced apart from a lower surface of the bulk semiconductor pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0129567, filed on September 25, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some embodiments of this disclosure relate to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor device including passive devices and a method of manufacturing the same. Background Technology

[0004] As one of the scaling techniques for increasing the density of integrated circuit devices, multi-gate transistors with fin-shaped or nanowire-shaped silicon bodies have been proposed for forming multi-gate transistors on the surface of the silicon bodies.

[0005] Because this multi-gate transistor uses a three-dimensional channel, it is easy to scale. Furthermore, current control capability can be improved even without increasing the gate length. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0006] According to embodiments of this disclosure, a semiconductor device may be provided that includes a passive device having improved compatibility with a back-side power delivery network (BSPDN).

[0007] According to embodiments of this disclosure, a method for manufacturing a semiconductor device can be provided, wherein a semiconductor device having improved yield and performance can be manufactured.

[0008] According to embodiments of this disclosure, a semiconductor device may include a stacked structure comprising: a bulk semiconductor pattern including a first well region; a sacrificial film on an upper surface of the bulk semiconductor pattern; and a semiconductor film on an upper surface of the sacrificial film. The semiconductor device may further include: a device isolation pattern on a side of the stacked structure; and a back-side wiring structure on a lower surface of the bulk semiconductor pattern and a lower surface of the device isolation pattern. The stacked structure further includes a first doped region extending across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film, and the first doped region is connected to the first well region. The first doped region is spaced apart from the lower surface of the bulk semiconductor pattern.

[0009] According to embodiments of this disclosure, a semiconductor device may include a stacked structure comprising: a bulk semiconductor pattern including a first well region having a first conductivity type; a sacrificial film on an upper surface of the bulk semiconductor pattern; and a semiconductor film on an upper surface of the sacrificial film. The semiconductor device may further include: a device isolation pattern on a side of the stacked structure; and a gate structure on the stacked structure and the device isolation pattern and intersecting the stacked structure, wherein the stacked structure further includes a first doped region on a first side of the gate structure, the first doped region being connected to the first well region and having a second conductivity type different from the first conductivity type, and wherein the first doped region extends across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film.

[0010] According to embodiments of this disclosure, a semiconductor device may include a stacked structure in a first region of the semiconductor device, the stacked structure including: a bulk semiconductor pattern; a sacrificial film on an upper surface of the bulk semiconductor pattern; and a first semiconductor film on the upper surface of the sacrificial film. The semiconductor device may further include: an active pattern including a fin pattern and a second semiconductor film in a second region of the semiconductor device, the fin pattern extending in a first direction and the second semiconductor film extending in the first direction and spaced apart from the upper surface of the fin pattern; a device isolation pattern on the sides of the bulk semiconductor pattern and the fin pattern; a first gate structure on the stacked structure and the device isolation pattern, intersecting the stacked structure; a second gate structure on the active pattern and the device isolation pattern, extending in a second direction intersecting the first direction; and a back-side wiring structure located on the lower surface of the bulk semiconductor pattern, the lower surface of the fin pattern, and the lower surface of the device isolation pattern, wherein the bulk semiconductor pattern and the fin pattern are at the same level, wherein the first semiconductor film and the second semiconductor film are at the same level, and wherein the stacked structure further includes a PN junction located at a level between the lower surface of the device isolation pattern and the upper surface of the bulk semiconductor pattern.

[0011] The aspects of the embodiments of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description of the embodiments of this disclosure additional aspects not mentioned herein. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become clearer from the detailed description of non-limiting exemplary embodiments with reference to the accompanying drawings, in which:

[0013] FIG. 1 This is an example layout diagram illustrating a semiconductor device according to some embodiments.

[0014] FIG. 2 It is along FIG. 1 The cross-sectional view taken from line A1-A1.

[0015] FIG. 3 It is along FIG. 1 The cross-sectional view taken from line B1-B1.

[0016] FIG. 4 It is along FIG. 1 The cross-sectional view taken from line C1-C1.

[0017] FIG. 5 to FIG. 10 These are various other cross-sectional views illustrating a semiconductor device according to some embodiments.

[0018] FIG. 11 This is an example layout diagram illustrating a semiconductor device according to some embodiments.

[0019] FIG. 12A Show along FIG. 11 The cross-sectional view taken from line A1-A1.

[0020] FIG. 12B Show along FIG. 11 The cross-sectional view taken from line A2-A2.

[0021] FIG. 13A Show along FIG. 11 The cross-sectional view taken from line B1-B1.

[0022] FIG. 13B Show along FIG. 11 The cross-sectional view taken from line B2-B2.

[0023] FIG. 14A Show along FIG. 11 The cross-sectional view taken from line C1-C1.

[0024] FIG. 14B Show along FIG. 11 The cross-sectional view taken from line C2-C2.

[0025] FIG. 15 to FIG. 36B This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0026] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, without departing from the spirit and scope of this disclosure, the first element, first component, or first segment discussed below may be referred to as the second element, second component, or second segment.

[0027] As used in this article, “equal” means not only “completely equal”, but also includes minor differences that may occur due to process allowances, etc.

[0028] It will be understood that when a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, it can be directly on, directly connected to, or directly coupled to the other component or layer, or there can be intermediate components or layers. Conversely, when a component or layer is referred to as being "directly" on, directly connected to, or directly coupled to another component or layer, there are no intermediate components or layers.

[0029] In the following text, reference will be made to FIG. 1 to FIG. 14B A semiconductor device according to an example embodiment is described.

[0030] FIG. 1 This is an example layout diagram illustrating a semiconductor device according to some embodiments. FIG. 2 It is along FIG. 1 The cross-sectional view taken from line A1-A1. FIG. 3 It is along FIG. 1 The cross-sectional view taken from line B1-B1. FIG. 4 It is along FIG. 1 The cross-sectional view taken from line C1-C1.

[0031] Reference FIG. 1 to FIG. 4 A semiconductor device according to some embodiments includes a stacked structure SS, a first device isolation pattern 105, a first gate structure G11 to a fourth gate structure G14, a first epitaxial pattern 160, a first interlayer insulating film 180, a front wiring structure FW, and a back wiring structure BW.

[0032] The stacked structure SS may include a bulk semiconductor pattern 110, a plurality of first sacrificial films 310 and a plurality of first semiconductor films 111 to 113.

[0033] The bulk semiconductor pattern 110 may be a bulk silicon pattern, or may include another material, such as, for example, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The bulk semiconductor pattern 110 may be formed by etching a portion of a substrate, or may be an epitaxial layer grown from the substrate. In the following description, by way of example, the bulk semiconductor pattern 110 is a silicon (Si) pattern.

[0034] In some embodiments, the bulk semiconductor pattern 110 may include a first well region WR1 having a first conductivity type. For example, the first well region WR1 may be an n-type doped region “n” formed by doping the bulk semiconductor pattern 110 with an n-type impurity (e.g., phosphorus (P), antimony (Sb), or arsenic (As)). Although the first conductivity type is described as n-type in the following description, this is merely an example, and the first conductivity type may be p-type.

[0035] Multiple first sacrificial films 310 and multiple first semiconductor films 111 to 113 may be alternately stacked on the upper surface of the bulk semiconductor pattern 110. For example, each of the first sacrificial films 310 and each of the first semiconductor films 111 to 113 may have a layered structure extending along a horizontal plane (e.g., an XY plane) parallel to the upper surface of the bulk semiconductor pattern 110. The first semiconductor films 111 to 113 may be sequentially stacked by being spaced apart from each other by the first sacrificial films 310. The number, arrangement, and thickness of the first sacrificial films 310 and the first semiconductor films 111 to 113 are merely examples and are not limited thereto.

[0036] Each of the first semiconductor films 111 to 113 may comprise silicon (Si) or germanium (Ge) as a semiconductor material. Alternatively, each of the first semiconductor films 111 to 113 may comprise a compound semiconductor, such as, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. A group IV-IV compound semiconductor may be a binary or ternary compound comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn) doped with group IV elements. A group III-V compound semiconductor may be, for example, a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements. In the following description, by way of example, each of the first semiconductor films 111 to 113 is a silicon (Si) film.

[0037] The first sacrificial film 310 may include a material that has etch selectivity relative to the first semiconductor films 111 to 113. For example, each of the first semiconductor films 111 to 113 may be a silicon (Si) film, and each of the first sacrificial films 310 may be a silicon-germanium (SiGe) film.

[0038] Although the stacked structure SS is shown as extending in the first direction X, this is only an example. The stacked structure SS can also extend in the second direction Y, which intersects the first direction X.

[0039] The first device isolation pattern 105 may cover at least a portion of the side surface of the stacked structure SS. For example, as shown, the first device isolation pattern 105 may cover a portion of the side surface of the bulk semiconductor pattern 110. In some embodiments, the first device isolation pattern 105 may be a shallow isolation trench (STI) formed by filling at least a portion of a shallow trench formed in the stacked structure SS with an insulating material. Although the upper portion of the bulk semiconductor pattern 110 is shown protruding above the uppermost surface of the first device isolation pattern 105, this is merely an example. As another example, the uppermost surface of the bulk semiconductor pattern 110 may be positioned coplanar with the uppermost surface of the first device isolation pattern 105.

[0040] The lower surface of the bulk semiconductor pattern 110 may be positioned coplanar with or higher than the lower surface of the first device isolation pattern 105. For example, the lower surface of the bulk semiconductor pattern 110 may not be lower than the lower surface of the first device isolation pattern 105. In some embodiments, as shown in the figures, the lower surface of the bulk semiconductor pattern 110 may be positioned coplanar with the lower surface of the first device isolation pattern 105.

[0041] The first device isolation pattern 105 may include, but is not limited to, an insulating material, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. For example, the first device isolation pattern 105 may include a silicon oxide layer.

[0042] The first gate structures G11 to the fourth gate structures G14 can be formed on the stacked structure SS and the first device isolation pattern 105. For example, the first gate structures G11 to the fourth gate structures G14 can extend along the upper surface of the first device isolation pattern 105 and the side and upper surfaces of the stacked structure SS. Each of the first gate structures G11 to the fourth gate structures G14 can intersect the stacked structure SS. For example, each of the first gate structures G11 to the fourth gate structures G14 can extend in the second direction Y. The first sacrificial film 310 and the first semiconductor films 111 to 113 can extend in the first direction X to pass through the first gate structures G11 to the fourth gate structures G14, respectively.

[0043] The first gate structure G11, the second gate structure G12, the third gate structure G13, and the fourth gate structure G14 may extend parallel to each other on the stacked structure SS. For example, the stacked structure SS may include a first portion P1, a second portion P2, and a third portion P3 arranged sequentially along a first direction X. The first gate structure G11 may be formed on the first portion P1 of the stacked structure SS. The second gate structure G12 may be formed on the boundary between the first portion P1 and the second portion P2 of the stacked structure SS. The third gate structure G13 may be formed on the boundary between the second portion P2 and the third portion P3 of the stacked structure SS. The fourth gate structure G14 may be formed on the third portion P3 of the stacked structure SS.

[0044] In some embodiments, a plurality of first gate structures G11 may be formed on a first portion P1 of the stacked structure SS. In some embodiments, some of the plurality of first gate structures G11 may be formed on an end of the first portion P1 of the stacked structure SS.

[0045] In some embodiments, a plurality of fourth gate structures G14 may be formed on the third portion P3 of the stacked structure SS. In some embodiments, some of the plurality of fourth gate structures G14 may be formed on the ends of the third portion P3 of the stacked structure SS.

[0046] Each of the first gate structure G11 to the fourth gate structure G14 may include a first gate dielectric film 120, a first gate electrode 130, a first gate spacer 140, and a first gate capping film 150.

[0047] A first gate dielectric film 120 may be formed on a stacked structure SS. The first gate dielectric film 120 may be interposed between the stacked structure SS and the first gate electrode 130. For example, the first gate dielectric film 120 may extend in a conformal manner to the contours of the side surface and the top surface of the stacked structure SS. In some embodiments, the first gate dielectric film 120 may further extend along the top surface of the first device isolation pattern 105.

[0048] The first gate dielectric film 120 may include a dielectric material, such as at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material with a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, but is not limited to, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0049] The first gate electrode 130 may be stacked on the first gate dielectric film 120. Each of the first sacrificial film 310 and the first semiconductor films 111 to 113 may extend in the first direction X to pass through the first gate electrode 130. The first gate electrode 130 may include, but is not limited to, at least one of, such as TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof.

[0050] Although the first gate electrode 130 is shown as a single film, this is merely an example, and it can be formed by stacking multiple conductive films. For example, the first gate electrode 130 may include a work function adjustment film for adjusting the work function and a filling conductive film for filling the space formed by the work function adjustment film. The work function adjustment film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0051] The first gate spacer 140 may extend along one side of the first gate electrode 130. Each of the first sacrificial film 310 and the first semiconductor films 111 to 113 may extend in the first direction X to pass through the first gate spacer 140. The first gate spacer 140 may include, but is not limited to, an insulating material, such as, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron nitride, silicon carbonitride, and combinations thereof.

[0052] In some embodiments, a portion of the first gate dielectric film 120 may be inserted between the first gate electrode 130 and the first gate spacer 140. For example, a portion of the first gate dielectric film 120 may extend along the inside of the first gate spacer 140.

[0053] The first gate capping film 150 may extend along the upper surface of the first gate electrode 130. The first gate capping film 150 may include, but is not limited to, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron nitride, silicon carbonitride, and combinations thereof.

[0054] The stacked structure SS may include a first doped region IR1 having a second conductivity type different from the first conductivity type. For example, the first doped region IR1 may be a heavily doped p-type doped region p+ formed by doping the stacked structure SS with heavily doped p-type impurities (e.g., boron (B), indium (In), gallium (Ga), or aluminum (Al)).

[0055] The first doped region IR1 can be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The first doped region IR1 can be directly connected to the first well region WR1. Therefore, the first well region WR1 and the first doped region IR1 can form a PN junction in the bulk semiconductor pattern 110.

[0056] In some embodiments, the first doped region IR1 may be formed in the second portion P2 of the stacked structure SS. For example, the first doped region IR1 may be formed in the stacked structure SS between the second gate structure G12 and the third gate structure G13.

[0057] In some embodiments, the second gate structure G12 and the third gate structure G13 may be spaced apart from each other by a gap greater than a gate pitch 1GP. In this case, a gate pitch 1GP may be defined as the sum of the minimum gap between gate structures (e.g., between the first gate structure G11 and the second gate structure G12) and the width of a gate structure (e.g., the second gate structure G12).

[0058] In some embodiments, the first doped region IR1 may be spaced apart from the lower surface of the bulk semiconductor pattern 110. For example, the lower portion (e.g., the lowermost surface) of the first doped region IR1 may be located at a horizontal position between the lower surface and the upper surface of the bulk semiconductor pattern 110.

[0059] In some embodiments, the side of each of the first sacrificial films 310 facing the first gate structure G11 to the fourth gate structure G14 may be recessed toward the interior of the stacked structure SS beyond the side of the first semiconductor films 111 to 113.

[0060] For example, such as FIG. 2 As shown, the side of each first sacrificial film 310 intersecting the first direction X may include a first recess 310r1. The first recess 310r1 may face the first gate structure G11 formed on the end of the first portion P1 and / or the fourth gate structure G14 formed on the end of the third portion P3. Furthermore, the first recess 310r1 may be recessed into the interior of the stacked structure SS beyond the side of the first semiconductor films 111 to 113 intersecting the first direction X. The first gate dielectric film 120 and / or the first gate electrode 130 may fill at least a portion of the first recess 310r1. In some embodiments, the first recess 310r1 may include a concave surface that is recessed toward the first gate structure G11 and / or the fourth gate structure G14 opposite to it.

[0061] Alternatively or otherwise, for example, such as FIG. 3As shown, the side of each of the first sacrificial films 310 intersecting the second direction Y may include a second recess 310r2. The second recess 310r2 may face the first gate structures G11 to the fourth gate structures G14. Furthermore, the second recess 310r2 may be recessed into the interior of the stacked structure SS beyond the side of the first semiconductor films 111 to 113 intersecting the second direction Y. The first gate dielectric film 120 and / or the first gate electrode 130 may fill at least a portion of the second recess 310r2. In some embodiments, the second recess 310r2 may include a concave surface recessed toward the first gate structures G11 to the fourth gate structures G14 opposite to it.

[0062] The first epitaxial pattern 160 may be formed on the stacked structure SS. In some embodiments, the first epitaxial pattern 160 may be formed on a first portion P1 and a third portion P3 of the stacked structure SS. For example, the first epitaxial pattern 160 may be formed on at least one side of the first gate structure G11 and at least one side of the fourth gate structure G14 in the stacked structure SS. The first epitaxial pattern 160 may be connected to the upper surface of the bulk semiconductor pattern 110, the side portion of the first sacrificial film 310, and the side portions of the first semiconductor films 111 to 113. The first epitaxial pattern 160 may be separated from the first gate electrode 130 by the first gate dielectric film 120 and / or the first gate spacer 140. In some embodiments, the lowermost surface of the first epitaxial pattern 160 may be positioned below the uppermost surface of the bulk semiconductor pattern 110.

[0063] The first epitaxial pattern 160 may include an epitaxial layer doped with impurities. For example, the first epitaxial pattern 160 may be an epitaxial layer grown from the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113 by an epitaxial growth process.

[0064] In some embodiments, the first epitaxial pattern 160 may have a first conductivity type. For example, the first epitaxial pattern 160 may include an n-type impurity (e.g., P, Sb, or As) and / or impurities for preventing the diffusion of the n-type impurity.

[0065] In some embodiments, the first epitaxial pattern 160 may further include a tensile stress material. For example, when each of the first semiconductor films 111 to 113 is a silicon (Si) film, the first epitaxial pattern 160 may include a material having a smaller lattice constant than that of silicon (Si) (e.g., silicon carbide (SiC)).

[0066] The first epitaxial pattern 160 can be directly connected to the first well region WR1. In some embodiments, the doping concentration of the first epitaxial pattern 160 can be greater than the doping concentration of the first well region WR1. For example, the first epitaxial pattern 160 can be a heavily doped n-type doped region n+ formed by doping with heavily doped n-type impurities.

[0067] The first interlayer insulating film 180 can be formed on the stacked structure SS, the first device isolation pattern 105, the first gate structure G11 to the fourth gate structure G14, and the first epitaxial pattern 160. The first interlayer insulating film 180 can be formed to fill the space on the outer side of the first gate structure G11 to the fourth gate structure G14.

[0068] The first interlayer insulating film 180 may include at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon boron nitride, silicon boron carbonitride, silicon carbonitride, and a low dielectric constant material with a dielectric constant less than that of silicon oxide. The low dielectric constant material may include, but is not limited to, at least one of the following: flowable oxide (FOX), toran siloxane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorosilicone glass (FSG), carbon-doped silica (CDO), degelatin, aerogel, amorphous fluorinated carbon, organosilicon glass (OSG), parylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymeric materials, and combinations thereof.

[0069] The front wiring structure FW can be formed on the upper surface of the first interlayer insulating film 180. For example, the front wiring structure FW may include a front wiring interlayer insulating film FI covering the upper surface of the first interlayer insulating film 180, and a front wiring pattern FM in the front wiring interlayer insulating film FI. The front wiring patterns FM may be insulated from each other and spaced apart from each other by the front wiring interlayer insulating film FI. The number of layers, shape, arrangement, etc. of the front wiring pattern FM are merely examples and are not limited to the examples shown.

[0070] The back-side wiring structure BW can be formed on the lower surface of the bulk semiconductor pattern 110 and the lower surface of the first device isolation pattern 105. For example, the back-side wiring structure BW may include a back-side wiring inter-insulating film BI covering the lower surface of the bulk semiconductor pattern 110 and the lower surface of the first device isolation pattern 105, and back-side wiring patterns BM within the back-side wiring inter-insulating film BI. The back-side wiring patterns BM may be insulated from each other and spaced apart from each other by the back-side wiring inter-insulating film BI. The number, number of layers, shape, arrangement, etc., of the back-side wiring patterns BM are merely examples and are not limited to the examples shown.

[0071] The first epitaxial pattern 160 can be electrically connected to the front wiring structure FW and / or the back wiring structure BW. For example, a first contact pattern 190 connecting the first epitaxial pattern 160 to a portion of the front wiring pattern FM can be formed through the first interlayer insulating film 180. The first epitaxial pattern 160 can electrically connect the first well region WR1 to the front wiring structure FW. A predetermined voltage can be applied to the first well region WR1 through the front wiring structure FW and the first epitaxial pattern 160.

[0072] The first doped region IR1 may be electrically connected to the front wiring structure FW and / or the back wiring structure BW. For example, a first contact pattern 190 connecting the first doped region IR1 to another portion of the front wiring pattern FM may be formed through the first interlayer insulating film 180. A predetermined voltage may be applied to the first doped region IR1 through the front wiring structure FW. In some embodiments, the first contact pattern 190 may be connected to the uppermost semiconductor film (e.g., the first semiconductor film 113) among the semiconductor films 111 to 113 in the first doped region IR1. In some embodiments, the first contact pattern 190 may extend in the second direction Y. In some embodiments, a plurality of first contact patterns 190 may be connected to the first doped region IR1.

[0073] In some embodiments, the first well region WR1, the first doped region IR1, and the front wiring structure FW can provide a PN diode.

[0074] A passive device, such as a diode, has been proposed using a process for fabricating semiconductor devices including multi-bridge channels. For example, a PN junction using a well region in a substrate can be provided, and contacts connected to the anode of the PN junction using an epitaxial pattern connected to the multi-bridge channel can be provided. However, a problem with such a PN junction is its incompatibility with so-called Backside Power Delivery Networks (BSPDNs), in which a power delivery network is provided from the back side of the substrate. For example, to implement a backside power delivery network, a thinning process can be performed on the back side of the substrate. The thinning process can be performed until the lower surface of a shallow isolation trench (STI) formed on the substrate is reached, and in this case, the well region forming the PN junction in the substrate may be removed.

[0075] On the other hand, semiconductor devices according to some embodiments can improve compatibility with back-side power delivery networks by using a PN junction formed in the bulk semiconductor pattern 110. For example, as described above, a PN junction can be provided in the bulk semiconductor pattern 110 for the first well region WR1 and the first doped region IR1. The PN junction can be located at a horizontal position between the lower surface of the first device isolation pattern 105 and the upper surface of the bulk semiconductor pattern 110. Therefore, the PN junction in the bulk semiconductor pattern 110 can be provided without problems even if the substrate is removed by a thinning process for the back-side power delivery network. As a result, semiconductor devices including passive devices with improved compatibility with back-side power delivery networks can be provided.

[0076] FIG. 5 to FIG. 10 Various other cross-sectional views of a semiconductor device according to some embodiments are shown. For ease of description, the above references may be provided briefly or omitted. FIG. 1 to FIG. 4 The given redundant description is for reference only. FIG. 5 to FIG. 9 It is along FIG. 1 Different cross-sectional views taken from line A1-A1, and FIG. 10 It is along FIG. 1 Another cross-sectional view taken from line C1-C1.

[0077] Reference FIG. 1 and FIG. 5 In a semiconductor device according to some embodiments, the stacked structure SS may include a first doped region IR1, a second doped region IR2, and a third doped region IR3.

[0078] The second doped region IR2 may be formed in the first portion P1 of the stacked structure SS. For example, the second doped region IR2 may be formed in the stacked structure SS between the first gate structure G11 and the second gate structure G12.

[0079] The third doped region IR3 can be formed in the third portion P3 of the stacked structure SS. For example, the third doped region IR3 can be formed in the stacked structure SS between the third gate structure G13 and the fourth gate structure G14.

[0080] Each of the second doped region IR2 and the third doped region IR3 can have a first conductivity type. For example, each of the second doped region IR2 and the third doped region IR3 can be a heavily doped n-type doped region n+ formed by doping a heavily doped n-type impurity (e.g., P, Sb, or As) in the stacked structure SS.

[0081] Each of the second doped region IR2 and the third doped region IR3 may be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. Each of the second doped region IR2 and the third doped region IR3 may be directly connected to the first well region WR1.

[0082] Each of the second doped region IR2 and the third doped region IR3 may be electrically connected to the front wiring structure FW and / or the back wiring structure BW. For example, at least one first contact pattern 190 connecting the second doped region IR2 and / or the third doped region IR3 to a portion of the front wiring pattern FM may be formed through the first interlayer insulating film 180. The second doped region IR2 and the third doped region IR3 may electrically connect the first well region WR1 to the front wiring structure FW. A predetermined voltage may be applied to the first well region WR1 through the front wiring structure FW, the second doped region IR2, and the third doped region IR3.

[0083] In some embodiments, the first well region WR1, the first doped region IR1, and the front wiring structure FW can provide a PN diode.

[0084] Reference FIG. 1 and FIG. 6 In a semiconductor device according to some embodiments, the bulk semiconductor pattern 110 may include a second well region WR2 and a third well region WR3.

[0085] The second well region WR2 may have a first conductivity type. For example, the second well region WR2 may be an n-type doped region “n” formed by doping an n-type impurity (e.g., P, Sb or As) in the bulk semiconductor pattern 110.

[0086] The third well region WR3 may have a second conductivity type. For example, the third well region WR3 may be a p-type doped region “p” formed by doping a p-type impurity (e.g., B, In, Ga, or Al) in the bulk semiconductor pattern 110.

[0087] The second well region WR2 and the third well region WR3 can be directly connected to each other. For example, as FIG. 6 As shown, the second well region WR2 and the third well region WR3 can be joined to each other in the first direction X. Therefore, the second well region WR2 and the third well region WR3 can form a PN junction in the bulk semiconductor pattern 110.

[0088] In some embodiments, the stacked structure SS may include a second doped region IR2 and a third doped region IR3.

[0089] The second doped region IR2 may have a first conductivity type. For example, the second doped region IR2 may be a heavily doped n-type doped region n+ formed by doping a heavily doped n-type impurity (e.g., P, Sb, or As) in the stacked structure SS. The second doped region IR2 may be formed across the body semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The second doped region IR2 may be directly connected to the second well region WR2.

[0090] The third doped region IR3 may have a second conductivity type. For example, the third doped region IR3 may be a heavily doped p-type doped region p+ formed by doping a heavily doped p-type impurity (e.g., B, In, Ga, or Al) in the stacked structure SS. The third doped region IR3 may be formed across the body semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The third doped region IR3 may be directly connected to the third well region WR3.

[0091] The second doped region IR2 can electrically connect the second well region WR2 to the front wiring structure FW. A predetermined voltage can be applied to the second well region WR2 through the front wiring structure FW and the second doped region IR2.

[0092] The third doped region IR3 can electrically connect the third well region WR3 to the front wiring structure FW. A predetermined voltage can be applied to the third well region WR3 through the front wiring structure FW and the third doped region IR3.

[0093] In some embodiments, the second well region WR2, the third well region WR3, and the front wiring structure FW can provide a PN diode.

[0094] Reference FIG. 1 and FIG. 7 In a semiconductor device according to some embodiments, the bulk semiconductor pattern 110 may include a fourth well region WR4, a fifth well region WR5, and a sixth well region WR6.

[0095] The fourth well region WR4 may be formed in the first portion P1 of the bulk semiconductor pattern 110. The fourth well region WR4 may have a second conductivity type. For example, the fourth well region WR4 may be a p-type doped region “p” formed by doping the bulk semiconductor pattern 110 with a p-type impurity (e.g., B, In, Ga, or Al).

[0096] The fifth well region WR5 may be formed in the second portion P2 of the bulk semiconductor pattern 110. The fifth well region WR5 may have a first conductivity type. For example, the fifth well region WR5 may be an n-type doped region “n” formed by doping the bulk semiconductor pattern 110 with an n-type impurity (e.g., P, Sb, or As).

[0097] The sixth well region WR6 may be formed in the third portion P3 of the bulk semiconductor pattern 110. The sixth well region WR6 may have a second conductivity type. For example, the sixth well region WR6 may be a p-type doped region “p” formed by doping the bulk semiconductor pattern 110 with a p-type impurity (e.g., B, In, Ga, or Al).

[0098] The fourth well region WR4 and the fifth well region WR5 can be directly connected to each other. For example, as shown... FIG. 7As shown, the fourth well region WR4 and the fifth well region WR5 can be joined to each other in the first direction X. Therefore, the fourth well region WR4 and the fifth well region WR5 can form a PN junction in the bulk semiconductor pattern 110.

[0099] The fifth well region WR5 and the sixth well region WR6 can be directly connected to each other. For example, as shown... FIG. 7 As shown, the fifth well region WR5 and the sixth well region WR6 can be joined to each other in the first direction X. Therefore, the fifth well region WR5 and the sixth well region WR6 can form a PN junction in the bulk semiconductor pattern 110.

[0100] In some embodiments, the stacked structure SS may include a first doped region IR1, a second doped region IR2, and a third doped region IR3.

[0101] The first doped region IR1 may have a first conductivity type. For example, the first doped region IR1 may be a heavily doped n-type doped region n+ formed by doping a heavily doped n-type impurity (e.g., P, Sb, or As) in the stacked structure SS. The first doped region IR1 may be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The first doped region IR1 may be directly connected to the fifth well region WR5.

[0102] The second doped region IR2 can have a second conductivity type. For example, the second doped region IR2 can be a heavily doped p-type doped region p+ formed by doping heavily doped p-type impurities (e.g., B, In, Ga, or Al) in the stacked structure SS. The second doped region IR2 can be formed across the body semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The second doped region IR2 can be directly connected to the fourth well region WR4.

[0103] The third doped region IR3 may have a second conductivity type. For example, the third doped region IR3 may be a heavily doped p-type doped region p+ formed by doping heavily doped p-type impurities (e.g., B, In, Ga, or Al) in the stacked structure SS. The third doped region IR3 may be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The third doped region IR3 may be directly connected to the sixth well region WR6.

[0104] The first doped region IR1 can electrically connect the fifth well region WR5 to the front wiring structure FW. A predetermined voltage can be applied to the fifth well region WR5 through the front wiring structure FW and the first doped region IR1.

[0105] The second doped region IR2 can electrically connect the fourth well region WR4 to the front wiring structure FW. A predetermined voltage can be applied to the fourth well region WR4 through the front wiring structure FW and the second doped region IR2.

[0106] The third doped region IR3 can electrically connect the sixth well region WR6 to the front wiring structure FW. A predetermined voltage can be applied to the sixth well region WR6 through the front wiring structure FW and the third doped region IR3.

[0107] In some embodiments, the fourth well region WR4, the fifth well region WR5, the sixth well region WR6, and the front wiring structure FW can provide bipolar junction transistors (e.g., PNP transistors).

[0108] Reference FIG. 1 and FIG. 8 In a semiconductor device according to some embodiments, the bulk semiconductor pattern 110 may include a seventh well region WR7 and an eighth well region WR8.

[0109] The seventh well region WR7 may be formed in the first portion P1 and the second portion P2 of the bulk semiconductor pattern 110. The seventh well region WR7 may have a first conductivity type. For example, the seventh well region WR7 may be an n-type doped region “n” formed by doping the bulk semiconductor pattern 110 with an n-type impurity (e.g., P, Sb or As).

[0110] The eighth well region WR8 may be formed in the third portion P3 of the bulk semiconductor pattern 110. The eighth well region WR8 may have a second conductivity type. For example, the eighth well region WR8 may be a p-type doped region “p” formed by doping the bulk semiconductor pattern 110 with a p-type impurity (e.g., B, In, Ga, or Al).

[0111] The seventh well region WR7 and the eighth well region WR8 can be directly connected to each other. For example, as shown... FIG. 8 As shown, the seventh well region WR7 and the eighth well region WR8 can be joined to each other in the first direction X. Therefore, the seventh well region WR7 and the eighth well region WR8 can form a PN junction in the bulk semiconductor pattern 110.

[0112] In some embodiments, the stacked structure SS may include a first doped region IR1, a second doped region IR2, and a third doped region IR3.

[0113] The first doped region IR1 may have a first conductivity type. For example, the first doped region IR1 may be a heavily doped n-type doped region n+ formed by doping a heavily doped n-type impurity (e.g., P, Sb, or As) in the stacked structure SS. The first doped region IR1 may be formed across the body semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The first doped region IR1 may be directly connected to the seventh well region WR7.

[0114] The second doped region IR2 can have a second conductivity type. For example, the second doped region IR2 can be a heavily doped p-type doped region p+ formed by doping a heavily doped p-type impurity (e.g., B, In, Ga, or Al) in the stacked structure SS. The second doped region IR2 can be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The second doped region IR2 can be directly connected to the seventh well region WR7. Therefore, the seventh well region WR7 and the second doped region IR2 can form a PN junction in the bulk semiconductor pattern 110.

[0115] The third doped region IR3 may have a second conductivity type. For example, the third doped region IR3 may be a heavily doped p-type doped region p+ formed by doping a heavily doped p-type impurity (e.g., B, In, Ga, or Al) in the stacked structure SS. The third doped region IR3 may be formed across the body semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The third doped region IR3 may be directly connected to the eighth well region WR8.

[0116] The first doped region IR1 can electrically connect the seventh well region WR7 to the front wiring structure FW. A predetermined voltage can be applied to the seventh well region WR7 through the front wiring structure FW and the first doped region IR1.

[0117] The third doped region IR3 can electrically connect the eighth well region WR8 to the front wiring structure FW. A predetermined voltage can be applied to the eighth well region WR8 through the front wiring structure FW and the third doped region IR3.

[0118] In some embodiments, the second doped region IR2, the seventh well region WR7, the eighth well region WR8, and the front wiring structure FW can provide a bipolar junction transistor (e.g., a PNP transistor).

[0119] Reference FIG. 9 The semiconductor device according to some embodiments may also include a second epitaxial pattern 165.

[0120] The second epitaxial pattern 165 can be formed on the stacked structure SS. In some embodiments, the second epitaxial pattern 165 can be formed on a second portion P2 of the stacked structure SS. For example, the second epitaxial pattern 165 can be formed in the stacked structure SS between the second gate structure G12 and the third gate structure G13. The second epitaxial pattern 165 can be connected to the upper surface of the bulk semiconductor pattern 110, the side surface of the first sacrificial film 310, and the side surface of the first semiconductor films 111 to 113. The second epitaxial pattern 165 can be separated from the first gate electrode 130 through the first gate dielectric film 120 and / or the first gate spacer 140. In some embodiments, the lowermost surface of the second epitaxial pattern 165 can be positioned below the uppermost surface of the bulk semiconductor pattern 110.

[0121] The second epitaxial pattern 165 may include an epitaxial layer doped with impurities. For example, the second epitaxial pattern 165 may be an epitaxial layer grown from the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113 by an epitaxial growth process.

[0122] In some embodiments, the second epitaxial pattern 165 may have a second conductivity type. For example, the second epitaxial pattern 165 may include p-type impurities (e.g., B, In, Ga, or Al) and / or impurities for preventing the diffusion of p-type impurities.

[0123] In some embodiments, the second epitaxial pattern 165 may further include a compressive stress material. For example, when each of the first semiconductor films 111 to 113 is a silicon (Si) film, the second epitaxial pattern 165 may include a material having a lattice constant greater than that of silicon (Si) (e.g., silicon germanium (SiGe)).

[0124] The second epitaxial pattern 165 can be directly connected to the first well region WR1. In some embodiments, the second epitaxial pattern 165 can be a heavily doped p-type doped region p+ formed by doping with heavily doped p-type impurities. Therefore, the first well region WR1 and the second epitaxial pattern 165 can form a PN junction in the bulk semiconductor pattern 110.

[0125] The second epitaxial pattern 165 may be electrically connected to the front wiring structure FW and / or the back wiring structure BW. For example, a first contact pattern 190 connecting the second epitaxial pattern 165 to a portion of the front wiring pattern FM may be formed through a first interlayer insulating film 180. A predetermined voltage may be applied to the second epitaxial pattern 165 through the front wiring structure FW.

[0126] In some embodiments, the first well region WR1, the second epitaxial pattern 165, and the front wiring structure FW can provide a PN diode.

[0127] Reference FIG. 1 and FIG. 10 In a semiconductor device according to some embodiments, the bulk semiconductor pattern 110 may include a ninth well region WR9 and a tenth well region WR10.

[0128] The ninth well region WR9 may have a first conductivity type. For example, the ninth well region WR9 may be an n-type doped region “n” formed by doping an n-type impurity (e.g., P, Sb or As) in the bulk semiconductor pattern 110.

[0129] The tenth well region WR10 may have a second conductivity type. For example, the tenth well region WR10 may be a p-type doped region “p” formed by doping a p-type impurity (e.g., B, In, Ga or Al) in the bulk semiconductor pattern 110.

[0130] The ninth well region WR9 and the tenth well region WR10 can be directly connected to each other. For example, as shown... FIG. 10 As shown, the ninth well region WR9 and the tenth well region WR10 can be bonded to each other in the second direction Y. Therefore, the ninth well region WR9 and the tenth well region WR10 can form a PN junction in the bulk semiconductor pattern 110.

[0131] In some embodiments, the stacked structure SS may include a fourth doped region IR4 and a fifth doped region IR5.

[0132] The fourth doped region IR4 can have a first conductivity type. For example, the fourth doped region IR4 can be a heavily doped n-type doped region n+ formed by doping a heavily doped n-type impurity (e.g., P, Sb, or As) in the stacked structure SS. The fourth doped region IR4 can be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The fourth doped region IR4 can be directly connected to the ninth well region WR9.

[0133] The fifth doped region IR5 can have a second conductivity type. For example, the fifth doped region IR5 can be a heavily doped p-type doped region p+ formed by doping heavily doped p-type impurities (e.g., B, In, Ga, or Al) in the stacked structure SS. The fifth doped region IR5 can be formed across the bulk semiconductor pattern 110, the first sacrificial film 310, and the first semiconductor films 111 to 113. The fifth doped region IR5 can be directly connected to the tenth well region WR10.

[0134] The fourth doped region IR4 can electrically connect the ninth well region WR9 to the front wiring structure FW. A predetermined voltage can be applied to the ninth well region WR9 through the front wiring structure FW and the fourth doped region IR4.

[0135] The fifth doped region IR5 can electrically connect the tenth well region WR10 to the front wiring structure FW. A predetermined voltage can be applied to the tenth well region WR10 through the front wiring structure FW and the fifth doped region IR5.

[0136] In some embodiments, the ninth well region WR9, the tenth well region WR10, and the front wiring structure FW can provide PN diodes.

[0137] FIG. 11 This is an example layout diagram illustrating a semiconductor device according to some embodiments. FIG. 12A to FIG. 12B Show along FIG. 11 The cross-sectional view taken by lines A1-A1 and A2-A2. FIG. 13A to FIG. 13B Show along FIG. 11 The cross-sectional view taken from lines B1-B1 and B2-B2. FIG. 14A to FIG. 14B Show along FIG. 11The cross-sectional views are taken from lines C1-C1 and C2-C2. For ease of description, the above references may be briefly provided or omitted. FIG. 1 to FIG. 10 The given redundant description.

[0138] Reference FIG. 11 to FIG. 14B According to some embodiments, the semiconductor device includes a first region I and a second region II.

[0139] Zone I and Zone II can be adjacent to each other or spaced apart from each other. Although Zone I and Zone II are shown arranged along a first direction X, this is only an example, and Zone I and Zone II can be arranged along various other directions (e.g., a second direction Y).

[0140] In some embodiments, the first region I may be a region in which a bandgap reference (BGR) generation circuit, an electrostatic discharge (ESD) protection circuit, a protection diode such as a transient voltage suppression (TVS) diode or a Zener diode, and / or a passive device such as a temperature sensor are disposed. In some embodiments, the second region II may be a region in which an active device such as a transistor is disposed.

[0141] The stacked structure SS, the first device isolation pattern 105, the first gate structure G11 to the fourth gate structure G14, the first epitaxial pattern 160, and the first interlayer insulating film 180 can be formed in the first region I. Although only referenced... FIG. 1 to FIG. 4 The semiconductor device described is formed in the first region I, but this is merely an example, and those skilled in the art with knowledge of the art to which this disclosure relates will understand that, with reference to FIG. 5 to FIG. 10 The semiconductor device described can be formed in the first region I.

[0142] Multiple active patterns AP, a second device isolation pattern 205, a fifth gate structure G2, a third epitaxial pattern 260, and a second interlayer insulating film 280 can be formed in the second region II.

[0143] Multiple active patterned APs may be spaced apart from each other in the second direction Y. Each active patterned AP may be elongated in the first direction X. Each active patterned AP may include a fin pattern 210 and multiple second semiconductor films 211 to 213.

[0144] The fin pattern 210 can be positioned at the same horizontal level as the bulk semiconductor pattern 110. In this specification, "positioned at the same horizontal level" means "at the same height in the vertical direction (e.g., the third direction Z)". For example, the lower surface of the fin pattern 210 can be positioned coplanar with the lower surface of the bulk semiconductor pattern 110, and the upper surface of the fin pattern 210 can be positioned coplanar with the upper surface of the bulk semiconductor pattern 110.

[0145] The fin pattern 210 can be formed in the same process as the bulk semiconductor pattern 110. In this specification, "formed in the same process" means "formed by the same manufacturing process". For example, the fin pattern 210 may have the same material (or the same material configuration) as the bulk semiconductor pattern 110.

[0146] Multiple second semiconductor films 211 to 213 may be stacked on the upper surface of the fin pattern 210 at intervals from each other. Each of the second semiconductor films 211 to 213 may be elongated in a first direction X and may be spaced apart from each other in a third direction Z. The second semiconductor films 211 to 213 may be used as a multi-bridge channel on the second region II. The channel region. The number, shape, arrangement, etc. of the second semiconductor films 211 to 213 are merely examples and are not limited to the examples shown.

[0147] The plurality of second semiconductor films 211 to 213 can be positioned at the same level as the plurality of first semiconductor films 111 to 113. The plurality of second semiconductor films 211 to 213 can be formed in the same process as the plurality of first semiconductor films 111 to 113.

[0148] The second device isolation pattern 205 may cover at least a portion of the side of each active pattern AP. For example, as shown, the second device isolation pattern 205 may cover a portion of the side of the fin pattern 210.

[0149] The second device isolation pattern 205 can be positioned at the same level as the first device isolation pattern 105. The second device isolation pattern 205 can be formed in the same process as the first device isolation pattern 105.

[0150] The active pattern AP can have a shape defined by active pattern APs separated by the second device isolation pattern 205. For example, the width W1 of the stacked structure SS in the second direction Y can be greater than the width W2 of each active pattern AP in the second direction Y. In some embodiments, the stacked structure SS can overlap with a plurality of active pattern APs in the first direction X.

[0151] A fifth gate structure G2 may be formed on the active pattern AP and the second device isolation pattern 205. The fifth gate structure G2 may intersect with the active pattern AP. For example, the fifth gate structure G2 may extend along the second direction Y. Each of the second semiconductor films 211 to 213 may extend along the first direction X to pass through the fifth gate structure G2. A plurality of fifth gate structures G2 may be spaced apart from each other in the first direction X.

[0152] The fifth gate structure G2 may include a second gate dielectric film 220, a second gate electrode 230, a second gate spacer 240, and a second gate capping film 250. The fifth gate structure G2 may be positioned at the same level as the first gate structures G11 to the fourth gate structures G14. The fifth gate structure G2 may be formed in the same process as the first gate structures G11 to the fourth gate structures G14. Since the second gate dielectric film 220, the second gate electrode 230, the second gate spacer 240, and the second gate capping film 250 can be similar to the first gate dielectric film 120, the first gate electrode 130, the first gate spacer 140, and the first gate capping film 150, respectively, repeated descriptions of them can be omitted below.

[0153] The third epitaxial pattern 260 can be formed on the active pattern AP. For example, the third epitaxial pattern 260 can be formed on at least one side of the fifth gate structure G2 in the active pattern AP. The third epitaxial pattern 260 can be connected to the upper surface of the fin pattern 210 and the sides of the second semiconductor films 211 to 213. The third epitaxial pattern 260 can be separated from the second gate electrode 230 through the second gate dielectric film 220 and / or the second gate spacer 240. In some embodiments, the lowermost surface of the third epitaxial pattern 260 can be positioned below the uppermost surface of the fin pattern 210.

[0154] The third epitaxial pattern 260 may include an epitaxial layer doped with impurities. For example, the third epitaxial pattern 260 may be an epitaxial layer grown from the fin pattern 210 and the second semiconductor films 211 to 213 by an epitaxial growth process.

[0155] When the second region II is an NFET region, the third epitaxial pattern 260 may include n-type impurities (e.g., P, Sb, or As) and / or impurities to prevent the diffusion of n-type impurities. In some embodiments, the third epitaxial pattern 260 may also include a tensile stress material. For example, when each of the second semiconductor films 211 to 213 is a silicon (Si) pattern, the third epitaxial pattern 260 may include a material having a smaller lattice constant than silicon (Si) (e.g., silicon carbide (SiC)).

[0156] When the second region II is a PFET region, the third epitaxial pattern 260 may include p-type impurities (e.g., B, In, Ga, or Al) and / or impurities to prevent the diffusion of p-type impurities. In some embodiments, the third epitaxial pattern 260 may also include a compressive stress material. For example, when each of the second semiconductor films 211 to 213 is a silicon (Si) pattern, the third epitaxial pattern 260 may include a material having a lattice constant larger than that of silicon (Si) (e.g., silicon-germanium (SiGe)).

[0157] like FIG. 14BAs shown, in the cross-section intersecting the first direction X, the third epitaxial pattern 260 is shown as a hexagon, but this is only an example. Depending on the conditions of the epitaxial growth process, the third epitaxial pattern 260 can have various cross-sections, such as pentagons and rhombuses.

[0158] The second interlayer insulating film 280 can be formed on the active pattern AP, the second device isolation pattern 205, the fifth gate structure G2, and the third epitaxial pattern 260. The second interlayer insulating film 280 can be formed to fill the space on the outer side of the fifth gate structure G2.

[0159] The second interlayer insulating film 280 can be positioned at the same level as the first interlayer insulating film 180. The second interlayer insulating film 280 can be formed in the same process as the first interlayer insulating film 180.

[0160] The third epitaxial pattern 260 may be electrically connected to the front wiring structure FW and / or the back wiring structure BW. For example, the second contact pattern 290, which connects the third epitaxial pattern 260 to a portion of the front wiring pattern FM, may be formed through the second interlayer insulating film 280.

[0161] In the following text, reference will be made to FIG. 1 to FIG. 36B A method for manufacturing a semiconductor device according to an example embodiment is described.

[0162] FIG. 15 to FIG. 36B This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. For ease of description, the above references may be provided briefly or omitted. FIG. 1 to FIG. 14B The given redundant description.

[0163] Reference FIG. 15 and FIG. 16A to FIG. 16B A first well region WR1 can be formed in the substrate 100.

[0164] The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include another material such as, for example, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In the following description, by way of example, the substrate 100 is a silicon (Si) substrate.

[0165] A first well region WR1 may be formed in the substrate 100 of the first region I. For example, an ion implantation process for doping an n-type impurity (e.g., P, Sb, or As) in the substrate 100 of the first region I may be performed.

[0166] Although the substrate 100 in region II is shown as undoped, this is merely an example. As another example, when region II is a PFET region, the substrate 100 in region II may also be doped with n-type impurities (e.g., P, Sb, or As).

[0167] Reference FIG. 17 to FIG. 19B A stacked structure SS can be formed in the first region I, and multiple fin structures FS can be formed in the second region II.

[0168] For example, sacrificial films and semiconductor films can be alternately stacked on the upper surface of the substrate 100. The sacrificial films may include materials that are etch-selective relative to the semiconductor films. For example, each semiconductor film may be a silicon (Si) film, and each sacrificial film may be a silicon-germanium (SiGe) film. Subsequently, a patterning process can be performed to pattern the substrate 100, the sacrificial films, and the semiconductor films. As a result, a stacked structure SS, including a bulk semiconductor pattern 110, a plurality of first sacrificial films 310, and a plurality of first semiconductor films 111 to 113, can be formed on the substrate 100 in the first region I. Furthermore, a plurality of fin structures FS, each including a fin pattern 210, a plurality of second sacrificial films 320, and a plurality of second semiconductor films 211 to 213, can be formed on the substrate 100 in the second region II. Each of the bulk semiconductor pattern 110 and the fin pattern 210 can be formed by etching a portion of the substrate 100.

[0169] After forming the stacked structure SS and multiple fin structures FS, a first device isolation pattern 105 and a second device isolation pattern 205 can be formed. The first device isolation pattern 105 can cover at least a portion of the side surface of the stacked structure SS. The second device isolation pattern 205 can cover at least a portion of the side surface of each fin structure FS.

[0170] Reference FIG. 20 to FIG. 22B Multiple first pseudo-gate structures DG1 can be formed on the stacked structure SS, and multiple second pseudo-gate structures DG2 can be formed on the fin structure FS.

[0171] Each of the first pseudo-gate structures DG1 may intersect with the stacked structure SS. Each of the second pseudo-gate structures DG2 may intersect with the fin structure FS. For example, each of the first pseudo-gate structures DG1 and the second pseudo-gate structures DG2 may extend in the second direction Y.

[0172] Each of the first dummy gate structures DG1 may include a dummy gate electrode 330, a mask pattern 350, and a first gate spacer 140. Each of the second dummy gate structures DG2 may include a dummy gate electrode 330, a mask pattern 350, and a second gate spacer 240. A material film can be formed on the stacked structure SS and the fin structure FS. Subsequently, a mask pattern 350 extending in the second direction Y can be formed on the material film. Subsequently, the mask pattern 350 can be used as an etching mask to perform a patterning process for patterning the material film. As a result, the dummy gate electrode 330 can be formed from the material film. The first gate spacer 140 may extend along the side of the dummy gate electrode 330 on the stacked structure SS. The second gate spacer 240 may extend along the side of the dummy gate electrode 330 on the fin structure FS.

[0173] The dummy gate electrode 330 may include a material that has etch selectivity relative to the first semiconductor films 111 to 113 and the second semiconductor films 211 to 213. For example, the dummy gate electrode 330 may be a polysilicon pattern.

[0174] Reference FIG. 23A to FIG. 23B It can form at least one first source / drain recess 160r and at least one second source / drain recess 260r.

[0175] At least one first source / drain recess 160r can be formed in the first portion P1 and the third portion P3 of the stacked structure SS. At least one second source / drain recess 260r can be formed in each of the fin structures FS. In the process of forming at least one first source / drain recess 160r and at least one second source / drain recess 260r, the second portion P2 of the stacked structure SS can be protected. For example, a masking process can be performed to selectively expose the first portion P1 and the third portion P3 of the stacked structure SS and the fin structure FS while covering the second portion P2 of the stacked structure SS. Subsequently, a recessing process can be performed on the first portion P1 and the third portion P3 of the stacked structure SS and the fin structure FS by using the first pseudo-gate structure DG1 and the second pseudo-gate structure DG2 as etching masks.

[0176] Reference FIG. 24A to FIG. 24B This can form a first extensional pattern 160 and a third extensional pattern 260.

[0177] The first outer pattern 160 can be filled. FIG. 23A The first source / drain recess 160r. For example, the first epitaxial pattern 160 can be grown from the bulk semiconductor pattern 110, the first sacrificial film 310 and the first semiconductor films 111 to 113 by an epitaxial growth process.

[0178] The third outer pattern 260 can be filled. FIG. 23BThe second source / drain recess 260r. For example, the third epitaxial pattern 260 can be grown from the fin pattern 210, the second sacrificial film 320, and the second semiconductor films 211 to 213 by an epitaxial growth process.

[0179] The first epitaxial pattern 160 and the third epitaxial pattern 260 can be formed in the same process or in different processes. In some embodiments, when the first epitaxial pattern 160 and the third epitaxial pattern 260 have the same conductivity type (e.g., a first conductivity type), the first epitaxial pattern 160 and the third epitaxial pattern 260 can be formed in the same process.

[0180] Reference FIG. 25 and FIG. 26A to FIG. 26B This can form the first doped region IR1.

[0181] A first doped region IR1 can be formed in the second portion P2 of the stacked structure SS. For example, an ion implantation process can be performed to dope the second portion P2 of the stacked structure SS with a heavily doped p-type impurity (e.g., B, In, Ga, or Al).

[0182] Reference FIG. 27A to FIG. 27B This can remove the dummy gate electrode 330.

[0183] For example, a first interlayer insulating film 180 filling the space on the outer side of the first dummy gate structure DG1 and a second interlayer insulating film 280 filling the space on the outer side of the second dummy gate structure DG2 can be formed. Subsequently, a planarization process for exposing the dummy gate electrode 330 can be performed. The dummy gate electrode 330 exposed by the planarization process can be selectively removed relative to the first semiconductor films 111 to 113 and the second semiconductor films 211 to 213.

[0184] Reference FIG. 28A to FIG. 28B and FIG. 29A to FIG. 29B It can remove the second sacrificial membrane 320.

[0185] The second sacrificial film 320 can be selectively removed relative to the second semiconductor films 211 to 213. In the process of removing the second sacrificial film 320, the first sacrificial film 310 may not be completely removed. Specifically, unlike the fin structure FS divided by the second device isolation pattern 205, the stacked structure SS may have a blocky shape not divided by the first device isolation pattern 105. Therefore, the etchant used in the etching process for removing the second sacrificial film 320 may not easily remove the first sacrificial film 310.

[0186] In some embodiments, each of the first sacrificial films 310 may include a first recess 310r1 and a second recess 310r2. The first recess 310r1 and the second recess 310r2 may be formed by removing a portion of the first sacrificial film 310 exposed in an etching process for removing the second sacrificial film 320.

[0187] Reference FIG. 30 to FIG. 32B This can form the first gate structure G11 to the fourth gate structure G14 and the fifth gate structure G2.

[0188] For example, a dielectric film and a conductive film can be sequentially stacked in the region where the dummy gate electrode 330 has been removed and in the region where the second sacrificial film 320 has been removed. Furthermore, a capping film can be formed covering the upper surface of the conductive film. As a result, first gate structures G11 to fourth gate structures G14, including a first gate dielectric film 120, a first gate electrode 130, a first gate spacer 140, and a first gate capping film 150, can be formed. Furthermore, a fifth gate structure G2, including a second gate dielectric film 220, a second gate electrode 230, a second gate spacer 240, and a second gate capping film 250, can be formed.

[0189] Reference FIG. 33A to FIG. 33B This can form a first contact pattern 190, a second contact pattern 290, and a front wiring structure FW.

[0190] The first contact pattern 190 can be connected to the first epitaxial pattern 160 and / or the first doped region IR1. The second contact pattern 290 can be connected to the third epitaxial pattern 260. The front wiring structure FW can be electrically connected to the first contact pattern 190 and / or the second contact pattern 290.

[0191] Reference FIG. 34A to FIG. 34B The front wiring structure FW can be attached to the carrier substrate 400.

[0192] For example, the carrier substrate 400 can be attached to FIG. 33A to FIG. 33B On the product. After attaching the carrier substrate 400, it can be flipped. FIG. 33A to FIG. 33B The product of.

[0193] Reference FIG. 35A to FIG. 35B The substrate 100 can be removed.

[0194] For example, a thinning process can be performed on the substrate 100. The thinning process may include, for example, a back-side grinding process for the back side of the substrate 100, but is not limited thereto. When the thinning process is performed, a first device isolation pattern 105 and / or a second device isolation pattern 205 may be exposed. In some embodiments, the surface of the first device isolation pattern 105 may be configured to be coplanar with the surface of the bulk semiconductor pattern 110.

[0195] Reference FIG. 36A to FIG. 36B A back-side wiring structure BW can be formed on the bulk semiconductor pattern 110, the first device isolation pattern 105, the fin pattern 210, and the second device isolation pattern 205.

[0196] Subsequently, referring to FIG. 2 This allows for the removal of the carrier substrate 400. As a result, a reference can be fabricated. FIG. 1 to FIG. 4 The semiconductor device described.

[0197] Although non-limiting exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure. These exemplary embodiments should be considered illustrative rather than restrictive in all respects.

Claims

1. A semiconductor device, comprising: The stacked structure includes: A bulk semiconductor pattern, which includes a first well region; A sacrificial film, on the upper surface of the bulk semiconductor pattern; and A semiconductor film on the upper surface of the sacrificial film; Device isolation patterns are present on the sides of the stacked structure; and The back-side wiring structure is located on the lower surface of the bulk semiconductor pattern and the lower surface of the device isolation pattern. The stacked structure further includes a first doped region extending across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film, and the first doped region is connected to the first well region. The first doped region is spaced apart from the lower surface of the bulk semiconductor pattern.

2. The semiconductor device according to claim 1, wherein, The first well region has a first conductivity type, and The first doped region has a second conductivity type that is different from the first conductivity type.

3. The semiconductor device according to claim 2, wherein, The stacked structure further includes a second doped region extending across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film, and the second doped region is connected to the first well region. The second doped region has the first conductivity type.

4. The semiconductor device according to claim 3, wherein, The doping concentration of the second doped region is higher than that of the first well region.

5. The semiconductor device according to claim 1, wherein, The bulk semiconductor pattern also includes a second well region connected to the first well region. Wherein, the first well region has a first conductivity type, and The second well region has a second conductivity type that is different from the first conductivity type.

6. The semiconductor device according to claim 5, wherein, The first well region and the second well region are arranged relative to each other along a horizontal direction parallel to the upper surface of the bulk semiconductor pattern.

7. The semiconductor device according to claim 1, wherein, The lower surface of the bulk semiconductor pattern is coplanar with or higher than the lower surface of the device isolation pattern.

8. The semiconductor device according to claim 1, wherein, The bulk semiconductor pattern includes a silicon pattern.

9. The semiconductor device according to claim 1, wherein, The sacrificial film comprises a silicon-germanium film, and The semiconductor film includes a silicon film.

10. The semiconductor device according to claim 1, wherein, The first doped region is formed by ion implantation of the stacked structure.

11. A semiconductor device, comprising: The stacked structure includes: A bulk semiconductor pattern, comprising a first well region having a first conductivity type; A sacrificial film, on the upper surface of the bulk semiconductor pattern; and A semiconductor film on the upper surface of the sacrificial film; Device isolation patterns are present on the sides of the stacked structure; A gate structure is located on the stacked structure and the device isolation pattern, and intersects with the stacked structure. The stacked structure further includes a first doped region on a first side of the gate structure, the first doped region being connected to the first well region and having a second conductivity type different from the first conductivity type. The first doped region extends across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film.

12. The semiconductor device of claim 11, further comprising an epitaxial pattern located on a second side of the gate structure opposite to the first side in the stacked structure, the epitaxial pattern being connected to the first well region and having the first conductivity type.

13. The semiconductor device of claim 11, further comprising a second doped region on a second side of the gate structure, the second doped region being connected to the first well region and having the first conductivity type, and in, The second doped region extends across the bulk semiconductor pattern, the sacrificial film, and the semiconductor film.

14. The semiconductor device according to claim 13, wherein, The doping concentration of the second doped region is higher than that of the first well region.

15. The semiconductor device of claim 11, further comprising a back-side wiring structure on the lower surface of the bulk semiconductor pattern and the lower surface of the device isolation pattern.

16. The semiconductor device according to claim 11, wherein, The side of the sacrificial film facing the gate structure includes a recess that extends beyond the side of the semiconductor film facing the gate structure.

17. A semiconductor device, comprising: A stacked structure, located in a first region of the semiconductor device, the stacked structure comprising: Bulk semiconductor pattern; A sacrificial film, on the upper surface of the bulk semiconductor pattern; and A first semiconductor film is disposed on the upper surface of the sacrificial film; An active pattern includes a fin pattern and a second semiconductor film located in a second region of the semiconductor device, the fin pattern extending in a first direction and the second semiconductor film extending in the first direction and spaced apart from the upper surface of the fin pattern; Device isolation patterns are located on the sides of the bulk semiconductor pattern and the sides of the fin pattern; A first gate structure is located on the stacked structure and the device isolation pattern, and intersects with the stacked structure; A second gate structure is provided on the active pattern and the device isolation pattern, and extends in a second direction intersecting the first direction; and The back-side wiring structure is located on the lower surface of the bulk semiconductor pattern, the lower surface of the fin pattern, and the lower surface of the device isolation pattern. Wherein, the bulk semiconductor pattern and the fin pattern are at the same level, and the first semiconductor film and the second semiconductor film are at the same level. The stacked structure further includes a PN junction at a horizontal position between the lower surface of the device isolation pattern and the upper surface of the bulk semiconductor pattern.

18. The semiconductor device according to claim 17, wherein, Each of the lower surface of the bulk semiconductor pattern and the lower surface of the fin pattern is coplanar with or higher than the lower surface of the device isolation pattern.

19. The semiconductor device according to claim 17, wherein, The PN junction includes: A well region, located within the bulk semiconductor pattern and having a first conductivity type; and The doped region extends across the bulk semiconductor pattern, the sacrificial film, and the first semiconductor film, and The doped region has a second conductivity type that is different from the first conductivity type.

20. The semiconductor device according to claim 17, wherein, The PN junction includes: A first well region, located within the bulk semiconductor pattern and having a first conductivity type; and The second well region is located in the bulk semiconductor pattern and has a second conductivity type different from the first conductivity type.

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