Semiconductor die with vertical transistor device

Abstract

The invention relates to a semiconductor die (1) having a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20); an additional transistor device (40) comprising a channel region (43.1) configured for vertical current flow; an isolation trench (60) extending into the semiconductor body (10); an isolation well (70) made of a second doping type; the isolation well (70) is vertically arranged below the additional transistor device (40), the isolation trench (60) is laterally arranged between the additional transistor device (40) and the vertical transistor device (20), and the isolation trench (60) extends to a depth (65) vertically between an upper end (70.1) of the isolation well (70) and a second side (10.2) of the semiconductor body (10).

Description

Technical Field

[0001] This disclosure relates to semiconductor dies having a semiconductor body, including vertical transistor devices. Background Technology

[0002] A vertical transistor device may have a first vertical load region on a first side of a semiconductor body and a second vertical load region on a vertically opposite second side of the semiconductor body, such as a source region on the first side and a drain region on the second side. The first and second vertical load regions may be made of a first doping type, for example, combined with a body region vertically arranged therebetween and made of a second doping type. Summary of the Invention

[0003] Examples of this application relate to advantageous semiconductor dies having a semiconductor body.

[0004] In one embodiment, in addition to the vertical transistor devices, the semiconductor die also includes additional transistor devices, with isolation trenches laterally arranged between the devices. Furthermore, an isolation well made of a second doping type is formed in the semiconductor body. It is disposed below the additional transistor devices, for example, vertically between the additional transistor devices and a second side of the semiconductor body, wherein the second side may be made of a first doping type. For example, a region of the first doping type, such as a semiconductor substrate, may form the second side, with the isolation well disposed above this region. For example, referring to a vertical position at the upper end of the isolation well, the isolation trench may extend to a depth vertically located between this upper end and the second side of the semiconductor body.

[0005] In other words, the isolation trench may extend at least into the isolation trap, but not completely through the semiconductor body; for example, it may not extend all the way down to the second side of the semiconductor body. The lower end of the isolation trench may, for example, be positioned below the upper end of the isolation trap and above the second side of the semiconductor body, for example, at a vertical distance below the upper end of the isolation trap and a vertical distance above the second side of the semiconductor body. An isolation trench terminating above the second side of the semiconductor body, for example, not completely intersecting the semiconductor body (e.g., not extending through the substrate of the semiconductor body), may, for example, reduce manufacturing effort. For example, wafer thinning (e.g., back-side grinding) may be less critical, for example, for wafer processing in subsequent steps.

[0006] Isolation trenches can provide lateral isolation, and isolation wells made with a second doping type can form vertical isolation, for example, via a junction between the isolation well and a second side of the semiconductor body (e.g., the substrate or the back side of the common drain). In other words, an isolation well under an additional device can form electrical isolation from the semiconductor substrate. Combined, vertical and lateral isolation can, for example, reduce parasitic effects between devices.

[0007] Further embodiments and features are provided in and throughout the claims. While each feature is disclosed independently of a particular class of claims, this disclosure relates to apparatus and device aspects, but also to methods and uses. If, for example, a die manufactured in a particular manner is described, this also discloses the corresponding manufacturing process, and vice versa. In general, the method of this application is to provide an integrated device with combined vertical and lateral isolation within a semiconductor body.

[0008] In one embodiment, the vertical transistor device includes a first vertical load region disposed on a first side of a semiconductor body and a second vertical load region disposed on a second side of the semiconductor body opposite to the first side. The first and second vertical load regions may be made of a first doping type opposite to the second doping type, i.e., opposite to the doping type of the doped well.

[0009] The first vertical load region can be a source region, and the second vertical load region can be a drain region, wherein the drain region is disposed on a second side (“back side”) of the semiconductor body. The implantation region or layer (e.g., substrate) forming the drain region can also extend laterally in the region of the additional transistor device, and the well region forms a junction isolation facing the lower first doped type region. The additional transistor device can be laterally embedded in an isolation trench, as seen in the vertical top view, which can form a closed line around the additional transistor device (see below) and be vertically embedded in the isolation well. The additional transistor device can, for example, be connected as a pull-down device to a vertical transistor device, such as a vertical FET, for example, grounding the gate terminal of the vertical FET, as detailed below.

[0010] For example, each of the vertical and additional transistor devices includes at least one transistor device cell, wherein the transistor device cells of the vertical and additional transistor devices have, for example, the same source doping and / or the same body doping and / or the same drift region doping and / or the same trench depth and / or the same gate oxide thickness. This can allow for the reuse of processing steps, for example, reducing the integration work of the additional transistor devices. For example, the device cells of the vertical and additional transistor devices can be structurally identical (e.g., they may differ only relative to each other due to minor manufacturing differences).

[0011] The lower end of the body region of the additional transistor device may be located at the same vertical height as the lower end of the body region of the vertical transistor device. Alternatively or additionally, the lower end of the source region of the additional transistor device may be located at the same vertical height as the lower end of the source region of the vertical transistor device. Alternatively or additionally, the upper end of the drift region of the additional transistor device may be located at the same vertical height as the upper end of the drift region of the vertical transistor device. Alternatively or additionally, the lower end of the drift region of the additional transistor device may be located at the same vertical height as the lower end of the drift region of the vertical transistor device. Alternatively or additionally, the upper end of the drain region of the additional transistor device may be located below the lower end of the gate trench of the additional and / or vertical transistor device, for example, at the same vertical height as the upper end of the drain region of the vertical device.

[0012] The semiconductor body may include, for example, a semiconductor substrate made of a first doping type. In other words, the vertical transistor device and the additional transistor device may share the same semiconductor substrate, which extends, for example, in the regions of the vertical transistor device and the additional transistor device without any lateral interruption between them. One or more epitaxial semiconductor layers may be disposed on the semiconductor substrate, for example, on a first side (front side) of the semiconductor substrate. The surface of the epitaxial layer facing away from the uppermost layer of the substrate may form the first side of the semiconductor body. The second side may, for example, be a side of the substrate facing away from one or more epitaxial layers. Independent of the epitaxial layers or layer stack, the first side and the second side are those sides of the semiconductor body that are perpendicularly opposite to each other, i.e., facing away from each other with respect to the vertical direction.

[0013] The term "vertical" or "perpendicularly" refers to a vertical direction, for example, perpendicular to the surface of the die (e.g., the surface of the substrate or an epitaxial layer formed on the substrate). "Above" means closer to a first side of the semiconductor body, while "below" means closer to a second side of the semiconductor body. The "upper end" of an element or region in the semiconductor body is the end closer to the first side of the semiconductor body or placed within the first side, while the "lower end" is the end closer to the second side or placed within the second side. An isolation trench may, for example, extend from the first side into the semiconductor body, with its lower end above the second side of the semiconductor body. "Lateral" or "laterally" refers to a lateral direction perpendicular to the vertical direction, in which, for example, a die region is taken.

[0014] A first vertical load region (e.g., source region) and a second vertical load region (e.g., drain region) of a vertical device are disposed on vertically opposite sides of the semiconductor body, where "first side" may also be referred to as the front side and "second side" may be referred to as the rear side. Within the body region of the device, a channel can be formed by applying a voltage to the gate electrode of the vertical device. Even though a transistor device is generally considered "vertical" due to its vertically opposite source and drain regions, lateral channels are generally conceivable, for example, when the gate region is disposed on top of the body region (and the source region is laterally located next to the body region).

[0015] However, in one embodiment, the gate electrode of the vertical device is arranged in a gate trench laterally adjacent to the body region, and the trench extends vertically alongside the trench. Below the body region, a drift region may be arranged, for example, made of a first doping type similar to the drain region, but with a lower doping concentration (e.g., compared to the substrate). Depending on the specific device design, the first doping type may be n-type, and the second doping type may be p-type.

[0016] In one embodiment, the isolation trench extends through the isolation well, for example, intersecting the isolation well vertically (but terminating above a second side of the semiconductor body). The lower end of the isolation trench can be positioned at the same vertical height as the lower end of the isolation well, or it can be positioned below it, i.e., offset downwards from the lower end of the isolation well. This allows, for example, reduction or avoidance of parasitic effects, such as those found in pn diodes. Using an adapted trench process, for example, the isolation trench can be etched such that its lower end is at the same vertical height as the lower end of the isolation well.

[0017] As discussed above, a vertical transistor device may include a gate trench in which the gate electrode of the vertical device is disposed laterally adjacent to the body region. Alternatively or additionally, an additional transistor device may include a gate trench in which the gate electrode of the additional device is disposed laterally adjacent to the body region. In one embodiment, an isolation trench extends deeper than the gate trench of the vertical device and / or the gate trench of the additional device, with the lower end of the isolation trench disposed below the lower end of the respective gate trench. In addition to the gate electrode, the respective gate trench may include a field electrode below the gate electrode. In some embodiments, the gate trench of the vertical transistor device and the gate trench of the additional transistor device extend parallel to each other in the same direction. Alternatively or additionally, the gate trench of the vertical transistor device and the gate trench of the additional transistor device may have at least one of substantially the same depth and substantially the same width. For example, the gate trench of the vertical transistor device and the gate trench of the additional transistor device may be fabricated in the same processing step.

[0018] In one embodiment, as seen in a vertical top view, the isolation trench forms a closed line around the attached device. Within the region surrounded by the isolation trench, the isolation trap can extend uninterruptedly, for example, forming a continuous layer within the region defined by the isolation trench. As seen in a horizontal cross-section (perpendicular to the vertical direction) through the isolation trap, the isolation trap can form a continuous region (without holes) that completely fills the area defined by the isolation trench. This can be applied, for example, to any vertical height, such as any horizontal cross-section through the isolation trap.

[0019] In one embodiment, an isolation well is formed in an epitaxial layer disposed on a semiconductor substrate. Typically, an additional epitaxial layer may be disposed therebetween; however, in one embodiment, the epitaxial layer having the well region is disposed directly on the semiconductor substrate. Independent of these details, a buried first-doped region may be formed in the same epitaxial layer within a region of the vertical device. In other words, within the same epitaxial layer or sublayer stack, an isolation well may be formed in a region of the additional device, and a buried first-doped region may be formed in a region of the vertical device. The upper end of the isolation well may be disposed at substantially the same vertical height as the upper end of the buried first-doped region, and / or the lower end of the isolation well may be disposed at substantially the same vertical height as the lower end of the buried first-doped region, for example, on a first / upper side of the semiconductor substrate.

[0020] A buried first-doped region made of a first-doped type can form part of the drain region of a vertical device. Therefore, the drain region of the vertical device can, for example, be enlarged or brought closer to the channel, which can, for example, reduce the on-resistance. The buried first-doped region can, for example, have a higher doping concentration than the drift region of the vertical device. The buried first-doped region forming the vertical portion of the drain region of the vertical device is arranged at the same height as the isolation trap, and the buried first-doped region and the isolation trap are isolated from each other by an isolation trench therebetween.

[0021] At least one epitaxial layer forming the first doped type region of the isolation trap and / or burial may have, for example, a thickness of at least 3 μm, 4 μm or 5 μm, with possible upper limits such as up to 15 μm, 10 μm or 8 μm.

[0022] The additional device may include first and second additional load regions, the first additional load region being, for example, the source region of the additional device, and the second additional load region being, for example, the drain region of the additional device. The first additional load region may be disposed on a first side of the semiconductor body, while the second additional load region is embedded in the semiconductor body in an embodiment. In other words, the second additional load region, such as the drain region, is vertically disposed between the first side of the semiconductor body and the isolation well, with the upper end of the second additional load region offset downward from the first side of the semiconductor body. The second additional load region may be disposed directly on the isolation well, i.e., adjacent to the isolation well, or another layer (e.g., an "intermediate region") may be disposed between them.

[0023] In the case of an additional transistor device having source and drain regions, the body region of the additional device can be vertically arranged therebetween. Furthermore, the additional device may include a drift region, which is vertically arranged between the body region and the drain region and has a lower doping concentration compared to the drain region. In the gate trench discussed above, the gate electrode can be laterally arranged beside it and capacitively coupled to the body region; alternatively, a field electrode capacitively coupled to the drift region can be arranged below.

[0024] In one embodiment, the second additional load region, such as the drain region, is electrically connected via a contact element extending from the first side into the semiconductor body. The contact element may include a sinker implant and / or a metal plug, for example, the sinker implant forming the lower portion of the contact element and the metal plug forming the upper portion of the contact element. Current vertically routed through the additional device and collected in the second additional load region (e.g., the drain region) can be routed to the first side of the semiconductor body via the contact element.

[0025] In other words, the additional device can be configured for vertical current flow, for example, vertically through a channel formed in the body region next to the gate trench, wherein a drain contact (via a contact element to the drain region) is provided on a first side. Although there are source and drain contacts on the first side of the semiconductor body, the current flow through the additional device is vertical, which may, for example, allow the use of the same device cell as the vertical device. The reference to "vertical" current flow should, for example, not exclude lateral current diffusion in the drift region (also known from vertical devices). Furthermore, the current collected in the drain region of the additional transistor device may also have a lateral component, for example, towards the contact element.

[0026] In one embodiment, a second additional load region of the additional device, such as a drain region, is connected to the terminals of the vertical device via contact elements, such as via a metallized and / or polysilicon structure. The second load region may be connected to the gate terminal of the vertical device, and the additional device may function, for example, as an integrated pull-down device that can ground the gate terminal of the vertical device in the on state (e.g., connected to the source region in the case of low-side switching).

[0027] In one embodiment, the surrounding trench is arranged laterally between the add-on device and the contact element. For example, the surrounding trench can provide field reduction or shielding between the different potentials of the first add-on load region and the vertical contact element, which is at the same potential as the second add-on load region. In other words, the surrounding trench can be arranged between the source region and the drain contact of the add-on device. As seen in the vertical top view, the surrounding trench can completely surround the add-on device, for example, forming a closed loop within a closed loop formed by an isolation trench.

[0028] Compared to isolation trenches, surrounding trenches can extend to a shallower depth, with their lower ends positioned at a greater height than the lower ends of isolation trenches. The lower ends of the surrounding trenches can be positioned above a second additional load region of the additional device, and the surrounding trenches, for example, extend into and terminate within the drift region.

[0029] As mentioned above, the intermediate region can be vertically arranged between the second additional load region and the isolation well. In other words, the intermediate region can be vertically embedded between the second additional load region and the isolation well, for example, placed adjacent to the second additional load region and / or adjacent to the isolation well. Independent of these details, the intermediate region can be made of a first doping type, but with a lower doping concentration than the second additional load region, or it can be undoped.

[0030] In one embodiment, a second additional load region, such as a drain region, of the additional transistor device is formed in an epitaxial layer, wherein an embedded first doped type region is formed in the same epitaxial layer in the vertical device region. For example, the epitaxial layer may span the entire semiconductor body. The embedded first doped type region may, for example, be embedded between an upper drift region and an lower buried first doped type region. It is formed in the region of the vertical device and may, for example, have the same doping concentration and / or vertical extension as the second additional load region of the additional device, for example, formed simultaneously. As for the vertical device, it may form a second vertical load region of the vertical device, such as a portion of the drain region, which, for example, is raised, see the description above.

[0031] In one embodiment, a method of manufacturing a semiconductor die may include forming an isolation trench and forming an isolation well. Forming an isolation trench may include etching and filling the trench, for example, with an insulating filler. The insulating filler (e.g., an oxide) may completely fill the insulating trench or only cover the sidewalls, for example, in combination with an insert that fills the trench.

[0032] In one embodiment, forming an isolation trap and forming a buried first doped type region includes (i) forming an epitaxial layer of a second doped type. This can be achieved by in-situ doping during deposition and / or by combining subsequent doping with the deposition of the epitaxial layer. Independent of these details, in a subsequent step (ii), a first doped type implantation is locally introduced to form at least a portion of the buried first doped type region. Steps i) and ii) can be repeated multiple times to form a layer consisting of multiple stacked sublayers, each sublayer having the same lateral doping distribution.

[0033] In one embodiment, a method of manufacturing a semiconductor die includes: i) For example, forming an epitaxial layer on a semiconductor substrate; ii) Etching trenches into the epitaxial layer in the vertical transistor device region and / or the additional transistor device region; iii) The injection is introduced into the trench at an angle; iv) Fill the trench with an extended filler; v) The injection diffuses outward into the epitaxial filler.

[0034] Tilt implantation via subsequently filled trenches can, for example, allow for the doping of a relatively thick epitaxial layer in a single step, as an alternative to the sublayer method discussed above. The tilt implantation in step iii) can, for example, be a first-doped-type implantation, such as to form a buried first-doped-type region in a region of the vertical device.

[0035] In one embodiment, a second doping type implantation is provided to the epitaxial layer prior to, for example, before etching the trench in step ii). This second doping type implantation can be introduced into both the regions of the vertical and lateral devices, for example, through in-situ doping during epitaxial layer deposition. The trench can then be etched only in the region of the vertical device, allowing the first doping type implantation to be introduced there, for example, forming a buried first doping type region.

[0036] Alternatively, trenches can be etched in the region of the vertical transistor device and the region of the additional transistor device, wherein a second doping type implantation is introduced into all trenches. Then, in a subsequent step, the trenches in the region of the additional transistor device can be covered, for example, with a resist mask, such that the subsequent first doping type implantation is introduced only into those trenches disposed in the region of the vertical device. The mask can then be removed, and the trenches can be filled with an epitaxial filler, as described above. Attached Figure Description

[0037] The semiconductor die and manufacturing method will now be explained in further detail with the aid of exemplary embodiments. The various features may also be related in different combinations.

[0038] Figure 1a A semiconductor die with a semiconductor body is shown in a vertical cross-section; Figure 1b A detailed view of the vertical transistor device is shown; Figure 1c A detailed view of the additional transistor device is shown; Figure 1d It shows crossing Figure 1a The horizontal cross-section of the semiconductor substrate; Figure 2 A semiconductor die with vertical transistor devices and additional transistor devices is shown in a vertical cross-section; Figure 3 The semiconductor die is shown in a vertical top view; Figure 4a -c indicates the possibility of using it to create buried doped regions; Figure 5a -c indicates the replacement steps used to create the buried doped region; Figure 6 The flowchart summarizes some of the manufacturing steps. Detailed Implementation

[0039] Figure 1a A semiconductor die 1 having a semiconductor body 10 is shown. The semiconductor body 10 includes a semiconductor substrate 11 and an epitaxial layer, which will be discussed in further detail below. A vertical transistor device 20 is formed in region 120 of the semiconductor die 1. It includes a first vertical load region 21 disposed on a first side 10.1 of the semiconductor body 10, and a second vertical load region 22 disposed on a vertically opposite second side 10.2 of the semiconductor body 10, as shown in more detail below. Figure 1b .

[0040] In another region 140 of the semiconductor die 1, an additional transistor device 40 is arranged. It includes a first additional load region 41 and a second additional load region 42. The first additional load region 41 is arranged on a first side 10.1 of the semiconductor body 10, and the second additional load region 42 is embedded in the semiconductor body 10 in the example shown. See more details. Figure 1c Below the additional transistor device 40, an isolation well 70 is arranged. It is made of a second doping type, that is, a doping type opposite to that of the first and second vertical load regions 21, 22 made of the first doping type.

[0041] An isolation trench 60 is laterally disposed between the additional transistor device 40 and the vertical transistor device 20. It extends from the first side 10.1 into the semiconductor body 10, for example, extending deeper than the gate trench 25 of the vertical transistor device 20 and the gate trench 45 of the additional transistor device 40. However, the isolation trench 60 does not completely intersect the semiconductor body 10; it extends to a vertical depth 65 above the second side 10.2 of the semiconductor body 10. In the example shown, it extends into but does not penetrate the semiconductor substrate 11, and the lower end 60.2 of the isolation trench 60 is disposed below the lower end 70.2 of the isolation well 70. Figure 1a In this configuration, a second additional load region 42, made of the first doping type, is directly disposed on the isolation trap 70, adjacent to the upper end 70.1 of the isolation trap 70.

[0042] In operation, with the first additional load region 41 perpendicularly embedded in the first side 10.1 and the second additional load region 42 in the semiconductor body 10, a vertical current flows through the additional transistor device 40. The current is routed to the first side 10.1 via contact elements 80 extending from the first side 10.1 into the semiconductor body 10. In other words, although a vertical current flows in the channel, the contact of the additional transistor device 40 is implemented on the same side of the semiconductor body 10.

[0043] An isolation well 70 is formed in the epitaxial layer 12, specifically in region 140 of the additional transistor device 40. A buried first-doped region 112 is formed in region 120 perpendicular to the transistor device 20. As discussed with reference to Figures 4 and 5, the epitaxial layer 12 can be deposited as a single layer or made of multiple sublayers.

[0044] A second additional load region 42 is formed in the epitaxial layer 13 above. The epitaxial layer 13 may be highly doped, for example, having a higher doping concentration than the buried first doped type region 112 and / or the drift region above. In region 120 of the vertical transistor device 20, at least one epitaxial layer 13 is part of the second vertical load region 22. In other words, the buried first doped type region 112 and the embedded first doped type region 122 enhance the second vertical load region 22, even if it is closer to the first side 10.1 of the semiconductor body 10.

[0045] Figure 1b The vertical device 20 is shown in a more detailed cross-sectional view. In the example shown, the first vertical load region 21 is the source region 121, and the second vertical load region is the drain region 122. Furthermore, the vertical transistor device 20 includes a body region 23 below the source region 121 and a drift region 24 below the body region 23. In the body region 23, a channel region 23.1 is formed adjacent to the gate trench 25, i.e., adjacent to the gate electrode 35 in the gate trench 25. Below the gate electrode 35, a field electrode 36 is disposed in the gate trench 25. The field electrode 36 is capacitively coupled to the drift region 24, and the gate electrode 35 is capacitively coupled to the body region 23, i.e., the channel region 23.1.

[0046] An insulating layer 90 is disposed on the first side 10.1 of the semiconductor body 10, and a metallization 95 disposed on the insulating layer is schematically shown. The metallization is electrically connected to the source region 121 and the body region 23 via contact plugs 26. The vertical current flow through the channel region 23.1, i.e., the current flow between the source region 121 and the drain region 122, can be controlled by a gate voltage applied to the gate electrode 35 (which is contacted outside the plane of the drawing). A backside metallization 97 can be disposed on the second side 10.2 of the semiconductor body 10.

[0047] Figure 1c The additional transistor device 40 is shown in a more detailed cross-sectional view. In the example shown, the first additional load region 41 is the source region 141, and the second additional load region 42 is the drain region 142. Furthermore, the additional transistor device 40 includes a body region 43 below the source region 141 and a drift region 44 below the body region 43. A gate electrode 55 and a field electrode 56 are disposed in the gate trench 45, with the gate electrode 55 capacitively coupled to the body region 43 and the field electrode 56 capacitively coupled to the drift region 44.

[0048] In metallization 95, source contact 241 and drain contact 242 are formed. Source contact 241 is connected to source region 141 and body region 43 via contact plug 96. By applying a voltage to gate electrode 55, the vertical current flow in channel region 43.1, i.e., the vertical current flow between source region 141 and the underlying drain region 142, can be controlled. Drain contact 242 is connected to drain region 142 via vertical contact 80. Specifically, contact element 80 includes submerged implant 81 and contact plug 82, which can be fabricated simultaneously with contact plug 96.

[0049] Figure 1d A horizontal cross-section through the semiconductor body 10 is shown; see [link / reference]. Figure 1a The reference cross section AA. An isolation trench 60 extends around a region 140 containing an additional transistor device, forming a closed line. This region 140, laterally defined by the isolation trench 60, is completely filled by an isolation well 70, which has no openings, etc. In region 120, the cross section penetrates a buried first doped layer 112.

[0050] Figure 2 It shows the relationship with Figure 1a A similar semiconductor die 1 is shown in a cross-sectional view. Generally, in this disclosure, the same reference numerals denote the same elements or elements having the same function, and reference is also made to the description of the corresponding other figures. The following description primarily emphasizes the differences.

[0051] and Figure 1a Conversely, the second additional load region 42 of the additional transistor device 40 is not directly disposed on the isolation well 70. Instead, an intermediate region 113 is disposed between them, which may be undoped. Alternatively, the intermediate region 113 may be made of a first doping type, but with a lower doping concentration compared to the second additional load region 42. It is formed in the epitaxial layer 14, where a higher first doping type implantation can be introduced in the region 120 perpendicular to the transistor device 20, i.e., in the first doping type region 114.

[0052] A surrounding trench 90 is laterally arranged between the additional transistor device 40 and the contact element 80. It extends to a depth 95 above the second additional load region 42, but is deeper than the gate trench 45. (As shown from...) Figure 3 As can be clearly seen in the top view shown, the surrounding trench 90 forms a closed loop around the additional transistor device 40, that is, around the gate trench 45. Furthermore, Figure 3 The trench isolation 60 is shown forming a closed loop around the additional transistor device 40.

[0053] As in Figure 3 It can also be seen that the contact element 80 can be arranged on more than one side of the additional transistor device 40. Figure 3In the middle, it was indicated Figure 2 The cross section BB (whereby the number of gate trenches 25, 45 differs between the cross section view and the top view for display purposes).

[0054] Figure 4a -c illustrates a first possibility for fabricating an isolation well 70 made of a second doping type, wherein a buried first doping type region 112 is adjacent to the isolation well 70. The epitaxial layer 12 is not deposited as a single layer, but rather multiple sublayers 12.1 are deposited one after another. After depositing the respective sublayers 12.1, a first doping type implantation 201 is introduced in the region 120 of the vertical transistor device, and a second doping type implantation 202 is introduced in the region of the additional transistor device, see [link to relevant documentation]. Figure 4a .

[0055] In detail, a second doping type implantation 202 can, for example, first be introduced into the entire sublayer 12.1, wherein a mask with openings in region 120 of the vertical transistor device can then be applied. A subsequent first doping type implantation 201 is then selectively applied to region 120. As... Figure 4b As shown, independent of these details, additional sublayers 12.1 can be subsequently deposited, each sublayer being selectively doped in regions 120, 140.

[0056] Figure 4c The semiconductor body 10 is shown after the formation of isolation trap 70 and buried first doped type region 112, which are covered by epitaxial layers 13 and 15, in which drift regions and additional device elements are later formed.

[0057] Figure 5a -c illustrates an alternative method for forming the isolation trap 70 and the buried first doped type region 112. In this method, the epitaxial layer 12 is initially deposited in one step, and in the example shown, it is an undoped layer. Then, a plurality of trenches 210 are etched into the epitaxial layer 12, and a tilted second doped type implantation 202 is introduced into the trenches 210, see [link to relevant documentation]. Figure 5a .

[0058] Then, as Figure 5b As shown, a mask 215 is formed to cover the trenches 210 disposed in the region 150 of the additional transistor device. Therefore, the subsequent tilted first doping type implantation 201 is applied only to the trenches 210 in the region 120 of the vertical transistor device. After removing the mask 215, the trenches 210 are filled with epitaxial fillers 215 to form a continuous epitaxial layer 12. Then, in a tempering step, the corresponding doping type implantations, namely the second doping type implantation in region 140 and the first doping type implantation in region 120, diffuse outward into the fillers 215.

[0059] Figure 6 The flowchart summarizes some of the manufacturing steps. The method may include forming an isolation well (301) and an isolation trench (302). As discussed with reference to Figures 4 and 5, when forming the isolation well (301), a first doped type region (303) may be formed.

Claims

1. A semiconductor die (1) having a semiconductor body (10), the semiconductor die (1) comprising: Vertical transistor device (20); An additional transistor device (40) includes a channel region (43.1) configured for vertical current flow; An isolation trench (60) extends into the semiconductor body (10); An isolation trap (70) made of a second doping type; The isolation trap (70) is arranged vertically below the additional transistor device (40). The isolation trench (60) is arranged laterally between the additional transistor device (40) and the vertical transistor device (20). The isolation trench (60) extends to a depth (65) between the upper end (70.1) of the isolation trap (70) and the second side (10.2) of the semiconductor body (10).

2. The semiconductor die (1) according to claim 1, The vertical transistor device (20) includes: A first vertical load region (21) is arranged on a first side (10.1) of the semiconductor body and a second vertical load region (22) is arranged on a second side (10.2) of the semiconductor body (10) opposite to the first side (10.1); The first vertical load region (21) and the second vertical load region (22) are made of the first doping type, which is opposite to the second doping type.

3. The semiconductor die (1) according to claim 1 or 2, wherein the isolation trench (60) extends through the isolation trap (70), and wherein the lower end (60.2) of the isolation trench (60) is arranged at the same vertical height as the lower end (70.2) of the isolation trap (70) or below the lower end (70.2).

4. The semiconductor die (1) according to any one of the preceding claims, wherein at least one of the vertical transistor device (20) and the additional transistor device (40) includes at least one gate trench (25, 45), wherein the isolation trench (60) extends deeper than the at least one gate trench (25, 45).

5. The semiconductor die (1) according to any of the preceding claims, wherein the isolation trench (60) forms a closed line around the additional device (20), wherein, as seen in a vertical section, the isolation trap (70) completely fills the area surrounded by the isolation trench (60).

6. The semiconductor die (1) according to any one of the preceding claims, wherein the semiconductor body (10) includes a semiconductor substrate (11) and an epitaxial layer (12), wherein an isolation well (70) is formed in the epitaxial layer (12) in a region (140) of the additional transistor device (40), and a buried first doped type region (112) is formed in the epitaxial layer (12) in a region (120) of the vertical transistor device (20).

7. The semiconductor die (1) according to any one of the preceding claims, The additional transistor device (40) includes: First additional load area (41) and second additional load area (42); The first additional load region (41) is disposed on the first side (10.1) of the semiconductor body (10), and the second additional load region (42) is embedded in the semiconductor body (10), that is, disposed vertically between the first side (10.1) of the semiconductor body (10) and the isolation trap (70).

8. The semiconductor die (1) according to claim 7, wherein the second additional load region (42) is electrically connected via a contact element (80) to a terminal of the vertical transistor device (20), particularly to the gate electrode (35) of the vertical transistor device (20), the contact element (80) extending from the first side (10.1) into the semiconductor body (10).

9. The semiconductor die (1) according to claim 8, wherein a surrounding trench (90) extending to a depth (95) above the second additional load region (42) is laterally arranged between the additional transistor device (40) and the contact element (80).

10. The semiconductor die (1) according to any one of claims 7 to 9, wherein an intermediate region (113) is arranged vertically between the second additional load region (42) and the isolation well (70), the intermediate region (113) being undoped or made of the first doping type, but having a lower doping concentration compared to the second additional load region (42).

11. The semiconductor die (1) according to any one of claims 7 to 10, wherein the semiconductor body (10) comprises a semiconductor substrate (11) and an epitaxial layer (13), wherein a second additional load region (42) of the additional transistor device (40) is formed in the epitaxial layer (13) in a region (140) of the additional transistor device (40), and an embedded first doped type region (122) is formed in the epitaxial layer (13) in a region (120) of the vertical transistor device (20).

12. A method for manufacturing a semiconductor die (1) according to any one of the preceding claims, comprising: - Form (302) isolation trench (60); - Form (301) isolation trap (70).

13. The method for manufacturing the semiconductor die (1) of claim 6 according to claim 12, wherein forming the isolation trap (70) and forming (303) the buried first doped type region (112) comprises: i) Forming an epitaxial sublayer of the second doping type (12.1); ii) Locally introduce a first doping type implantation (201) to form at least a portion of a buried first doping type region (112), Steps i) and ii) are repeated multiple times.

14. The method of manufacturing the semiconductor die of claim 6 according to claim 12, wherein forming the isolation trap (70) and forming (303) the buried first doped type region (112) comprises: i) Formation of an epitaxial layer (12); ii) In at least one of the regions (120) of the vertical transistor device (20) and the regions (140) of the additional transistor device (40), a trench (210) is etched into the epitaxial layer (12); iii) The injection (201, 202) is introduced obliquely into the trench (210); iv) Fill the groove (210) with an extension filler (215); v) The injection (201) diffuses outward into the epitaxial filler (215).

15. The method according to claim 14, wherein the implantation in step iii) is a first doping type implantation, wherein a second doping type implantation (202) is provided to the epitaxial layer (12) prior to step ii), and in step ii), trenches are not etched in the region (140) of the additional transistor device (40).

16. The method of claim 14, wherein trenches (210) are etched in the region (120) of the vertical transistor device (20) and in the region (140) of the additional transistor device (40), wherein a second doping type implantation (202) is introduced into all trenches (210) prior to a first doping type implantation (201) in the region (120) of the vertical transistor device (20).

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