Semiconductor device

Abstract

A semiconductor device includes a substrate, an active region, an insulating structure, and a plurality of plugs. The active regions are defined in the substrate in a mutually separated mode, each active region comprises an active fin and active end portions arranged on the two sides of the active fin, and the active fins and the active end portions are made of different materials. The insulating structure is arranged in the substrate and surrounds the active region; and a plurality of plugs disposed on the substrate, the plugs being in contact with the active fins and the active end portions at the same time, the top surfaces of the active fins in contact with the plugs being lower than the top surfaces of the active end portions in contact with the plugs. Under the arrangement, the extension range of the active region can be improved, and direct and stable contact between the subsequently formed storage contact plug structure and the active region can be ensured.

Description

[0001] This application is a divisional application of Chinese Patent CN202111404609.1, filed on November 24, 2021, entitled "Semiconductor Device and Method of Forming the Same". Technical Field

[0002] This invention relates to a semiconductor device, and more particularly to a semiconductor device comprising an active region and an insulating structure. Background Technology

[0003] With the miniaturization of semiconductor devices and the increasing complexity of integrated circuits, the size of components continues to shrink, and their structures are constantly changing. Therefore, maintaining the performance of small-sized semiconductor components is currently the industry's primary goal. In semiconductor manufacturing processes, multiple active regions are typically defined on a substrate as a basis, and the desired components are then formed on these active regions. Generally, active regions are multiple patterns formed on the substrate using processes such as photolithography and etching. However, with the demands of size reduction, the width of active regions is gradually decreasing, and the spacing between each active region is also shrinking, which presents many limitations and challenges to the manufacturing process, making it impossible to meet product requirements. Summary of the Invention

[0004] One object of the present invention is to provide a semiconductor device whose active region includes active fins and active ends made of different materials disposed on both sides of the active fins. This improves the extension range of the active region, ensuring that the storage node contact (SNC) can make direct and stable contact with the active region. With this configuration, the storage node contact structure has optimized structural stability, thereby improving the device performance of the semiconductor device of the present invention.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, active regions, an insulating structure, and a plurality of plugs. The active regions are defined parallel to and spaced apart from each other within the substrate. Each active region includes an active fin and active ends disposed on both sides of the active fin. The active fin and the active ends are made of different materials. The insulating structure is disposed within the substrate, surrounding the active regions. A plurality of plugs are disposed on the substrate, and each plug simultaneously contacts both the active fin and the active ends. The top surface of the active fin contacting the plug is lower than the top surface of the active end contacting the plug.

[0006] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate; a plurality of active regions defined within the substrate by an insulating structure, each active region including an active fin and an active end disposed on both sides of the active fin, wherein the active fin and the active end are made of different materials; and a plurality of plugs disposed on the substrate, the plugs simultaneously contacting the active fins and the active ends, wherein the top surface of the active fin contacting the plug is lower than the top surface of the active end contacting the plug.

[0007] To achieve the above objectives, one embodiment of the present invention provides a method for forming a semiconductor device, comprising the following steps: First, a substrate is provided. Then, a plurality of active regions and an insulating structure are formed within the substrate, the insulating structure surrounding the active regions, wherein each active region includes an active fin and active ends disposed on both sides of the active fin, the active fin and the active ends respectively comprising different materials; a plurality of plugs are formed on the substrate, the plugs simultaneously contacting the active fins and the active ends, the top surface of the active fin contacting the plug being lower than the top surface of the active end contacting the plug. Attached Figure Description

[0008] Figures 1 to 7 A schematic diagram illustrating the fabrication process of the semiconductor device in a first preferred embodiment of the present invention is shown; wherein, Figure 1 This is a top view of the semiconductor device of the present invention after the active unit has been formed; Figure 2 for Figure 1 A cross-sectional view along tangent A-A'; Figure 3 This is a top view of the semiconductor device of the present invention after the opening has been formed; Figure 4 for Figure 3 A cross-sectional view along tangent A-A'; Figure 5 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after undergoing an epitaxial fabrication process. Figure 6 This is a top view of the semiconductor device of the present invention after the formation of the insulating layer; and Figure 7 for Figure 6 A cross-sectional view along the tangent A-A'.

[0009] Figure 8 A cross-sectional schematic diagram of a semiconductor device after an epitaxial fabrication process is shown in another preferred embodiment.

[0010] Figure 9A cross-sectional view of the semiconductor device after epitaxial fabrication is shown in another preferred embodiment.

[0011] Figure 10 A cross-sectional schematic diagram of a semiconductor device according to a preferred embodiment of the present invention is shown.

[0012] Figures 11 to 12 A schematic diagram illustrating the fabrication process of a semiconductor device according to a second preferred embodiment of the present invention is shown; wherein... Figure 11 This is a schematic cross-sectional view of the semiconductor device of the present invention after the formation of the insulating layer; and Figure 12 This is a cross-sectional view of the semiconductor device of the present invention after an etching process.

[0013] Figures 13 to 15 A schematic diagram illustrating the fabrication process of a semiconductor device according to a third preferred embodiment of the present invention is shown; wherein... Figure 13 This is a schematic cross-sectional view of the semiconductor device of the present invention after the active unit is formed; Figure 14 for Figure 13 A cross-sectional view along tangent A-A'; and Figure 15 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after undergoing an epitaxial fabrication process.

[0014] The reference numerals in the attached figures are explained as follows: 100 substrate 101 mask pattern 101a surface 102 Shallow Ditches 110 active unit 110a top surface 110b sidewall 111 end 113, 117, 213, 413 active terminals 115, 415 active fins 120 First Insulation Layer Top surfaces of 120a, 120b, and 120c 130, 430 mask layers 131, 431 opening 140 Second Insulation Layer 140a top surface 150, 150a, 450 active regions 160 insulation structure 300 and 500 semiconductor devices 320 insulation layer 320a top surface 321 opening 410 active fragment 420 First Insulation Layer 430 mask layer 440 Second Insulation Layer 440a top surface 540 First Conductor 541 dielectric layer 543 gate dielectric layer 545 gate 547 cap layer 560 Second Conductor 560a contact 561 semiconductor layer 563 Barrier Layer 565 conductive layer 567 cap layer 570 gap wall 571 First gap wall 573 Second spacer wall 575 Third gap wall 580 dielectric layer 590 plug D1, x, y directions g interval h1, h2 height difference Lengths of L1, L2, and L3 Detailed Implementation To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0015] Please refer to the following first. Figures 1 to 7 The illustration shows a schematic diagram of the fabrication process of the semiconductor device 300 in the first preferred embodiment of the present invention, wherein... Figure 1 , Figure 3 as well as Figure 6 These are top views of the semiconductor device 300 at different stages of its fabrication. Figure 2 , Figure 4 , Figure 5 ,as well as Figure 7This is a cross-sectional schematic diagram of the semiconductor device 300 at different formation stages. First, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate. At least one first insulating layer 120 is disposed within the substrate 100 to define a plurality of active area units 110. Each active area unit 110 extends parallel to and spaced apart from each other along a direction D1, and is alternately arranged, wherein the direction D1, for example, intersects and is not perpendicular to the y-direction or x-direction. Figure 1 As shown. In one embodiment, each active unit 110 has, for example, the same length L1 in direction D1, and adjacent active units 110 may also have the same spacing g.

[0016] In one embodiment, the formation of the active unit 110 can be achieved by, but is not limited to, the patterning fabrication process described below. For example, a mask layer (not shown) is first formed on a substrate 100, the mask layer including a plurality of mask patterns 101 for defining the active unit 110 and exposing a portion of the substrate 100. An etching process is then performed using the mask layer to remove the portion of the substrate 100, forming at least one shallow trench 102. An insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, is then filled into the shallow trench 102, thereby forming a first insulating layer 120 with its top surface 120 aligned with the surface 101a of the mask layer, simultaneously defining the active unit 110. Figure 1 as well as Figure 2 As shown. In one embodiment, the active unit 110 can also be formed using a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, but is not limited thereto.

[0017] Please refer to Figure 3 as well as Figure 4 As shown, a mask layer 130 is formed on the substrate 100 while retaining the mask pattern 101. This mask layer includes a plurality of openings 131, which expose the underlying first insulating layer 120 and the ends 111 of the active units 110 at the intervals g between adjacent active units 110. The ends 111, for example, refer to the openings of each active unit 110 at the intervals g. Figure 3 In the top view shown, the side extending in the y-direction, in this embodiment, the end portion 111 includes at least the side extending in the y-direction, and a portion of the side adjacent to at least one side extending in the D1 direction, as shown. Figure 3 As shown. Then, an etching process is performed through the mask layer 130 to remove the mask pattern 101 remaining above the end 111 of the active unit 110, thereby exposing a portion of the top surface 110a of the active unit 110. Furthermore, the exposed first insulating layer 120 is partially removed, such that the top surface 120b of a portion of the first insulating layer 120 is lower than the top surface 110a of the active unit 110 after the etching process. Figure 4 As shown. Thus, after the etching process is performed, the top surface 110a of the end 111 of the active unit 110 and part of the sidewall 110b can be exposed.

[0018] Please refer to Figure 5 As shown, a selective epitaxial growth process is performed while retaining the mask layer 130 and the mask pattern 101 to form the active end 113. Please refer to [the documentation / reference]. Figure 5 as well as Figure 6 As shown, in this embodiment, the active end 113 is as follows: Figure 6 The top view shown shows that the system is formed on the side of each active unit 110 extending in the y direction, and on the portion of the side adjacent to at least one side extending in the D1 direction, thus presenting an L-shape; while as Figure 5 The cross-sectional view shown shows the exposed top surface 110a and part of the sidewall 110b of the end 111 of the active unit 110, which can also be L-shaped, but is not limited to this. On the other hand, the remaining unreacted active units 110 form active fins 115, so that the active end 113 and the active fins 115 can together constitute multiple active regions 150 within the substrate 100. It should be noted that the active end 113 may include an epitaxial material different from that of the substrate 100. For example, when the substrate 100 is, for example, a silicon substrate, the active end 113 may include silicon germanium, but is not limited to this. Thus, the top surface of the active end 113 may be significantly slightly higher than the top surface of the active fins 115 and the top surface 140a of the second insulating layer 140, and has a height difference h1, such as Figure 7 As shown. On the other hand, the active end 113 may also have a different surface roughness than the substrate 100 (active fin 115). For example, when the substrate 100 is, for example, a silicon substrate, its surface roughness is smaller, while the surface roughness of the active end 113 (e.g., including silicon germanium) is larger. However, the specific difference in roughness may also vary depending on the material, and is not limited to the foregoing. Then, the mask layer 130 and the mask pattern 101 are completely removed.

[0019] Please refer to Figure 6 as well as Figure 7As shown, a second insulating layer 140 is formed above the first insulating layer 120 of the aforementioned portion, such that the top surface 140a of the second insulating layer 140 is flush with the top surface (i.e., top surface 110a) of the active fin 115, as shown. Figure 7 As shown. Thus, the first insulating layer 120 and the second insulating layer 140 together constitute an insulating structure 160 within the substrate 100, surrounding the active region 150. The second insulating layer 140 is disposed between adjacent active regions 150 and surrounded by the first insulating layer 120, as shown. Figure 6 As shown. With this configuration, the insulation structure 160 can further isolate the adjacent active region 150 and achieve a better insulation effect.

[0020] Thus, the semiconductor device 300 of the first preferred embodiment of the present invention is completed. The semiconductor device 300 has a plurality of active regions 150 and an insulating structure 160 surrounding the active regions 150. The active regions 150 include active fins 115 of different materials and active ends 113 disposed on both sides of the active fins 115, thereby obtaining a relatively extended length L2 in the direction D1. In this way, when other elements are subsequently formed on the active regions 150, a more stable contact and conductivity effect can be provided through the extended length of the active ends 113 and the epitaxial material.

[0021] However, those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device and its fabrication process of the present invention may have other forms or be achieved by other means, and are not limited to the foregoing. For example, in one embodiment, during the selective epitaxial growth process, the range of epitaxial material formation can be selectively increased to form an active end 117 with a relatively large thickness. Thus, the top surface of the active end 117 can be significantly higher than the top surface of the active fin 115 (i.e., top surface 110a) and the top surface 140a of the second insulating layer 140, and has a relatively large height difference h2, such as... Figure 8As shown. Under this configuration, the active region 150a (including the active end 117 and the active fin 115) can not only obtain a further extended length L3 in the direction D1, but the height difference h2 between the active fin 115 and the active end 117 can further increase the contact area with the subsequently formed storage contact plug structure, thereby optimizing the overall structure. Alternatively, in another embodiment, when performing the etching process through the mask layer 130, the mask pattern 101 remaining above the end 111 of the active unit 110 can be removed, and the exposed first insulating layer 120 can be partially removed, exposing only the top surface of the end 111 of the active unit 110. That is, after the etching process, the top surface 120c of part of the first insulating layer 120 can be flush with the top surface 110a of the active unit 110 but the sidewall 110b of the end 111 of the active unit 110 is not exposed. Figure 9 As shown. Thus, during the subsequent selective epitaxial growth fabrication process, the active end 213 can be formed only on the top surface 110a of the end 111 of the active unit 110, so that the active end 213 in this embodiment can appear as a straight line in a cross-sectional view, as shown. Figure 9 As shown. Therefore, the configuration of the two embodiments described above can also effectively improve the extension range of the active region, ensuring that the subsequently formed storage contact plug structure can make direct and stable contact with the active region.

[0022] Furthermore, those skilled in the art will readily understand that, to meet actual product requirements, the present invention may also have other forms of forming semiconductor devices and methods, and is not limited to those described above. Other embodiments or variations of the method for forming semiconductor devices according to the present invention will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. In addition, the same components in the various embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0023] Please refer to Figure 10 The diagram illustrates a cross-sectional view of a semiconductor device 500 in a preferred embodiment of the present invention. The structure of the semiconductor device 500 in this embodiment is generally the same as that of the semiconductor device 300 in the first embodiment described above, including a substrate 100, an active region 150 (including active fins 115 and active ends 113), and an insulating structure 160 (including active fins 115 and active ends 113), etc., which will not be described in detail here. The main difference between this embodiment and the first embodiment is that the semiconductor device 500 in this embodiment additionally includes a plurality of first conductive lines 540 formed within the substrate 100, a plurality of second conductive lines 560 formed on the substrate 100, and a plurality of plugs 590.

[0024] In detail, the first conductor 540 extends parallel to each other along the y-direction, traversing the active region 150 and passing through both the first insulating layer 120 and the second insulating layer 140. In one embodiment, a plurality of parallel and spaced-apart trenches (not shown) extending along the y-direction are first formed within the substrate 100. Then, a dielectric layer 541 covering the entire surface of the trenches, a gate dielectric layer 543 covering the lower half of the trenches, a gate 545 filling the lower half of the trenches, and a capping layer 547 filling the upper half of the trenches are sequentially formed. Thus, the surface of the capping layer 547 can be flush with the top surface (i.e., top surface 110a) of the active fin 115, such as... Figure 10 As shown, the first conductive line 540 located within the substrate 100 can serve as a buried word line (WL) 540 of the semiconductor device 500, and intersects with the active fins 115 of the active region 150 to receive or transmit voltage signals from each memory cell (not shown). Although the extension direction of the trench or the first conductive line 540 is not specifically shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that, viewed from a top view, the first conductive line 540 extending in the y-direction should intersect with the active region 150 and pass through the insulating structure 160 (including the insulating layer 120 and the second insulating layer 140).

[0025] On the other hand, the second conductor 560 extends parallel to each other along the x-direction to cross the active region 150, and may intersect the first conductor 540 perpendicularly in a projected direction (not shown). The second conductor 560 and the plug 590 are alternately disposed within the dielectric layer 580 above the substrate 100, and adjacent plugs 590 and second conductors 560 are isolated from each other through spacers 570, such as... Figure 10As shown. In one embodiment, the spacer wall 570 may include, for example, a first spacer wall 571 (containing a material such as silicon nitride), a second spacer wall 573 (containing a material such as silicon oxide), and a third spacer wall 575 (containing a material such as silicon nitride) sequentially stacked on the sidewall of the second conductor 560, but is not limited thereto. Each second conductor 560 may include, for example, a semiconductor layer (e.g., containing polysilicon) 561, a barrier layer 563 (e.g., containing titanium and / or titanium nitride), a conductive layer 565 (e.g., containing a low-resistivity metal such as tungsten, aluminum, or copper), and a capping layer 567 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride), but is not limited thereto. It should be noted that a bit line contact (BLC) 560a is also formed below the second conductor 560, which can further extend into the active fin 115 of the substrate 100 and is located between two adjacent first conductors 540 and two adjacent active ends 113. In this embodiment, the contact 560a is integrally formed with the semiconductor layer 561 of the second conductor 560 and directly contacts the active fin 115, but is not limited thereto. The plug 590 can simultaneously contact the active fin 115, the active end 113, and part of the capping layer 547 of the first conductor 540, thereby forming a more stable storage node contact (SNC) structure. It should also be noted that when the thickness of the active end 113 is significantly higher than that of the active fin 115, the bottom of the plug 590 can also have a corresponding height difference h1, making the plug 590 more stable.

[0026] Therefore, the semiconductor device 500 of this embodiment can be used as a dynamic random access memory (DRAM) device, including at least one transistor assembly (not shown) and at least one capacitor assembly (not shown), to serve as the smallest unit of memory in the DRAM array and receive voltage information from the second conductor 560 (bit line) and the first conductor 540 (word line). The active region 150 of the semiconductor device 500 also includes active fins 115 of different materials and active ends 113 disposed on both sides of the active fins 115, allowing the plug 590 to be more stably disposed on the active fins 115, the active ends 113, and the junction between them, forming a more stable contact and conductivity. With this configuration, the semiconductor device 500 of this embodiment can achieve a more optimized structure and device performance.

[0027] Please refer to Figures 11 to 12The diagram illustrates the fabrication process of a semiconductor device in a second embodiment of the present invention. The fabrication process of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above, and will not be repeated here. The main difference between this embodiment and the first embodiment lies in that the insulating layer 320 is directly used as a mask layer, and etching and selective epitaxial growth processes are performed sequentially.

[0028] In detail, this embodiment involves defining a plurality of active cells 110 on the substrate 100, then removing the mask pattern (not shown), and then forming an insulating layer 320 to further surround and cover all the active cells 110. In other words, the top surface 320a of the insulating layer 320 is higher than the top surface 110a of the active cells 110, such as... Figure 11 As shown.

[0029] Next, a mask layer (not shown) is formed on the substrate 100, which includes a plurality of openings (not shown) that are respectively etched through the space g between adjacent active units 110 to form a plurality of corresponding openings 321 in the insulating layer 320, exposing the top surface 110a and sidewall 110b of the end 111 of each active unit 110, as shown. Figure 12 As shown in the first embodiment above. Subsequently, the process can proceed as described in the first embodiment above. Figures 5 to 7 As shown, the selective epitaxial growth process is performed while retaining the insulating mask 321 to form the fabrication process described above. Figures 6 to 7 The active end 113 shown, or formed as Figure 8 The active end 117 is shown, but not limited to this. Then, a planarization process (not shown) is performed to remove the insulating layer 320 above the active unit 110, leaving only the insulating layer 320 on the top surface 320a below the top surface 110a of the active unit 110. This insulating layer can surround the active unit 110 to form an insulating structure. Thus, the aforementioned active end 113 or active end 117 effectively improves the extension range of the active region, ensuring that the subsequently formed storage contact plug structure can make direct and stable contact with the active region.

[0030] Please refer to Figures 13 to 15 The diagram illustrates the fabrication process of a semiconductor device according to a third embodiment of the present invention. The fabrication process of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above, and the similarities will not be repeated here. The main difference between the fabrication process in this embodiment and that in the first embodiment is that the active segment 410 is formed using a self-aligned double patterning fabrication process or a self-aligned reverse patterning fabrication process.

[0031] For details, please refer to Figure 13 as well as Figure 14 As shown, firstly, a plurality of active segments 410 are formed in the substrate 100 using the self-aligned dual patterning process or the self-aligned reverse patterning process. Each active segment 410 extends parallel to each other along direction D1 and is surrounded by a first insulating layer 420. Next, a mask layer 430 is formed on the substrate 100, which includes a plurality of openings 431 to partially expose the underlying active segments 410. Then, an etching process is performed through the mask layer 430 to partially remove the active segments 410 exposed from each opening 431, and shallow trenches 102 are formed in the substrate 100, thereby truncating each active segment 410 into the following shapes: Figure 1 The diagram shows multiple active units 110. Furthermore, after the aforementioned etching process, another etching process, such as a wet etching process, can be performed to partially remove the first insulating layer 420 surrounding the active units 110, particularly the first insulating layer 420 adjacent to the ends 111 of the active units 110, thereby forming a structure similar to... Figure 3 The structural pattern shown.

[0032] Subsequently, a selective epitaxial growth process can be performed while retaining the mask layer 430 to form active ends 413 on both sides of the active unit 110, while the remaining active units 110 form active fins 415, constituting the active region 450, as shown below. Figure 15 As shown. It should be noted that in this embodiment, if a top view (not shown, similar) is used... Figure 6 From the top view shown, the active end 413 should be formed on the side of each active unit 110 extending in the y direction, and on the portion of the side adjacent to at least one side extending in the D1 direction, thus presenting an L-shape; while Figure 15 In the cross-sectional view shown, the active end 413 is formed on the exposed surfaces on both sides of the active unit 110 (i.e., Figure 15 The shallow trench 102 shown can be U-shaped on its sidewalls and bottom surface. Then, after forming at the active end 413, a second insulating layer 440 is formed within the shallow trench 102. The top surface 440a of the second insulating layer 440 can be lower than the top surface 110a of the active unit 110, such as... Figure 15 As shown, or in another embodiment, it can be flush with the top surface 110a of the active unit 110. Thus, the remaining first insulating layer 420 and second insulating layer 440 can together constitute the insulating structure of this embodiment. Therefore, the active end 413 can also be formed through the manufacturing process of this embodiment, which can also effectively improve the extension range of the active region 450, ensuring that the subsequently formed storage contact plug structure can make direct and stable contact with the active region.

[0033] Overall, the semiconductor device of the present invention forms an active region with a composite material. The active region within the semiconductor device includes active fins of different materials and active ends disposed on both sides of the active fins. The active ends are formed through a selective epitaxial growth process, thereby allowing the active region to achieve a relatively extended length overall. This effectively improves the extension range of the active region, increases the contact area between the active region and the plug structure, and ensures that the subsequently formed storage contact plug structure can make direct and stable contact with the active region.

[0034] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple active regions are defined separately within the substrate. Each active region includes an active fin and active ends disposed on both sides of the active fin. The active fin and the active ends are made of different materials. An insulating structure is disposed within the substrate and surrounds the active regions. as well as Multiple plugs are disposed on the substrate, and the plugs simultaneously contact the active fins and the active end. The top surface of the active fins in contact with the plugs is lower than the top surface of the active end in contact with the plugs.

2. The semiconductor device according to claim 1, characterized in that, The active fins and the active end caps each have different roughness.

3. The semiconductor device according to claim 1, characterized in that, The active end includes an epitaxial material.

4. The semiconductor device according to claim 1 or 3, characterized in that, There is a height difference between the active end and the active fin.

5. The semiconductor device according to claim 1, characterized in that, The insulation structure includes a first insulation layer and a plurality of second insulation layers, wherein the second insulation layers are respectively disposed between adjacent active regions and surrounded by the first insulation layer.

6. The semiconductor device according to claim 5, characterized in that, Also includes: A plurality of first wires are disposed within the substrate and intersect with the active region, the first wires passing through both the first insulating layer and the second insulating layer.

7. The semiconductor device according to claim 1, characterized in that, Also includes: Multiple second wires are disposed on the substrate and intersect with the active region. The second wires directly contact the active fins and are alternately disposed with the plugs. as well as A spacer wall is disposed on the substrate and located between the second wire and the plug.

8. The semiconductor device according to claim 7, characterized in that, Also includes: Multiple contacts are disposed below the second conductor, and the contacts are located between adjacent active ends.

9. A method for forming a semiconductor device according to claim 1, characterized in that, The active end is U-shaped.

10. A method for forming a semiconductor device according to claim 1, characterized in that, The active end is L-shaped in a top view.

11. A semiconductor device, characterized in that, include: Substrate; Multiple active regions are defined within the substrate by an insulating structure, each active region including an active fin and an active end disposed on both sides of the active fin, wherein the active fin and the active end are made of different materials; as well as Multiple plugs are disposed on the substrate, and the plugs simultaneously contact the active fins and the active end. The top surface of the active fins in contact with the plugs is lower than the top surface of the active end in contact with the plugs.

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