Layout structure of charge pump unit circuit and semiconductor device

Abstract

The invention provides a layout structure of a charge pump unit circuit and a semiconductor device, and the layout structure comprises a cross coupling region which comprises a first working region, a first MOS tube of a first channel type, and a second MOS tube of a second channel type; the second working region comprises a third MOS tube and a fourth MOS tube of a second channel type, and the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are arranged in a cross coupling mode to form a switch topology of the cross coupling charge pump; wherein a first isolating ring is arranged on the periphery of the first working area to electrically isolate the first MOS tube and the second MOS tube from the second working area, and a second isolating ring is arranged on the periphery of the second working area to electrically isolate the third MOS tube and the fourth MOS tube from the first working area. In the layout structure of the charge pump unit circuit provided by the invention, the MOS transistors with the same channel type share the same isolating ring, so that the semiconductor device area occupied by the charge pump unit circuit can be reduced, and the integration level is improved.

Description

Technical Field

[0001] This application relates to the field of charge pump technology, and more particularly to a layout structure and semiconductor device for a charge pump unit circuit. Background Technology

[0002] Charge pumps can be classified into Dickson charge pump topologies, stepped topologies, and cross-coupled topologies based on different topologies. Among them, the cross-coupled topology charge pump consists of two sets of cross-coupled MOSFETs and two capacitors. Since there is no diode forward voltage drop in this structure, the charge pump's transfer efficiency is improved.

[0003] However, as power supplies for modern electronic devices trend towards miniaturization, higher demands are placed on the integration of charge pumps, requiring them to occupy less semiconductor device area. How to further reduce the semiconductor device area occupied by the charge pump unit circuit while ensuring its normal operation has become one of the pressing problems for those skilled in the art. Summary of the Invention

[0004] This application provides a technical solution aimed at minimizing the area of ​​semiconductor devices occupied by the charge pump unit circuit.

[0005] To achieve the above objectives, this application provides a layout structure for a charge pump unit circuit. The charge pump unit circuit is disposed on a semiconductor substrate, and the layout structure includes a cross-coupling region, which includes:

[0006] The first working region includes a first MOSFET and a second MOSFET of the first channel type;

[0007] The second working area is located on the semiconductor substrate near the first working area, and includes a third MOS transistor and a fourth MOS transistor of the second channel type. The first MOS transistor and the second MOS transistor are cross-coupled with the third MOS transistor and the fourth MOS transistor to form a switching topology of a cross-coupled charge pump.

[0008] The first working area is surrounded by a first isolation ring, which is used to electrically isolate the first MOSFET and the second MOSFET in the first working area from the second working area. The second working area is surrounded by a second isolation ring, which is used to electrically isolate the third MOSFET and the fourth MOSFET in the second working area from the first working area.

[0009] In some embodiments, the charge pump unit circuit further includes a third isolation ring, which at least surrounds the cross-coupling region to electrically isolate the cross-coupling region from the area outside the area surrounded by the third isolation ring.

[0010] In some embodiments, a first working area and a second working area are arranged side by side on a semiconductor substrate, wherein a second MOS transistor is located on a first side of a first MOS transistor, a third MOS transistor is located on a second side of a first MOS transistor, the second side is adjacent to the first side, and a fourth MOS transistor is located on one side of the third MOS transistor and is adjacent to the second MOS transistor.

[0011] In some embodiments, the charge pump unit circuit further includes a first capacitor located on one side of the cross-coupling region. One end of the first capacitor is connected to the drain of the first MOS transistor and the third MOS transistor, and the other end of the first capacitor is used to receive a first clock control signal.

[0012] The second capacitor is located on the other side of the cross-coupling region and is opposite to the first capacitor. One end of the second capacitor is connected to the drain of the second MOSFET and the fourth MOSFET, and the other end of the second capacitor is used to receive the second clock control signal.

[0013] In some embodiments, the first capacitor and the second capacitor are MOM capacitor arrays.

[0014] In some embodiments, the first MOSFET and the third MOSFET are configured with a common gate, and the drain of the first MOSFET is connected to the drain of the third MOSFET to form a first horizontal arm. The second MOSFET and the fourth MOSFET are configured with a common gate, and the drain of the second MOSFET is connected to the drain of the fourth MOSFET to form a second horizontal arm. The first horizontal arm is connected to the first capacitor and the common gate of the second MOSFET and the fourth MOSFET, respectively. The second horizontal arm is connected to the second capacitor and the common gate of the first MOSFET and the third MOSFET, respectively. The sources of the first MOSFET and the second MOSFET are connected to an input terminal, and the sources of the third MOSFET and the fourth MOSFET are connected to an output terminal.

[0015] In some embodiments, a first clock control circuit and a second clock control circuit are also included.

[0016] The first clock control circuit is connected to the first capacitor;

[0017] The second clock control circuit is connected to the second capacitor.

[0018] The first clock control circuit and the second clock control circuit are used to control the alternating charging and discharging of the first capacitor and the second capacitor to achieve voltage doubling throughout the entire cycle.

[0019] In some embodiments, the first clock control circuit is located on one side of the first capacitor and opposite to the cross-coupling region, and the second clock control circuit is located on one side of the second capacitor and opposite to the cross-coupling region.

[0020] In some embodiments, the first clock control circuit is used to output a first clock control signal, and the second clock control circuit is used to output a second clock control signal. The first clock control signal and the second clock control signal are two-phase non-overlapping clock signals.

[0021] This application also provides a semiconductor device that includes a charge pump unit circuit in the layout structure described above.

[0022] The layout structure and semiconductor device of the charge pump unit circuit provided in this application provide four cross-coupled MOS transistors to form a cross-coupled charge pump unit circuit. Furthermore, a first working area and a second working area are designed. A first MOS transistor and a second MOS transistor, both having the same first channel type, are placed in the first working area, while a third MOS transistor and a fourth MOS transistor, both having the same second channel type, are placed in the second working area. Through this layout design, MOS transistors with the same channel type are placed in the same working area, and an isolation ring is set around the periphery of this working area. This allows two MOS transistors with the same channel type in the same working area to share the same isolation ring, thereby reducing the semiconductor device area occupied by the charge pump unit circuit and improving integration density. Moreover, the areas enclosed by the two isolation rings do not overlap, ensuring the isolation effect of the two isolation rings. Attached Figure Description

[0023] Figure 1 A schematic diagram of a charge pump unit circuit with a cross-coupled topology is provided in this application;

[0024] Figure 2a This is a schematic diagram of the circuit layout structure of the charge pump unit provided in the first embodiment of this application;

[0025] Figure 2b This is a schematic diagram of the circuit layout structure of the charge pump unit provided in the second embodiment of this application;

[0026] Figure 3 This is a top view schematic diagram of the charge pump unit circuit structure provided in the second embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the circuit layout structure of the charge pump unit provided in the third embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the circuit layout structure of the charge pump unit provided in the fourth embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the circuit layout structure of the charge pump unit provided in the fifth embodiment of this application;

[0030] Figure 7A schematic diagram of the timing signals of the first clock circuit and the second clock circuit provided in the embodiments of this application;

[0031] Figure 8 This is a schematic diagram of a two-stage cascaded charge pump topology.

[0032] Figure 9 This is a schematic diagram of an n-stage cascaded charge pump layout provided for an embodiment of this application. Detailed Implementation

[0033] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0034] Charge pumps are widely used in integrated circuits. They achieve functions such as voltage multiplication and negative voltage by transferring charge through capacitors.

[0035] like Figure 1 The diagram illustrates a cross-coupled topology charge pump unit circuit, comprising two pump capacitors (referred to in this application as the first capacitor C1 and the second capacitor C2), a first MOSFET M1 and a second MOSFET M2 having a first channel type, and a third MOSFET M3 and a fourth MOSFET M4 having a second channel type. The first MOSFET M1 and the third MOSFET M3 share a common gate, with the drain of the first MOSFET M1 connected to the drain of the third MOSFET M3 to form a first horizontal arm. The second MOSFET M2 and the fourth MOSFET M4 share a common gate, with the drain of the second MOSFET M2 connected to the drain of the fourth MOSFET M4 to form a second horizontal arm. The first horizontal arm is connected to the first capacitor C1 and the common gate of the second MOSFET M2 and the fourth MOSFET M4, respectively. The second horizontal arm is connected to the second capacitor C2 and the common gate of the first MOSFET M1 and the third MOSFET M3, respectively. The sources of the first MOSFET M1 and the second MOSFET M2 are connected to an input terminal, and the sources of the third MOSFET M3 and the fourth MOSFET M4 are connected to an output terminal. For the charge pump unit circuit of this cross-coupled topology, the required voltage can be output throughout the entire cycle.

[0036] The purpose of this application is to provide a technical solution that can reduce the semiconductor device area occupied by the charge pump unit circuit 100. Based on this purpose, such as Figure 2aAs shown, this application embodiment provides a layout structure of a charge pump unit circuit 100 disposed on a semiconductor substrate. The charge pump unit circuit 100 includes a cross-coupling region 11. The cross-coupling region 11 includes a first working region 111 and a second working region 112, with the second working region 112 located on the semiconductor substrate adjacent to the first working region 111. The first working region 111 includes a first MOS transistor 1111 and a second MOS transistor 1112 of a first channel type, and the second working region 112 includes a third MOS transistor 1121 and a fourth MOS transistor 1122 of a second channel type. The first MOS transistor 1111 and the second MOS transistor 1112 are cross-coupled with the third MOS transistor 1121 and the third MOS transistor 1121 to form a switching topology of a cross-coupled charge pump. The first working area 111 is surrounded by a first isolation ring 113, which is used to electrically isolate the first MOSFET 1111 and the second MOSFET 1112 in the first working area 111 from the second working area 112; the second working area 112 is surrounded by a second isolation ring 114, which is used to electrically isolate the third MOSFET 1121 and the fourth MOSFET 1122 in the second working area 112 from the first working area 111.

[0037] It should be noted that a first-channel MOSFET (hereinafter referred to as a first-channel MOSFET) refers to a MOSFET with a conductive channel of the first channel type, and a second-channel MOSFET (hereinafter referred to as a second-channel MOSFET) refers to a MOSFET with a conductive channel of the second channel type. The first channel type and the second channel type are different; the first channel type is either N-channel or P-channel, and the second channel type is either N-channel or P-channel. An N-channel MOSFET is a MOSFET whose conductive channel is constructed from N-type semiconductor material, and a P-channel MOSFET is a MOSFET whose conductive channel is constructed from P-type semiconductor material.

[0038] like Figure 2aAs shown, the charge pump unit circuit 100 provided in this embodiment includes a first MOSFET 1111, a second MOSFET 1112, a third MOSFET 1121, and a fourth MOSFET 1122. The first MOSFET 1111 and the second MOSFET 1112 both have a first-channel conductive channel, while the third MOSFET 1121 and the fourth MOSFET 1122 both have a second-channel conductive channel. In the charge pump unit circuit 100 provided in this embodiment, MOSFETs with the same channel type are disposed in the same working area, and an isolation ring is disposed around the periphery of each working area. In this way, MOSFETs with the same channel type share the same isolation ring, thereby reducing the semiconductor device area occupied by the charge pump unit circuit 100 and improving the integration density of the charge pump unit circuit 100 while ensuring its robustness.

[0039] In one embodiment, such as Figure 2a As shown, the first MOSFET 1111, the second MOSFET 1112, the third MOSFET 1121, and the fourth MOSFET 1122 can be arranged in parallel. That is, the first MOSFET 1111, the second MOSFET 1112, the third MOSFET 1121, and the fourth MOSFET 1122 can be substantially on the same straight line. Among them, the first MOSFET 1111 and the second MOSFET 1112 are both located in the first working region 111 and share the first isolation ring 113; the third MOSFET 1121 and the fourth MOSFET 1122 are both located in the second working region 112 and share the second isolation ring 114.

[0040] In another embodiment, such as Figure 2b As shown, the first working area 111 and the second working area 112 are arranged side by side on the semiconductor substrate. The second MOS transistor 1112 is located on the first side of the first MOS transistor 1111, the third MOS transistor 1121 is located on the second side of the first MOS transistor 1111, the second side is adjacent to the first side, and the fourth MOS transistor 1122 is located on one side of the third MOS transistor 1121 and is adjacent to the second MOS transistor 1112.

[0041] For ease of explanation, the embodiments of this application also define, as follows: Figure 2b The up and down and left and right directions are shown. Specifically, the direction parallel to the first working area 111 and pointing to the second working area 112 is defined as the left and right direction, and the direction parallel to the first MOS transistor 1111 and pointing to the second MOS transistor 1112 is defined as the up and down direction (in this embodiment of the application, the description of the up and down and left and right directions follows the above definition, and will not be repeated hereafter).

[0042] like Figure 2bAs shown, the first working region 111 is located to the left of the second working region 112. The first MOSFET 1111 and the third MOSFET 1121 are located in the upper half of the cross-coupling region 11, and the second MOSFET 1112 and the fourth MOSFET 1122 are located in the lower half of the cross-coupling region 11. The second MOSFET 1112 is located below the first MOSFET 1111 and is positioned opposite to it; the third MOSFET 1121 is located to the right of the first MOSFET 1111 and is adjacent to it; the fourth MOSFET 1122 is located below the third MOSFET 1121, is positioned opposite to it, and is adjacent to the second MOSFET 1112.

[0043] Combination Figure 1 and Figure 2b In the charge pump unit circuit 100, the first MOSFET 1111 and the second MOSFET 1112 are arranged opposite each other, and the third MOSFET 1121 and the fourth MOSFET 1122 are arranged opposite each other. The first MOSFET 1111, the second MOSFET 1112, the third MOSFET 1121 and the fourth MOSFET 1122 are arranged compactly. This layout structure of the charge pump unit circuit 100 can minimize the trace length in the cross-coupling area 11, improve transmission efficiency and avoid additional power loss.

[0044] based on Figure 2b The layout design shown is as follows: Figure 3 The diagram illustrates a schematic top view of the charge pump unit circuit structure. In this embodiment, the charge pump unit circuit 100 is disposed on a semiconductor substrate, and a cross-coupling region 11 is disposed on the semiconductor substrate. The cross-coupling region 11 includes a first working region 111 and a second working region 112. The first working region 111 includes an epitaxial layer having a second conductivity type, and a first well region 1111a, a second well region 1111b, a third well region 1112a, and a fourth well region 1112b having a first conductivity type are disposed in the epitaxial layer. A first insulating gate layer 1111c is formed between the first well region 1111a and the second well region 1111b. The first well region 1111a, the second well region 1111b, and the first insulating gate layer 1111c form a first MOSFET 1111 with a first channel type. A second insulating gate layer 1112c is formed between the third well region 1112a and the fourth well region 1112b. The third well region 1112a, the fourth well region 1112b, and the second insulating gate layer 1112c form a second MOSFET 1112 with a first channel type. A first isolation ring 113 with a first conductivity type is disposed around the first working region 111.

[0045] The second working region 112 includes an epitaxial layer having a second conductivity type. A fifth well region 101 having a first conductivity type is disposed in the epitaxial layer. In the fifth well region 101, a sixth well region 1121a, a seventh well region 1121b, an eighth well region 1122a, and a ninth well region 1122b having a second conductivity type are disposed near the surface of the semiconductor substrate. A third insulating gate layer 1121c is formed between the sixth well region 1121a and the seventh well region 1121b. The sixth well region 1121a, the seventh well region 1121b, and the third insulating gate layer 1121c form a third MOS transistor 1121 having a second channel type. A fourth insulating gate layer 1122c is formed between the eighth well region 1122a and the ninth well region 1122b. The eighth well region 1122a, the ninth well region 1122b, and the fourth insulating gate layer 1122c form a fourth MOS transistor 1122 having a second channel type. A second isolation ring 114 with a first conductivity type is provided around the second working area 112. It should be noted that the conductivity type of the charge used as signal charge is called the first conductivity type, and the conductivity type opposite to the first conductivity type is called the second conductivity type.

[0046] The first well region 1111a serves as the source terminal of the first MOSFET 1111, and the third well region 1112a serves as the source terminal of the second MOSFET 1112. The first well region 1111a and the third well region 1112a are connected to the input terminal of the charge pump unit circuit 100. The seventh well region 1121b serves as the source terminal of the third MOSFET 1121, and the ninth well region 1122b serves as the source terminal of the fourth MOSFET 1122. The seventh well region 1121b and the ninth well region 1122b are connected to the output terminal of the charge pump unit circuit 100.

[0047] The first insulating gate layer 1111c is connected to the third insulating gate layer 1121c, enabling the first MOSFET 1111 and the third MOSFET 1121 to share a common gate. The second well region 1111b and the sixth well region 1121a are connected, enabling the first MOSFET 1111 and the third MOSFET 1121 to share a common drain, forming a first horizontal arm. The second insulating gate layer 1112c is connected to the fourth insulating gate layer 1122c, enabling the second MOSFET 1112 and the fourth MOSFET 1122 to share a common gate. The fourth well region 1112b and the eighth well region 1122a are connected, enabling the second MOSFET 1112 and the fourth MOSFET 1122 to share a common drain, forming a second horizontal arm. The first horizontal arm is connected to the second insulating gate layer 1112c and the fourth insulating gate layer 1122c, respectively, and the second horizontal arm is connected to the first insulating gate layer 1111c and the third insulating gate layer 1121c, respectively.

[0048] Combination Figure 1 and Figure 3A first capacitor 13 can be connected to the first horizontal arm, and a second capacitor 14 can be connected to the second horizontal arm. Controlled by a clock control circuit, the charge pump unit circuit 100 can achieve functions such as voltage multiplication and negative voltage. In one embodiment, the first capacitor 13 and the second capacitor 14 can be set separately from the charge pump unit circuit 100.

[0049] like Figure 4 As shown, as an optional implementation, the charge pump unit circuit 100 provided in this application embodiment further includes a third isolation ring 12. The third isolation ring 12 at least surrounds the cross-coupling region 11 to electrically isolate the cross-coupling region 11 from the area outside the area surrounded by the third isolation ring 12. In this way, the cross-coupling region 11 belonging to the high voltage domain can be isolated from other low voltage domains, preventing crosstalk between high and low voltage regions and improving the robustness of the charge pump unit circuit 100. It should be noted that in the charge pump unit circuit 100, the high voltage domain and low voltage domain are relative, and the voltage of the high voltage domain is higher than that of the low voltage domain. In this application embodiment, the specific voltage values ​​of the high and low voltage domains are not limited.

[0050] To further illustrate the charge pump unit circuit provided in the embodiments of this application, the structure of the charge pump unit circuit will be described below with the first channel type being an N-type channel and the second channel type being a P-type channel as an example.

[0051] Combination Figure 3 and Figure 4A P-type epitaxial layer is formed on a semiconductor substrate. In the first working region of the P-type epitaxial layer, N-type doping is performed in selected areas near the surface of the semiconductor substrate, forming a first well region 1111a, a second well region 1111b, a third well region 1112a, and a fourth well region 1112b, each having a first conductivity type. The first well region 1111a, the second well region 1111b, the third well region 1112a, and the fourth well region 1112b are not in contact with each other. A first insulating gate layer 1111c is formed by forming polysilicon on the surface of the semiconductor substrate in the region between the first well region 1111a and the second well region 1111b; a second insulating gate layer 1112c is formed by forming polysilicon on the surface of the semiconductor substrate in the region between the third well region 1112a and the fourth well region 1112b. Aluminum plates can be disposed on the surfaces of the first well region 1111a, the second well region 1111b, the third well region 1112a, and the fourth well region 1112b, respectively, so that the first well region 1111a, the second well region 1111b, and the first insulating gate layer 1111c form a first MOSFET 1111, and the third well region 1112a, the fourth well region 1112b, and the second insulating gate layer 1112c form a second MOSFET 1112. A first isolation ring 113 is formed by DNW doping around the first working region. The first MOSFET 1111 and the second MOSFET 1112 share the first isolation ring 113.

[0052] Continue to refer to Figure 3 and Figure 4 In the second working region of the P-type epitaxial layer, N-type doping is performed in a selected area to obtain a fifth well region 101 with a first conductivity type. In the fifth well region 101, a selected area near the surface of the semiconductor substrate is P-type doped to obtain a sixth well region 1121a, a seventh well region 1121b, an eighth well region 1122a, and a ninth well region 1122b with a second conductivity type. The sixth well region 1121a, the seventh well region 1121b, the eighth well region 1122a, and the ninth well region 1122b are not in contact with each other. A third insulating gate layer 1121c is formed by depositing polysilicon on the surface of the semiconductor substrate in the region between the sixth well region 1121a and the seventh well region 1121b; a fourth insulating gate layer 1122c is formed by depositing polysilicon on the surface of the semiconductor substrate in the region between the eighth well region 1122a and the ninth well region 1122b. Aluminum plates can be disposed on the surfaces of the sixth well region 1121a, the seventh well region 1121b, the eighth well region 1122a, and the ninth well region 1122b, respectively, so that the sixth well region 1121a, the seventh well region 1121b, and the third insulating gate layer 1121c form the third MOSFET 1121, and the eighth well region 1122a, the ninth well region 1122b, and the fourth insulating gate layer 1122c form the fourth MOSFET 1122. A second isolation ring 114 is formed by DNW doping around the second operating region. The third MOSFET 1121 and the fourth MOSFET 1122 share the second isolation ring 114.

[0053] Based on the above description, the charge pump unit circuit provided in this application places MOS transistors with the same channel type in the same working area and sets an isolation ring around the working area, so that MOS transistors with the same channel type share the same isolation ring, thereby reducing the semiconductor device area occupied by the charge pump unit circuit and improving the integration density.

[0054] A third isolation ring 12 is formed by P-type heavy doping around the cross-coupling region 11. In this way, the cross-coupling region 11, which belongs to the high voltage domain, is electrically isolated from other low voltage domains, preventing crosstalk between high and low voltage regions and improving the robustness of the charge pump unit circuit 100.

[0055] like Figure 5 As shown, in one embodiment, the charge pump unit circuit 100 further includes a first capacitor 13 and a second capacitor 14 integrated on a semiconductor substrate. The first capacitor 13 is located on one side of the cross-coupling region 11. One end of the first capacitor 13 is connected to the drain of the first MOSFET 1111 and the third MOSFET 1121. The other end of the first capacitor 13 is used to receive a first clock control signal. The second capacitor 14 is located on the other side of the cross-coupling region 11 and is opposite to the first capacitor 13. One end of the second capacitor 14 is connected to the drain of the second MOSFET 1112 and the fourth MOSFET 1122. The other end of the second capacitor 14 is used to receive a second clock control signal.

[0056] Specifically, such as Figure 5 As shown, the first capacitor 13 and the second capacitor 14 are positioned opposite each other, located on the upper and lower sides of the cross-coupling region 11, respectively. Combined with... Figure 1 and Figure 5 As can be seen, in the layout structure of the charge pump unit circuit 100 provided in this application embodiment, the direction from the input terminal to the output terminal of the circuit is basically parallel to the left and right direction. In the vertical direction, the layout structure of the charge pump unit circuit 100 provided in this application embodiment makes full use of the vertical spatial layout, and the first capacitor 13 and the second capacitor 14 are placed symmetrically and compactly in the vertical direction. In this way, the trace length of the high current path between the capacitor and the MOSFET can be effectively controlled, thereby avoiding the increase in delay caused by excessive parasitic resistance and parasitic capacitance of the high current trace between the capacitor and the MOSFET, and reducing circuit loss.

[0057] In one embodiment, the first capacitor 13 and the second capacitor 14 can be an MOM (Metal-Oxide-Metal) capacitor array. The MOM capacitor array includes a substrate and a conductive layer. The conductive layer includes two comb-shaped structures: a first electrode and a second electrode. The first and second electrodes have opposite polarities, and the electrode strips contained in each of the two comb-shaped structures are arranged in an alternating pattern, thereby forming capacitance between the electrode strips of different electrodes. The capacitance value of the MOM capacitor array is equal to the sum of the capacitances formed by these electrode strips. Using an MOM capacitor array design helps to increase the capacitance per unit area, thereby helping to reduce the area occupied by MOM capacitors and thus helping to improve the integration density of semiconductor circuits.

[0058] In another embodiment, the first capacitor 13 and the second capacitor 14 may also be a MIM (Metal-Insulator-Metal) capacitor array. Alternatively, the first capacitor 13 and the second capacitor 14 may also be a combination of a MOM capacitor array and a MIM capacitor array.

[0059] In one embodiment, the charge pump unit circuit 100 further includes a first clock control circuit 15 and a second clock control circuit 16. The first clock control circuit 15 is connected to the first capacitor 13, and the second clock control circuit 16 is connected to the second capacitor 14. The first clock control circuit 15 and the second clock control circuit 16 are used to control the alternating charging and discharging of the first capacitor 13 and the second capacitor 14, so that the charge pump unit circuit 100 can achieve voltage doubling throughout the entire cycle.

[0060] In one embodiment, the first clock control circuit 15, the first capacitor 13, the second clock control circuit 16, and the second capacitor 14 are arranged substantially symmetrically on both sides of the cross-coupling region 11 in the circuit layout.

[0061] Specifically, such as Figure 6 As shown, the first capacitor 13 and the second capacitor 14 are arranged symmetrically on the upper and lower sides of the cross-coupling region 11, and the first clock control circuit 15 and the second clock control circuit 16 are arranged symmetrically on the upper and lower sides of the cross-coupling region 11. Furthermore, the first capacitor 13 is located between the cross-coupling region 11 and the first clock control circuit 15, and the second capacitor 14 is located between the cross-coupling region 11 and the second clock control circuit 16. It should be noted that the area where the clock control circuits are located belongs to the low-voltage domain relative to the cross-coupling region 11. In this embodiment, through the above layout design, capacitors are used to separate the area where the clock control circuits are located from the cross-coupling region 11, ensuring a certain distance between the low-voltage domain and the high-voltage domain, reducing the risk of latch-up in the layout, and also facilitating the separate layout of low-voltage and high-voltage power ground traces.

[0062] Furthermore, the charge pump unit circuit 100 provided in this embodiment, through its symmetrical layout, ensures that the rectangular structure and internal wiring of the single-stage charge pump unit circuit 100 are completely consistent and symmetrical, reducing the probability of mismatch. It minimizes the wiring distance between modules in the single-stage charge pump unit circuit 100, thereby reducing wiring parasitics, improving switching efficiency, enhancing the robustness of the single-stage charge pump unit circuit 100, and ensuring that the overall layout of the multi-stage cascaded charge pump unit circuit 100 is rectangular, facilitating layout and connection with other circuit modules.

[0063] The first clock control circuit 15 outputs a first clock control signal, and the second clock control circuit 16 outputs a second clock control signal. The first and second clock control signals are two-phase non-overlapping clock signals. For example,... Figure 7 The diagram shows the clock control signals of the first clock control circuit and the second clock control circuit. For ease of explanation, the output clock control signal of the first clock control circuit is denoted as the first clock control signal CLKN, and the output clock control signal of the second clock control circuit is denoted as the second clock control signal CLKN. Figure 7 As shown, the first clock control signal and the second clock control signal are two-phase non-overlapping clock signals. Combined with... Figure 1 and Figure 7 When the first clock control signal CLKN changes from high to low and the second clock control signal CLKN changes from low to high, the second clock control signal CLKN first becomes high, turning off the second MOSFET 1112 to prevent reverse current from flowing through node 2 (i.e., the connection node between the second capacitor 14 and the second horizontal arm) to the input terminal. Conversely, when the first clock control signal CLKN changes from low to high and the second clock control signal CLKN changes from high to low, the first clock control signal CLKN first becomes high, turning off the first MOSFET 1111 to prevent reverse current from flowing through node 1 (i.e., the connection node between the first capacitor 13 and the first horizontal arm) to the input terminal.

[0064] This application also provides a charge pump, which includes a plurality of charge pump unit circuits provided in the embodiments of this application, and the charge pump unit circuits are cascaded.

[0065] To further illustrate the charge pump provided in the embodiments of this application, the following will use examples such as... Figure 8 Taking the two-stage cascaded charge pump shown as an example, the working state of the charge pump will be explained.

[0066] like Figure 8As shown, the two-stage cascaded charge pump includes a first charge pump unit circuit and a second charge pump unit circuit, which are cascaded together (i.e., the output terminal of the first charge pump unit circuit in the preceding stage is connected to the input terminal of the second charge pump unit circuit in the following stage).

[0067] For ease of explanation, the two pump capacitors in the first charge pump unit circuit are denoted as capacitor C1 and capacitor C2, respectively, and the four switching transistors are denoted as transistor MN1, transistor MN2, transistor MP1, and transistor MP2, respectively. Among them, transistor MN1 and transistor MN2 have N-type conductive channels, and transistor MP1 and transistor MP2 have P-type conductive channels.

[0068] The two pump capacitors in the second charge pump unit circuit are denoted as capacitor C3 and capacitor C4, respectively, and the four switching transistors are denoted as transistor MN3, transistor MN4, transistor MP3, and transistor MP4, respectively. Among them, transistor MN3 and transistor MN4 have N-type conductive channels, and transistor MP3 and transistor MP4 have P-type conductive channels.

[0069] In the first charge pump unit circuit, transistors MN1 and MP1 are connected via a common drain to form the first horizontal arm, and the connection node between capacitor C1 and the first horizontal arm is denoted as node a. Transistors MN2 and MP2 are connected via a common drain to form the second horizontal arm, and the connection node between capacitor C2 and the second horizontal arm is denoted as node b. In the second charge pump unit circuit, transistors MN3 and MP3 are connected via a common drain to form the third horizontal arm, and the connection node between capacitor C3 and the third horizontal arm is denoted as node c. Transistors MN4 and MP4 are connected via a common drain to form the fourth horizontal arm, and the connection node between capacitor C4 and the fourth horizontal arm is denoted as node d.

[0070] Assuming that the first clock control signal CLKN and the second clock control signal CLK are two non-overlapping clocks, the charge pump circuit operates in two states throughout the entire cycle under the control of the two clock signals.

[0071] In the first half of the cycle, when CLK is at a high potential and CLKN is at a low potential, node a generates a higher node voltage V1, and node b generates a lower node voltage V2, causing transistors MN2 and MP1 to conduct, and MN1 and MP2 to be turned off. The power supply transfers charge to pump capacitor C2 through the conducting MN2, and pump capacitor C1 transfers charge to the next stage through the conducting MP1. Simultaneously, node c generates a lower node voltage V3, and node d generates a higher node voltage V4, causing transistors MN3 and MP4 to conduct, and MP3 and MN4 to be turned off. Pump capacitor C3 obtains charge from the previous stage through the conducting MN3, while pump capacitor C4 transfers charge to the next stage through the conducting MP4.

[0072] In the latter half of the cycle, when CLK is at a low potential and CLKN is at a high potential, node a generates a lower node voltage V1, and node b generates a higher node voltage V2, causing MN1 and MP2 to conduct, and MN2 and MP1 to be cut off. The power supply transfers charge to pump capacitor C1 through the conducting MN1, and pump capacitor C2 transfers charge to the next stage through the conducting MP2. Simultaneously, node c generates a higher node voltage V3, and node d generates a lower node voltage V4, causing MN4 and MP3 to conduct, and MP4 and MN3 to be cut off. Pump capacitor C4 obtains charge from the previous stage through the conducting MN4, while pump capacitor C3 transfers charge to the next stage through the conducting MP3. The charge pump, composed of cascaded charge pump units, can output the required voltage throughout the entire cycle, achieving voltage multiplication and negative voltage functions.

[0073] This application also provides a semiconductor device comprising a charge pump unit circuit in the layout structure described above. In one embodiment, such as Figure 9 As shown, this diagram illustrates a schematic design of an n-stage cascaded charge pump according to an embodiment of this application. In the diagram, Mn1 is the first MOS transistor of the nth stage charge pump, Mn2 is the second MOS transistor of the nth stage charge pump, Mn3 is the third MOS transistor of the nth stage charge pump, and Mn4 is the fourth MOS transistor of the nth stage charge pump. According to... Figure 9 As can be seen, MOSFETs with the same channel type (such as the first and second MOSFETs, and the third and fourth MOSFETs) share the same isolation ring, and the four MOSFETs of each charge pump share one isolation ring to achieve high and low voltage domain isolation. Through the above layout design, the semiconductor device area occupied by each charge pump stage can be reduced, and the integration density of the semiconductor device can be improved.

[0074] In the description of this application, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0075] The above-disclosed embodiments are merely preferred embodiments of this application, but are not intended to limit the scope of this application. Those skilled in the art will understand that any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and scope of this application and the appended claims are equivalent substitutions and still fall within the scope of the invention.

[0076] The application fields of the present invention include, but are not limited to, the field of electronic power conversion technology. As long as the essence of the technical solution does not deviate from the scope of the technical solutions of the various embodiments of the present invention, it shall fall within the protection scope of the present invention.

[0077] Although preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present application as disclosed in the appended claims.

Claims

1. A layout structure of a charge pump cell circuit, characterized by, The charge pump unit circuit is arranged on a semiconductor substrate, and a layout structure of the charge pump unit circuit comprises: a cross-coupling region comprising: a first working region comprising a first MOS transistor and a second MOS transistor of a first channel type; a second working region located adjacent to the first working region on the semiconductor substrate, comprising a third MOS transistor and a fourth MOS transistor of a second channel type, the first MOS transistor and the second MOS transistor being arranged in cross-coupling with the third MOS transistor and the fourth MOS transistor to form a switch topology of a cross-coupling charge pump; wherein a first isolation ring is arranged around the first working region to electrically isolate the first MOS transistor and the second MOS transistor in the first working region from the second working region, and a second isolation ring is arranged around the second working region to electrically isolate the third MOS transistor and the fourth MOS transistor in the second working region from the first working region.

2. The layout structure of a charge pump cell circuit according to claim 1, wherein, The charge pump unit circuit further comprises a third isolation ring surrounding at least the cross-coupling region to electrically isolate the cross-coupling region from regions outside the third isolation ring.

3. The layout structure of the charge pump unit circuit according to claim 1, wherein: the first working region and the second working region are arranged side by side on the semiconductor substrate, wherein the second MOS transistor is located on a first side of the first MOS transistor, the third MOS transistor is located on a second side of the first MOS transistor, the second side is adjacent to the first side, and the fourth MOS transistor is located on a side of the third MOS transistor and adjacent to the second MOS transistor.

4. The layout structure of charge pump cell circuit according to claim 1, wherein, The charge pump unit circuit further comprises: a first capacitor located on one side of the cross-coupling region, one end of the first capacitor being commonly connected to the drains of the first MOS transistor and the third MOS transistor, and the other end of the first capacitor being configured to receive a first clock control signal; a second capacitor located on the other side of the cross-coupling region and opposite to the first capacitor, one end of the second capacitor being commonly connected to the drains of the second MOS transistor and the fourth MOS transistor, and the other end of the second capacitor being configured to receive a second clock control signal.

5. The layout structure of charge pump cell circuit according to claim 4, characterized in that: The first capacitor and the second capacitor are MOM capacitor arrays.

6. The layout structure of charge pump cell circuit according to claim 4, wherein: The first MOS transistor and the third MOS transistor are connected in common gate, the drain of the first MOS transistor is connected to the drain of the third MOS transistor to form a first horizontal arm, the second MOS transistor and the fourth MOS transistor are connected in common gate, the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor to form a second horizontal arm, the first horizontal arm is connected to the first capacitor and the common gate of the second MOS transistor and the fourth MOS transistor respectively, the second horizontal arm is connected to the second capacitor and the common gate of the first MOS transistor and the third MOS transistor respectively, and the source of the first MOS transistor and the second MOS transistor is connected to an input terminal, and the source of the third MOS transistor and the fourth MOS transistor is connected to an output terminal.

7. The layout structure of charge pump cell circuit according to claim 4, wherein, The charge pump unit circuit further comprises a first clock control circuit and a second clock control circuit; The first clock control circuit is connected to the first capacitor; The second clock control circuit is connected to the second capacitor, The first clock control circuit and the second clock control circuit are used to control the first capacitor and the second capacitor to alternately charge and discharge to achieve voltage multiplication in a full cycle.

8. The layout structure of the charge pump unit circuit according to claim 7, wherein, The first clock control circuit is located on one side of the first capacitor and opposite to the cross-coupled region, and the second clock control circuit is located on one side of the second capacitor and opposite to the cross-coupled region.

9. The layout structure of charge pump cell circuit according to claim 7, wherein, The first clock control circuit is used to output a first clock control signal, and the second clock control circuit is used to output a second clock control signal, and the first clock control signal and the second clock control signal are two-phase non-overlapping clock signals.

10. A semiconductor device, characterized by comprising: The semiconductor device comprises the charge pump unit circuit in the layout structure according to any one of claims 1-9.

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