Image sensor

Abstract

The image sensor may include: a substrate; a dummy isolation pattern; and a wiring layer on the substrate. The substrate may include a pixel region having pixels, a power supply region outside the pixel region, a photoelectric converter in the substrate and corresponding to the pixels, and a ground portion in the power supply region and surrounded by a dummy isolation pattern. The ground portion may be electrically insulated from the photoelectric converter by the dummy isolation pattern. The wiring layer may include a first connection wiring structure and a second connection wiring structure. The first connection wiring structure may overlap the ground portion in a vertical direction, and may be configured to receive a power supply voltage. The second connection wiring structure may vertically overlap the photoelectric converter and may electrically connect the substrate and the first connection wiring structure. The first connection wiring structure may include a first contact electrode electrically connected to the ground portion.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0129543, filed on September 25, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to an image sensor. Background Technology

[0003] Complementary metal-oxide-semiconductor (CMOS) image sensors are solid-state image sensing devices that utilize CMOS. Compared to charge-coupled device (CCD) image sensors, which have high-voltage analog circuitry, CMOS image sensors offer lower manufacturing costs and lower power consumption due to their smaller component size. CMOS image sensors are primarily used in household appliances, including portable devices such as smartphones and digital cameras.

[0004] The pixel array that makes up a CMOS image sensor includes a photodiode in each pixel. The photodiode generates an electrical signal that varies according to the amount of incident light, and the CMOS image sensor can synthesize an image by processing the electrical signal.

[0005] Recently, in response to the demand for high-resolution images, the pixels that make up CMOS image sensors are being required to be miniaturized. As this demand for size reduction increases, effectively reducing the occurrence of dark current and white spots can be crucial. Summary of the Invention

[0006] This disclosure relates to an image sensor with improved reliability.

[0007] An image sensor according to an embodiment may include: a first chip including a first surface; and a second chip on the first chip, including a second surface, the second surface of the second chip facing the first surface of the first chip. The first chip may also include a first connection pad on the first surface of the first chip. The second chip may also include a transistor and a second connection pad electrically connected to the transistor. The second connection pad may be on the second surface of the second chip. The first connection pad and the second connection pad may be electrically connected to each other. The first chip may also include: a substrate; a plurality of photoelectric converters in the substrate and corresponding to a plurality of pixels in a pixel region of the substrate; a ground portion in a peripheral region of the substrate; a dummy isolation pattern surrounding the ground portion and extending through the substrate; and a wiring layer. The substrate may include a third surface and a fourth surface opposite to each other. The wiring layer may include a first connection wiring structure. The first connection wiring structure may be on the third surface of the substrate in the peripheral region and may be electrically connected to the second connection pad. The first connection wiring structure may include a first contact electrode electrically connected to the ground portion in the peripheral region.

[0008] An image sensor according to an embodiment may include: a substrate including a pixel region having a plurality of pixels, a power region outside the pixel region and configured to receive a power supply voltage, a plurality of photoelectric converters in the substrate corresponding to the plurality of pixels, and a ground portion in the power region of the substrate; a dummy isolation pattern surrounding the ground portion and extending through the substrate; and a wiring layer on the substrate. The ground portion may be electrically insulated from the plurality of photoelectric converters by the dummy isolation pattern. The wiring layer may further include a first connection wiring structure and a second connection wiring structure. The first connection wiring structure may be stacked with the ground portion in a vertical direction. The first connection wiring structure may be configured to receive a power supply voltage. The second connection wiring structure may be stacked with the plurality of photoelectric converters in a vertical direction. The second connection wiring structure may be electrically connected to the substrate and the first connection wiring structure. The first connection wiring structure may include a first contact electrode. The first contact electrode may be electrically connected to the ground portion.

[0009] An image sensor according to an embodiment may include: a first chip including a first surface; and a second chip on the first chip, including a second surface, the second surface of the second chip facing the first surface of the first chip. The first chip may also include a first connection pad on the first surface of the first chip. The second chip may also include a transistor and a second connection pad electrically connected to the transistor. The second connection pad may be on the second surface of the second chip. The first connection pad and the second connection pad may be electrically connected to each other. The first chip may also include: a substrate; a plurality of photoconverters in the substrate and corresponding to a plurality of pixels in a pixel region of the substrate; a pixel isolation pattern between the plurality of photoconverters; a ground portion in a peripheral region of the substrate; a dummy isolation pattern surrounding the ground portion and through the substrate; a wiring layer; a microlens layer; and a first connection wiring structure. The substrate may include a third surface and a fourth surface facing each other. The dummy isolation pattern may be spaced apart from the pixel isolation pattern. The microlens layer may be on the fourth surface of the substrate in the pixel region. The first connection wiring structure may be on the third surface of the substrate in the peripheral region and electrically connected to the second connection pad. The first connection wiring structure may include a plurality of connection wirings, a plurality of vias connecting the plurality of connection wirings, and a first contact electrode between the plurality of connection wirings and the ground portion. The first connection wiring can be electrically connected to the grounding part.

[0010] According to one embodiment, a portion of the wiring layer can be electrically connected to the ground portion of the power supply area, allowing charge to be released into the ground portion. Therefore, the reliability of the image sensor can be improved. Attached Figure Description

[0011] Figure 1 This is a block diagram of an image sensor according to an embodiment.

[0012] Figure 2 This is a circuit diagram of the pixel array of an image sensor according to an embodiment.

[0013] Figure 3 This is a cross-sectional view showing the pixel region and optical black region of an image sensor according to an embodiment.

[0014] Figures 4 to 6 This is a cross-sectional view showing the pixel region and peripheral region of an image sensor according to an embodiment.

[0015] Figure 7 This is a plan view of the power supply area of ​​an image sensor according to an embodiment, shown as an example.

[0016] Figure 8 This is a cross-sectional view showing the pixel region and peripheral region of an image sensor according to an embodiment.

[0017] Figure 9 This is a cross-sectional view showing the power supply area of ​​an image sensor according to some embodiments.

[0018] Figure 10 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example.

[0019] Figure 11 and Figure 12 It is shown Figure 10 A cross-sectional view of the power supply area in an embodiment.

[0020] Figure 13 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example.

[0021] Figure 14 It is shown Figure 13 A cross-sectional view of the power supply area in an embodiment.

[0022] Figure 15 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example.

[0023] Figure 16 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example.

[0024] Figures 17 to 19 It is shown Figure 15 A cross-sectional view of the power supply area in an embodiment. Detailed Implementation

[0025] In the following detailed description, some example embodiments are shown and described. However, example embodiments may be implemented in various forms and are not limited to the presented embodiments.

[0026] The accompanying drawings and descriptions are intended to be illustrative rather than restrictive. Throughout the specification, the same reference numerals denote the same elements.

[0027] Furthermore, for ease of understanding and description, the dimensions and thicknesses of each structure shown in the accompanying drawings are arbitrary, but the exemplary embodiments are not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of understanding and description. The concept of "substantially identical" elements can indicate that elements can be completely identical, and can also indicate that elements can be determined to be identical taking into account errors or deviations that occur during the manufacturing process.

[0028] Additionally, it will be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, the element may be directly on that other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, when an element is referred to as being "on" a reference portion, the element is positioned above or below the reference portion, and does not necessarily mean that the element is positioned "above" or "on" in a direction opposite to gravity.

[0029] Furthermore, throughout the specification, unless explicitly stated otherwise, the word “comprising” and its variations shall be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0030] Additionally, throughout the instruction manual, when "on a plane" is mentioned, it refers to viewing the target portion from above, and when "on a cross-section" is mentioned, it refers to viewing the cross-section obtained by vertically cutting the target portion from the side.

[0031] In the following text, reference will be made to Figure 1 An image sensor according to an embodiment is described.

[0032] Figure 1 This is a block diagram of an image sensor according to an embodiment.

[0033] Reference Figure 1 The image sensor 10 according to the embodiment may include a controller 1100, a timing generator 1200, a line driver 1300, a pixel array 1400, a readout circuit 1500, a ramp signal generator 1600, a data buffer 1700, and an image signal processor 1800.

[0034] In one embodiment, the image signal processor 1800 may be located outside the image sensor 10.

[0035] Image sensor 10 generates an image signal by converting light received from the outside into an electrical signal. The image signal (IMS) can be provided to image signal processor 1800.

[0036] The image sensor 10 can be installed in an electronic device with image or light sensing capabilities. For example, the image sensor 10 can be installed in electronic devices such as cameras, smartphones, wearable devices, IoT (Internet of Things) devices, home appliances, tablet PCs (personal computers), personal digital assistants (PDAs), portable multimedia players (PMPs), navigation devices, drones, advanced driver assistance systems (ADAS), etc. Furthermore, the image sensor 10 can be installed as a component integrated into electronic devices such as vehicles, furniture, manufacturing equipment, doors, and various measuring devices.

[0037] The controller 1100 typically controls individual components 1200, 1300, 1500, 1600, and 1700 included in the image sensor 10. The controller 1100 can use control signals to control the operating timing of the individual components 1200, 1300, 1500, 1600, and 1700.

[0038] In an embodiment, the controller 1100 may receive a mode signal indicating an imaging mode from an application processor, and typically controls the image sensor 10 based on the received mode signal. For example, the application processor may determine the imaging mode of the image sensor 10 based on various scenarios (such as lighting in the imaging environment, user resolution settings, sensing or learning status, etc.) and provide the determined result as a mode signal to the controller 1100.

[0039] The controller 1100 can perform control such that the multiple pixels PX of the pixel array 1400 output pixel signals according to the imaging mode, and the pixel array 1400 can output pixel signals of multiple individual pixels PX or some of the pixel signals of multiple pixels PX, and the readout circuit 1500 can sample and process the pixel signals received from the pixel array 1400.

[0040] Timing generator 1200 generates signals that serve as a reference for the operating timing of the components of image sensor 10. Timing generator 1200 controls the timing of line driver 1300, readout circuit 1500, and ramp signal generator 1600. Timing generator 1200 can provide control signals to control the timing of line driver 1300, readout circuit 1500, and ramp signal generator 1600.

[0041] The pixel array 1400 may include multiple pixels PX and multiple row lines RL and multiple column lines LL respectively connected to the multiple pixels PX.

[0042] Multiple pixels PX included in pixel array 1400 can be arranged in a matrix. Each pixel PX may include a transmission transistor. Each pixel PX may also include a logic transistor.

[0043] Logic transistors can be reset transistors, select transistors, or source follower transistors. Transfer transistors may include a transfer gate (…). Figure 3 The accompanying reference numeral "TG" is used. Each pixel PX may also include a photoelectric converter PD and a floating diffusion region (…). Figure 3 (Referring to the reference numeral "FD" in the attached diagram). Logic transistors can be shared by multiple pixels (PX).

[0044] A photoelectric converter (PD) senses incident light from the outside and converts the incident light into an electrical signal, i.e., into multiple analog pixel signals, based on the amount of light. A PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0045] Furthermore, the photoelectric converter PD can be a single-photon avalanche diode (SPAD) used in 3D sensor pixels. The level of the analog pixel signal output from the photoelectric converter PD is proportional to the amount of charge output from the photoelectric converter PD. In other words, the level of the analog pixel signal output from the photoelectric converter PD can be determined based on the amount of light entering the pixel array 1400.

[0046] Transmission transistors can be converted from photoelectric converters ( Figure 3 The charge generated by the reference numeral "PD" in the attached diagram is transferred to the floating diffusion region ( Figure 3 The attached diagram is labeled "FD". Floating diffusion area ( Figure 3 The reference numeral "FD" in the attached diagram can receive and accumulate signals from the photoelectric converter ( Figure 3 The charge generated (labeled "PD" in the attached diagram) depends on the accumulation in the floating diffusion region ( Figure 3 The amount of photoelectric charge in the figure (labeled "FD") can be controlled by the source follower transistor.

[0047] The reset transistor can periodically reset the accumulated charge in the floating diffusion region. Figure 3 The charge is indicated by the reference numeral "FD" in the attached diagram. The drain electrode of the reset transistor can be connected to the floating diffusion region ( Figure 3 The reference numeral "FD" is used in the attached diagram, and the source electrode of the reset transistor can be connected to the power supply voltage. When the reset transistor is turned on, the power supply voltage connected to the source electrode of the reset transistor can be applied to the floating diffusion region (FD). Figure 3 (Referring to the reference numeral "FD" in the attached diagram). Therefore, when the reset transistor is turned on, energy accumulates in the floating diffusion region (…). Figure 3 The charge in the attached diagram (labeled "FD") can be released, thereby resetting the floating diffusion region FD.

[0048] A source follower transistor, including a source follower gate electrode, can be used as a source follower buffer amplifier. The source follower transistor amplifies potential changes in the floating diffusion region (FD) and outputs the result to the output line.

[0049] The selection transistor, including the gate electrode selection transistor, can select the pixel PX to be read out row by row. When the selection transistor is turned on, the power supply voltage VDD can be applied to the drain electrode of the source follower transistor.

[0050] Multiple row lines RL can extend in a first direction and connect to pixels PX arranged along the first direction. For example, control signals output from row driver 1300 to row lines RL can be transmitted to the gates of transistors connected to the respective pixel PX of row lines RL.

[0051] Each column line LL can extend in a second direction intersecting the first direction and connect to multiple pixels PX arranged along the second direction. Multiple pixel signals output from the multiple pixels PX can be transmitted to the readout circuit 1500 through the multiple column lines LL.

[0052] A color filter layer and a microlens layer may be positioned on the pixel array 1400. The microlens layer may include a plurality of microlenses, and at least one pixel PX corresponding to each of the plurality of microlenses may be positioned on the microlens layer.

[0053] The color filter layer may include color filters such as red, green, and blue. For example, for a pixel PX, a color filter of one color may be positioned between pixel PX and the microlens corresponding to that pixel PX.

[0054] The row driver 1300 can generate drive signals for driving the pixel array 1400 in response to control signals from the timing generator 1200, and provides the drive signals to multiple pixels PX of the pixel array 1400 through multiple row lines RL. In an embodiment, the row driver 1300 can drive regions ( Figure 2 The reference numeral "DR" in the attached diagram provides drive signals to multiple pixels (PX).

[0055] In an embodiment, the row driver 1300 can control pixels PX on a row-line basis, enabling the pixels to sense incident light. Each row-line unit may include at least one row line RL. For example, the row driver 1300 may provide drive signals, including transmission signals, reset signals, selection signals, etc., to the pixel array 1400.

[0056] The readout circuit 1500, in response to a control signal from the timing generator 1200, converts a pixel signal (or electrical signal) received from a pixel PX connected to a selected row line RL among a plurality of pixels PX into a pixel value indicating the amount of light. The readout circuit 1500 can also convert pixel signals output through corresponding column lines LL into pixel values. For example, the readout circuit 1500 can convert a pixel signal into a pixel value by comparing a pixel signal and a ramp signal. The pixel value can be an image data item, each of which has multiple bits. Specifically, the readout circuit 1500 may include a selector, multiple comparators, multiple counter circuits, etc.

[0057] The ramp signal generator 1600 can generate a reference signal and transmit the reference signal to the readout circuit 1500.

[0058] The ramp signal generator 1600 may include a current source, a resistor, and a capacitor. The ramp signal generator 1600 can adjust the ramp voltage by adjusting the current magnitude of the variable current source or the resistance value of the variable resistor, the ramp voltage being the voltage applied to the ramp resistor. In this way, the ramp signal generator can generate multiple ramp signals with a decreasing or increasing slope determined according to the current magnitude of the variable current source or the resistance value of the variable resistor.

[0059] The data buffer 1700 can store pixel values ​​of a plurality of pixels PX connected to a selected column line LL received from the readout circuit 1500, and output the stored pixel values ​​in response to an enable signal from the controller 1100.

[0060] The image signal processor 1800 can perform image signal processing on image signals received from the data buffer 1700. For example, the image signal processor 1800 can receive multiple image signals from the data buffer 1700 and combine the received image signals to generate an image.

[0061] The image sensor 10 according to an embodiment may further include a power supply unit that provides a power supply voltage to the pixel PX or peripheral elements for operating the pixel. The power supply unit may apply a power supply voltage to the pixel PX or a first substrate on which the pixel PX is located (…). Figure 3 The reference numeral "110" is located inside the power supply area (see attached diagram). For example, the power supply unit can be accessed through the power supply area (…). Figure 2 The reference numeral "PR" in the attached figure indicates that a power supply voltage is applied to pixel PX or the first substrate on which pixel PX is located ( Figure 3 The reference numeral "110" is located inside the figure. The power supply voltage can be, for example, the voltage used to drive the pixel PX, or the voltage used to apply a voltage having a desired and / or optionally predetermined size to the first substrate (…). Figure 3The voltage (referred to as "110" in the accompanying diagram) is used as an example. As an example, the power supply voltage can be a negative bias voltage. As another example, the power supply voltage can include the ground voltage.

[0062] In the following text, reference will be made to Figure 2 and Figure 3 An image sensor according to an embodiment is described.

[0063] Figure 2 This is a circuit diagram of the pixel array of an image sensor according to an embodiment. Figure 3 This is a cross-sectional view showing the pixel region and optical black region of an image sensor according to an embodiment.

[0064] Reference Figure 2 and Figure 3 According to an embodiment, the image sensor 10 may include a first chip CH1 and a second chip CH2. The first chip CH1 includes a first connection pad 24, and the second chip CH2 includes a second connection pad 124. In an embodiment, the image sensor may have a structure in which the first chip CH1 and the second chip CH2 are joined. In other words, the first chip CH1 may be positioned on the second chip CH2.

[0065] The first chip CH1 can perform image sensing functions. The second chip CH2 may include circuitry for driving the first chip CH1 or for processing and storing electrical signals generated by the first chip CH1. The first chip CH1 may include a first surface. The first surface of the first chip CH1 may refer to the lower surface of the first chip CH1. The first surface of the first chip CH1 may be the surface facing the second chip CH2.

[0066] According to an embodiment, the first chip CH1 of the image sensor may include a first substrate 110 comprising a pixel region APS and a peripheral region ER, a pixel isolation pattern DTI1, a plurality of photoelectric converters PD located within the first substrate 110 in the pixel region APS, and a ground portion DD located within the first substrate 110 in the peripheral region ER (see...). Figure 4 ), the virtual isolation pattern DTI2 surrounding the grounding part DD (see Figure 4 ) and wiring layer 120 positioned on one surface of the first substrate 110.

[0067] The first substrate 110 may include a front surface and a rear surface facing each other. Hereinafter, the front surface and the rear surface will be referred to as the third surface 110a and the fourth surface 110b, respectively. The fourth surface 110b of the first substrate 110 may be a light-receiving surface into which light enters.

[0068] The first substrate 110 may include a pixel region APS, an optical black region OB, and a peripheral region ER.

[0069] The optical black area OB and the peripheral area ER can be located on at least one side of the pixel area APS. For example, as Figure 2 As shown, the optical black region OB and the peripheral region ER can be sequentially positioned outside the pixel region APS, and the optical black region OB can surround the pixel region APS. In other words, the optical black region OB can be positioned between the pixel region APS and the peripheral region ER.

[0070] The peripheral region ER may include a power supply region PR, a drive region DR, a sampler region CR, a cover region MR, and a protection region GR. In an embodiment, the power supply region PR, drive region DR, sampler region CR, cover region MR, and protection region GR may be positioned separately from the pixel region APS and the optical black region OB.

[0071] The driving region DR, cover region MR, sampler region CR, and protection region GR can be located outside the optical black region OB. For example, the driving region DR can be located on opposite sides of the optical black region OB in the first direction (X direction), the protection region GR can be located on opposite sides of the optical black region OB in the first direction (X direction), the sampler region CR can be located on one side of the optical black region OB in the second direction (Y direction), and the cover region MR can be located on the other side of the optical black region OB in the second direction (Y direction); however, the arrangement of the driving region DR, cover region MR, sampler region CR, and protection region GR is not limited to this.

[0072] In an embodiment, the drive region DR may refer to the region used to drive the drive signal from the row driver ( Figure 1 The reference numeral "1300" in the attached diagram indicates the area where the wiring to the multiple pixels PX is located. Additionally, the sampler region CR may refer to the area used to provide the pixel signals received from the multiple pixels PX to the readout circuitry. Figure 1 The wiring (marked by reference numeral "1500") is located in the area indicated in the attached diagram. The cover region MR may refer to the area where noise present in the drive signals provided to and / or the pixel signals received from the multiple pixels PX is decoupled. In an embodiment, a capacitor for decoupling noise may be included in the cover region MR.

[0073] The power supply region PR can be located outside the optical black region OB. For example, multiple power supply regions PR can be set and located at the edge of the optical black region OB. Multiple power supply regions PR can be set around the optical black region OB; however, this disclosure is not limited thereto. The power supply regions PR can be located on opposite sides of the drive region DR in the second direction (Y direction) and / or on opposite sides of the sampler region CR and the cover region MR in the first direction (X direction); however, this disclosure is not limited thereto.

[0074] In this embodiment, the power supply region PR may refer to the region where a power supply voltage is applied from the second chip CH2 to the pixel PX or the interior of the first substrate 110. For example, some of the plurality of power supply regions PR may be regions where wiring (e.g., the first connection wiring structure CS1) is provided for applying the power supply voltage to the pixel PX. Others of the plurality of power supply regions PR may be regions where wiring is provided for applying the power supply voltage to the first substrate 110. In this case, a negative bias voltage or a ground voltage may be applied to the first substrate 110. Therefore, the power supply voltage applied from the second chip CH2 can be provided to the pixel PX or the first substrate 110 through the power supply region PR.

[0075] The protective region GR can be located outside the optical black region OB. For example, the protective region GR can be located on the opposite side of the optical black region OB in the first direction (X direction); however, this disclosure is not limited thereto. The protective region GR can serve to block light or electrons generated by specific circuitry in the peripheral region ER from penetrating into the pixel region APS and / or the optical black region OB.

[0076] Furthermore, the conductive pad 34 may be further positioned in a region including the peripheral region ER of the image sensor 10 according to the embodiment. The conductive pad 34 may be positioned outside the pixel region APS. For example, the conductive pad 34 may be positioned at the edge portion of the first substrate 110 and on one side of the cover region MR in the second direction (Y direction); however, the arrangement of the conductive pad 34 is not limited thereto.

[0077] Already referred to Figure 2 The description describes each of the power supply region PR, drive region DR, sampler region CR, cover region MR, and protection region GR as being located outside the optical black region OB in a first direction (X direction) and / or a second direction (Y direction); however, this is an example, and the arrangement of the power supply region PR, drive region DR, sampler region CR, cover region MR, and protection region GR may be varied.

[0078] The first substrate 110 may be, for example, a silicon single-crystal wafer, a silicon epitaxial layer, or a silicon-on-insulator (SOI) substrate. The first substrate 110 may contain impurities of a first conductivity type. The first substrate 110 may be doped with impurities of the first conductivity type. For example, the impurities of the first conductivity type may be p-type impurities (such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga)).

[0079] In the following text, for ease of explanation, the constituent elements of the pixel area APS and the optical black area OB will be described in detail.

[0080] The pixel isolation pattern DTI1 can be located inside the first substrate 110. The pixel isolation pattern DTI1 can be located inside the pixel region APS and the optical black region OB. The pixel isolation pattern DTI1 can pass through the first substrate 110. The pixel isolation pattern DTI1 can be front-side deep trench isolation (FDTI).

[0081] In an embodiment, the pixel isolation pattern DTI1 may extend completely through the first substrate 110. For example, each side surface of the pixel isolation pattern DTI1 may contact the third surface 110a and the fourth surface 110b of the first substrate 110. The upper surface of the pixel isolation pattern DTI1 and the fourth surface 110b of the first substrate 110 may be flat. However, this disclosure is not limited thereto, and each upper surface of the pixel isolation pattern DTI1 may include a surface curved relative to the fourth surface 110b of the first substrate 110.

[0082] In an embodiment, the pixel isolation pattern DTI1 may have a shape in which its width decreases as it travels from the third surface 110a of the first substrate 110 toward the fourth surface 110b. In other words, the pixel isolation pattern DTI1 may have sloping side surfaces. However, this disclosure is not limited thereto, and the pixel isolation pattern DTI1 may have a shape in which its width increases as it travels from the third surface 110a of the first substrate 110 toward the fourth surface 110b, or it may have a constant width.

[0083] A pixel isolation pattern DTI1 can be positioned between a plurality of photoelectric converters PDs, as described below. The pixel isolation pattern DTI1 defines and isolates the plurality of photoelectric converters PDs. The pixel isolation pattern DTI1 may include portions extending in the first direction (X direction) and portions extending in the second direction (Y direction) on a plane defined by a first direction (X direction) and a second direction (Y direction). The pixel isolation pattern DTI1 may have a lattice structure on the plane defined by the first direction (X direction) and the second direction (Y direction) and may divide a plurality of pixels PX.

[0084] The optical black region OB may include at least one black pixel OPX. Within the optical black region OB, a pixel isolation pattern DTI1 may be positioned within the first substrate 110, isolating and defining the black pixel OPX. For example, the optical black region OB may include a first black pixel OPX1 and a second black pixel OPX2, and the first black pixel OPX1 and the second black pixel OPX2 may be isolated and defined by the pixel isolation pattern DTI1. In an embodiment, a portion of the pixel isolation pattern DTI1 may be further positioned at the boundary between the optical black region OB and the peripheral region ER.

[0085] The pixel isolation pattern DTI1 may include a first insulating isolation pattern 41, a first conductive isolation pattern 43, and a first isolation cover pattern 45.

[0086] The first insulating isolation pattern 41 may extend to conform to the inner surface of the isolation trench. The first insulating isolation pattern 41 may comprise a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high-dielectric-constant material (e.g., hafnium oxide or aluminum oxide). As another example, the first insulating isolation pattern 41 may comprise multiple layers, and individual layers may comprise different materials. In an embodiment, the first insulating isolation pattern 41 may have a refractive index lower than that of the first substrate 110. However, the materials comprised in the first insulating isolation pattern 41 are not limited to this and may vary.

[0087] The first conductive isolation pattern 43 may be positioned on the first insulating isolation pattern 41. The first conductive isolation pattern 43 may be surrounded by the first insulating isolation pattern 41. The first insulating isolation pattern 41 may be positioned between the first conductive isolation pattern 43 and the first substrate 110.

[0088] The first conductive isolation pattern 43 may comprise, for example, a crystalline semiconductor material (such as polycrystalline silicon). The first conductive isolation pattern 43 may also comprise impurities, which may comprise impurities of a first conductivity type or an impurity of a second conductivity type. Here, the first conductivity type impurity may refer to a p-type impurity, and the second conductivity type impurity may refer to an n-type impurity.

[0089] As another example, the first conductive isolation pattern 43 may comprise a crystalline semiconductor material (such as undoped polycrystalline silicon). Here, the term "undoped" may mean that no intentional doping process has been performed. However, the material comprised of the first conductive isolation pattern 43 is not limited to this and may vary.

[0090] The first isolation cover pattern 45 of the pixel isolation pattern DTI1 can be positioned on the first conductive isolation pattern 43. The first conductive isolation pattern 43 and the first isolation cover pattern 45 can be positioned to overlap in the vertical direction (Z direction), and the first isolation cover pattern 45 can be positioned adjacent to the third surface 110a of the first substrate 110.

[0091] exist Figure 3 In the diagram, one surface of the first isolation cover pattern 45 and the third surface 110a of the first base 110 are shown to be flat; however, one surface of the first isolation cover pattern 45 and the third surface 110a of the first base 110 may have curvature.

[0092] The first isolation cover pattern 45 may comprise a non-conductive material. The first isolation cover pattern 45 may comprise a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high dielectric constant material (e.g., hafnium oxide or aluminum oxide). However, the material comprised in the first isolation cover pattern 45 is not limited to these and may vary.

[0093] The image sensor according to an embodiment may also include an element isolation pattern (STI) positioned inside the first substrate 110.

[0094] The component isolation pattern STI can be positioned inside the first substrate 110. The component isolation pattern STI can be positioned adjacent to the third surface 110a of the first substrate 110. The component isolation pattern STI can be a shallow trench isolation (STI) layer.

[0095] The component isolation pattern STI can be penetrated by the pixel isolation pattern DTI1. In other words, the component isolation pattern STI can be positioned as a portion of the side surface surrounding the pixel isolation pattern DTI1. Additionally, the component isolation pattern STI can be penetrated by the dummy isolation pattern DTI2, which will be described below. The component isolation pattern STI can be positioned as a portion of the side surface surrounding the dummy isolation pattern DTI2.

[0096] The component isolation pattern (STI) may have a shape in which its width decreases as it travels from the third surface 110a of the first substrate 110 toward the fourth surface 110b. The component isolation pattern (STI) may be positioned separately from the photoelectric converter (PD).

[0097] exist Figure 3 In the diagram, one surface of the element isolation pattern STI and the third surface 110a of the first substrate 110 are shown to be flat; however, one surface of the element isolation pattern STI and the third surface 110a of the first substrate 110 may have curvature.

[0098] The photoelectric converter PD in the pixel region APS can be located inside the first substrate 110 to correspond to each of the plurality of pixels PX. For example, the pixel region APS may include a plurality of pixels PX arranged in two dimensions along a first direction (X direction) and a second direction (Y direction). The plurality of pixels PX may include a number of pixels PX in an N×M array. The photoelectric converter PD can be located inside the first substrate 110 to correspond to each of the plurality of pixels PX arranged in two dimensions along the first direction (X direction) and the second direction (Y direction). Here, each of N and M may be an integer greater than 1 independently. In an embodiment, the photoelectric converter PD may be defined by a pixel isolation pattern DTI1. In addition, the photoelectric converter PD in the optical black region OB can be located inside the first substrate 110 to correspond to a portion of the plurality of black pixels OPX1 and OPX2.

[0099] In this embodiment, the optical black region OB can be a region where light does not enter the first substrate 110. The photoelectric converter PD in the optical black region OB can be located inside the first substrate 110 to correspond to the first black pixel OPX1, and may not be located inside the first substrate 110 corresponding to the second black pixel OPX2. In other words, in the optical black region OB, the region of the first substrate 110 corresponding to the second black pixel OPX2 can be a dummy region without any impurities.

[0100] The photoelectric converter PD located inside the first substrate 110 in the optical black region OB to correspond to the first black pixel OPX1 may have a structure similar to or the same as that of the photoelectric converter PD located inside the first substrate 110 in the pixel region APS to correspond to the pixel PX, but may not perform the same operations as the photoelectric converter PD located inside the first substrate 110 to correspond to the pixel PX (i.e., the operation of receiving light and generating electrical signals).

[0101] The first black pixel OPX1 can sense the amount of charge that can be generated from the photoelectric converter PD when the light is blocked, and provides a first reference charge amount. When calculating the amount of charge generated from pixel PX, the first reference charge amount can be converted into a relative reference value.

[0102] Furthermore, in the optical black area OB, the signal generated in the dummy area of ​​the first substrate 110 corresponding to the second black pixel OPX2 can be used as information for removing subsequent process noise. In other words, the second black pixel OPX2 can sense the amount of charge that can be generated without the photoelectric converter PD and provide a second reference charge amount. The second reference charge amount can be used as information for removing process noise.

[0103] The photodiode PD may contain impurities of a second conductivity type. The photodiode PD may be a region in the first substrate 110 doped with impurities of the second conductivity type. The impurities of the second conductivity type may have a conductivity type opposite to that of the impurities of the first conductivity type. For example, the impurities of the second conductivity type may include n-type impurities (such as phosphorus, arsenic, bismuth, and / or antimony). The n-type impurities implanted in the photodiode PD may form a pn junction with the p-type impurities implanted in the first substrate 110 to provide a photodiode.

[0104] A single photoconverter PD may include a first region adjacent to a third surface 110a of the first substrate 110 and a second region adjacent to a fourth surface 110b. A difference in impurity concentration may exist between the first and second regions of the photoconverter PD. Therefore, the photoconverter PD may have a potential gradient between the third surface 110a and the fourth surface 110b of the first substrate 110. However, in some embodiments, the photoconverter PD may not have a potential gradient between the third surface 110a and the fourth surface 110b of the first substrate 110.

[0105] In the pixel region APS and the optical black region OB, the transmission gate TG can be positioned on the third surface 110a of the first substrate 110 to correspond to the pixel PX and the black pixels OPX1 and OPX2. The transmission gate TG can be positioned between the pixel isolation pattern DTI1 that defines the pixel PX and the black pixels OPX1 and OPX2.

[0106] In an embodiment, the transfer gate TG may be vertical. A portion of the transfer gate TG may be located inside the first substrate 110, and another portion may protrude from the third surface 110a of the first substrate 110. The portion of the transfer gate TG located inside the first substrate 110 may have a shape in which its width decreases as the transfer gate TG travels from the third surface 110a toward the fourth surface 110b of the first substrate 110. Therefore, the portion of the transfer gate TG located inside the first substrate 110 may have sloping side surfaces. However, the shape of the transfer gate TG is not limited to this and may be varied. For example, the transfer gate TG may be planar in which the portion located inside the first substrate 110 is omitted.

[0107] Although not in Figure 3 As shown, but the gate spacer may be further positioned on the opposite side surface of the first portion of the transfer gate TG. The gate spacer may comprise, for example, silicon nitride, silicon carbonitride, or silicon oxynitride.

[0108] The gate dielectric layer Gox may be positioned between the transmission gate TG and the first substrate 110. The gate dielectric layer Gox may comprise various insulating materials. For example, the gate dielectric layer Gox may comprise silicon nitride, silicon carbonitride, or silicon oxynitride.

[0109] The image sensor 10 according to an embodiment may further include a floating diffusion region FD located inside the first substrate 110.

[0110] The floating diffusion region FD may be positioned inside the first substrate 110 on one side of the transmission gate TG. The floating diffusion region FD may be positioned adjacent to the third surface 110a of the first substrate 110. The floating diffusion region FD may be doped with an impurity of a second conductivity type. For example, the impurity of the second conductivity type may be an n-type impurity.

[0111] The image sensor 10 according to the embodiment can be a back-illuminated image sensor. Light can enter the first substrate 110 through the fourth surface 110b of the first substrate 110. Electron-hole pairs can be generated at the pn junction by the incident light. The generated electrons can migrate to the photoelectric converter PD. In other words, when a voltage is applied to the transmission gate TG, the aforementioned electrons can migrate to the floating diffusion region FD.

[0112] Wiring layer 120 may be positioned on the third surface 110a of the first substrate 110. Wiring layer 120 may be positioned in the pixel region APS, optical black region OB, and peripheral region ER. Wiring layer 120 may be positioned between the second chip CH2 and the first substrate 110. For example, wiring layer 120 may be positioned between the second surface of the second chip CH2 and the third surface 110a of the first substrate 110. Wiring layer 120 may contact each of the second surface of the second chip CH2 and the third surface 110a of the first substrate 110. In an embodiment, wiring layer 120 may be electrically connected to constituent elements located inside the first substrate 110. As an example, wiring layer 120 may be electrically connected to the second chip CH2 and the first substrate 110.

[0113] The wiring layer 120 may include a first connection wiring M1 to a fourth connection wiring M4, a via VA, and a first upper interlayer insulating layer to a sixth upper interlayer insulating layer IL1, IL2, IL3, IL4, IL5, and IL6 positioned between the third surface 110a of the first substrate 110 and the second chip CH2.

[0114] Each of the first to sixth upper interlayer insulating layers IL1, IL2, IL3, IL4, IL5, and IL6 may be composed of at least one of, for example, silicon oxide film, silicon nitride film, silicon oxynitride film, and porous low-dielectric film. However, the number and materials of the layers included in the upper interlayer insulating layers IL are not limited thereto and may vary.

[0115] First connecting wires M1 to fourth connecting wires M4 may be located between or within the first upper interlayer insulating layer to the sixth upper interlayer insulating layer IL1, IL2, IL3, IL4, IL5, and IL6. First connecting wires M1 to fourth connecting wires M4 may contain, for example, a conductive material (such as copper (Cu)). First connecting wires M1 to fourth connecting wires M4 may be interconnected via vias VA located within the first upper interlayer insulating layer to the sixth upper interlayer insulating layer IL1, IL2, IL3, IL4, IL5, and IL6.

[0116] In an embodiment, the first connecting wiring M1 to the fourth connecting wiring M4 and the via VA between them can constitute a connecting wiring structure CS. The connecting wiring structure CS can be located in the pixel region APS, the power region PR, the cover region MR, the drive region DR, and the protection region GR, respectively. For example, in the pixel region APS, the first connecting wiring M1 to the fourth connecting wiring M4 and the via VA between them can constitute a second connecting wiring structure CS2.

[0117] The second connection wiring structure CS2 can be located within the pixel region APS. The second connection wiring structure CS2 can be superimposed on the photoelectric converter PD in the vertical direction (Z direction). Here, the second connection wiring structure CS2 can be specified as a connection wiring structure located within the pixel region APS.

[0118] In one embodiment, the second connection wiring structure CS2 can be electrically connected to a plurality of pixels PX. The second connection wiring structure CS2 can also be electrically connected to a device for controlling the plurality of pixels PX. Furthermore, the second connection wiring structure CS2 can be electrically connected to a photoelectric converter PD. For example, as... Figure 3 As shown, the second connection wiring structure CS2 can be electrically connected to the transmission gate TG. In this case, the second connection wiring structure CS2 can transmit the electrical signal used to drive the transmission transistor from the transistor TR of the second chip CH2 to the transmission gate TG. As another example, the second connection wiring structure CS2 can be electrically connected to the floating diffusion region FD. As a further example, as... Figure 5 As shown, the second connection wiring structure CS2 can be floating within the pixel region APS. In other words, the second connection wiring structure CS2 can be floating so as not to be electrically connected to multiple pixels PX.

[0119] In this embodiment, the second connection wiring structure CS2 is electrically connected to at least one of the connection wiring structures located in the pixel region APS, power region PR, cover region MR, drive region DR, and protection region GR. Therefore, signals or voltages applied from the second chip CH2 can be transmitted to the photoelectric converter PD through the connection wiring structures located in the pixel region APS, power region PR, cover region MR, drive region DR, and protection region GR, and the second connection wiring structure CS2.

[0120] In an embodiment, the second connection wiring structure CS2 may include multiple connection wirings M1 to M4, but is not limited thereto, and may consist of only one connection wiring.

[0121] Furthermore, in the image sensor according to the embodiment, in the power supply region PR, the first connecting wires M1 to the fourth connecting wires M4 and the vias VA between them can constitute a first connecting wire structure CS1; in the cover region MR, the first connecting wires M1 to the fourth connecting wires M4 and the vias VA between them can constitute a third connecting wire structure CS3; in the drive region DR, the first connecting wires M1 to the fourth connecting wires M4 and the vias VA between them can constitute a fourth connecting wire structure CS4; and in the protection region GR, the first connecting wires M1 to the fourth connecting wires M4 and the vias VA between them can constitute a fifth connecting wire structure CS5. This will be described below.

[0122] According to an embodiment, the first chip CH1 of the image sensor may further include a first upper contact plug 31 and a second upper contact plug 33 located inside the first upper interlayer insulating layer IL1.

[0123] The first upper contact plug 31 can pass through the first upper interlayer insulating layer IL1 in the pixel region APS and connect the transmission gate TG and the second connection wiring structure CS2 located on the third surface 110a of the first substrate 110.

[0124] The second upper contact plug 33 can pass through the first upper interlayer insulating layer IL1 in the pixel region APS and connect the floating diffusion region FD and the connection wirings M1 to M4 located adjacent to the third surface 110a of the first substrate 110. In an embodiment, the second upper contact plug 33 can connect the floating diffusion region FD and the second connection wiring structure CS2.

[0125] The first upper contact plug 31 and the second upper contact plug 33 may contain conductive materials (such as tungsten, titanium nitride, tantalum nitride and tungsten nitride), but are not limited thereto.

[0126] The first connection pad 24 may be positioned inside the sixth upper interlayer insulating layer IL6. The first connection pad 24 may be exposed from the first surface of the first chip CH1 facing the second chip CH2 and contact the second connection pad 124 of the second chip CH2. The lower surface of the first connection pad 24 may be positioned coplanarly with the first surface of the first chip CH1. The first connection pad 24 may form a metal junction with the second connection pad 124. Thus, an electrical connection path may be provided between the transistor TR of the second chip CH2 and the connection wiring structure CS of the first chip CH1. This will be described below when describing the second chip CH2. In an embodiment, the first connection pad 24 may be electrically connected to the fourth connection wiring M4 via a through-hole via 15.

[0127] The image sensor 10 according to the embodiment may further include a back-side insulating layer 51, an anti-diffusion pattern 53, a first optical black pattern 55, a passivation layer 57, a grid pattern 60, color filters CF1 and CF2, a second optical black pattern CFB, and a microlens layer MLL positioned on a fourth surface 110b of a first substrate 110.

[0128] The back insulating layer 51 may include at least one of a bottom anti-reflective coating (BARC) layer, a fixed charge layer, an adhesive layer, an anti-reflective layer, and a protective layer.

[0129] The fixed charge layer can be composed of a metal oxide film or a metal fluoride film containing oxygen or fluorine in amounts smaller than their stoichiometry. Therefore, the fixed charge layer can have a negative fixed charge.

[0130] The fixed charge layer may contain a metal oxide or metal fluoride containing at least one metal selected from hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides.

[0131] Hole accumulation can occur around the fixed charge layer. Therefore, the occurrence of dark current and white spots can be effectively reduced.

[0132] The antireflective layer can limit and / or prevent light reflection, so that incident light on the fourth surface 110b of the first substrate 110 can smoothly reach the photoelectric converter PD. For example, the antireflective layer may contain a metal oxide (e.g., aluminum oxide or hafnium oxide) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0133] In the optical black region OB and the peripheral region ER, the anti-diffusion pattern 53 and the first optical black pattern 55 can be sequentially positioned on the back insulating layer 51.

[0134] The anti-diffusion pattern 53 may contain a metal nitride (such as TiN, TaN or WN), and the first optical black pattern 55 may contain a conductive material (such as tungsten (W)).

[0135] In the pixel region APS, color filters CF1 and CF2 and grid pattern 60 can be positioned on the back insulating layer 51.

[0136] A color filter CF located in the pixel region APS can include a primary color filter. The color filter CF can include a first color filter CF1, a second color filter CF2, and a third color filter, each having a different color from the others. For example, the first color filter CF1 can be a green color filter, the second color filter CF2 can be a red color filter, and the third color filter can be a blue color filter. As another example, the first color filter CF1 can be a cyan color filter, the second color filter CF2 can be a magenta color filter, and the third color filter can be a yellow color filter.

[0137] In an embodiment, the color filter CF positioned in the pixel region APS may have a Bayer pattern on a plane. In other words, the color filter CF may have a pattern in which the number of first color filters CF1 is approximately twice the number of second color filters CF2 or the number of third color filters.

[0138] The first color filter CF1, the second color filter CF2, and the third color filter can be positioned to correspond to multiple pixels PX, respectively. In other words, the first color filter CF1, the second color filter CF2, and the third color filter can be superimposed on the photoelectric converter PD, which is positioned to correspond to multiple pixels PX, in the vertical direction (Z direction). In other words, the first color filter CF1, the second color filter CF2, and the third color filter can be positioned on the photoelectric converter PD.

[0139] The grid pattern 60 can be positioned between adjacent color filters CF1 and CF2, and isolates adjacent color filters CF1 and CF2.

[0140] The grid pattern 60 can be positioned to overlap a portion of the pixel isolation pattern DTI1 in the third direction Z, which is the vertical direction. In other words, the grid pattern 60, as well as the color filters CF1 and CF2, can be offset from the center portion of the photoelectric converter PD. In other words, the center portion of the grid pattern 60, as well as the center portions of the color filters CF1 and CF2, can be offset from the center portion of each photoelectric converter PD in the first direction (X direction). However, the arrangement relationship between the grid pattern 60 and the pixel isolation pattern DTI1 is not limited to this and can be changed differently. For example, the grid pattern 60 can be positioned to completely overlap with the pixel isolation pattern DTI1 in the vertical direction. As another example, the grid pattern 60 can be offset to overlap with the pixel isolation pattern DTI1.

[0141] The degree to which the grid pattern 60 and color filters CF1 and CF2 are offset from the center portion of the photoelectric converter PD can increase with increasing distance from the center portion of the first substrate 110 (i.e., as the grid pattern 60 moves toward the peripheral portion of the first substrate 110). This is to correct for light that is tilted into areas other than the center portion of the first substrate 110, so that the tilted incident light can be centered on the center of each pixel PX.

[0142] The upper surface of the grid pattern 60 can be covered by adjacent color filters CF1 and CF2. For example, a portion of the upper surface of the grid pattern 60 can be covered by the first color filter CF1, while another portion can be covered by the second color filter CF2. However, the arrangement relationship between the grid pattern 60 and the color filters CF is not limited to this and can be varied.

[0143] The grid pattern 60 may include a first grid pattern 62 and a second grid pattern 64 stacked sequentially. The thickness of the first grid pattern 62 in the third direction Z may be different from the thickness of the second grid pattern 64 in the third direction Z.

[0144] In an embodiment, the first mesh pattern 62 and the second mesh pattern 64 may comprise different materials. The first mesh pattern 62 may comprise at least one of a metallic material and a metal nitride. For example, the first mesh pattern 62 may comprise at least one of titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), and copper (Cu).

[0145] The second mesh pattern 64 may contain a material having a refractive index lower than that of the color filter CF. For example, the second mesh pattern 64 may contain an organic material (such as a polymer layer containing silica nanoparticles). However, the materials contained in the first mesh pattern 62 and the second mesh pattern 64 are not limited to this and may vary.

[0146] exist Figure 3 The diagram shows that the grid pattern 60 consists of two layers; however, the number of layers included in the grid pattern 60 is not limited to this and can be varied. For example, the grid pattern 60 may consist of a single layer.

[0147] Within the optical black region OB and the peripheral region ER, a second optical black pattern CFB may be positioned on the back insulating layer 51. The second optical black pattern CFB may contain, for example, the same material as the blue filter.

[0148] The passivation layer 57 can be positioned between the color filters CF1 and CF2 and the back insulating layer 51, between the grid pattern 60 and the color filters CF1 and CF2, and between the second optical black pattern CFB and the first optical black pattern 55.

[0149] The passivation layer 57 may contain an insulating material (such as a high dielectric constant material). For example, the passivation layer 57 may contain aluminum oxide or hafnium oxide.

[0150] The pixel region APS and the optical black region OB can be covered by the microlens layer MLL. The microlens layer MLL may not be located in the peripheral region ER; however, this disclosure is not limited thereto, and the microlens layer MLL may extend into the peripheral region ER.

[0151] The microlens layer MLL may include multiple microlenses ML positioned on the color filter CF within the pixel region APS. The upper surface of the microlens ML may include a convex curved surface for refracting and converging incident light from the outside. However, the shape of the microlens ML is not limited to this and may vary. For example, the upper surface of the microlens ML may have a rectangular shape with rounded corners.

[0152] In the pixel region APS, the central portion of the microlens ML can be offset in a first direction (X direction) so as to be misaligned with the central portions of the first color filter CF1 and the second color filter CF2. In other words, the thickest portion of the microlens ML can be positioned to be misaligned with the central portions of the first color filter CF1 and the second color filter CF2.

[0153] Furthermore, compared to the grid pattern 60 and color filters CF1 and CF2, the microlens ML can be further offset relative to the center portion of the photoelectric converter PD in the first direction (X direction). Therefore, the photoelectric converter PD, color filters CF1 and CF2, and microlens ML can be positioned such that they are superimposed but their center portions are not aligned.

[0154] Here, "overlay" can mean not only an overlay relationship in the third direction Z (vertical), but also an overlay relationship in the propagation direction of the incident light to the photoconverter PD. In other words, the photoconverter PD, color filters CF1 and CF2, and microlens ML can be positioned to be overlaid along the path of the incident light from the outside to the photoconverter PD. For example, since the central portions of the photoconverter PD, the color filters CF1 and CF2, and the microlens ML are positioned misaligned with each other, the central portions of the photoconverter PD, the color filters CF1 and CF2, and the microlens ML can be positioned on the extension line of the path of the light entering the photoconverter PD. This is to correct the light that enters at an angle into the area other than the central portion of the first substrate 110, so that the angled incident light can be centered on the center of each pixel PX as described above.

[0155] In the following text, we will refer to... Figures 4 to 6 Describe the peripheral region of the image sensor according to an embodiment.

[0156] Figures 4 to 6 This is a cross-sectional view showing the pixel region and peripheral region of an image sensor according to an embodiment.

[0157] The peripheral region ER of the image sensor 10 according to the embodiment may include a power supply region PR, a cover region MR, a protection region GR, a drive region DR, and a sampler region CR.

[0158] The power supply area PR may include a ground portion DD located inside the first substrate 110, a dummy isolation pattern DTI2 surrounding the ground portion DD, and a first connection wiring structure CS1 electrically connected to the ground portion DD.

[0159] Refer to together Figures 4 to 6The dummy isolation pattern DTI2 can be positioned inside the power region PR of the first substrate 110. The dummy isolation pattern DTI2 can pass through the first substrate 110. The dummy isolation pattern DTI2 can be a front deep trench isolation (FDTI).

[0160] In an embodiment, the dummy isolation pattern DTI2 may completely penetrate the first substrate 110. For example, a side surface of the dummy isolation pattern DTI2 may contact each of the third surface 110a and the fourth surface 110b of the first substrate 110. Each upper surface of the dummy isolation pattern DTI2 and the fourth surface 110b of the first substrate 110 may be flat. However, this disclosure is not limited thereto, and each upper surface of the dummy isolation pattern DTI2 may include a surface curved relative to the fourth surface 110b of the first substrate 110.

[0161] In an embodiment, the dummy isolation pattern DTI2 may have a shape in which its width decreases as it extends from the third surface 110a of the first substrate 110 toward the fourth surface 110b. In other words, the dummy isolation pattern DTI2 may have sloping side surfaces. However, this disclosure is not limited thereto, and the dummy isolation pattern DTI2 may have a shape in which its width increases as it extends from the third surface 110a of the first substrate 110 toward the fourth surface 110b, or it may have a constant width.

[0162] The dummy isolation pattern DTI2 can be located within the outer region ER. For example, as... Figure 4 As shown, a dummy isolation pattern DTI2 may be positioned within a power region PR. The dummy isolation pattern DTI2 may surround a ground portion DD positioned within the power region PR of the first substrate 110, as described below. The dummy isolation pattern DTI2 may define the ground portion DD, as described below. In other words, the portion of the first substrate 110 surrounded by the dummy isolation pattern DTI2 may be defined as the ground portion DD. Therefore, the ground portion DD can be isolated from other portions of the first substrate 110 by the dummy isolation pattern DTI2. The dummy isolation pattern DTI2 may be a front deep trench isolation (FDTI), but is not limited to this. For example, the dummy isolation pattern DTI2 may be a back deep trench isolation (BDTI).

[0163] In this embodiment, multiple dummy isolation patterns DTI2 may be provided. For example, the dummy isolation patterns DTI2 may include an inner dummy isolation pattern DTI2_I surrounding the ground portion DD and an outer dummy isolation pattern DTI2_E surrounding the inner dummy isolation pattern DTI2_I. Therefore, the ground portion DD and the photoelectric converter PD can be effectively insulated from each other.

[0164] In an embodiment, the upper surface of the dummy isolation pattern DTI2 may be positioned at substantially the same height as the upper surface of the pixel isolation pattern DTI1. In other words, the upper surfaces of the dummy isolation pattern DTI2 and the pixel isolation pattern DTI1 may be positioned at substantially the same distance from the fourth surface 110b of the first substrate 110. Therefore, the length of the dummy isolation pattern DTI2 in the third direction (Z direction) may be the same as or substantially the same as the length of the pixel isolation pattern DTI1 in the third direction (Z direction); however, this disclosure is not limited thereto.

[0165] In an embodiment, the dummy isolation pattern DTI2 can be positioned separately from the pixel isolation pattern DTI1. Since the power region PR is spaced apart from the pixel region APS and the optical black region OB as described above, the dummy isolation pattern DTI2 surrounding the ground portion DD in the power region PR can be positioned spaced apart from the pixel isolation pattern DTI1 positioned between the photoelectric converter PD.

[0166] Despite Figure 4 The diagram shows a dummy isolation pattern DTI2 positioned in the power region PR, but this disclosure is not limited thereto, and the dummy isolation pattern DTI2 may be further positioned in the drive region DR. This will be referred to below. Figure 7 Describe it.

[0167] The dummy isolation pattern DTI2 may include a second insulating isolation pattern 42, a second conductive isolation pattern 44, and a second isolation cover pattern 46.

[0168] The second insulating isolation pattern 42 may extend to conform to the inner surface of the isolation trench. The second insulating isolation pattern 42 may contain the same material as the first insulating isolation pattern 41. The second insulating isolation pattern 42 may contain a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high-dielectric-constant material (e.g., hafnium oxide or aluminum oxide). As another example, the second insulating isolation pattern 42 may include multiple layers, and individual layers may contain different materials. In an embodiment, the second insulating isolation pattern 42 may have a lower refractive index than the first substrate 110. However, the material contained in the second insulating isolation pattern 42 is not limited to this and may vary.

[0169] The second conductive isolation pattern 44 may be positioned on the second insulating isolation pattern 42. The second conductive isolation pattern 44 may be surrounded by the second insulating isolation pattern 42. The second insulating isolation pattern 42 may be positioned between the second conductive isolation pattern 44 and the first substrate 110.

[0170] The second conductive isolation pattern 44 may contain the same material as the first conductive isolation pattern 43. For example, the second conductive isolation pattern may contain a crystalline semiconductor material (such as polycrystalline silicon). The second conductive isolation pattern 44 may also contain impurities, which may be impurities of a first conductivity type or impurities of a second conductivity type. Here, impurities of the first conductivity type may refer to p-type impurities, and impurities of the second conductivity type may refer to n-type impurities.

[0171] As another example, the second conductive isolation pattern 44 may comprise a crystalline semiconductor material (such as undoped polycrystalline silicon). Here, the term "undoped" may mean that no intentional doping process has been performed. However, the material comprised of the second conductive isolation pattern 44 is not limited to this and may vary.

[0172] The second isolation cover pattern 46 of the dummy isolation pattern DTI2 can be positioned on the second conductive isolation pattern 44. The second conductive isolation pattern 44 and the second isolation cover pattern 46 can be positioned to overlap in the vertical direction (Z direction), and the second isolation cover pattern 46 can be positioned adjacent to the third surface 110a of the first substrate 110.

[0173] exist Figure 4 The diagram shows that one surface of the second isolation cover pattern 46 and the third surface 110a of the first substrate 110 are flat; however, one surface of the second isolation cover pattern 46 and the third surface 110a of the first substrate 110 may have curvature.

[0174] The second isolation cover pattern 46 may contain the same material as the first isolation cover pattern 45. The second isolation cover pattern 46 may contain a non-conductive material. The second isolation cover pattern 46 may contain a silicon-based insulating material (e.g., silicon nitride, silicon oxide, or silicon oxynitride) or a high dielectric constant material (e.g., hafnium oxide or aluminum oxide). However, the material contained in the second isolation cover pattern 46 is not limited to these and may vary.

[0175] The grounding portion DD can be positioned within the first substrate 110 in the peripheral region ER. For example, the grounding portion DD can be positioned within the first substrate 110 in the power region PR. The grounding portion DD can be defined by a dummy isolation pattern DTI2. The grounding portion DD can be surrounded by the dummy isolation pattern DTI2. The grounding portion DD can be completely surrounded by the dummy isolation pattern DTI2. Therefore, the grounding portion DD can be spaced apart from the photoelectric converter PD. The grounding portion DD can be electrically insulated from the photoelectric converter PD through the dummy isolation pattern DTI2. The grounding portion DD can be superimposed on the dummy isolation pattern DTI2 in the first direction (X direction). In an embodiment, the grounding portion DD can be positioned in the same layer as the photoelectric converter PD.

[0176] In an embodiment, the ground portion DD may contain impurities of a first conductivity type. The ground portion DD may be doped with impurities of the first conductivity type. For example, the impurity of the first conductivity type may be a p-type impurity (such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga)); however, this disclosure is not limited thereto. In some embodiments, regions doped with different concentrations may also be included in the ground portion DD. This will be referred to below. Figure 10 Describe it.

[0177] The ground portion DD is electrically connected to the first connection wiring structure CS1. The ground portion DD is electrically connected to the first contact electrode CT1 of the first connection wiring structure CS1, which will be described below. One surface of the ground portion DD can contact the first contact electrode CT1, which will be described below. Therefore, the ground portion DD can be electrically connected to the second chip CH2 through the first connection wiring structure CS1.

[0178] In an embodiment, the first connection wiring M1 to the fourth connection wiring M4 of the wiring layer 120 and the via VA between them can constitute a first connection wiring structure CS1 in the power supply region PR. The first connection wiring structure CS1 can electrically connect the ground portion DD and the second chip CH2. The first connection wiring structure CS1 will be described below.

[0179] In the image sensor 10 according to an embodiment, the protection area GR may include a protection pattern 156 located inside the first substrate 110.

[0180] The protective pattern 156 may be positioned within the first substrate 110 in the protected region GR. The protective pattern 156 may be positioned adjacent to the third surface 110a of the first substrate 110. The protective pattern 156 may be a shallow trench isolation (STI) layer. The protective pattern 156 may serve to block light or electrons generated by specific circuitry in the peripheral region ER from penetrating into the pixel region APS and / or the optical black region OB.

[0181] The protective pattern 156 may have a shape in which its width decreases as it extends from the third surface 110a of the first substrate 110 toward the fourth surface 110b. The protective pattern 156 may be positioned separately from the dummy isolation pattern DTI2 and the pixel isolation pattern DTI1. In addition, the protective pattern 156 may be positioned separately from the ground portion DD and the photoelectric converter PD.

[0182] exist Figure 4 In the diagram, one surface of the protective pattern 156 and the third surface 110a of the first substrate 110 are shown to be flat; however, one surface of the protective pattern 156 and the third surface 110a of the first substrate 110 may have curvature.

[0183] Refer again Figure 3The second chip CH2 may include a second substrate 210, a plurality of transistors TR located inside the second substrate 210, a lower interlayer insulating layer 220 covering the second substrate 210, and a second connection pad 124 located inside the lower interlayer insulating layer 220.

[0184] In one embodiment, the second chip CH2 may include a second surface that faces the first surface of the first chip CH1. The second surface of the second chip CH2 may face the first surface of the first chip CH1. The second surface of the second chip CH2 may be the upper surface of the second chip CH2.

[0185] The lower interlayer insulating layer 220 may have a single or multiple membrane structure of at least one of silicon oxide film, silicon nitride film, silicon oxynitride film and porous insulating film.

[0186] In an embodiment, the second chip CH2 may have a chip-to-chip (C2C) structure bonded to the first chip CH1 by a wafer bonding method (e.g., hybrid bonding). For example, the second surface of the second chip CH2 may be a bonding surface with the first surface of the first chip CH1. Alternatively, the first surface of the first chip CH1 may be a bonding surface with the second surface of the second chip CH2. Specifically, the second connection pad 124 of the second chip CH2 may form a metal junction with the first connection pad 24 of the first chip CH1. The first surface of the first chip CH1 and the lower surface of the first connection pad 24 may be positioned on the same plane, and the second surface of the second chip CH2 and the upper surface of the second connection pad 124 may be positioned on the same plane. That is, the first connection pad 24 may be disposed on the first surface of the first chip CH1, and the second connection pad 124 may be disposed on the second surface of the second chip CH2. In an embodiment, the first surface of the first chip CH1 and the second surface of the second chip CH2 may be in contact with each other. Therefore, the second connection pad 124 may be bonded to the first connection pad 24, thereby providing an electrical connection path from the transistor TR of the second chip CH2 to the connection wiring structure CS of the first chip CH1.

[0187] In an embodiment, the second connection pad 124 may contain the same conductive material as the first connection pad 24, such as copper.

[0188] Although not in Figure 3 and Figure 4As shown, however, the bonding insulating layer may be further positioned at the interface between the first chip CH1 and the second chip CH2. In other words, the first chip CH1 may include an upper bonding insulating layer at its interface with the second chip CH2, and the second chip CH2 may include a lower bonding insulating layer at its interface with the first chip CH1, and the upper and lower bonding insulating layers may be in direct contact with each other. The upper and lower bonding insulating layers may be bonded to form a junction insulating layer. For example, the upper and lower bonding insulating layers may comprise at least one of SiCN, SiOCN, and SiC.

[0189] In the following text, reference will be made to Figure 2 and Figures 4 to 6 The wiring layer of an image sensor according to an embodiment is described.

[0190] Reference Figure 2 and Figures 4 to 6 According to an embodiment, the wiring layer 120 of the image sensor 10 may include first connection wiring M1 to fourth connection wiring M4 and vias VA between them. In an embodiment, the first connection wiring M1 to fourth connection wiring M4 and vias VA between them may constitute a connection wiring structure CS.

[0191] Specifically, the wiring layer may include a first connection wiring structure CS1 located in the power region PR, and may also include a third connection wiring structure CS3 located in the cover region MR, a fourth connection wiring structure CS4 located in the drive region DR, and a fifth connection wiring structure CS5 located in the protection region GR.

[0192] A first connection wiring structure CS1 may be positioned within a power supply region PR. The first connection wiring structure CS1 may be superimposed on a ground portion DD in the vertical direction (Z direction). The first connection wiring structure CS1 may be electrically connected to the ground portion DD. At least a portion of the first connection wiring structure CS1 may be in contact with the ground portion DD. In an embodiment, the first connection wiring structure CS1 may be superimposed on a first connection pad 24 and a second connection pad 124 in the vertical direction (Z direction). Here, the first connection wiring structure CS1 may refer to a connection wiring structure located within the power supply region PR.

[0193] The first connection wiring structure CS1 can be electrically connected to the first connection pad 24 located inside the sixth upper interlayer insulating layer IL6. Therefore, the first connection wiring structure CS1 can be electrically connected to the transistor TR of the second chip CH2 through the first connection pad 24 and the second connection pad 124.

[0194] In an embodiment, the first connection wiring structure CS1 may include first connection wiring M1 to fourth connection wiring M4, via VA connecting them, and first contact electrode CT1 positioned between the first connection wiring M1 to fourth connection wiring M4 and ground portion DD.

[0195] First connection wiring M1 to fourth connection wiring M4 may be positioned on first connection pad 24. Via VA may connect first connection wiring M1 to fourth connection wiring M4. First connection wiring M1 to fourth connection wiring M4 may contain, for example, a conductive material (such as, copper (Cu)).

[0196] exist Figure 4 and Figure 5 The diagram shows four connection wires M1 to M4; however, this disclosure is not limited thereto and may include three or fewer connection wires, or five or more connection wires. Furthermore, in Figure 4 and Figure 5 In the diagram, a via is shown at each of the following locations: between the first connecting wire M1 and the second connecting wire M2, between the second connecting wire M2 and the third connecting wire M3, and between the third connecting wire M3 and the fourth connecting wire M4; however, the number of vias VA is not limited thereto. This will be referred to below. Figure 7 Describe it.

[0197] The first contact electrode CT1 can be positioned between the first connecting wire M1 to the fourth connecting wire M4 and the ground portion DD. For example, the first contact electrode CT1 can be positioned between the first connecting wire M1 and the ground portion DD, with the first connecting wire M1 positioned at the top. Here, the first connecting wire M1 can be the connecting wire closest to the third surface 110a of the first substrate 110.

[0198] The first contact electrode CT1 can penetrate the first upper interlayer insulating layer IL1. The first contact electrode CT1 can be positioned in the same layer as the first upper contact plug 31 and the second upper contact plug 33. In an embodiment, the upper surface of the first contact electrode CT1 can be positioned at substantially the same height as the upper surface of the second upper contact plug 33; however, this disclosure is not limited thereto. In other words, the upper surface of the first contact electrode CT1 and the upper surface of the second upper contact plug 33 can be positioned at substantially the same distance from the second surface of the second chip CH2.

[0199] The first contact electrode CT1 can be electrically connected to the ground portion DD. The first contact electrode CT1 can contact the ground portion DD. The first contact electrode CT1 can be electrically connected to the first connection wiring M1 to the fourth connection wiring M4 and the ground portion DD. Therefore, the transistor TR of the second chip CH2 can have an electrical connection path to the ground portion DD through the first connection wiring M1 to the fourth connection wiring M4 and the first contact electrode CT1.

[0200] The first contact electrode CT1 may contain a conductive material. For example, the first contact electrode CT1 may contain a conductive material (such as copper (Cu)). As another example, the first contact electrode CT1 may contain a conductive material (such as tungsten, titanium nitride, tantalum nitride, and tungsten nitride), but is not limited thereto.

[0201] exist Figure 4 and Figure 5 The diagram shows a first contact electrode CT1 positioned between a first connection wiring M1 and a ground portion DD; however, this disclosure is not limited thereto. For example, two or more first contact electrodes CT1 may be included between the first connection wiring M1 and the ground portion DD.

[0202] In an embodiment, the first connection wiring structure CS1 may be electrically connected to the second connection wiring structure CS2. At least one of the first connection wiring M1 to the fourth connection wiring M4 of the first connection wiring structure CS1 may extend to the pixel region APS and be electrically connected to the second connection wiring structure CS2. For example, as Figure 4 As shown, the third connection wiring M3 of the first connection wiring structure CS1 can extend to the cover region MR and the protection region GR and is electrically connected to the third connection wiring structure CS3 of the cover region MR and the fifth connection wiring structure CS5 of the protection region GR, and the second connection wiring M2 of the fifth connection wiring structure CS5 can extend to the pixel region APS and is electrically connected to the second connection wiring structure CS2. However, this disclosure is not limited thereto, and any connection wiring of the first connection wiring structure CS1 can extend to the pixel region APS and be directly connected to the second connection wiring structure CS2.

[0203] In this case, such as Figure 4 As shown, the second connection wiring structure CS2 can be electrically connected to each of the plurality of pixels PX. In this case, the electrical connection path from the second chip CH2 to the plurality of pixels PX can be formed by the first connection wiring structure CS1, the fifth connection wiring structure CS5, and the second connection wiring structure CS2. Meanwhile, as... Figure 5 As shown, the second connection wiring structure CS2 can be floating.

[0204] The third connection wiring structure CS3 can be positioned in the cover region MR. The third connection wiring structure CS3 can be superimposed on the portion of the first substrate 110 positioned in the cover region MR in the vertical direction (Z direction).

[0205] In an embodiment, the third connection wiring structure CS3 may include first connection wiring M1 to fourth connection wiring M4, vias VA connecting them, and capacitor elements positioned between the first connection wiring M1 to fourth connection wiring M4 and the first substrate 110.

[0206] For example, the third connection wiring structure CS3 may include a first electrode PC and a dielectric layer 155 sequentially positioned on the first connection wiring M1. The first electrode PC may contain a conductive material. The dielectric layer 155 may be positioned between the first substrate 110 and the first electrode PC. In an embodiment, a portion of the first substrate 110 positioned in the cover region MR, the dielectric layer 155, and the first electrode PC may constitute a capacitor element. The capacitor element may be used to decouple noise present in drive signals to be provided to and / or pixel signals received from the multiple pixels PX. In an embodiment, the first electrode PC may be electrically connected to the first connection wiring M1 via a through-via VA1.

[0207] However, this disclosure is not limited thereto, and the capacitor element of the third connection wiring structure CS3 can be configured such that the gate insulating layer in the capacitor element serves as a dielectric layer in a transistor structure including a source, a drain and a gate.

[0208] In an embodiment, the third connection wiring structure CS3 may be electrically connected to the first connection wiring structure CS1. At least one of the first connection wiring M1 to the fourth connection wiring M4 of the third connection wiring structure CS3 may extend to the power supply region PR and be electrically connected to the first connection wiring structure CS1. For example, as Figure 4 As shown, the third connection wiring M3 of the third connection wiring structure CS3 can extend to the power supply area PR and is electrically connected to the first connection wiring structure CS1. Additionally, the third connection wiring M3 of the third connection wiring structure CS3 can extend to the protection area GR and is electrically connected to the fifth connection wiring structure CS5.

[0209] The fifth connection wiring structure CS5 can be positioned within the protection zone GR. The fifth connection wiring structure CS5 can be superimposed on the portion of the first substrate 110 positioned within the protection zone GR in the vertical direction (Z direction).

[0210] In an embodiment, the fifth connection wiring structure CS5 may include first connection wiring M1 to fourth connection wiring M4, via VA connecting them, and through via VA2 positioned between the first connection wiring M1 to fourth connection wiring M4 and the first substrate 110.

[0211] The through-via VA2 can be positioned between the first connecting wire M1 to the fourth connecting wire M4 and the first substrate 110 located in the protection region GR. For example, the through-via VA2 can be positioned between the first connecting wire M1 and the first substrate 110, with the first connecting wire M1 positioned at the top. Here, the first connecting wire M1 can be the connecting wire closest to the third surface 110a of the first substrate 110.

[0212] The through-hole VA2 can pass through the first upper interlayer insulating layer IL1. The through-hole VA2 can be positioned in the same layer as the first contact electrode CT1, the first upper contact plug 31, and the second upper contact plug 33. In an embodiment, the upper surface of the through-hole VA2 can be positioned at substantially the same level as the upper surface CT1_a of the first contact electrode CT1 and the upper surface of the second upper contact plug 33; however, this disclosure is not limited thereto. In other words, the upper surface of the through-hole VA2, the upper surface CT1_a of the first contact electrode CT1, and the upper surface of the second upper contact plug 33 can be positioned at substantially the same distance from the second surface of the second chip CH2.

[0213] Through-via VA2 can be electrically connected to the first substrate 110. Through-via VA2 can contact the first substrate 110. For example, through-via VA2 can contact the portion of the first substrate 110 positioned between the protective patterns 156. Through-via VA2 can electrically connect the first connection wiring M1 to the fourth connection wiring M4 and the first substrate 110. Therefore, the transistor TR of the second chip CH2 can have an electrical connection path with the protective region GR through the first connection wiring M1 to the fourth connection wiring M4 and the through-via VA2. Therefore, the protective region GR can block light or electrons generated by specific circuits in the peripheral region ER from penetrating into the pixel region APS and / or the optical black region OB.

[0214] The through-hole VA2 may contain a conductive material. The through-hole VA2 may contain the same material as, but is not limited to, the first contact electrode CT1. For example, the through-hole VA2 may contain a conductive material (such as copper (Cu)). As another example, the through-hole VA2 may contain a conductive material (such as tungsten, titanium nitride, tantalum nitride, and tungsten nitride), but is not limited to.

[0215] In one embodiment, the fifth connection wiring structure CS5 is electrically connected to the second connection wiring structure CS2. At least one of the first to fourth connection wirings M1 of the fifth connection wiring structure CS5 extends to the power supply region PR and is electrically connected to the first connection wiring structure CS1. Additionally, the fifth connection wiring structure CS5 is electrically connected to both the second and third connection wiring structures CS2 and CS3. At least one of the first to fourth connection wirings M4 of the fifth connection wiring structure CS5 extends to both the power supply region PR and the cover region MR, and is electrically connected to both the first and third connection wiring structures CS1 and CS3.

[0216] Refer to together Figure 6 According to an embodiment, the ground portion DD of the image sensor 10 may be further positioned within the driving region DR. In an embodiment, the wiring layer 120 may include a fourth connection wiring structure CS4 positioned within the driving region DR.

[0217] The fourth connection wiring structure CS4 can be located in the drive area DR. The fourth connection wiring structure CS4 can be stacked with the ground part DD in the vertical direction (Z direction). The fourth connection wiring structure CS4 can be electrically connected to the ground part DD. At least a portion of the fourth connection wiring structure CS4 can be in contact with the ground part DD. Here, the fourth connection wiring structure CS4 can be specified as a connection wiring structure located in the drive area DR.

[0218] In an embodiment, the fourth connection wiring structure CS4 may include first connection wiring M1 to fourth connection wiring M4, via VA connecting them, and second contact electrode CT2 positioned between the first connection wiring M1 to fourth connection wiring M4 and ground portion DD.

[0219] The second contact electrode CT2 can be positioned between the first connecting wire M1 to the fourth connecting wire M4 and the ground portion DD. For example, the second contact electrode CT2 can be positioned between the first connecting wire M1 and the ground portion DD, with the first connecting wire M1 positioned at the top. Here, the first connecting wire M1 can be the connecting wire closest to the third surface 110a of the first substrate 110.

[0220] The second contact electrode CT2 can pass through the first upper interlayer insulation layer IL1. The second contact electrode CT2 can be positioned in the same layer as the first contact electrode CT1. The second contact electrode CT2 can be electrically connected to the ground portion DD. The second contact electrode CT2 can contact the ground portion DD. In other words, the upper surface CT2_a of the second contact electrode CT2 can be electrically connected to the first connection wiring M1 to the fourth connection wiring M4 and the ground portion DD. The second contact electrode CT2 can contain a conductive material. The second contact electrode CT2 can contain the same material as the first contact electrode CT1, but is not limited thereto. The remaining description of the second contact electrode CT2 is substantially the same as the description of the first contact electrode CT1, and therefore will not be repeated.

[0221] In an embodiment, the fourth connection wiring structure CS4 may be electrically connected to the second connection wiring structure CS2. At least one of the first connection wiring M1 to the fourth connection wiring M4 of the fourth connection wiring structure CS4 may extend to the pixel region APS and be electrically connected to the second connection wiring structure CS2. For example, as Figure 6As shown, the third connection wiring M3 of the fourth connection wiring structure CS4 can extend to the pixel region APS and is electrically connected to the second connection wiring structure CS2. In this case, the second connection wiring structure CS2 can be electrically connected to the transmission gate TG via the first upper contact plug 31. Therefore, an electrical connection path can be formed from the transistor TR of the second chip CH2 via the second connection pad 124, the first connection pad 24, the fourth connection wiring structure CS4, and the second connection wiring structure CS2 to the transmission gate TG. The drive signal applied from the second chip CH2 can be applied to the transmission gate TG via the fourth connection wiring structure CS4 and the second connection wiring structure CS2.

[0222] In an embodiment, the shape, arrangement, and connection relationship between the fourth connection wiring structure CS4 of the drive region DR and the ground part DD can be substantially the same as the shape, arrangement, and connection relationship between the first connection wiring structure CS1 of the power region PR and the ground part DD.

[0223] Already referred to Figures 4 to 6 Each of the connection wiring structures CS is described as including four connection wires M1 to M4 and one via VA, wherein the via VA is located in each of the locations between the connection wires M1 to M4; however, the number of connection wires M1 to M4 and the number of vias VA are not limited thereto.

[0224] In the following text, we will refer to... Figure 7 Describes the power supply region of the image sensor according to an embodiment.

[0225] Figure 7 This is a plan view illustrating the power supply region of an image sensor according to an embodiment, as an example. Figure 7 For ease of explanation, the dummy isolation pattern DTI2 of the power supply area PR, the ground portion DD, the first contact electrode CT1, the via VA, and the first connection pad 24 are shown, and other components are omitted. Reference will be made below. Figure 7 Describe the planar arrangement of the grounding part DD, the first contact electrode CT1, and the via VA.

[0226] Refer to together Figure 7 The image sensor according to an embodiment may include a plurality of vias VA. For example, a first connection wiring structure CS1 located in a power supply region PR may include a plurality of vias VA arranged in a first direction (X direction) and a second direction (Y direction). The plurality of vias VA may be positioned separately from each other in a plane. The plurality of vias VA may be superimposed on a ground portion DD in a vertical direction (Z direction).

[0227] In embodiments, a plurality of first contact electrodes CT1 may be provided. For example, a first connection wiring structure CS1 located in a power supply region PR may include a plurality of first contact electrodes CT1 arranged in a first direction (X direction) and a second direction (Y direction). The plurality of first contact electrodes CT1 may be positioned separately from each other in a plane. The plurality of first contact electrodes CT1 may be stacked with a ground portion DD in a vertical direction (Z direction). In embodiments, at least a portion of the plurality of first contact electrodes CT1 may be stacked with a via VA in a vertical direction (Z direction); however, this disclosure is not limited thereto. In embodiments, at least a portion of the plurality of first contact electrodes CT1 may be stacked with a first connection pad 24 in a vertical direction (Z direction). For example, as Figure 7 As shown, the first connecting pad 24 may be stacked with two first contact electrodes CT1 in the vertical direction (Z direction); however, the number of first contact electrodes CT1 stacked with the first connecting pad 24 in the vertical direction (Z direction) is not limited to this.

[0228] In the following text, reference will be made to Figure 8 An image sensor according to an embodiment is described.

[0229] Figure 8 This is a cross-sectional view showing the pixel region and peripheral region of an image sensor according to an embodiment.

[0230] Reference Figure 8 As described above, desired and / or optionally predetermined signals and / or voltages can be applied from the transistor TR of the second chip CH2 to the first chip CH1. The transistor TR of the second chip CH2 is electrically connected to the second connection pad 124 and the first connection pad 24, and is electrically connected to the elements of the first chip CH1 through the wiring layer 120.

[0231] For example, the first connection wiring structure CS1, located in the power supply region PR, is directly connected to the first connection pad 24. Therefore, the first connection wiring structure CS1 can be electrically connected to the transistor TR of the second chip CH2.

[0232] In an embodiment, since the first connection wiring structure CS1 is electrically connected to the third connection wiring structure CS3 located in the cover region MR, a first path P1 can be provided through the first connection wiring structure CS1 and the third connection wiring structure CS3. The first path P1 is an electrical connection path between the second chip CH2 and the capacitor element of the cover region MR.

[0233] In addition, since the first connection wiring structure CS1 is electrically connected to the fifth connection wiring structure CS5 located in the protection area GR, a second path P2 can be provided through the first connection wiring structure CS1 and the fifth connection wiring structure CS5. The second path P2 is an electrical connection path between the second chip CH2 and the first substrate 110 of the protection area GR.

[0234] In addition, since the first connection wiring structure CS1 is electrically connected to the second connection wiring structure CS2 located in the pixel region APS, a third path P3 can be provided through the first connection wiring structure CS1 and the second connection wiring structure CS2. The third path P3 is an electrical connection path between the second chip CH2 and multiple pixels PX of the pixel region APS.

[0235] Furthermore, since the first connection wiring structure CS1 is electrically connected to the ground part DD through the first contact electrode CT1, a fourth path P4 can be provided through the first contact electrode CT1. The fourth path P4 is the electrical connection path between the second chip CH2 and the ground part DD.

[0236] During the formation of the image sensor 10 according to the embodiment, a plasma process can be repeatedly performed. When the plasma process is performed, charge can be generated, and the generated charge can be accumulated in the wiring layer 120, etc. The accumulated charge can be released to the first substrate 110 through the connection wiring structure CS of the wiring layer 120. For example, the charge accumulated by the plasma process can be released to the first substrate 110 through the first path P1 to the third path P3.

[0237] Meanwhile, during the formation of the wiring layer 120 of the image sensor 10 according to the embodiment, there may be a step before electrically connecting the second connection wiring structure CS2 to the fifth connection wiring structure CS5 to the first substrate 110. In this case, the first path P1 to the third path P3 may not be fully formed, and the charge accumulated in the wiring layer 120 by the plasma process may not be released through the first path P1 to the third path P3. Since the first contact electrode CT1 is electrically connected to the ground portion DD of the power supply region PR, even if the first path P1 to the third path P3 are not fully formed, the first connection wiring structure CS1 of the image sensor 10 according to the embodiment can be discharged through the fourth path P4. Therefore, the reliability of the image sensor 10 according to the embodiment can be improved.

[0238] In the following text, reference will be made to Figures 9 to 19 Image sensors according to various embodiments are described. In the following embodiments, components that are the same as those in the above embodiments will be indicated by the same reference numerals, and their redundant descriptions will be omitted or will be brief, with the main focus being on their differences from the above embodiments.

[0239] Figure 9 This is a cross-sectional view showing the power supply area of ​​an image sensor according to some embodiments. Figure 10 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example. Figure 11 and Figure 12 It is shown Figure 10 A cross-sectional view of the power supply area in an embodiment. Figure 13 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example. Figure 14 It is shown Figure 13 A cross-sectional view of the power supply area in an embodiment. Figure 15 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example. Figure 16 This is a plan view of the power supply area of ​​an image sensor according to some embodiments, shown as an example. Figures 17 to 19 It is shown Figure 15 A cross-sectional view of the power supply area in an embodiment.

[0240] exist Figures 9 to 19 In the embodiment, the power supply region PR is shown, and the pixel region APS, optical black region OB, guard region GR, cover region MR, and sampler region CR are not shown. It is clear that... Figures 9 to 19 The description of the power supply region PR in the embodiment can be applied in the same way to the drive region DR.

[0241] Reference Figure 9 According to some embodiments, the first connection wiring structure CS1 of the image sensor 10 may include a plurality of first contact electrodes CT1. The plurality of first contact electrodes CT1 may be positioned on the first connection wiring M1. The plurality of first contact electrodes CT1 may be positioned separately from each other in a first direction (X direction) and a second direction (Y direction). The plurality of first contact electrodes CT1 may be arranged in the first direction (X direction) and the second direction (Y direction). Even in this case, each of the plurality of first contact electrodes CT1 may contact a surface of the ground portion DD. The plurality of first contact electrodes CT1 may be stacked with the ground portion DD in the vertical direction (Z direction).

[0242] In addition, multiple vias VA can be provided. These multiple vias VA can be positioned separately from each other in the first direction (X-direction) and the second direction (Y-direction). The multiple vias VA can be arranged in the first direction (X-direction) and the second direction (Y-direction).

[0243] Reference Figures 10 to 12 According to some embodiments, the image sensor 10 may include an impurity region located inside a ground portion DD in a power supply region PR.

[0244] For example, such as Figure 10 and Figure 11 As shown, the image sensor 10 may further include a first impurity region (or "first ground impurity region") 161, which is located inside a ground portion DD in the power supply region PR and electrically connected to the first contact electrode CT1. The first impurity region 161 may be buried in the ground portion DD. The lower surface of the first impurity region 161 may be positioned on the same plane as the lower surface of the ground portion DD. The first impurity region 161 may contact the first contact electrode CT1. In some embodiments, the first impurity region 161 may be stacked in the vertical direction (Z direction) with at least a portion of the via VA and the first connection pad 24; however, this disclosure is not limited thereto. In some embodiments, the first impurity region 161 may contain impurities of a first conductivity type. The first impurity region 161 may be doped to the same conductivity type as the first substrate 110. The first impurity region 161 may be doped with impurities of the first conductivity type. For example, the first conductivity type impurity may be a p-type impurity (such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga)). Therefore, the first connection wiring structure CS1 can be stably connected to the grounding part DD through the first impurity region 161.

[0245] As another example, such as Figure 12 As shown, the image sensor 10 may further include a second impurity region 162, which is located inside the ground portion DD in the power supply region PR and electrically connected to the first contact electrode CT1. In some embodiments, the second impurity region 162 may contain impurities of a second conductivity type. The second impurity region 162 may be doped with a conductivity type different from that of the first substrate 110. The second impurity region 162 may be doped with impurities of a second conductivity type. For example, impurities of the second conductivity type may include n-type impurities (such as phosphorus, arsenic, bismuth, and / or antimony). Therefore, the first connection wiring structure CS1 can be stably connected to the ground portion DD through the second impurity region 162.

[0246] Reference Figures 13 to 15 According to some embodiments, the image sensor 10 may include a first impurity region 161 and a second impurity region 162, which are located inside the ground portion DD in the power supply region PR.

[0247] The first impurity region 161 and the second impurity region 162 can be positioned separately from each other. For example, as Figure 13 As shown, the first impurity region 161 and the second impurity region 162 may extend in the second direction (Y direction) and be positioned separately from each other in the first direction (X direction). In this case, the device isolation region 163 may be positioned between the first impurity region 161 and the second impurity region 162. As another example, as Figure 15As shown, the first impurity region 161 may surround the second impurity region 162. In this case, the first impurity region 161 and the second impurity region 162 may be spaced apart from each other by a device isolation region.

[0248] In some embodiments, the first impurity region 161 may be stacked in the vertical direction (Z direction) with at least a portion of the via VA and the first connecting pad 24; however, this disclosure is not limited thereto. Additionally, the second impurity region 162 may be stacked in the vertical direction (Z direction) with at least a portion of the first connecting pad 24 and the via VA; however, this disclosure is not limited thereto.

[0249] In some embodiments, the first impurity region 161 and the second impurity region 162 may be doped with impurities of different conductivity types. For example, the first impurity region 161 may contain impurities of a first conductivity type, and the second impurity region 162 may contain impurities of a second conductivity type. Here, the first conductivity type may refer to p-type, and the second conductivity type may refer to n-type.

[0250] In some embodiments, each of the first impurity region 161 and the second impurity region 162 may be electrically connected to the first connection wiring structure CS1. For example, the first contact electrode CT1 may include a first sub-contact electrode CT1a and a second sub-contact electrode CT1b, and the first impurity region 161 may be electrically connected to the first sub-contact electrode CT1a, and the second impurity region 162 may be electrically connected to the second sub-contact electrode CT1b. The first impurity region 161 may contact the first sub-contact electrode CT1a, and the second impurity region 162 may contact the second sub-contact electrode CT1b. Therefore, the first connection wiring structure CS1 can be stably connected to the ground portion DD through the first impurity region 161 and the second impurity region 162.

[0251] Reference Figure 16 and Figure 17 According to some embodiments, the image sensor 10 may include a first impurity region 161 and a second impurity region 162, which are located inside the ground portion DD in the power supply region PR.

[0252] The second impurity region 162 may surround the first impurity region 161. In some embodiments, with Figure 15 In some embodiments, the first impurity region 161 and the second impurity region 162 may be in contact with each other.

[0253] In some embodiments, a first impurity region 161 may be located inside a ground portion DD, and a second impurity region 162 may be located between the first impurity region 161 and the ground portion DD. In this case, the side and top surfaces of the first impurity region 161 may be covered by the second impurity region 162. The lower surface of the first impurity region 161 may be located on the same plane as the lower surface of the second impurity region 162 and the lower surface of the ground portion DD; however, this disclosure is not limited thereto. In some embodiments, a first contact electrode CT1 may be electrically connected to the first impurity region 161. The first contact electrode CT1 may contact the first impurity region 161.

[0254] In some embodiments, the first impurity region 161 may contain impurities of a first conductivity type, and the second impurity region 162 may contain impurities of a second conductivity type. Meanwhile, as described above, the ground portion DD may contain impurities of the first conductivity type. Here, the first conductivity type may refer to p-type, and the second conductivity type may refer to n-type. Therefore, the first impurity region 161, the second impurity region 162, and the ground portion DD can be used as a PNP bipolar junction transistor (BTE) with a PNP structure. In this case, the first impurity region 161 may constitute the emitter of the PNP BTE, the second impurity region 162 may constitute the base of the PNP BTE, and the ground portion DD may constitute the collector of the PNP BTE. In some embodiments, the second impurity region 162 may be floating, such that the first connection wiring structure CS1 is stably connected to the ground portion DD.

[0255] Reference Figure 18 According to some embodiments, the image sensor 10 may also include a first electrode pattern 171 and a dielectric pattern 172 positioned between the first contact electrode CT1 and the ground portion DD.

[0256] The capacitor structure CPE may include a first electrode pattern 171 and a dielectric pattern 172 sequentially positioned on the first contact electrode CT1.

[0257] A first electrode pattern (or "contact gate electrode") 171 may be positioned between the first contact electrode CT1 and the ground portion DD. The first electrode pattern 171 may be superimposed on the ground portion DD and the first contact electrode CT1 in the vertical direction (Z direction). The first electrode pattern 171 may be electrically connected to the first contact electrode CT1. The first electrode pattern 171 may be in contact with the first contact electrode CT1. The first electrode pattern 171 may contain a conductive material. At least a portion of the first electrode pattern 171 may be superimposed on the element isolation pattern STI in the vertical direction (Z direction); however, this disclosure is not limited thereto.

[0258] A dielectric pattern 172 (or "gate insulating layer") may be positioned between a ground portion DD and a first electrode pattern 171. The dielectric pattern 172 may contact both the ground portion DD and the first electrode pattern 171. At least a portion of the dielectric pattern 172 may be superimposed on a component isolation pattern STI in the vertical direction (Z direction); however, this disclosure is not limited thereto. In some embodiments, the first electrode pattern 171, the dielectric pattern 172, and the ground portion DD may constitute a capacitor structure CPE. The capacitor structure CPE may be used to store signals and / or voltages received from the first connection wiring structure CS1.

[0259] Refer to together Figure 19 According to some embodiments, the image sensor 10 may also include a capacitor structure CPE positioned between the first contact electrode CT1 and the ground portion DD, and in the power supply region PR, the dummy isolation pattern DTI2 may be omitted.

[0260] One or more of the elements disclosed above may include or be implemented in processing circuitry, which is hardware such as including logic circuitry; a hardware / software combination (such as a processor executing software); or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0261] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it should be understood that embodiments of the inventive concept are not limited to the disclosed embodiments. Rather, embodiments of the inventive concept are intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0262] <Explanation of Symbols> CH1: First Chip CH2: Second chip 110: First basement 120: Wiring layer CS1: First connection wiring structure CS2: Second connection wiring structure PD: Photoelectric converter FD: Floating diffusion region TG: Transfer Gate MLL: Microlens layer APS: Pixel Area OB: Optical Dark Area ER: Peripheral Area DTI1: Pixel Isolation Pattern DTI2: Dummy Isolation Pattern

Claims

1. An image sensor, comprising: The first chip includes a first surface; as well as A second chip is disposed on the first chip and includes a second surface, the second surface of the second chip facing the first surface of the first chip, wherein... The first chip also includes a first connection pad on a first surface of the first chip. The second chip also includes transistors and second connection pads electrically connected to the transistors. The second connection pad is on the second surface of the second chip. The first connecting pad and the second connecting pad are electrically connected to each other. The first chip also includes: a substrate; multiple photoelectric converters in the substrate and corresponding to multiple pixels in the pixel region of the substrate; a ground portion in the peripheral region of the substrate; a dummy isolation pattern surrounding the ground portion and passing through the substrate; and a wiring layer. The substrate includes a third surface and a fourth surface that are opposite each other. The wiring layer includes a first connection wiring structure. The first connection wiring structure is located on the third surface of the substrate in the peripheral region and is electrically connected to the second connection pad. The first connection wiring structure includes a first contact electrode electrically connected to the ground in the peripheral area.

2. The image sensor according to claim 1, wherein, The first connection wiring structure also includes multiple connection wirings and multiple vias connecting the multiple connection wirings, and The first contact electrode is located between the multiple connection wires and the grounding part.

3. The image sensor according to claim 1, wherein, The wiring layer also includes a second connection wiring structure. The second connection wiring structure is electrically connected to the plurality of photoelectric converters in the pixel region, and The second connection wiring structure is electrically connected to the first connection wiring structure.

4. The image sensor according to claim 1, wherein, The first contact electrode makes contact with the grounding part.

5. The image sensor according to claim 1, wherein, The peripheral region includes a power supply region that is located separately from the pixel region. The power supply area is configured to receive power supply voltage from the second chip, and The first connection wiring structure is in the power supply area.

6. The image sensor according to claim 5, wherein, The grounding part is in the power supply area, and The first connection wiring structure overlaps with the grounding part in the vertical direction.

7. The image sensor according to claim 5, wherein, The outer area also includes the covered area. The covered area is outside the pixel area. The wiring layer also includes a third connection wiring structure. The third connection wiring structure is electrically connected to the substrate and the first connection wiring structure in the cover area, and The third connection wiring structure includes multiple connection wirings, multiple vias connecting the multiple connection wirings, a first electrode between the multiple connection wirings and the substrate, and a dielectric layer between the first electrode and the substrate. The first electrode of the third connection wiring structure is in contact with the third surface of the substrate.

8. The image sensor according to claim 5, wherein, The peripheral region also includes a driving region configured to receive driving signals for driving the plurality of photoelectric converters. The wiring layer also includes a second connection wiring structure in the pixel region and a fourth connection wiring structure in the driving region. The second connection wiring structure is electrically connected to the plurality of photoelectric converters. The fourth connection wiring structure is configured to transmit drive signals from the second chip to the second connection wiring structure. The fourth connection wiring structure includes a second contact electrode, and The second contact electrode is electrically connected to the substrate in the driving region.

9. The image sensor according to claim 1, wherein, The grounding portion of the substrate includes a first grounding impurity region, and The first ground impurity region is connected to the first contact electrode.

10. The image sensor according to claim 9, wherein, The substrate contains impurities of the first conductivity type. The plurality of photoelectric converters contain impurities of a second conductivity type. The second conductivity type is different from the first conductivity type, and The impurities in the first grounding impurity region are of the first conductivity type.

11. The image sensor according to claim 10, wherein, The grounding portion of the substrate includes a second grounding impurity region. The second ground impurity region surrounds the first ground impurity region, and The impurities in the second grounding impurity region are of the second conductivity type.

12. The image sensor according to claim 1, further comprising: Device isolation pattern, in the substrate, wherein, The grounding portion of the substrate also includes a first grounding impurity region and a second grounding impurity region on one side of the first grounding impurity region. The device isolation pattern is located between the first ground impurity region and the second ground impurity region, and Each of the first ground impurity region and the second ground impurity region is connected to the first connection wiring structure.

13. The image sensor according to any one of claims 1 to 12, Also includes: The contact gate electrode is positioned between the first contact electrode and the ground portion, and A gate insulating layer is located between the ground portion and the contact gate electrode.

14. The image sensor according to any one of claims 1 to 12, wherein, The first surface of the first chip is in contact with the second surface of the second chip, and The first connecting pad is in contact with the second connecting pad.

15. The image sensor according to any one of claims 1 to 12, wherein, The virtual isolation pattern completely surrounds the grounding part.

16. An image sensor, comprising: The substrate includes a pixel region having multiple pixels, a power region outside the pixel region and configured to receive a power supply voltage, a plurality of photoelectric converters in the substrate and corresponding to the plurality of pixels, and a ground portion in the power region of the substrate. A virtual isolation pattern is created, surrounding the grounding area and extending through the substrate; as well as The wiring layer, on the substrate, wherein, The grounding part is electrically insulated from the plurality of photoelectric converters by a dummy isolation pattern. The wiring layer includes a first connection wiring structure and a second connection wiring structure. The first connection wiring structure overlaps with the grounding part in the vertical direction. The first connection wiring structure is configured to receive power supply voltage. The second connection wiring structure is stacked vertically with the plurality of photoelectric converters. The second connection wiring structure is an electrical connection substrate and the first connection wiring structure. The first connection wiring structure includes a first contact electrode, and The first contact electrode is electrically connected to the grounding part.

17. The image sensor according to claim 16, wherein, The first connection wiring structure also includes multiple connection wirings and multiple vias connecting the multiple connection wirings, and The first contact electrode is located between the multiple connection wires and the grounding part.

18. The image sensor according to claim 16, wherein, The grounding portion of the substrate includes a first grounding impurity region. The first ground impurity region is connected to the first contact electrode, and The conductivity type of the first grounding impurity region is different from that of the substrate.

19. The image sensor according to any one of claims 16 to 18, wherein, The first contact electrode makes contact with the grounding part.

20. An image sensor, comprising: The first chip includes a first surface; as well as A second chip is disposed on the first chip and includes a second surface, the second surface of the second chip facing the first surface of the first chip, wherein... The first chip also includes a first connection pad on a first surface of the first chip. The second chip also includes transistors and second connection pads electrically connected to the transistors. The second connection pad is on the second surface of the second chip. The first connecting pad and the second connecting pad are electrically connected to each other. The first chip further includes: a substrate; a plurality of photoelectric converters in the substrate and corresponding to a plurality of pixels in a pixel region of the substrate; a pixel isolation pattern between the plurality of photoelectric converters; a ground portion in a peripheral region of the substrate; a dummy isolation pattern surrounding the ground portion and passing through the substrate; a wiring layer; a microlens layer; and a first connection wiring structure. The substrate includes a third surface and a fourth surface that face each other. The virtual isolation pattern is separated from the pixel isolation pattern. The microlens layer is located on the fourth surface of the substrate in the pixel region. The first connection wiring structure is located on the third surface of the substrate in the peripheral region and is electrically connected to the second connection pad. The first connection wiring structure includes multiple connection wirings, multiple vias connecting the multiple connection wirings, and a first contact electrode between the multiple connection wirings and the ground portion. The first connection wiring is electrically connected to the grounding part.

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