Iron-based superconducting heterojunction and preparation method thereof
By optimizing the microstructure of iron-based superconducting heterojunctions through post-annealing, the problems of interface defects caused by lattice mismatch and component volatility were solved, resulting in a significant increase in zero resistance temperature and improvement in electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-03-27
AI Technical Summary
In iron-based superconductor heterostructures, interfacial defects caused by lattice mismatch and component volatility affect the superconducting critical temperature and critical current, which are difficult to effectively solve with existing technologies.
Iron-based superconducting heterojunctions were prepared in a vacuum chamber using a post-annealing process. The microstructure of the material was optimized by precisely controlled thermal cycling to reduce interface defects. Sb2Te3 bulk material was used to supplement volatile components to ensure the stability of chemical composition.
It significantly improves the zero-resistance temperature, reaching a maximum of 8.99K, an increase of up to 90.33%, and increases it by at least 2.0K within the preferred post-annealing time, thereby improving the electrical performance of the heterojunction.
Smart Images
Figure CN121751972A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to topological superconducting heterostructure, in particular to an iron-based superconducting heterostructure and a preparation method thereof. BACKGROUND
[0002] Since the first discovery of iron-based superconductor in 2006 and the discovery of LaOFeAs with 26K superconducting transition temperature in 2008, the research of high-temperature iron-based superconductor has been constantly breaking through. The iron-based superconductor has very strong electronic correlation, and its unconventional superconducting mechanism is not completely suitable for BCS theory. Among them, the structure of iron chalcogenide superconductor is simpler, which is conducive to the research of iron-based superconducting mechanism, and it does not contain high-toxicity elements such as As, which has attracted widespread attention in the scientific community. Among them, iron selenide tellurium (FeSe x Te 1-x , FST) has better superconducting performance and has good epitaxial characteristics in pulsed laser deposition (PLD) growth, so it is often used to construct heterostructures. The heterostructure formed in this way can form a superconducting proximity effect between the superconductor and the general metal. When the general metal is replaced by a topological insulator (TI), a long-range proximity effect may occur, which is a potential material for braiding Majorana zero mode in quantum computing. The application of this aspect is called superconducting topological quantum computing.
[0003] In the PLD-grown iron-based superconductor heterostructure, the commonly used substrate strontium titanate (SrTiO3, STO) structure belongs to the cubic crystal system, while the FST belongs to the tetragonal crystal system, and there is inevitably a lattice mismatch between the thin film and the thin film. Therefore, there are interface effects, substrate effects, stress and stress effects in the interface, which can be alleviated by annealing. However, the third type of topological insulator Bi2Se3, Bi2Te3, Sb2Te3 and the like evaporate Se and Te more easily than Bi and Sb during the PLD growth process. Due to the volatilization characteristics of the components and the decomposition characteristics of the material, chemical component segregation and other problems occur during the annealing process, which will directly affect the superconducting critical temperature and critical current of the heterostructure. Zhang Yalin et al. found that the Se and Te components were reduced during the growth process, and the metal element component was improved, and in the most serious case, the ratio of metal element and Te was as high as 21:1 (Y. Zhang, T. Wang, Z. Wang, and Z. Xing, "Effects of Te- and Fe-doping on the superconducting properties in FeySe1-xTex thin films," Scientific Reports, Article vol. 12, no. 1, Jan 10 2022, Art no. 391, doi: 10.1038 / s41598-021-04403-4). Therefore, many experiments using the PLD process to prepare FST / TI do not undergo annealing treatment, but this will often bring the problems of poor interface quality, stress between thin films cannot be effectively released, stoichiometric ratio of topological insulator material at the interface is out of adjustment, and defects increase, which will greatly weaken the penetration depth and lifetime of Cooper from the superconductor to the topological insulator, and directly show the decrease of the superconducting zero resistance temperature T c 0 (N. N. Hao and J. P. Hu, "Topological Phases in the Single-Layer FeSe," Physical Review X, vol. 4, no. 3, Sep 2014, Art no. 031053, doi:10.1103 / PhysRevX.4.031053.). SUMMARY
[0004] The purpose of the present application is to provide an iron-based superconducting heterojunction with a higher zero resistance temperature.
[0005] Another purpose of the present application is to provide a preparation method of the above-mentioned iron-based superconducting heterojunction.
[0006] Technical solution: The iron-based superconducting heterojunction provided by the application is a layered structure, comprising a titanium dioxide buffer layer, an iron selenium tellurium superconducting layer and an antimony telluride topological insulating layer which are sequentially grown on the surface of a strontium titanate substrate.
[0007] The preparation method of the iron-based superconducting heterojunction provided by the application comprises the following steps: (1) Preparation of Sb2Te3 block material: Sb element and Te element are used as raw materials to sinter to obtain Sb2Te3 block material; (2) Pretreatment and loading of STO substrate: the substrate table with the STO substrate adhered is loaded into the PLD device; (3) Growth of the TiO2 buffer layer on the surface of the STO substrate by using the PLD process; (4) Growth of the FST superconducting layer on the surface of the TiO2 buffer layer by using the PLD process; (5) Growth of the Sb2Te3 topological insulating layer on the surface of the TiO2 buffer layer by using the PLD process to obtain an iron-based superconducting heterojunction precursor; (6) Post annealing: the Sb2Te3 block material obtained in step (1) and the precursor obtained in step (5) are subjected to post annealing to obtain the iron-based superconducting heterojunction.
[0008] In step (1), the atomic ratio of the Sb element and the Te element is 2:2.5-3.5; and in step (1), the highest temperature of the sintering is 700-800℃.
[0009] In the PLD process of step (3), the highest temperature is 450-550℃, and the temperature rising rate is 8-12℃ / min; in the PLD processes of steps (3) and (4), the laser frequency is 1.5-2.5Hz, the preset laser energy is 400-500mJ, and the laser operation time is 3-7min.
[0010] In the PLD process of step (5), the highest temperature is 250-350℃, and the temperature rising rate is 8-12℃ / min; in the PLD process of step (5), the laser frequency is 1.5-2.5Hz, the preset laser energy is 250-350mJ, and the laser operation time is 0.8-1.2h.
[0011] In step (6), the holding time is 30-120min; and in step (6), the holding time is 60-90min.
[0012] Invention principle: In the growing FST / Sb2Te3 heterostructure, due to the volatility of the material, the chemical composition deviates from the original target material during annealing. This deviation usually becomes more serious with the increase of annealing temperature and time. Annealing has the advantages of eliminating interface stress, reducing lattice distortion, making the interface more dense and the structure more stable. In order to not affect the composition during annealing, the present application uses post-annealing technology to prepare iron-based heterojunction. Post-annealing technology, as a key material heat treatment process, its core principle is to provide enough energy and power for the internal atoms of the material through precise control of the heat cycle, such as heating, holding, and slow cooling, so that they can rearrange, diffuse and restructure, thereby optimizing the microstructure of the material, and ultimately achieving the specific goal of eliminating internal stress, improving mechanical properties or stabilizing electrical properties. In the present application, annealing is not performed in the vacuum chamber of PLD, because the loss of volatile components such as Te and Se is more likely to occur in the vacuum chamber, affecting the quality of the sample. The sample is taken out after cooling in the vacuum chamber and placed in a quartz tube. The bulk material in the quartz tube will also volatilize some components such as Te during the annealing process, creating a corresponding atmosphere, relieving the change in the composition during sample growth, reducing the deviation from the chemical composition of the target material, and reducing the interface defects of the material.
[0013] At the microscopic level, the superconducting state is a macroscopic quantum coherent state described by a unified "order parameter". Interface defects can locally destroy this order, especially in unconventional high-temperature superconductors (such as copper-based and iron-based superconductors), interface defects can introduce local magnetic moments that strongly interact with the electron spins of Cooper pairs, destroying Cooper pairs and causing resistance to appear; Certain types of defects can change the electron scattering process, resulting in diffusion scattering and weakening the electron-phonon coupling strength for forming Cooper pairs. Both of these effects will cause the zero resistance temperature to decrease due to interface defects.
[0014] Beneficial effects: Compared with the prior art, the present application has the following significant advantages: the present application uses post-annealing process to prepare superconducting heterojunction, and the zero resistance temperature of the prepared superconducting heterojunction is significantly improved, and the best can reach 8.99K, compared with the heterojunction obtained without using the process, the zero resistance temperature is improved by 4.26741K, and the improvement amplitude is as high as 90.33%; In the further preferred post-annealing time range of 60-90min, the zero resistance temperature is improved by at least 2.0K, and the improvement amplitude is 42.57%; When the post-annealing time is 120min, the effect is poor, but it can also be improved by 0.38K. BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1 SEM cross-sectional view of the heterojunction prepared in Example 1; Figure 2 XRD spectrum of the heterojunction prepared in Example 1; Figure 3 Normalized resistance-temperature curve of the heterojunction prepared for each experiment; Figure 4 Zero resistance temperature-post annealing time curve of the heterojunction prepared for each experiment. DETAILED DESCRIPTION
[0016] The technical solutions of the application are further described below in combination with examples.
[0017] The STO substrate and the TiO2 target used in the application are purchased from Hefei Jingke Material Technology Co., Ltd.
[0018] The preparation process of the FST target used in the application is as follows: prepared by a self-fusion method with high-purity materials (iron 99.99%, tellurium 99.999% and selenium 99.999%) in an atomic ratio of 1:0.4:0.6. The iron, selenium and tellurium are fully ground and pressed into a column with a diameter of 3 / 4 inch, and then packaged in a vacuum quartz tube. The vacuum quartz tube is calcined in a muffle furnace at a temperature of 850°C for 72 hours, and then slowly cooled to room temperature at a rate of 3°C / min.
[0019] The preparation process of the Sb2Te3 target used in the application is as follows: prepared by a self-fusion method with high-purity materials (antimony 99.99%, tellurium 99.999%) in an atomic ratio of 2:3. The antimony and tellurium are fully ground and pressed into a column with a diameter of 3 / 4 inch, and then packaged in a vacuum quartz tube. The vacuum quartz tube is calcined in a muffle furnace at a temperature of 450°C for 12 hours, and then at a temperature of 750°C for 72 hours, and then slowly cooled to room temperature at a rate of 3°C / min.
[0020] Example 1 The iron-based superconducting heterojunction described in the application is a layered structure, which comprises a titanium dioxide buffer layer, an iron selenium tellurium superconducting layer and an antimony telluride topological insulating layer, which are sequentially grown on the surface of a strontium titanate substrate.
[0021] The preparation method of the iron-based superconducting heterojunction described in the application comprises the following steps: (1) Preparation of Sb2Te3 block material: 5g of Sb and Te elemental powders with a purity of 99.99% are mixed uniformly in an atomic ratio of 2:3, ground for 2h, and pressed into a cylinder with a diameter of 3 / 4 inch in a mold. The cylinder is sealed in a quartz tube with a vacuum degree better than 10 -2 mbar by a hydrogen-oxygen flame machine, and the quartz tube is placed in a muffle furnace for sintering. The sintering parameters are set as follows: from 25°C to 450°C at a rate of 1°C / min and kept for 12h, then from 450°C to 750°C at a rate of 1°C / min and kept for 15h, and then from 750°C to 25°C at a rate of 1°C / min. The Sb2Te3 block material is obtained and ready for use.
[0022] (2) Pretreatment and loading of STO substrate: The STO substrate is cleaned with alcohol three times, the substrate table is polished and cleaned, the STO substrate is adhered to the center of the substrate table using high-temperature resistant epoxy silver paste, the substrate table loaded with the substrate is heated under an infrared light lamp with a power of 100-200 W for 10-15 min, and after heating, it is cooled. The substrate table is loaded into a pulsed laser deposition device, and the vacuum degree is maintained to be not less than 4x10 -6 mbar.
[0023] (3) Growth of TiO2 buffer layer: After polishing the TiO2 target, it is installed on the target seat, and the target seat is loaded on the substrate table. The TiO2 buffer layer is grown using the PLD process. The temperature is increased to 500°C at a rate of 10°C / min, the laser frequency is set to 2Hz, the preset laser energy is 450mJ, the oxygen is injected to make the vacuum degree not less than 10 -4 mbar, the laser is operated for 5 min, and the TiO2 buffer layer is grown on the surface of the STO substrate. When the temperature is decreased to 110°C at a rate of 5°C / min, the oxygen injection is stopped, and the temperature is continuously decreased to 25°C.
[0024] (4) Growth of FST superconducting layer: The target on the target seat is replaced with an FST target and is returned to its original position. The FST superconducting layer is grown using the PLD process. The temperature is increased to 300°C at a rate of 10°C / min, the laser frequency is set to 2Hz, the preset laser energy is 450mJ, the vacuum degree of the environment is set to be not less than 5x10 -7 mbar, the laser is operated for 5 min, and the FST superconducting layer is grown on the surface of the TiO2 buffer layer. The temperature is decreased to 25°C at a rate of 5°C / min.
[0025] (5) Growth of Sb2Te3 topological insulating layer: The target on the target seat is replaced with an Sb2Te3 target and is returned to its original position. The Sb2Te3 topological insulating layer is grown using the PLD process. The temperature is increased to 300°C at a rate of 10°C / min, the laser frequency is set to 2Hz, the preset laser energy is 300mJ, the vacuum degree of the environment is set to be not less than 5x10 -7 mbar, the laser is operated for 1h, and the Sb2Te3 topological insulating layer is grown on the surface of the TiO2 buffer layer. When the temperature is decreased to 40°C at a rate of 5°C / min, the target and the substrate table are removed, and the temperature is continuously decreased to 25°C. An iron-based superconducting heterojunction precursor is obtained.
[0026] (6) Post-annealing: The Sb2Te3 bulk material obtained in step (1) and the precursor obtained in step (5) are sealed in a vacuum quartz tube with the bulk material at the bottom and the Sb2Te3 topological insulator layer of the precursor facing up on the bulk material using a hydrogen-oxygen flame machine. The quartz tube is placed in a muffle furnace, which is raised from 25 °C to 250 °C at a rate of 1 °C / min and held for 60 min, and then lowered to 25 °C at a rate of 1 °C / min, and the sample is immediately removed and placed in a vacuum box. An iron-based superconducting heterojunction is obtained.
[0027] Example 2 The same as in Example 1 is not repeated, and the difference is that the holding time in step (6) is 30 min.
[0028] Example 3 The same as in Example 1 is not repeated, and the difference is that the holding time in step (6) is 90 min.
[0029] Example 4 The same as in Example 1 is not repeated, and the difference is that the holding time in step (6) is 120 min.
[0030] Example 5 The same as in Example 1 is not repeated, and the difference is that the atomic ratio of the Sb and Te elements in step (1) is 2:2.5, the maximum sintering temperature is 700 °C; the maximum PLD substrate temperature used in step (3) is 450 °C, and the temperature rise rate is 8 °C / min; in the PLD process described in steps (3) and (4), the laser frequency is 1.5 Hz, the preset laser energy is 400 mJ, and the laser operating time is 3 min; in the PLD process described in step (5), the maximum temperature is 250 °C, the temperature rise rate is 8 °C / min, the laser frequency is 1.5 Hz, the preset laser energy is 250 °C / min, and the laser operating time is 0.8 h.
[0031] Example 6 The same as in Example 1 is not repeated, and the difference is that the atomic ratio of the Sb and Te elements in step (1) is 2:3.5, the maximum sintering temperature is 800 °C; the maximum PLD substrate temperature used in step (3) is 550 °C, and the temperature rise rate is 12 °C / min; in the PLD process described in steps (3) and (4), the laser frequency is 2.5 Hz, the preset laser energy is 500 mJ, and the laser operating time is 7 min; in the PLD process described in step (5), the maximum temperature is 350 °C, the temperature rise rate is 12 °C / min, the laser frequency is 3.5 Hz, the preset laser energy is 350 °C / min, and the laser operating time is 1.2 h.
[0032] Comparative Example 1 The same as that of Example 1 is not repeated, and the difference is that the holding time in step (6) is 0.
[0033] Figure 1 The SEM cross-section of the heterojunction prepared in Example 1 can clearly show that the heterojunction is a layered structure, including a TiO2 buffer layer, an FST superconducting layer, and an Sb2Te3 topological insulating layer grown on the surface of the STO substrate in turn. Figure 2 The XRD pattern of the heterojunction prepared in Example 1 can show that the TiO2 buffer layer, the FST superconducting layer, and the Sb2Te3 topological insulating layer on the surface of the STO substrate all exist, and both FST and Sb2Te3 are (001) oriented; the pattern obviously has the (001), (002), (003), and (004) absorption peaks of FST, which can indicate that the heterojunction contains the c-axis grown FST superconducting layer.
[0034] The zero-resistance temperature of each prepared heterojunction was tested by using the four-probe method, and the results are shown in Table 1. Figure 3 The zero-resistance temperature is the highest temperature with a resistance of 0 within the accuracy range of the instrument. It can be seen that the iron-based superconducting heterojunction precursor without postannealing has a lower zero-resistance temperature (Comparative Example 1, about 5K), because the interface has relatively more defects caused by interface stress and lattice distortion, which affects the transmission of Cooper pairs in the proximity effect. When the postannealing time of the multilayer heterojunction constructed by the method is extended to 90 min and 120 min (Examples 3-4), the zero-resistance temperature of the heterojunction gradually decreases, because long-time annealing breaks the thermodynamic equilibrium, leading to material decomposition, and excessive grain growth, which can cause the film to be less dense and the mechanical properties to be poor, resulting in more electrical defects in the heterojunction as a whole, destroying the topological surface state, and shortening the coherence length of Cooper pairs. Between the two, the zero-resistance temperature can be obviously seen to increase, because when the postannealing time is appropriate, it can retain the advantages of annealing to promote crystallization, improve orientation, and remove defects, significantly improving the electrical properties of the heterojunction. At the same time, the atmosphere supplemented by the Sb2Te3 bulk material in the postannealing process reduces the loss of chemical components, resulting in a more dense interface of the film, so that the Cooper pairs that produce superconducting effect in the proximity effect have a longer coherence length, and thus exhibit a lower zero-resistance temperature. When the postannealing time is 60 min (Example 1), the zero-resistance temperature reaches the highest value of 8.99191K, close to 10K. In addition, it can be seen from Table 1 that the resistance of the heterojunction suddenly changes and drops to 0, which is the most prominent feature of superconductors. Figure 3
Claims
1. A type of iron-based superconducting heterostructure, characterized in that, The heterojunction is a layered structure, comprising a titanium dioxide buffer layer, an iron selenide telluride superconducting layer, and an antimony telluride topological insulating layer sequentially grown on the surface of a strontium titanate substrate.
2. A method for preparing an iron-based superconducting heterojunction as described in claim 1, characterized in that, Includes the following steps: (1) Preparation of Sb2Te3 bulk material: Sb and Te are used as raw materials and sintered to obtain Sb2Te3 bulk material; (2) Pre-processing and loading STO substrate: Load the substrate stage with STO substrate attached into the PLD device; (3) Use PLD process to grow TiO2 buffer layer on STO substrate surface; (4) The FST superconducting layer is grown on the surface of the TiO2 buffer layer using the PLD process; (5) Using the PLD process, an Sb2Te3 topological insulating layer is grown on the surface of the TiO2 buffer layer to obtain an iron-based superconducting heterojunction precursor; (6) Post-annealing: The Sb2Te3 bulk material obtained in step (1) and the precursor obtained in step (5) are post-annealed to obtain an iron-based superconducting heterojunction.
3. The preparation method according to claim 2, characterized in that, The heat preservation time mentioned in step (6) is 30-120 minutes.
4. The preparation method according to claim 2, characterized in that, The heat preservation time mentioned in step (6) is 60-90 minutes.
5. The preparation method according to claim 2, characterized in that, In the PLD process described in step (3), the highest temperature is 450-550℃ and the heating rate is 8-12℃ / min.
6. The preparation method according to claim 2, characterized in that, In the PLD process described in steps (3) and (4), the laser frequency is 1.5-2.5Hz, the preset laser energy is 400-500mJ, and the laser running time is 3-7min.
7. The preparation method according to claim 2, characterized in that, In the PLD process described in step (5), the highest temperature is 250-350℃ and the heating rate is 8-12℃ / min.
8. The preparation method according to claim 2, characterized in that, In the PLD process described in step (5), the laser frequency is 1.5-2.5Hz, the preset laser energy is 250-350mJ, and the laser running time is 0.8-1.2h.
9. The preparation method according to claim 2, characterized in that, The atomic ratio of Sb and Te in step (1) is 2:2.5-3.
5.
10. The preparation method according to claim 2, characterized in that, The maximum sintering temperature described in step (1) is 700-800℃.