Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming an oxide layer on the substrate; forming a stacked sacrificial layer and a patterned photoresist layer on the oxide layer, and patterning the sacrificial layer to expose a part of the oxide layer; performing a first ion implantation process, and implanting ions into the substrate below the exposed oxide layer; the photoresist layer is removed; performing a second ion implantation process, and forming a well region in the substrate below the exposed oxide layer; the sacrificial layer is removed; wherein the beam intensity of the second ion implantation process is larger than that of the first ion implantation process, and the implantation energy of the second ion implantation process is smaller than that of the first ion implantation process. According to the semiconductor device, ion reflection in the ion implantation process is reduced, so that damage to the oxide layer is reduced or even avoided, and the performance and stability of the semiconductor device are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Generally, in the process of preparing a well region, the ion implantation dose of ion implantation process (IMP) can reach the order of magnitude of E12-E13. For the advanced process of 28nm, the ion implantation dose of the well region has the demand of high beam, which usually needs to reach the order of magnitude of E15. At this time, the energy demand of high beam ion implantation process is relatively low.

[0003] However, in the ion implantation process of the well region, there is a well-proximity effect, that is, if the photoresist layer (PR) of the well region is thick, the collision probability of ions and the photoresist layer will increase, which leads to the increase of the dose of the reflected implantation ions at the interface between the photoresist layer and the oxide layer (Oxide) below the interface. The interface becomes a weak point, which is easy to produce defects. After the oxide layer is removed by wet etching (WET), it is easy to cause active area damage (AA damage). SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce the oxide layer damage caused by ion reflection in the process of forming a well region.

[0005] The present application provides a manufacturing method of a semiconductor device, comprising:

[0006] providing a substrate, wherein an oxide layer is formed on the substrate;

[0007] forming a stack of a sacrificial layer and a patterned photoresist layer on the oxide layer, and performing a patterned treatment on the sacrificial layer to expose part of the oxide layer;

[0008] performing a first ion implantation process to implant ions into the substrate below the exposed oxide layer;

[0009] removing the photoresist layer;

[0010] performing a second ion implantation process to form a well region in the substrate below the exposed oxide layer;

[0011] removing the sacrificial layer;

[0012] The second ion implantation process has a beam intensity greater than the first ion implantation process and an implantation energy less than the first ion implantation process.

[0013] In one of the embodiments, before forming the sacrificial layer on the oxide layer, the method further comprises:

[0014] Performing decoupling plasma oxidation on the oxide layer.

[0015] In one of the embodiments, the first ion implantation process has a beam intensity ranging from 1*10 13 mA to 1*10 14 mA, an implantation energy ranging from 50 Kev to 3000 Kev, and implantation ions including one of phosphorus ions and arsenic ions.

[0016] The second ion implantation process has a beam intensity ranging from 1*10 15 mA to 1*10 16 mA, an implantation energy ranging from 2 Kev to 10 Kev, and implantation ions including germanium ions.

[0017] In one of the embodiments, the thickness of the sacrificial layer is positively correlated with at least one of the beam intensity, the implantation energy, and the implantation time of the second ion implantation process.

[0018] In one of the embodiments, the thickness of the sacrificial layer ranges from 2 kÅ to 3 kÅ.

[0019] In one of the embodiments, the photoresist layer has a thickness ranging from 8 kÅ to 50 kÅ.

[0020] In one of the embodiments, the photoresist layer has a material different from that of the sacrificial layer.

[0021] In one of the embodiments, the photoresist layer removal method and the sacrificial layer removal method both include a wet etching process, and the etching rate of the photoresist layer is greater than that of the sacrificial layer during the removal of the photoresist layer.

[0022] In one of the embodiments, after removing the sacrificial layer, the method further comprises:

[0023] Performing an annealing process;

[0024] Removing the oxide layer.

[0025] Correspondingly, the application also provides a semiconductor device manufactured by the method for manufacturing a semiconductor device.

[0026] The unexpected effect of the present application is that a sacrifice layer and a photoresist layer are formed on the oxide layer to protect the oxide layer in the subsequent ion implantation process; the first ion implantation process is based on the photoresist layer and the second ion implantation process is based on the sacrifice layer, and the beam intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process, so as to reduce ion reflection in the two ion implantation processes while forming the well region, thereby reducing the damage of the oxide layer caused by ion reflection, and effectively improving the performance and stability of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0028] Figure 1 A structure diagram corresponding to the step of forming a doped region in a manufacturing method of a semiconductor device in the related art.

[0029] Figure 2 A structure diagram corresponding to the step of removing a photoresist layer in a manufacturing method of a semiconductor device in the related art.

[0030] Figure 3 A structure diagram corresponding to the step of performing an annealing process in a manufacturing method of a semiconductor device in the related art.

[0031] Figure 4 A structure diagram corresponding to the step of removing a silicon oxide layer in a manufacturing method of a semiconductor device in the related art.

[0032] Figure 5 A flowchart of a manufacturing method of a semiconductor device provided by one of the embodiments of the present application.

[0033] Figure 6 A structure diagram corresponding to the step of providing a substrate and forming an oxide layer on the substrate in a manufacturing method of a semiconductor device provided by one of the embodiments of the present application.

[0034] Figure 7 A structure diagram corresponding to the step of forming a sacrifice layer on the oxide layer in a manufacturing method of a semiconductor device provided by one of the embodiments of the present application.

[0035] Figure 8The structure diagram corresponding to the step of forming a patterned photoresist layer on the sacrificial layer in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0036] Figure 9 The structure diagram corresponding to the step of performing a patterned treatment on the sacrificial layer in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0037] Figure 10 The structure diagram corresponding to the step of performing a first ion implantation process in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0038] Figure 11 The structure diagram corresponding to the step of removing the photoresist layer in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0039] Figure 12 The structure diagram corresponding to the step of performing a second ion implantation process in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0040] Figure 13 The structure diagram corresponding to the step of removing the sacrificial layer in the method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0041] In the drawings, reference numerals include: 100 - substrate; 101 - doped region; 110 - silicon oxide layer; 120 - photoresist layer; 200 - substrate; 201 - well region; 210 - oxide layer; 220 - sacrificial layer; 230 - photoresist layer. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0044] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0045] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional

[0046] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0047] Figures 1 to 4 Fig. 1 is a schematic diagram of a structure corresponding to a partial step in a manufacturing method of a semiconductor device according to a prior art. Figures 1 to 4 The following describes a method for forming a general doped region.

[0048] First, referring to Fig. 1, a substrate 100 is provided, and a silicon oxide layer 110 and a patterned photoresist layer 120 are formed on the substrate 100. An ion implantation process (IMP) is performed to form a doped region 101 in the substrate 100 under the silicon oxide layer 110 exposed by the photoresist layer 120. Optionally, the doped region 101 can be a well region. Figure 1

[0049] It is noted that, since the photoresist layer is thick (e.g., 8kA), a large amount of ions will be reflected to the interface between the silicon oxide layer and the photoresist layer during the ion implantation process for forming the doped region, and the interface will become a weak point (indicated by the circle in Fig. 1), which is prone to defects. Figure 1

[0050] Next, referring to Fig. 2, the photoresist layer 120 is removed. Optionally, a wet etching process is used to remove the photoresist layer 120. It is noted that, during the removal of the photoresist layer 120, the silicon oxide layer 110 will also be damaged by etching, which will degrade the quality of the silicon oxide layer and further increase the risk of defects in the silicon oxide layer 110. Figure 2 Subsequently, referring to Figs. 3 and 4, an annealing process is performed on the substrate 100 and the silicon oxide layer 110. Then, the silicon oxide layer 110 is removed for subsequent process. Optionally, a wet etching process is used to remove the silicon oxide layer 110.

[0051] Figure 3 It is noted that, since the silicon oxide layer has a weak point and is damaged during the removal of the photoresist layer, the removal rate of the weak point in the silicon oxide layer is faster than that of the remaining part of the silicon oxide layer during the removal of the silicon oxide layer, which will cause the substrate under the weak point to be exposed and damaged by etching first, and even cause active area damage (AA Damage) in the semiconductor device, which will seriously affect the yield and stability of the semiconductor device. Figure 4 Therefore, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce the damage to the oxide layer caused by ion reflection during the formation of the well region.

[0052]

[0053]

[0054] Figure 5 ​​​​​A flow chart of a method for manufacturing a semiconductor device is provided in one of the embodiments of the present application. Referring to Figure 5 A method for manufacturing a semiconductor device is provided in one of the embodiments of the present application, which comprises the following steps S01 to S06.

[0055] Step S01: providing a substrate, wherein an oxide layer is formed on the substrate.

[0056] Step S02: forming a stack of a sacrificial layer and a patterned photoresist layer on the oxide layer, and performing a patterning process on the sacrificial layer to expose part of the oxide layer.

[0057] Step S03: performing a first ion implantation process to implant ions into the substrate under the exposed oxide layer.

[0058] It should be noted that, since the sacrificial layer is formed on the oxide layer, during the first ion implantation process, the reflected ions will preferentially enter the sacrificial layer, thereby reducing or even avoiding the probability of the reflected ions entering the oxide layer, so as to reduce the ion damage to the oxide layer.

[0059] Step S04: removing the photoresist layer.

[0060] Step S05: performing a second ion implantation process to form a well region in the substrate under the exposed oxide layer; wherein the beam intensity of the second ion implantation process is greater than the beam intensity of the first ion implantation process, and the implantation energy of the second ion implantation process is less than the implantation energy of the first ion implantation process.

[0061] It should be noted that, since the beam intensity of the second ion implantation process is greater than the beam intensity of the first ion implantation process, and the implantation energy of the second ion implantation process is less than the implantation energy of the first ion implantation process, that is, the first ion implantation process is a high-energy medium-beam ion implantation process, and the second ion implantation process is a low-energy high-beam ion implantation process. It can be known from the common knowledge in the art that the ion reflection in the high-energy medium-beam ion implantation process is relatively less, and therefore, the first ion implantation process with high-energy medium-beam can further reduce the probability of ion damage to the oxide layer. In the second ion implantation process with low-energy high-beam, the reflected ions generated during the process will preferentially enter the sacrificial layer under the blockage of the sacrificial layer, thereby minimizing the probability of the ions reflecting into the oxide layer, and effectively reducing the risk of damage to the oxide layer.

[0062] Step S06: removing the sacrificial layer.

[0063] The manufacturing method of the semiconductor device as described above forms a sacrifice layer and a photoresist layer on the oxide layer to protect the oxide layer in the subsequent ion implantation process; the first ion implantation process based on the photoresist layer and the second ion implantation process based on the sacrifice layer, and the beam intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process, so as to reduce ion reflection in the two ion implantation processes while forming the well region, thereby reducing the damage of the oxide layer caused by ion reflection and effectively improving the performance and stability of the semiconductor device.

[0064] Figures 6 to 13 The manufacturing method of the semiconductor device provided in one of the embodiments of the present application is shown in the structure diagram of the corresponding part of the steps. The following will be described in combination with Figures 6 to 13 The manufacturing method of the semiconductor device provided in one of the embodiments of the present application is shown in the structure diagram of the corresponding part of the steps. The following will be described in combination with

[0065] Firstly, referring to Figure 6 , a substrate 200 is provided, and an oxide layer 210 is formed on the substrate 200. In one of the embodiments, before the sacrifice layer is formed on the oxide layer 210, the manufacturing method of the semiconductor device further includes: performing a decoupled plasma oxidation (DPO) process on the oxide layer to repair the damage of the oxide layer 210 caused in the previous process, improve the surface flatness and density of the oxide layer 210, and thereby reduce the ion reflection in the subsequent ion implantation process. Optionally, the material of the oxide layer 210 includes silicon dioxide (SiO2).

[0066] Then, referring to Figures 7 to 9 , a sacrifice layer 220 and a patterned photoresist layer 230 are formed on the oxide layer 210, and the sacrifice layer 220 is patterned to expose part of the oxide layer 210. In one of the embodiments, the material of the photoresist layer 230 is different from that of the sacrifice layer 220, so as to remove the photoresist layer 230 and the sacrifice layer 220 respectively in the subsequent process. Optionally, the material of the sacrifice layer 220 includes silicon nitride (SiN).

[0067] In one of the embodiments, the thickness of the sacrifice layer ranges from 2kÅ to 3kÅ, and the thickness of the photoresist layer ranges from 8kÅ to 50kÅ. It should be noted that in other embodiments of the present application, the specific thickness range of the oxide layer, the sacrifice layer and the photoresist layer can be adjusted according to the process parameters of the subsequent ion implantation process, or the corresponding thickness range can be set according to the actual needs, as long as the combined thickness of the oxide layer and the sacrifice layer is sufficient to protect the substrate and avoid damage to the substrate caused by ion implantation, which is not limited in the present application.

[0068] In one embodiment, the forming process of the sacrifice layer and the photoresist layer includes: Figure 7 depositing a sacrifice layer 220 on the oxide layer 210; then, Figure 8 forming a photoresist layer 230 on the sacrifice layer 220, and performing exposure and etching processes on the photoresist layer 230 to form a patterned photoresist layer 230; then, Figure 9 using the photoresist layer 230 as a mask to etch the sacrifice layer 220 to realize the patterning of the sacrifice layer 220 and expose part of the oxide layer 210 for the subsequent ion implantation process of the well region.

[0069] then, Figure 10 performing a first ion implantation process to implant ions into the substrate under the exposed oxide layer 210. In one embodiment, the beam intensity of the first ion implantation process ranges from 1 x 10 13 mA to 1 x 10 14 mA, the implantation energy ranges from 50 Kev to 3000 Kev, and the implanted ions include one of phosphorus ions (P) and arsenic ions (As).

[0070] It is emphasized that, since the first ion implantation process is a high-energy medium-beam ion implantation process, the ion reflection is relatively less in this ion implantation process, and thus the first ion implantation process with high-energy medium-beam can reduce the probability of ion damage to the oxide layer.

[0071] then, Figure 10 and Figure 11 removing the photoresist layer 230. In one embodiment, the photoresist layer 230 can be removed by using a gray etching process and a wet etching process, and the etching rate of the photoresist layer 230 is greater than the etching rate of the sacrifice layer 220 during the removal of the photoresist layer 230, so as to avoid the sacrifice layer 220 being removed together with the photoresist layer 230 during the removal of the photoresist layer 230.

[0072] then, Figure 12 performing a second ion implantation process to form a well region 201 in the substrate 200 under the exposed oxide layer 210; wherein the beam intensity of the second ion implantation process is greater than the beam intensity of the first ion implantation process, and the implantation energy of the second ion implantation process is less than the implantation energy of the first ion implantation process. In one embodiment, the beam intensity of the second ion implantation process ranges from 1 x 10 15 mA to 1 x 10 16 mA, the implantation energy ranges from 2 Kev to 10 Kev, and the implanted ions include germanium ions (Ge).

[0073] In other embodiments of the present application, the implanting ions of the first ion implantation process and the second ion implantation process can also be other ions meeting the process requirements according to actual needs, as long as the condition that the types of the implanting ions corresponding to the first ion implantation process and the second ion implantation process are different is met, and the present application does not limit this.

[0074] It should be noted that in the second ion implantation process with low energy and high beam current, the reflected ions generated in the process will preferentially enter the sacrificial layer under the blocking of the sacrificial layer, thereby maximizing the probability of reducing the reflection of ions into the oxide layer and effectively reducing the risk of damage to the oxide layer. At the same time, the sacrificial layer will be damaged by a large amount of ions during the second ion implantation process, and in severe cases, it can even cause the thickness of the sacrificial layer to be thinned. Therefore, when setting the thickness of the sacrificial layer, the process parameters of the second ion implantation process need to be adjusted to ensure that the sacrificial layer can always protect the oxide layer during the second ion implantation process. In one embodiment, the thickness of the sacrificial layer is positively correlated with at least one of the beam intensity, the implantation energy, and the implantation time of the second ion implantation process.

[0075] Subsequently, referring to Figure 13 , the sacrificial layer 220 is removed. In one embodiment, a wet etching process is used to remove the sacrificial layer 220. In other embodiments of the present application, other methods can also be used to remove the sacrificial layer 220, and the present application does not limit this.

[0076] In one embodiment, after the sacrificial layer is removed, the semiconductor device manufacturing method further includes: performing an annealing process to repair the ion implantation damage in the semiconductor device; and removing the oxide layer to facilitate subsequent process procedures.

[0077] Correspondingly, continuing to refer to Figure 13 , one embodiment of the present application also provides a semiconductor device manufactured by the semiconductor device manufacturing method described above. In other embodiments of the present application, the semiconductor device manufacturing method described above can also be used to manufacture a doped region, an ion implantation region, or other similar semiconductor structures to reduce or even avoid the damage to the oxide layer or the active region caused by ion reflection, thereby helping to improve the performance and stability of the semiconductor device.

[0078] The application has the unexpected effect that: a sacrifice layer and a photoresist layer are formed on the oxide layer to protect the oxide layer in the subsequent ion implantation process; the first ion implantation process is based on the photoresist layer, the second ion implantation process is based on the sacrifice layer, the beam intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process, so as to reduce ion reflection in the two ion implantation processes while forming the well region, thereby reducing damage to the oxide layer caused by ion reflection and effectively improving the performance and stability of the semiconductor device.

[0079] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0080] The technical features of the above-described embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as the scope of the present application.

[0081] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent application scope. It should be noted that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which an oxide layer is formed; A sacrificial layer and a patterned photoresist layer are stacked on the oxide layer. The sacrificial layer is patterned based on the patterned photoresist layer to expose a portion of the oxide layer. A first ion implantation process is performed to implant ions into the substrate beneath the exposed oxide layer; Remove the photoresist layer; A second ion implantation process is performed to form a trap region within the substrate beneath the exposed oxide layer; Remove the sacrificial layer; The beam current intensity of the second ion implantation process is greater than that of the first ion implantation process, and the implantation energy of the second ion implantation process is less than that of the first ion implantation process.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before forming a sacrificial layer on the oxide layer, the method for manufacturing the semiconductor device further includes: The oxide layer is subjected to decoupled plasma oxidation treatment.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The beam current intensity range of the first ion implantation process includes 1×10⁻⁶. 13 mA~1×10 14 mA, with implantation energy ranging from 50 KeV to 3000 KeV, and implanted ions including either phosphorus ions or arsenic ions; The beam current intensity range of the second ion implantation process includes 1×10⁻⁶. 15 mA~1×10 16 mA, with implantation energies ranging from 2 KeV to 10 KeV, and implanted ions including germanium ions.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The thickness of the sacrificial layer is positively correlated with at least one of the parameters of the second ion implantation process: beam intensity, implantation energy, and implantation time.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The thickness of the sacrificial layer ranges from 2kÅ to 3kÅ.

6. The method for manufacturing a semiconductor device according to claim 1 or 5, characterized in that, The thickness of the photoresist layer ranges from 8 kÅ to 50 kÅ.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The photoresist layer is made of a different material than the sacrificial layer.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Both the photoresist layer removal method and the sacrificial layer removal method include a wet etching process, and during the removal of the photoresist layer, the etching rate of the photoresist layer is greater than the etching rate of the sacrificial layer.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: Perform the annealing process; Remove the oxide layer.

10. A semiconductor device, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 9.

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