Semiconductor element and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes performing a first patterning process to form a first trench in a substrate structure, where the substrate structure includes a substrate and a compound semiconductor layer over the substrate, and the first trench passes through the compound semiconductor layer and exposes the substrate. The manufacturing method further includes forming a capacitor structure in the first trench, wherein forming the capacitor structure includes forming a first metal layer lined in the first trench and in contact with the substrate, forming a first dielectric layer lined in the first metal layer and in contact with the first metal layer, and forming a second metal layer lined in the first dielectric layer and in contact with the first dielectric layer. A photomask for forming the deep groove and the lower electrode and / or the upper electrode of the capacitor can be omitted, the process is further simplified, and the process efficiency is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor element and a method for manufacturing the same. Background Technology

[0002] As manufacturing technology advances, semiconductor devices are continuously miniaturized to increase integration density. However, some problems in manufacturing semiconductor devices may arise due to process miniaturization. For example, as critical dimensions shrink, the electrode surface area of ​​capacitors decreases, leading to a reduction in capacitance. Therefore, how to improve the capacitance density of semiconductor devices is one of the problems that the industry urgently needs to invest research and development resources to solve. Summary of the Invention

[0003] In view of this, one object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.

[0004] One aspect of the present invention relates to a method of manufacturing a semiconductor element, comprising performing a first patterning process to form a first trench in a substrate structure, wherein the substrate structure includes a substrate and a compound semiconductor layer located above the substrate, and the first trench passes through the compound semiconductor layer and exposes the substrate. The manufacturing method further comprises forming a capacitor structure in the first trench, wherein forming the capacitor structure includes forming a first metal layer lining the first trench and contacting the substrate, forming a first dielectric layer lining the first metal layer and contacting the first metal layer, and forming a second metal layer lining the first dielectric layer and contacting the first dielectric layer.

[0005] Another aspect of the present invention relates to a semiconductor device comprising a substrate structure and a capacitor structure. The substrate structure includes a substrate and a compound semiconductor layer situated above the substrate. The capacitor structure is situated above the substrate structure and includes a first metal layer, a first dielectric layer, and a second metal layer. The first metal layer has a portion extending downward through the compound semiconductor layer and contacting the substrate. The first dielectric layer is situated above the first metal layer and clad against the portion of the first metal layer. The second metal layer is situated above the portion of the first metal layer and above the first dielectric layer, and clad against the first dielectric layer.

[0006] In summary, in some embodiments of the semiconductor device and its manufacturing method of the present invention, trenches for forming deep trench capacitors can be formed simultaneously when forming trenches used as dicing paths, thereby improving capacitance and capacitance density. Furthermore, metal interconnects of the metal interconnect structure can be used as the lower and / or upper electrodes of the deep trench capacitor. In this way, compared to current common processes, the photomask for forming the deep trench and the lower and / or upper electrodes of the capacitor can be eliminated, further simplifying the process and improving process efficiency. Attached Figure Description

[0007] The accompanying drawings illustrate one or more embodiments of the invention and, together with the written description, serve to explain the principles of the invention. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements, wherein:

[0008] Figures 1 to 4 This is a partial cross-sectional view of an intermediate stage in a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0009] Figure 5 This is a top view of an intermediate stage in a method for manufacturing a semiconductor element according to some embodiments of the present invention.

[0010] Figure 6 This is a partial cross-sectional view of a semiconductor device according to other embodiments of the present invention.

[0011] Figure 7 This is a partial cross-sectional view of a semiconductor device according to yet another embodiment of the present invention. Detailed Implementation

[0012] Figures 1 to 4 These are partial cross-sectional views of intermediate stages in a method for manufacturing a semiconductor element according to some embodiments of the present invention.

[0013] First, please refer to Figure 1 Provides a base material structure 100. For example... Figure 1 As shown, the substrate structure 100 includes a substrate 102 and a compound semiconductor layer 104 located above the substrate 102. The substrate 102 may include a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or an aluminum nitride (AlN) substrate. The compound semiconductor layer 104 may include a III-V compound semiconductor. Specifically, the compound semiconductor layer 104 may include gallium nitride, aluminum gallium nitride, aluminum nitride, or a combination thereof. For example, the compound semiconductor layer 104 may include a gallium nitride layer and an aluminum gallium nitride layer located on top of the gallium nitride layer, wherein the gallium nitride layer may include a channel region that allows two-dimensional electron gas (2DEG) to pass through. In some embodiments, the substrate structure 100 may have active elements such as… Figure 1 The transistor TR in the example has a gate contact G and source / drain contacts S / D located on both sides of the gate contact G on the top surface of the compound semiconductor layer 104. The transistor TR can be a high electron mobility transistor (HEMT), but is not limited to this.

[0014] like Figure 1As shown, a metal interconnect structure and multiple dielectric layers are provided above the substrate structure 100. Specifically, dielectric layer 110 is located above the substrate structure 100 and covers the top surface of transistor TR and compound semiconductor layer 104. The metal interconnect structure may include via 120 and metal layer 130. Via 120 contacts and is electrically connected to the source / drain contacts S / D of transistor TR through dielectric layer 110. Metal layer 130 is located above dielectric layer 110 and connected to via 120. Metal layer 130 may also be referred to as the first metal interconnect (M1) of the metal interconnect structure. Dielectric layer 140 is located above dielectric layer 110 and covers the top surface of metal layer 130 and dielectric layer 110. The metal interconnect structure may also include other metal interconnects and vias connected to metal layer 130 and disposed in dielectric layer 140. Dielectric layer 140 may be a stack of dielectric layers formed by multiple different processes, and the present invention is not limited thereto.

[0015] Next, a first patterning process is performed on the above structure to form trenches T1 and T2 in the substrate structure 100. For example... Figure 1 As shown, trenches T1 and T2 are located on one side of transistor TR and pass through dielectric layer 140, dielectric layer 110, and compound semiconductor layer 104, exposing a portion of substrate 102. In some embodiments, the bottom surface of trenches T1 and T2 may be lower than the top surface of substrate 102. The height H of trenches T1 and T2 may be between 5 micrometers and 30 micrometers. For example, the height H of trenches T1 and T2 may be 15 micrometers.

[0016] Next, please refer to Figure 2 A metal layer 150 is formed lining the top surface of the dielectric layer 140, trench T1, and trench T2. The metal layer 150 extends downwards from above the transistor TR along the sidewall of trench T1 through the dielectric layer 140, dielectric layer 110, and compound semiconductor layer 104, and contacts the substrate 102. In some embodiments, the bottom surface of the horizontal portion 150a of the metal layer 150 contacting the substrate 102 may be lower than the top surface of the substrate 102. The top surface of the horizontal portion 150a of the metal layer 150 may be lower than the top surface of the compound semiconductor layer 104. Similarly, the metal layer 150 may extend downwards from the top surface of the dielectric layer 140 along the sidewall of trench T2 and contact the substrate 102.

[0017] In some embodiments, after the metal layer 150 is formed, a second patterning process is performed to pattern the metal layer 150, thereby removing portions of the metal layer 150 located in the trench T2 and re-exposing a portion of the substrate 102. In some embodiments, multiple portions of the metal layer 150 adjacent to the trench T2 and located above the dielectric layer 140 are also removed by the second patterning process, such as... Figure 2 As shown in the diagram, the formed metal layer 150 serves as the top metal interconnect of the metal interconnect structure.

[0018] Next, please refer to Figure 3 A dielectric layer 160 is formed above and liner the metal layer 150. The dielectric layer 160 extends from above the transistor TR along the metal layer 150 into the trench T1. The dielectric layer 160 is partially below the top surface of the compound semiconductor layer 104. In some embodiments, the dielectric layer 160 also liner the trench T2, such as... Figure 3 As shown, dielectric layer 160 extends from the top surface of dielectric layer 140 into trench T2 and contacts the substrate 102 exposed at the bottom of trench T2. The bottom surface of the portion of dielectric layer 160 that contacts substrate 102 may be lower than the top surface of substrate 102. The top surface of the portion of dielectric layer 160 that contacts substrate 102 may be lower than the top surface of compound semiconductor layer 104.

[0019] Next, a metal layer 170 is formed liner the dielectric layer 160. The metal layer 170 extends along the dielectric layer 160 into the trench T1. The metal layer 170 may be partially below the top surface of the compound semiconductor layer 104.

[0020] In some embodiments, after the metal layer 170 is formed, a third patterning process is performed to pattern the metal layer 170, thereby removing portions of the metal layer 170 located in the trench T2 and exposing the dielectric layer 160 located in the trench T2. In some embodiments, multiple portions of the metal layer 170 adjacent to the trench T2 and located above the dielectric layer 140 are also removed by the third patterning process, such as... Figure 3 As shown in the image.

[0021] Next, a dielectric layer 180 is formed covering the dielectric layer 160 and the metal layer 170. The dielectric layer 180 partially contacts the dielectric layer 160. Next, the dielectric layer 180 is patterned to form openings OP1, OP2, and OP3. Openings OP1 and OP2 expose the top surfaces of the metal layers 150 and 170, respectively. Opening OP3 is located at the bottom of the trench T2 and exposes the substrate 102.

[0022] Next, please refer to Figure 4 The trench T2 is used as a scribe line to cut and separate the die containing semiconductor elements through the trench T2. For example, a cutting process is performed using a blade C along the opening OP3 at the bottom of the trench T2 to cut the processed substrate structure into multiple dies. In other embodiments, cutting can be performed by laser or plasma etching.

[0023] After cutting, semiconductor element 10 is formed. For example... Figure 4As shown, the semiconductor element 10 includes a substrate structure 100, a metal interconnect structure located above the substrate structure 100, and multiple dielectric layers. The substrate structure 100 includes a substrate 102 and a compound semiconductor layer 104 located above the substrate 102. The metal interconnect structure includes a through-hole 120, a metal layer 130, and a metal layer 150. The metal layer 130 serves as the first metal interconnect line of the metal interconnect structure. The metal layer 150 serves as the top metal interconnect line of the metal interconnect structure. The structural features of each layer are the same as described above and will not be repeated here.

[0024] like Figure 4 As shown, the semiconductor device 10 further includes a dielectric layer 160, a metal layer 170, and a dielectric layer 180 above the metal interconnect structure. The dielectric layer 160 is located above, lining, and in contact with the metal layer 150. The metal layer 170 is lining and in contact with the dielectric layer 160. The dielectric layer 180 is located above the metal layer 170 and has openings OP1 and OP2 that expose the top surfaces of the metal layers 150 and 170, respectively.

[0025] In this configuration, the metal layer 150 of the metal interconnect structure, together with the overlying dielectric layer 160 and metal layer 170, can form a deep trench metal-insulator-metal (MIM) capacitor in trench T1. Metal layer 150 serves as the lower electrode, and metal layer 170 serves as the upper electrode. The lower and upper electrodes are electrically insulated from each other by dielectric layer 160. By forming a deep trench capacitor, the contact area between the lower and upper electrodes and dielectric layer 160 can be increased, thereby improving the capacitance and capacitance density. In some embodiments, metal layers 150 and 170 may include conductive materials, such as titanium nitride (TiN), aluminum, copper, or other suitable conductive materials. Dielectric layer 160 may include a high-k dielectric material, such as silicon oxide (SiO2), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O3), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or other suitable dielectric materials.

[0026] The manufacturing method of this invention allows for the simultaneous formation of a trench T1, which can be used to form a deep trench capacitor, during the subsequent process of forming a trench T2 or through-via that can be used as a dicing path through the compound semiconductor layer 104. In other words, trench T1 and trench T2 are formed simultaneously using the same photomask. Furthermore, the top metal interconnect of the metal interconnect structure can be used as the lower electrode of the deep trench capacitor. Thus, compared to current common processes that require the use of two additional photomasks to form trench T1 and a patterned lower electrode metal layer after completing the metal interconnect structure and forming trench T2, the manufacturing method of this invention simplifies the process and improves process efficiency.

[0027] Please refer to Figure 5 This is a partial top view of an intermediate stage in a method for manufacturing a semiconductor element according to some embodiments of the present invention. The trench distribution formed after performing the first patterning process is shown in the figure. In some embodiments, the top view profile of the trenches can be rectangular. For example, the top view profile of trench T1 is rectangular, wherein the side lengths S1 and S2 of trench T1 can each be 10 micrometers, and the spacing D1 between trench T1 and adjacent trenches can be 10 micrometers. The trench T1 height is 15 micrometers and the thickness of the dielectric layer 160 is... In this case, the deep trench MIM capacitor formed by metal layer 150, dielectric layer 160, and metal layer 170 can have a capacitance of 1.44 fF / μm. 2 The capacitance density value is 2.5 times that of a planar MIM capacitor. In some embodiments, the trench T2 ( Figure 5 The side length of the trench (not shown) may differ from the side lengths S1 and S2 of the trench T1. For example, the side length of the trench T2 may be between 70 micrometers and 100 micrometers. In some embodiments, the top view profile of the trench may be circular, elliptical, hexagonal, or polygonal, but is not limited thereto.

[0028] In some implementations, other metal interconnects in the metal interconnect structure can be used as the lower and / or upper electrodes of the deep trench capacitor. For example, please refer to... Figure 6 This is a partial top view of a semiconductor element 20 according to other embodiments of the present invention. The difference between semiconductor element 20 and semiconductor element 10 is that semiconductor element 20 uses the first metal interconnect of the metal interconnect structure as the lower electrode of the deep trench capacitor and the top metal interconnect of the metal interconnect structure as the upper electrode. Specifically, the first metal interconnect of semiconductor element 20 is... Figure 6 The metal layer 230 has a top metal interconnect called metal layer 250. Metal layer 230 has portions 230a and 230b. Portion 230a is located above dielectric layer 110 and connected to via 120. Portion 230b is located on one side of transistor TR and extends downward from above dielectric layer 110 through dielectric layer 110 and compound semiconductor layer 104, contacting substrate 102. Dielectric layer 240 covers metal layer 230 and clads portion 230b. Metal layer 250 clads dielectric layer 240. Thus, portion 230b of metal layer 230, dielectric layer 240, and metal layer 250 form a deep trench capacitor. Notably, the portion 230b of metal layer 230 contacting the bottom surface of substrate 102 may be lower than the top surface of substrate 102. Metal layer 250 may be completely higher than the top surface of compound semiconductor layer 104. In addition, the dielectric layer 280 covers the metal layer 250 and has an opening OP1 to expose a portion of the metal layer 250.

[0029] In the manufacturing method of semiconductor element 20, before forming metal layer 230, a first patterning process is performed to form a trench (corresponding to trench T1 of semiconductor element 10) passing through dielectric layer 110 and compound semiconductor layer 104, exposing substrate 102. Next, metal layer 230 is formed over dielectric layer 110 and extends into the trench, such that portion 230a of metal layer 230 connects to via 120, and portion 230b of metal layer 230 liner the trench and contacts substrate 102. Then, dielectric layer 240, metal layer 250, and dielectric layer 280 are sequentially formed liner the metal layer 230. In some embodiments, the first patterning process may simultaneously form trenches serving as dicing paths (corresponding to trench T2 of semiconductor element 10).

[0030] Please refer to Figure 7 This is a partial cross-sectional view of a semiconductor element 30 according to further embodiments of the present invention. The difference between semiconductor element 30 and semiconductor element 20 is that semiconductor element 30 further includes a dielectric layer 260 and a metal layer 270. The dielectric layer 260 is located above and clad against the metal layer 250. The metal layer 270 is located above and clad against the dielectric layer 260. The dielectric layer 280 is located above the metal layer 270 and has openings OP1 and OP2 exposing the metal layers 250 and 270, respectively. In this way, portion 230a of the metal layer 230, the dielectric layer 240, the metal layer 250, the dielectric layer 260, and the metal layer 270 form a deep trench capacitor to further increase capacitance density. Furthermore, as... Figure 7 As shown, metal layer 250, dielectric layer 260, and metal layer 270 can be completely above the top surface of compound semiconductor layer 104. The method of manufacturing semiconductor device 20 further includes forming dielectric layer 260 over transistor TR and trench and lining metal layer 250, forming metal layer 270 over trench and lining dielectric layer 260, and forming dielectric layer 280 covering dielectric layer 260 and metal layer 270 and having openings OP1 and OP2.

[0031] In summary, in some embodiments of the semiconductor device and its manufacturing method of the present invention, trenches for forming deep trench capacitors can be formed simultaneously when forming trenches used as dicing paths, thereby improving capacitance and capacitance density. Furthermore, metal interconnects of the metal interconnect structure can be used as the lower and / or upper electrodes of the deep trench capacitor. In this way, compared to current common processes, the photomask for forming the deep trench and the lower and / or upper electrodes of the capacitor can be eliminated, further simplifying the process and improving process efficiency.

[0032] [Symbol Explanation]

[0033] 10, 20, 30: Semiconductor components

[0034] 100: Substrate Structure

[0035] 102: Substrate

[0036] 104: Compound semiconductor layer

[0037] 110, 140, 160, 180, 240, 260, 280: Dielectric layer

[0038] 120: piercing

[0039] 130, 150, 170, 230, 250, 270: Metal layer

[0040] 150a: Horizontal part

[0041] 230a, 230b: Location

[0042] C: Blade

[0043] D1: Spacing

[0044] G: Gate contact

[0045] H: Height

[0046] OP1, OP2, OP3: Openings

[0047] S / D: Source / Drain Contact

[0048] S1, S2: Side lengths

[0049] T1, T2: Trench

[0050] TR: Transistor.

Claims

1. A method of manufacturing a semiconductor element, characterized by, Comprising: performing a first patterning process to form a first trench in a substrate structure, wherein the substrate structure comprises a substrate and a compound semiconductor layer over the substrate, the first trench passing through the compound semiconductor layer and exposing the substrate; and forming a capacitor structure in the first trench, wherein forming the capacitor structure comprises: forming a first metal layer lining the first trench and contacting the substrate; forming a first dielectric layer lining the first metal layer and contacting the first metal layer; and forming a second metal layer lining the first dielectric layer and contacting the first dielectric layer. The substrate structure has a transistor, and forming the first metal layer is such that the first metal layer extends from over the transistor along the first trench to a side of the transistor. Forming the first metal layer is such that the first metal layer has a portion electrically connected to a source / drain contact of the transistor through a via.

2. The production method according to claim 1, characterized by Forming the capacitor structure further comprises:

3. The production method according to claim 2, characterized by forming a second dielectric layer lining the second metal layer and contacting the second metal layer; and 4. The production method according to claim 3, characterized by forming a third metal layer lining the second dielectric layer and contacting the second dielectric layer. The second metal layer is partially below a top surface of the compound semiconductor layer.

6. The manufacturing method of claim 1, wherein:

5. The production method according to claim 1, characterized by the first patterning process further comprises forming a second trench in the substrate structure and exposing the substrate; forming the capacitor structure further comprises: forming the first metal layer such that the first metal layer lines the second trench; and after forming the first metal layer, performing a second patterning process on the first metal layer to remove the first metal layer in the second trench to again expose the substrate through the second trench; and the manufacturing method further comprises performing a cutting process through the second trench. Comprising: a substrate structure comprising a substrate and a compound semiconductor layer over the substrate; and a capacitor structure over the substrate structure and comprising: a first metal layer having a portion extending downward through the compound semiconductor layer and contacting the substrate; 7. A semiconductor element characterized by comprising: a first dielectric layer over the first metal layer and lining the portion of the first metal layer; and a second metal layer over the portion of the first metal layer and over the first dielectric layer and lining the first dielectric layer. The substrate structure has a transistor, and the first metal layer has another portion over the transistor and electrically connected to a source / drain contact of the transistor through a via. further comprising a second dielectric layer over the second metal layer and lining the second metal layer, and a third metal layer over the second dielectric layer and lining the second dielectric layer. The second metal layer is partially below a top surface of the compound semiconductor layer. ​ ​ 8. The semiconductor device according to claim 7, wherein ​ 9. The semiconductor element according to claim 7 or 8, characterized by, ​ 10. The semiconductor device according to claim 7 or 8, wherein ​

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