Manufacturing method of direct cooling substrate-free power module

Abstract

The invention provides a manufacturing method of a direct cooling substrate-free power module, and belongs to the technical field of power module manufacturing. A matrix type flow channel structure is processed in a copper-based cooling plate, and hydrophilic modification treatment is carried out; in the silver sintering process, an ultrasonic transmitter is adopted to scan an interface, and the sintering pressure and the sintering temperature are adjusted in real time according to acoustic resonance spectrum characteristic values. An interface thermal stress rapid prediction model is constructed through intrinsic orthogonal decomposition and a neural network agent model, the thickness ratio of a silver sintering layer to a direct copper-clad ceramic layer is adjusted according to interface shear stress distribution, and the interval of a matrix type flow channel structure is adjusted according to the junction temperature of a power chip. The power chip is fixed on the direct copper-clad ceramic layer through the silver sintering layer and then attached to the surface of the copper-based cooling plate through the heat-conducting medium layer to form a direct heat conduction path, and the technical problem that the heat dissipation efficiency is insufficient due to the fact that the heat conduction path of the power module is too long is solved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of power module manufacturing, and in particular, relates to a manufacturing method of a directly-cooled substrate-free power module. BACKGROUND

[0002] Power modules bear the function of power conversion in power electronic systems, and a large amount of heat is generated during the operation of power chips, which needs to be dissipated in time to ensure reliable operation. The traditional power module adopts a multi-layer structure in which the power chip is welded on a directly-coated-copper ceramic substrate, the ceramic substrate is then fixed on a copper bottom plate through a solder layer, and finally the heat is dissipated through an independent cooling plate. In the current high-power-density application scenarios, since the traditional structure contains multiple heat conduction links such as chip silicon layer, solder layer, ceramic substrate, bottom plate solder layer, copper bottom plate, thermal interface material layer, and cooling plate, and there is a contact thermal resistance at each interface, the cumulative total thermal resistance leads to excessively high junction temperature of the power chip, which limits the power density improvement space. At the same time, the mismatch of the thermal expansion coefficients between the multiple heterogeneous materials generates interface thermal stress under temperature cycling conditions, accelerates the fatigue failure of the solder layer, and reduces the reliability of the power module. That is, there is a technical problem of insufficient heat dissipation efficiency caused by a long heat conduction path of the power module in the prior art. SUMMARY

[0003] Therefore, the present application provides a manufacturing method of a directly-cooled substrate-free power module, which can solve the technical problem of insufficient heat dissipation efficiency caused by a long heat conduction path of the power module in the prior art.

[0004] The present application is implemented in the following manner: The present application provides a manufacturing method of a directly-cooled substrate-free power module, which includes preparing an embedded micro-channel cooling plate, processing a matrix flow channel structure inside the copper-based cooling plate, and performing hydrophilic modification treatment on the surface of the matrix flow channel structure; performing online detection of silver sintering interface voids, coating nano-silver paste on the surface of the copper-based cooling plate after placing the power chip, scanning the nano-silver paste interface through an ultrasonic transmitter, collecting time-domain signals of reflected waves and calculating acoustic resonance spectral characteristic values; adjusting sintering process parameters in real time according to the acoustic resonance spectral characteristic values; constructing an interface thermal stress rapid prediction model, performing reduced-order modeling on the thickness ratio of the chip silicon layer, the silver sintering layer, the directly-coated-copper ceramic layer, and the thermal conductive medium layer, extracting the main modal of the temperature field through proper orthogonal decomposition and training a neural network proxy model to calculate the interface shear stress distribution; adjusting the material thickness ratio according to the interface shear stress distribution; performing micro-channel flow heat transfer multi-scale simulation optimization; and completing the manufacturing of the directly-cooled substrate-free power module.

[0005] Specifically, the matrix flow channel structure is processed by processing a matrix flow channel structure with a width of 0.5 mm and a depth of 0.8 mm inside the copper-based cooling plate, and the flow channel spacing is 1.2 mm.

[0006] The acoustic resonance spectrum characteristic value refers to the frequency domain amplitude distribution of the reflected wave time domain signal of the ultrasonic wave generated at the multilayer interface of the silver sintering layer after fast Fourier transform.

[0007] The acoustic resonance spectrum characteristic value and the corresponding relationship of the porosity are established through a calibration experiment, a silver sintering sample with a known porosity is prepared in the calibration experiment, the acoustic resonance spectrum characteristic value of the silver sintering sample is measured, and a linear relationship equation is obtained by least square fitting.

[0008] The step of adjusting the sintering process parameters in real time according to the acoustic resonance spectrum characteristic value is specifically that when the porosity corresponding to the acoustic resonance spectrum characteristic value exceeds 0.5%, the sintering pressure is increased from 10 MPa to 15 MPa and the holding pressure time is extended by 5 minutes, and at the same time, the sintering temperature is adjusted from 240 degrees Celsius to 260 degrees Celsius.

[0009] The intrinsic orthogonal decomposition is a reduced-order modeling technique, which extracts the temperature field mode with the largest contribution rate as the basis function by singular value decomposition of a large number of finite element simulation results in the temperature cycle process.

[0010] The neural network proxy model adopts a three-layer hidden layer structure, the input layer includes the thickness of the chip silicon layer, the thickness of the silver sintering layer, the thickness of the direct copper clad ceramic layer, the thickness of the thermal conductive medium layer, the thickness of the copper-based cooling plate, and the thermal expansion coefficient and elastic modulus of the corresponding materials, and the output layer is the peak value and peak position coordinates of the interface shear stress distribution.

[0011] The step of adjusting the material thickness ratio according to the interface shear stress distribution is specifically that when the peak value of the interface shear stress distribution exceeds 150 MPa, the thickness of the silver sintering layer is increased from 50 microns to 80 microns, and the thickness of the direct copper clad ceramic layer is adjusted from 0.38 mm to 0.32 mm.

[0012] The material thickness ratio is obtained by iterative optimization of the neural network proxy model, and the peak value of the interface shear stress distribution is minimized as the objective function in the iterative optimization process, and a genetic algorithm is used to search for the optimal material thickness ratio.

[0013] The step of performing micro-channel flow heat transfer multi-scale simulation optimization is specifically that a fine grid precision of 0.05 mm is used in the hot spot area of the power chip, and a coarse grid precision of 0.2 mm is used in the peripheral area of the power chip, and a temperature field distribution is calculated by a thermal conduction path adaptive reconstruction algorithm.

[0014] The thermal conduction path adaptive reconstruction algorithm equivalent three-dimensional heat conduction problem to resistance network, and uses an improved Dijkstra algorithm to search for the minimum thermal resistance path from the heat source to the cooling liquid.

[0015] Wherein, in the micro-channel flow heat transfer multi-scale simulation optimization step, the matrix flow channel structure spacing is reduced from 1.2mm to 0.8mm when the power chip junction temperature exceeds 125 degrees Celsius.

[0016] Wherein, the hydrophilic modification treatment is to form a micro-nano rough structure on the surface of the matrix flow channel structure through plasma etching or chemical oxidation, so that the contact angle of the surface of the matrix flow channel structure is reduced from 90 degrees to below 20 degrees.

[0017] Wherein, the nano-silver paste is a paste formed by dispersing silver particles with a particle size range of 50-100nm in an organic solvent, and after the organic solvent is volatilized in the sintering process, the silver particles undergo solid-phase diffusion under the action of sintering temperature and sintering pressure.

[0018] Wherein, the step of completing the manufacturing of the direct cooling substrate-free power module is specifically to fix the power chip on the direct copper clad ceramic layer through the silver sintering layer, and to adhere the direct copper clad ceramic layer to the surface of the copper-based cooling plate through the heat-conducting medium layer, forming a direct heat conduction path from the chip to the cooling liquid.

[0019] Wherein, the direct copper clad ceramic layer is a direct copper clad ceramic substrate, which is bonded by eutectic reaction of aluminum oxide ceramic or aluminum nitride ceramic and copper layer at high temperature.

[0020] The present application fixes the power chip directly on the direct copper clad ceramic layer through the silver sintering layer, and then adheres the copper-based cooling plate with embedded micro-channels to the surface of the copper-based cooling plate through the heat-conducting medium layer, thereby omitting the bottom solder layer and independent cooling plate in the traditional structure, so that heat is directly transmitted from the power chip to the cooling liquid through the silver sintering layer, the direct copper clad ceramic layer and the heat-conducting medium layer, thereby shortening the heat conduction path and reducing the total thermal resistance. The present application introduces ultrasonic interface cavity online detection technology in the silver sintering process, adjusts the sintering pressure and sintering temperature in real time according to the acoustic resonance spectrum characteristic value, controls the cavity ratio at a low level, and improves the thermal conductivity of the silver sintering layer. The present application quickly predicts the interface thermal stress distribution through intrinsic orthogonal decomposition reduction modeling and neural network proxy modeling, optimizes the material thickness ratio to reduce the peak value of the interface shear stress, and alleviates the fatigue failure caused by thermal expansion mismatch. In summary, the present application solves the technical problem of insufficient heat dissipation efficiency caused by the long heat conduction path of the power module in the background art. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 The flowchart of the method of the present application.

[0022] Figure 2 The acoustic resonance spectrum characteristic value distribution graph for different scanning positions.

[0023] Figure 3 The loss function convergence curve graph of the neural network proxy model training process.

[0024] Figure 4 The interface shear stress peak trend graph in the genetic algorithm optimization process.

[0025] Figure 5 The power chip temperature field distribution three-dimensional cloud chart. DETAILED DESCRIPTION

[0026] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application are described clearly and completely below.

[0027] As Figure 1 shown, it is a flow chart of a manufacturing method of a direct cooling substrateless power module provided by the present application, and the method comprises the following steps:

[0028] S01, preparing an embedded micro-channel cooling plate, processing a matrix flow channel structure with a width of 0.5 mm and a depth of 0.8 mm in the copper-based cooling plate, the flow channel spacing is 1.2 mm, and the surface of the matrix flow channel structure is subjected to hydrophilic modification treatment;

[0029] S02, performing online detection of silver sintering interface cavities, placing a power chip after coating nano-silver paste on the surface of the copper-based cooling plate, scanning the nano-silver paste interface by an ultrasonic transmitter at a frequency of 5 MHz, collecting time domain signals of reflected waves and calculating acoustic resonance spectrum characteristic values;

[0030] S03, adjusting the sintering process parameters in real time according to the acoustic resonance spectrum characteristic values, when the cavity rate corresponding to the acoustic resonance spectrum characteristic values exceeds 0.5%, the sintering pressure is increased from the initial sintering pressure 10 MPa to the adjusted sintering pressure 15 MPa and the pressure holding time is extended by 5 minutes, and at the same time, the sintering temperature is adjusted from the initial sintering temperature 240 DEG C to the adjusted sintering temperature 260 DEG C;

[0031] S04, constructing an interface thermal stress rapid prediction model, performing reduced-order modeling on the thickness ratio of the chip silicon layer, the silver sintering layer, the DBC ceramic layer and the heat-conducting medium layer, extracting the temperature field main mode by intrinsic orthogonal decomposition and training a neural network proxy model, and calculating the interface shear stress distribution output by the interface thermal stress rapid prediction model;

[0032] S05, when the peak value of the interface shear stress distribution exceeds the stress threshold value 150 MPa, adjusting the material thickness ratio, increasing the silver sintering layer thickness from the initial silver sintering layer thickness 50 μm to the adjusted silver sintering layer thickness 80 μm, adjusting the DBC ceramic layer thickness from the initial DBC ceramic layer thickness 0.38 mm to the adjusted DBC ceramic layer thickness 0.32 mm, so that the peak value of the interface shear stress distribution is reduced to below 120 MPa;

[0033] S06, performing micro-channel flow heat transfer multi-scale simulation optimization, using fine grid precision 0.05mm in the power chip hotspot area, using coarse grid precision 0.2mm in the power chip peripheral area, calculating the temperature field distribution through the self-adaptive reconstruction algorithm of heat conduction path, when the power chip junction temperature exceeds the junction temperature threshold 125℃, reducing the matrix flow channel structure spacing from the initial flow channel spacing 1.2mm to the adjusted flow channel spacing 0.8mm;

[0034] S07, completing the manufacturing of the direct cooling substrateless power module, fixing the power chip on the DBC ceramic layer through the silver sintering layer, adhering the DBC ceramic layer to the surface of the copper-based cooling plate through the heat-conducting medium layer, forming a direct heat conduction path from the chip to the cooling liquid.

[0035] The acoustic resonance spectrum characteristic value is the frequency domain amplitude distribution of the reflected wave time domain signal of the ultrasonic wave generated at the multi-layer interface of the silver sintering layer after fast Fourier transform, and the position and size of the interface cavity are determined by identifying the attenuation coefficient in the frequency range of 3MHz to 7MHz in the frequency domain amplitude distribution. The larger the attenuation coefficient, the higher the cavity rate at the position. The corresponding relationship between the acoustic resonance spectrum characteristic value and the cavity rate is established through calibration experiments. In the calibration experiment, 10 groups of silver sintering samples with known cavity rate range of 0.1% to 5% are prepared, the acoustic resonance spectrum characteristic values of the 10 groups of silver sintering samples are measured, and the linear relationship equation between the acoustic resonance spectrum characteristic value and the cavity rate is obtained by using the least square method.

[0036] The initial sintering pressure 10MPa, the adjusted sintering pressure 15MPa, the initial sintering temperature 240℃, and the adjusted sintering temperature 260℃ are determined through sintering process optimization experiments. In the sintering process optimization experiment, the sintering pressure range is set to 5MPa to 25MPa, and the sintering temperature range is set to 220℃ to 300℃. 30 groups of nano-silver sintering samples with different sintering pressure and sintering temperature combinations are prepared, the cavity rate and shear strength of the 30 groups of nano-silver sintering samples are measured, the sintering pressure and sintering temperature with cavity rate lower than 0.5% and shear strength higher than 40MPa are selected as the initial sintering pressure and initial sintering temperature, and the sintering pressure and sintering temperature with cavity rate lower than 0.3% and shear strength higher than 50MPa are selected as the adjusted sintering pressure and adjusted sintering temperature.

[0037] Wherein, the proper orthogonal decomposition is a reduced order modeling technique, by singular value decomposition of a large number of finite element simulation results in the temperature cycle process, the top 8 temperature field modes with the largest contribution rate are extracted as the basis function, and the temperature field distribution under any working condition is expressed as the linear combination of the 8 temperature field modes, thereby simplifying the partial differential equation with hundreds of thousands of degrees of freedom into an algebraic equation with 8 coefficients, the implementation process of the proper orthogonal decomposition is to perform singular value decomposition on the temperature field data matrix of 100 groups of temperature cycle finite element simulation, and the singular vectors corresponding to the top 8 singular values with a cumulative contribution rate of 99% are selected as the main modes of the temperature field.

[0038] Wherein, the neural network surrogate model adopts a 3-layer hidden layer structure, the input layer includes 15 input parameters of chip silicon layer thickness, chip silicon layer thermal expansion coefficient, chip silicon layer elastic modulus, silver sintering layer thickness, silver sintering layer thermal expansion coefficient, silver sintering layer elastic modulus, DBC ceramic layer thickness, DBC ceramic layer thermal expansion coefficient, DBC ceramic layer elastic modulus, heat conduction medium layer thickness, heat conduction medium layer thermal expansion coefficient, heat conduction medium layer elastic modulus, copper-based cooling plate thickness, copper-based cooling plate thermal expansion coefficient, copper-based cooling plate elastic modulus, and the output layer is the peak value and peak position coordinate of the interface shear stress distribution, the neural network surrogate model is trained by 1000 groups of finite element simulation data, the 1000 groups of finite element simulation data cover the thickness variation range, thermal expansion coefficient variation range and elastic modulus variation range of each material layer, and the peak value prediction error of the interface shear stress distribution is controlled within 5% after training, and the single prediction time is 0.3 seconds.

[0039] Wherein, the stress threshold 150MPa is determined by a fatigue life experiment, 15 groups of power module samples with different material thickness ratios are prepared in the fatigue life experiment, and the samples are subjected to accelerated aging test under the temperature cycle condition of-40℃ to 150℃, the peak value of the interface shear stress distribution of the 15 groups of power module samples and the failure cycle number are recorded, and the peak value of the interface shear stress distribution corresponding to the failure cycle number of 5000 times is selected as the stress threshold 150MPa.

[0040] Wherein, the initial silver sintering layer thickness 50μm, the adjusted silver sintering layer thickness 80μm, the initial DBC ceramic layer thickness 0.38mm and the adjusted DBC ceramic layer thickness 0.32mm are obtained by iterative optimization of the neural network surrogate model, in the iterative optimization process, the minimization of the peak value of the interface shear stress distribution is taken as the objective function, the silver sintering layer thickness range 30μm to 100μm and the DBC ceramic layer thickness range 0.25mm to 0.50mm are taken as the constraint conditions, the genetic algorithm is used to search for the optimal material thickness ratio, the population size of the genetic algorithm is set to 50, and the iteration number is set to 100 generations.

[0041] Wherein, the heat conduction path adaptive reconstruction algorithm equivalent three-dimensional heat conduction problem to resistance network, the thermal resistance between copper base cooling plate and power chip is resistance network branch resistance, the heat flow is resistance network branch current, the improved Dijkstra algorithm is used to search the minimum thermal resistance path from heat source to cooling liquid, when the local temperature exceeds the local temperature threshold 115℃, the grid density is refined in the area where the local temperature exceeds the local temperature threshold 115℃ and the thermal resistance distribution is recalculated, the full field temperature distribution is obtained by sparse matrix fast solution technique, the heat conduction path adaptive reconstruction algorithm supports real-time calculation of 200 million nodes.

[0042] Wherein, the junction temperature threshold 125℃ is the highest allowable operating temperature of power chip, which is specified by the data manual provided by the power chip manufacturer, when the power chip junction temperature exceeds the junction temperature threshold 125℃, the power chip performance decay accelerates and the failure risk increases.

[0043] Wherein, the initial flow channel spacing 1.2mm and the adjusted flow channel spacing 0.8mm are determined by micro-channel heat transfer performance experiment, in the micro-channel heat transfer performance experiment, 8 groups of copper base cooling plates with matrix flow channel structure spacing range of 0.6mm to 2.0mm are prepared, the heat transfer coefficient and pressure drop of the 8 groups of copper base cooling plates are measured under the condition of cooling liquid flow rate 5L / min, the flow channel spacing with heat transfer coefficient higher than 8000 and pressure drop lower than 30kPa is selected as the initial flow channel spacing 1.2mm, the flow channel spacing with heat transfer coefficient higher than 12000 and pressure drop lower than 50kPa is selected as the adjusted flow channel spacing 0.8mm.

[0044] Wherein, the nano-silver paste is a paste formed by dispersing silver particles with particle size range of 50nm to 100nm in organic solvent, during sintering process, the organic solvent volatilizes, the silver particles undergo solid phase diffusion under the action of sintering temperature and sintering pressure, the interface between silver particles disappears to form a continuous silver sintered layer, the silver sintered layer has high thermal conductivity and high temperature stability.

[0045] Wherein, the hydrophilic modification treatment is to form micro-nano rough structure on the surface of matrix flow channel structure through plasma etching or chemical oxidation, so that the contact angle of the surface of matrix flow channel structure is reduced from 90 degrees to below 20 degrees, the wettability and flow stability of cooling liquid in the matrix flow channel structure are enhanced, and the heat transfer deterioration caused by bubble retention is prevented.

[0046] Wherein, the DBC ceramic layer is a direct copper clad ceramic substrate, which is bonded by eutectic reaction between aluminum oxide ceramic or aluminum nitride ceramic and copper layer at high temperature, the DBC ceramic layer provides electrical insulation function and buffers the thermal expansion mismatch between chip silicon layer and metal layer.

[0047] The direct cooling substrate-free power module structure is to fix the power chip on the DBC ceramic layer through the silver sintering layer, and the DBC ceramic layer is attached to the surface of the copper-based cooling plate through the heat-conducting medium layer, so that the solder layer between the DBC ceramic substrate and the copper bottom plate and the independent cooling plate in the traditional structure are omitted, heat is directly transmitted from the power chip to the cooling liquid through the silver sintering layer, the DBC ceramic layer, the heat-conducting medium layer, the heat conduction path is shortened, and the total thermal resistance is reduced.

[0048] The direct cooling substrate-free power module obtained by the method has the following specific structure: a copper-based cooling plate, the inside of the copper-based cooling plate is provided with a matrix flow channel structure, the width of the matrix flow channel structure is 0.5 mm, the depth is 0.8 mm, the flow channel spacing is 0.8 mm to 1.2 mm, and the surface of the matrix flow channel structure is subjected to hydrophilic modification treatment; a DBC ceramic layer, the DBC ceramic layer is attached to the surface of the copper-based cooling plate through a heat-conducting medium layer, and the thickness of the DBC ceramic layer is 0.32 mm to 0.38 mm; a silver sintering layer, the silver sintering layer is arranged on the upper surface of the DBC ceramic layer, the thickness of the silver sintering layer is 50 μm to 80 μm, and the void rate of the silver sintering layer is less than 0.5%; and a power chip, the power chip is fixed on the DBC ceramic layer through the silver sintering layer, and the power chip is a chip silicon layer structure.

[0049] The matrix flow channel structure is a matrix-arranged flow channel formed in the inside of the copper-based cooling plate, and is used for cooling liquid flow and taking away the heat generated by the power chip.

[0050] The hydrophilic modification treatment is to form a micro-nano rough structure on the surface of the matrix flow channel structure through plasma etching or chemical oxidation, so that the contact angle of the surface of the matrix flow channel structure is reduced from 90 degrees to 20 degrees or below, the wettability and flow stability of the cooling liquid in the matrix flow channel structure are enhanced, and the heat transfer deterioration caused by bubble retention is prevented.

[0051] The DBC ceramic layer is a direct copper clad ceramic substrate, which is bonded by eutectic reaction between aluminum oxide ceramic or aluminum nitride ceramic and copper layer at high temperature, and provides electrical insulation function and buffers the thermal expansion mismatch between the chip silicon layer and the metal layer.

[0052] The heat-conducting medium layer is a thermal interface material layer, the thickness of the heat-conducting medium layer is 0.05 mm to 0.20 mm, and the heat-conducting medium layer is used to fill the interface gap between the DBC ceramic layer and the copper-based cooling plate and provide a heat conduction channel.

[0053] The silver sintering layer is a continuous metal layer formed by sintering process of nano-silver particles, has high thermal conductivity and high temperature stability, and has a thermal conductivity of 200 to 300 .

[0054] The power chip is a semiconductor power device, and the power chip includes an IGBT chip, a MOSFET chip or a diode chip, and the chip silicon layer thickness of the power chip is 0.15 mm to 0.30 mm.

[0055] The thermal conduction path of the direct cooling substrate-free power module is that the heat generated by the power chip is sequentially transmitted to the copper-based cooling plate through the silver sintering layer, the DBC ceramic layer and the thermal conductive medium layer, and finally taken away by the cooling liquid in the matrix flow channel structure, thereby omitting the solder layer between the DBC ceramic substrate and the copper base plate and the independent cooling plate in the traditional structure, shortening the thermal conduction path and reducing the total thermal resistance.

[0056] The copper-based cooling plate has a thickness of 2 mm to 5 mm, a thermal conductivity of 380 to 400 , and a thermal expansion coefficient of 17 ppm / K.

[0057] The thermal expansion coefficient of the chip silicon layer is 2.6 ppm / K, the thermal expansion coefficient of the silver sintering layer is 19 ppm / K, the thermal expansion coefficient of the ceramic part in the DBC ceramic layer is 6 ppm / K to 8 ppm / K, and the thermal expansion coefficient mismatch between the power chip, the silver sintering layer, the DBC ceramic layer, the thermal conductive medium layer and the copper-based cooling plate is controlled to be below 120 MPa by optimizing the material thickness ratio to control the interface shear stress distribution peak.

[0058] The specific implementation of the above steps is described in detail below.

[0059] The specific implementation of step S01 is to first select high-purity copper material as the cooling plate base material, adopt precise numerical control milling processing technology to form a matrix flow channel structure in the length direction and width direction inside the copper-based cooling plate alternately, control the cross-sectional size of a single flow channel through a micro-milling cutter during the processing, the flow channel width is set to 0.5 mm, the flow channel depth is set to 0.8 mm, the spacing between adjacent flow channels is set to 1.2 mm, and the arrangement mode of the matrix flow channel structure adopts an orthogonal grid layout to realize uniform distribution and efficient heat exchange of the cooling liquid. After the processing, the surface of the matrix flow channel structure is subjected to hydrophilic modification treatment, which forms a micro-nano rough structure on the inner wall of the flow channel through plasma etching or chemical oxidation method, so that the surface contact angle is reduced from the initial 90 degrees to below 20 degrees. The purpose of the hydrophilic modification treatment is to enhance the wettability and flow stability of the cooling liquid in the flow channel, prevent bubbles from being retained in the flow channel to cause local heat transfer deterioration, and thus improve the overall cooling efficiency.

[0060] The specific implementation of step S02 is to first uniformly coat the nano-silver paste on the surface of the copper-based cooling plate, the nano-silver paste is formed by dispersing silver particles with a particle size range of 50 nm to 100 nm in an organic solvent, and the coating thickness is controlled at about 50 μm to ensure the thickness uniformity of the subsequent sintered layer. Then, the power chip is accurately placed on the position coated with the nano-silver paste, an ultrasonic wave signal with a frequency of 5 MHz is emitted to the silver paste interface through an ultrasonic transmitter, the ultrasonic wave is reflected at the multi-layer interface of the silver paste, the time domain signal of the reflected wave is collected and converted into a frequency domain amplitude distribution through fast Fourier transform. The calculation principle of the acoustic resonance spectrum characteristic value is to use the reflection characteristics of ultrasonic waves at different acoustic impedance interfaces. When there is a cavity at the interface, the frequency domain amplitude of the reflected wave appears attenuation in the frequency range of 3 MHz to 7 MHz, and the attenuation coefficient is directly related to the position and size of the cavity. The larger the attenuation coefficient, the higher the cavity rate at that position. The corresponding relationship between the acoustic resonance spectrum characteristic value and the cavity rate is established through calibration experiments. In the calibration experiment, 10 groups of silver sintered samples with known cavity rate range of 0.1% to 5% are prepared, the acoustic resonance spectrum characteristic value of each group of samples is measured, and the linear relationship equation between the acoustic resonance spectrum characteristic value and the cavity rate is obtained by least square fitting. The equation is used to inversely deduce the interface cavity rate according to the measured acoustic resonance spectrum characteristic value in the subsequent real-time monitoring process.

[0061] The specific implementation of step S03 is to determine the interface porosity in real time according to the acoustic resonance spectrum characteristic value calculated in step S02, and when the acoustic resonance spectrum characteristic value corresponds to a porosity of more than 0.5%, the adaptive adjustment mechanism of the sintering process parameters is started. The initial sintering pressure is increased from 10 MPa to 15 MPa in the sintering pressure adjustment process, and the increase of the sintering pressure can enhance the contact pressure between the nano-silver particles, promote the elimination of the interface between the silver particles in the solid phase diffusion process, and thus reduce the formation of the internal pores of the sintered layer. At the same time, the holding time is extended by 5 minutes, and the purpose of extending the holding time is to provide sufficient diffusion time for the silver particles, so that the silver particles form a more compact metallurgical bond. The initial sintering temperature is increased from 240℃ to 260℃ in the sintering temperature adjustment process, and the increase of the sintering temperature can accelerate the solid phase diffusion rate of the silver particles and improve the density and shear strength of the silver sintered layer. The reference values of the initial sintering pressure 10 MPa, the adjusted sintering pressure 15 MPa, the initial sintering temperature 240℃, and the adjusted sintering temperature 260℃ are determined through the sintering process optimization experiment. In the experiment, the sintering pressure range is set to 5 MPa to 25 MPa, the sintering temperature range is set to 220℃ to 300℃, and 30 groups of nano-silver sintered samples with different parameter combinations are prepared. The porosity and shear strength of each group of samples are measured, and the parameters with a porosity of less than 0.5% and a shear strength of more than 40 MPa are selected as the initial process parameters, and the parameters with a porosity of less than 0.3% and a shear strength of more than 50 MPa are selected as the adjusted process parameters.

[0062] The specific implementation of step S04 is to construct an interface thermal stress rapid prediction model, which adopts the reduced-order modeling technology combining proper orthogonal decomposition with a neural network surrogate model. The implementation process of proper orthogonal decomposition is to perform singular value decomposition on the temperature field data matrix of 100 groups of temperature cycle finite element simulation, select the first 8 singular vectors corresponding to the singular values with a cumulative contribution rate of 99% as the temperature field principal modes, and express the temperature field distribution under any working condition as a linear combination of the 8 temperature field principal modes, thereby simplifying the partial differential equation with tens of thousands of degrees of freedom into an algebraic equation with 8 coefficients. The neural network surrogate model adopts a 3-layer hidden layer structure, the input layer includes 15 input parameters including chip silicon layer thickness, chip silicon layer thermal expansion coefficient, chip silicon layer elastic modulus, silver sintering layer thickness, silver sintering layer thermal expansion coefficient, silver sintering layer elastic modulus, DBC ceramic layer thickness, DBC ceramic layer thermal expansion coefficient, DBC ceramic layer elastic modulus, heat conduction medium layer thickness, heat conduction medium layer thermal expansion coefficient, heat conduction medium layer elastic modulus, copper-based cooling plate thickness, copper-based cooling plate thermal expansion coefficient, and copper-based cooling plate elastic modulus, and the output layer is the peak value and peak position coordinate of the interface shear stress distribution. The neural network surrogate model is trained by 1000 groups of finite element simulation data, and after the training is completed, the peak value prediction error of the interface shear stress distribution is controlled within 5%, and the single prediction time is 0.3 seconds. After the interface shear stress distribution is calculated, the peak position and size are analyzed, which provides a quantitative basis for subsequent material thickness ratio optimization.

[0063] The specific implementation of step S05 is to optimize and adjust the material thickness ratio according to the peak value of the interfacial shear stress distribution output by the interfacial thermal stress rapid prediction model in step S04. When the peak value of the interfacial shear stress distribution exceeds the stress threshold 150 MPa, the material thickness adjustment mechanism is started. The reference value of the stress threshold 150 MPa is determined through fatigue life experiments. In the experiments, 15 groups of power module samples with different material thickness ratios are prepared, and accelerated aging tests are carried out under temperature cycling conditions of -40°C to 150°C. The peak value of the interfacial shear stress distribution and the failure cycle number of each group of samples are recorded. The peak value of the interfacial shear stress distribution corresponding to the failure cycle number of 5000 is selected as the stress threshold. In the material thickness adjustment process, the silver sintering layer thickness is increased from the initial silver sintering layer thickness of 50 μm to the adjusted silver sintering layer thickness of 80 μm. Increasing the silver sintering layer thickness can improve the flexibility of the interface and relieve the stress concentration caused by the thermal expansion mismatch between the chip silicon layer and the DBC ceramic layer. At the same time, the DBC ceramic layer thickness is adjusted from the initial DBC ceramic layer thickness of 0.38 mm to the adjusted DBC ceramic layer thickness of 0.32 mm. Reducing the DBC ceramic layer thickness can reduce the stiffness of the ceramic layer itself and reduce the stress transfer at the interface. The optimal material thickness ratio is obtained by iterative optimization of the neural network proxy model. In the iterative optimization process, the minimization of the peak value of the interfacial shear stress distribution is taken as the objective function, the silver sintering layer thickness range of 30 μm to 100 μm and the DBC ceramic layer thickness range of 0.25 mm to 0.50 mm are taken as the constraint conditions, the genetic algorithm is used to search for the optimal solution, the population size of the genetic algorithm is set to 50, the iteration number is set to 100 generations, and finally the peak value of the interfacial shear stress distribution is reduced to below 120 MPa.

[0064] The specific implementation of step S06 is to perform a micro-channel flow heat transfer multi-scale simulation optimization, and an adaptive mesh division strategy is adopted to use a fine grid precision of 0.05 mm in the hotspot area of the power chip and a coarse grid precision of 0.2 mm in the peripheral area of the power chip. The fine grid can accurately capture the temperature gradient change in the hotspot area, and the coarse grid can reduce the calculation amount on the premise of ensuring the calculation precision. The adaptive reconstruction algorithm of the heat conduction path equivalent three-dimensional heat conduction problem to a resistance network, the thermal resistance between the copper-based cooling plate and the power chip is the branch resistance of the resistance network, and the heat flow is the branch current of the resistance network. The improved Dijkstra algorithm is used to search for the minimum thermal resistance path from the heat source to the cooling liquid. When it is detected that the local temperature exceeds the local temperature threshold 115°C, the grid density in the area is refined and the thermal resistance distribution is recalculated, and the full-field temperature distribution is obtained by the sparse matrix fast solving technique. The algorithm supports real-time calculation of 2 million nodes. The junction temperature of the power chip is calculated and compared with the junction temperature threshold 125°C. The junction temperature threshold 125°C is the maximum allowable working temperature of the power chip. When the junction temperature of the power chip exceeds the junction temperature threshold 125°C, the performance of the power chip decays rapidly and the risk of failure increases. If the junction temperature of the power chip exceeds the junction temperature threshold, the matrix flow channel structure spacing is reduced from the initial flow channel spacing 1.2 mm to the adjusted flow channel spacing 0.8 mm. Reducing the flow channel spacing can increase the number of flow channels and the heat exchange area, improve the heat exchange coefficient between the cooling liquid and the copper-based cooling plate, and thus reduce the junction temperature of the power chip. The reference values of the initial flow channel spacing 1.2 mm and the adjusted flow channel spacing 0.8 mm are determined through a micro-channel heat transfer performance experiment. In the experiment, 8 groups of copper-based cooling plates with a matrix flow channel structure spacing ranging from 0.6 mm to 2.0 mm are prepared, the heat transfer coefficient and pressure drop of each group of copper-based cooling plates are measured under the condition of a cooling liquid flow rate of 5 L / min, and the flow channel spacing with a heat transfer coefficient higher than 8000 and a pressure drop lower than 30 kPa is selected as the initial flow channel spacing, and the flow channel spacing with a heat transfer coefficient higher than 12000 and a pressure drop lower than 50 kPa is selected as the adjusted flow channel spacing.

[0065] The specific implementation of step S07 is to complete the manufacturing of the direct cooling substrateless power module, fix the power chip on the DBC ceramic layer through the silver sintering layer, the silver sintering layer is a continuous metal layer formed by nano silver particles through a sintering process, and has high thermal conductivity and high temperature stability. The DBC ceramic layer is attached to the surface of the copper-based cooling plate through the thermal conductive medium layer, the thermal conductive medium layer is a thermal interface material layer, the thickness ranges from 0.05 mm to 0.20 mm, and is used to fill the interface gap between the DBC ceramic layer and the copper-based cooling plate and provide a heat conduction channel. A direct heat conduction path from the chip to the cooling liquid is formed, and the heat generated by the power chip is transmitted to the copper-based cooling plate through the silver sintering layer, the DBC ceramic layer and the thermal conductive medium layer in turn, and finally taken away by the cooling liquid in the matrix flow channel structure, thereby omitting the solder layer between the DBC ceramic substrate and the copper base plate and the independent cooling plate in the traditional structure, shortening the heat conduction path and reducing the total thermal resistance.

[0066] It should be noted that the key technical ideas of the present application include silver sintering interface cavity online detection and adaptive adjustment technology, interface thermal stress rapid prediction technology based on intrinsic orthogonal decomposition and neural network, and multi-scale simulation optimization technology of adaptive reconstruction of heat conduction path. The silver sintering interface cavity online detection and adaptive adjustment technology can monitor the interface cavity rate in the sintering process in real time through ultrasonic detection, and dynamically adjust the sintering process parameters according to the detection results. Compared with the traditional offline detection method, defects can be found and corrected in time during the manufacturing process, avoiding the generation of unqualified products, and significantly improving the reliability and yield of the silver sintering layer. The interface thermal stress rapid prediction technology based on intrinsic orthogonal decomposition and neural network reduces the complex finite element simulation problem to a simple algebraic equation solution, which shortens the calculation time from several hours to 0.3 seconds compared with the traditional full-scale finite element analysis method, making real-time optimization in the manufacturing process possible, and effectively reducing the interface thermal stress through optimization of material thickness ratio, prolonging the service life of the power module. The multi-scale simulation optimization technology of adaptive reconstruction of heat conduction path realizes efficient calculation of temperature field through resistance network equivalence and adaptive grid refinement, which greatly reduces the calculation resource consumption while ensuring the calculation accuracy of the hot spot area compared with the traditional uniform grid method, supports real-time calculation of large-scale nodes, and provides a fast and accurate simulation tool for the optimization design of micro-channel structure. The synergistic effect of the three technologies realizes the whole-process closed-loop optimization from material interface quality control to structure thermal stress optimization and heat dissipation performance improvement, which can monitor and adjust key parameters in real time during the manufacturing process compared with the traditional trial-and-error method, ensuring that each manufacturing link is in the optimal state, and finally obtaining a direct cooling substrateless power module with high reliability and excellent heat dissipation performance.

[0067] It should be noted that the present application also solves the technical problems that the silver sintering interface cavity is difficult to detect online, resulting in unstable sintering quality. The traditional silver sintering process adopts fixed sintering pressure and sintering temperature parameters, and cannot monitor the interface cavity formation in real time during the sintering process, resulting in that the cavity defects can only be found after sintering is completed through destructive detection, causing low yield. The present application scans the interface of the nano-silver paste at a certain frequency through the ultrasonic transmitter, collects the time domain signal of the reflected wave and obtains the frequency domain amplitude distribution through fast Fourier transform, judges the position and size of the interface cavity according to the attenuation coefficient in a certain frequency range, establishes a quantitative corresponding relationship between the acoustic resonance spectrum characteristic value and the cavity rate, and when the cavity rate exceeds the threshold value, the sintering pressure is increased in real time and the holding pressure time is prolonged while the sintering temperature is increased, promoting the silver particle solid phase diffusion to fill the cavity, realizing the online detection of the silver sintering interface cavity and the closed-loop control of the sintering process parameters, and ensuring the quality stability of the silver sintering layer.

[0068] Specifically, the principle of the present application is that the traditional power module contains multiple series thermal resistance links, and the contact thermal resistance of each interface is accumulated to form a larger total thermal resistance, which limits the heat transfer rate from the chip to the cooling medium. The present application directly fixes the power chip on the direct copper clad ceramic layer through the silver sintering layer, omits the traditional solder layer of the bottom plate, and then adheres the direct copper clad ceramic layer to the surface of the copper-based cooling plate with embedded micro-channels through the heat-conducting medium layer, so that the cooling liquid and the power chip are separated by only three heat transfer links, i.e. the silver sintering layer, the direct copper clad ceramic layer and the heat-conducting medium layer, reducing the number of series thermal resistances. The silver sintering layer has higher thermal conductivity and high-temperature resistance than the traditional solder layer, and the embedded micro-channel cooling plate enables the cooling liquid to be directly close to the heat source, thereby strengthening the convective heat transfer. The present application can online monitor the silver sintering interface cavity through ultrasonic detection technology and adjust the sintering process parameters in real time, thereby reducing the interface thermal resistance. The present application can quickly predict the interface thermal stress distribution through reduced-order modeling and neural network proxy model, optimize the material thickness ratio, shorten the heat conduction path, control the interface stress generated by thermal expansion mismatch, and ensure the structural reliability. Therefore, the scheme of the present application conforms to the basic principle of heat conduction and can improve the heat dissipation efficiency.

[0069] A specific embodiment 1 of the present application is provided below, and the specific implementation of steps S01, S03, S05 and S07 in the embodiment 1 is the same as the foregoing, and will not be described in detail here. The specific implementation of other steps is described in detail as follows.

[0070] The specific implementation of step S02 is that the nano-silver paste is first uniformly coated on the surface of the copper-based cooling plate, and the coating thickness is controlled to be 50 to 80 Then, the power chip is accurately placed above the coating area, and the ultrasonic transmitter is used to scan the interface at a frequency of 5 The center frequency emits ultrasonic waves to the interface of the nano-silver paste, the ultrasonic waves are reflected at the multi-layer interface of the silver sintering layer, and the reflected wave time domain signal is collected The frequency domain amplitude distribution is obtained by performing fast Fourier transform on the reflected wave time domain signal The calculation formula is as follows:

[0071] ;

[0072] In the formula, is the frequency domain amplitude distribution, and the unit is ; is the reflected wave time domain signal, and the unit is ; is the frequency, and the unit is ; is the time variable, and the unit is ; is the sampling time window, and the unit is , and the value is usually 0.001; is the imaginary unit, and satisfies . The attenuation coefficient is extracted in the frequency range 3 to 7 as the acoustic resonance frequency spectrum characteristic value, and the attenuation coefficient calculation formula is as follows:

[0073] ;

[0074] In the formula, is the attenuation coefficient, and is dimensionless; is the amplitude at the reference frequency, and the unit is , and the frequency domain amplitude at the frequency 3 is taken; is the reference frequency, and the unit is , and the value is 3000000. According to the linear relationship equation between the acoustic resonance frequency spectrum characteristic value and the void ratio established by the calibration experiment, the void ratio is calculated, and the formula is as follows:

[0075] ;

[0076] In the formula, is the void ratio percentage value, and when , it indicates that the void ratio is 3.5 ; is the average value of the attenuation coefficient in the frequency range 3 to 7 , and is dimensionless, and the calculation method is , wherein is the frequency sampling point number, is the i Each frequency sampling point Number the frequency sampling points; The slope is a dimensionless linear fit, calculated using 10 sets of known void ratios within the range of 0.1. Up to 5 The measurement data of the silver sintered sample were obtained by least squares fitting, and the empirical value was 1.85. The linear fitting intercept is dimensionless and has an empirical value of 0.12.

[0077] The specific implementation of step S04 is as follows: First, the temperature field data of 100 sets of temperature cycling finite element simulations are modeled in order reduction using intrinsic orthogonal decomposition technology, and the temperature field data are modeled according to the reference temperature. Normalization is performed to obtain the dimensionless temperature field data matrix. ,in The value is usually 273. Temperature field data matrix Represented as a column vector combination of the normalized temperature field under various operating conditions, the singular value decomposition of the temperature field data matrix is ​​expressed by the following formula:

[0078] ;

[0079] In the formula, The normalized temperature field data matrix is ​​dimensionless and has a dimension of . ,in For the number of nodes, The number of working conditions is 100. It is a left singular vector matrix, dimensionless, with dimension . ; It is a singular value diagonal matrix, dimensionless, with dimension 1. ; It is a right singular vector matrix, dimensionless, with dimension . Select those with a cumulative contribution rate of 99%. The left singular vectors corresponding to the first 8 singular values ​​are used as the dominant modes of the temperature field. ,in The modal number represents the temperature field distribution under any operating condition. It can be expressed as a linear combination of the principal modes of the temperature field, as shown in the following formula:

[0080] ;

[0081] In the formula, This is the temperature field distribution vector, in units of... ; For the first Each modal coefficient, in units of ; For the first A temperature field principal mode vector, dimensionless. The mapping relationship between the input parameters and the peak value of the interface shear stress distribution is obtained through the neural network surrogate model training ; is the maximum value of the interface shear stress distribution, and the unit is , and the peak position coordinate output unit is .

[0082] The specific implementation of step S06 is to use a heat conduction path adaptive reconstruction algorithm to equivalent a three-dimensional heat conduction problem to a resistance network, and the thermal resistance of the first heat conduction path between the copper-based cooling plate and the power chip The calculation formula is as follows:

[0083] ;

[0084] In the formula, is the total thermal resistance of the first heat conduction path, and the unit is , wherein is the heat conduction path number; is the total number of material layers passed by the first path; is the material layer number; is the thickness of the first material layer, and the unit is ; is the thermal conductivity of the first material layer, and the unit is ; is the heat transfer cross-sectional area of the first material layer, and the unit is . The improved Dijkstra algorithm is used to search for the minimum thermal resistance path from the heat source to the cooling liquid. When it is detected that the local temperature of the power chip exceeds the local temperature threshold value 115℃, the grid density is refined in the region and the thermal resistance distribution is recalculated, and the full-field temperature distribution is obtained through sparse matrix fast solution, wherein is the temperature of the local region of the power chip, and the unit is ℃, is the spatial temperature distribution of the entire power module, and the unit is ℃.

[0085] For the explanation of the acoustic resonance frequency spectrum characteristic value part, the calculation principle is based on the reflection and transmission characteristics of ultrasonic waves at multi-layer interfaces. When the ultrasonic wave passes through the silver sintering layer, the cavities at the interface will cause a sudden change in acoustic impedance, causing the amplitude of the reflected wave to attenuate within a certain frequency range, and the attenuation coefficient The calculation formula is , wherein the numerator represents the amplitude attenuation amount in the frequency domain, and the denominator represents the frequency normalization factor, and the larger the decay coefficient represents the higher the porosity of the position. The linear relationship equation established by the calibration experiment can realize the quantitative detection of porosity. In the calibration experiment, 10 groups of silver sintered samples covering the porosity range of 0.1 to 5 The least square method is used to fit the measured data to obtain the slope and intercept parameters of the linear relationship equation.

[0086] For the explanation of the proper orthogonal decomposition part, the principle of the reduced order modeling is to extract the main mode with the largest contribution rate in the temperature field data matrix by singular value decomposition. The singular value decomposition formula is , which simplifies the partial differential equation with hundreds of thousands of degrees of freedom to an algebraic equation with 8 modal coefficients. In the implementation process, 100 groups of temperature cycle finite element simulation results are singular value decomposed, and the singular vectors corresponding to the first 8 singular values with a cumulative contribution rate of 99 are selected as the basis functions. The temperature field distribution under any working condition can be expressed as , thereby greatly reducing the calculation complexity and improving the prediction speed.

[0087] For the explanation of the adaptive reconstruction algorithm part of the heat conduction path, the principle is to equivalent the three-dimensional heat conduction problem to a resistance network, and the heat resistance calculation formula is In the formula, the heat resistance of each material layer is in series to obtain the total heat resistance, and the heat resistance between the copper-based cooling plate and the power chip is equivalent to the branch resistance of the resistance network, and the heat flow is equivalent to the branch current of the resistance network. When the improved Dijkstra algorithm is used to search for the minimum heat resistance path from the heat source to the cooling liquid, the grid density is refined in the area where the local temperature exceeds the local temperature threshold 115℃ and the heat resistance distribution is recalculated, and the full-field temperature distribution is obtained by sparse matrix fast solving technology. This algorithm supports real-time calculation of 2 million nodes, and can complete a single prediction in 0.3 seconds.

[0088] It should be noted that the variables involved in the present embodiment are explained in detail as shown in Table 1.

[0089] Table 1 Variable explanation table

[0090]

[0091] For better understanding and implementation of the present application, the following provides an embodiment 2 of a specific application scenario of the present application: the drive system of a certain electric vehicle adopts a three-phase inverter topology structure, each phase bridge arm contains 2 IGBT chips and 2 diode chips, the power loss peak of a single IGBT chip reaches 180W, and the chip junction temperature often exceeds 140℃ to trigger thermal protection under high-speed working conditions. The skilled person first prepares an embedded micro-channel cooling plate, selects copper material with a purity of 99.9% as the substrate material, and adopts a precision milling process to process a matrix flow channel structure inside the copper-based cooling plate. The flow channel width is set to 0.5mm, the depth is set to 0.8mm, the initial flow channel spacing is set to 1.2mm, and the total length of the flow channel is 850mm. After processing, the flow channel surface is treated by plasma etching, the treatment power is 300W, the treatment time is 120 seconds, and the contact angle of the flow channel surface after treatment is 15 degrees, meeting the hydrophilic requirement.

[0092] The skilled person then performs online detection of silver sintering interface cavities, uniformly coats nano-silver paste with a particle size of 70nm on the surface of the copper-based cooling plate, and controls the coating thickness to be 60μm. After placing the IGBT chip, start the ultrasonic detection system, set the ultrasonic transmitter operating frequency to 5MHz, the scanning step pitch to 0.2mm, and the single scanning time to 45 seconds. The system collects the time domain signal of the reflected wave and performs fast Fourier transform to obtain the frequency domain amplitude distribution data as shown in Table 2.

[0093] Table 2 Acoustic resonance frequency spectrum characteristic values at different scanning positions

[0094]

[0095] As shown in Figure 2 , the cavity rates of scanning positions 4 and 5 exceed the 0.5% threshold, and the system automatically triggers sintering process parameter adjustment. The sintering pressure is increased from the initial 10MPa to 15MPa, the sintering temperature is adjusted from the initial 240℃ to 260℃, and the pressure holding time is extended by 5 minutes to a total of 20 minutes. After adjustment, re-scan detection, the cavity rate of all positions is reduced to below 0.4%, and the sintering layer shear strength test result is 52MPa, meeting the performance requirements.

[0096] The skilled person constructs an interface thermal stress rapid prediction model, collects 100 groups of finite element simulation data under temperature cycling conditions, and the temperature cycling range is -40°C to 150°C. Through the intrinsic orthogonal decomposition technology, the temperature field data matrix is singular value decomposed, and the first 8 temperature field principal modes with a cumulative contribution rate of 99.2% are extracted. The neural network proxy model adopts a 3-layer hidden layer structure, with 32, 64 and 32 neurons in each layer, and the input layer includes 15 parameters such as the thickness of the chip silicon layer 0.20mm, the thickness of the silver sintering layer 50μm, the thickness of the DBC ceramic layer 0.38mm, and the thickness of the thermal conductive medium layer 0.10mm. As shown in Figure 3 , the model training uses 1000 groups of finite element simulation data, and the loss function converges to 0.003 after 3000 iterations, the prediction error of the interface shear stress peak value is 4.2%, and the single prediction time is 0.28 seconds.

[0097] The peak value of the interface shear stress distribution in the initial material ratio scheme output by the prediction model reaches 165MPa, and the position coordinates are 2.3mm inward from the chip edge, exceeding the stress threshold of 150MPa. The skilled person starts the material thickness ratio optimization program, uses genetic algorithm for iterative search, sets the population size to 50, the iteration number to 100 generations, the crossover probability to 0.8, and the mutation probability to 0.1. The optimization process is shown in Table 3.

[0098] Table 3 Material thickness ratio optimization iteration process

[0099]

[0100] As shown in Figure 4 , after 100 generations of iteration, the optimal material thickness ratio scheme is obtained, the silver sintering layer thickness is increased from the initial 50μm to 80μm, the DBC ceramic layer thickness is adjusted from the initial 0.38mm to 0.32mm, and the interface shear stress peak value is reduced to 115MPa, meeting the design requirements.

[0101] The skilled person performs multi-scale simulation optimization of micro-channel flow heat transfer, uses fine mesh in the IGBT chip hotspot area, sets the mesh accuracy to 0.05mm, and the node number reaches 850,000; uses coarse mesh in the chip peripheral area, sets the mesh accuracy to 0.2mm, and the node number is 320,000. The temperature field distribution is calculated using the adaptive reconstruction algorithm of heat conduction path, which equivalent three-dimensional heat conduction problem to a resistance network containing 1.17 million branches, and uses the improved Dijkstra algorithm to search for the minimum thermal resistance path. The simulation results show that under the conditions of power loss 180W, cooling liquid flow rate 5L / min, and cooling liquid inlet temperature 60°C, the chip junction temperature peak value reaches 132°C, exceeding the junction temperature threshold of 125°C. As shown in Figure 5As shown, the area of the region where the local temperature exceeds 115℃ is 38% of the total area of the chip, mainly distributed in the center and edge regions of the chip.

[0102] The system automatically triggers the flow channel spacing optimization, reducing the spacing of the matrix flow channel structure from the initial 1.2mm to 0.8mm, increasing the number of flow channels from 42 to 63, and increasing the cooling liquid flow rate from 1.8m / s to 2.4m / s. After re-simulation, the chip junction temperature peak is reduced to 118℃, the temperature distribution uniformity is significantly improved, and the area of the region where the temperature exceeds 115℃ is reduced to 12% of the total area of the chip. The cooling plate pressure drop increases from the original 24kPa to 46kPa, still meeting the system pump power limit requirements. The heat transfer coefficient increases from the original 8500 to 13200 , and the total thermal resistance decreases from 0.42 to 0.28 .

[0103] The skilled person completes the manufacture of the direct-cooled substrate-free power module, fixes the IGBT chip on the DBC ceramic layer with a thickness of 0.32mm through a silver sintering layer with a thickness of 80μm, and the DBC ceramic layer adopts an aluminum nitride ceramic substrate with a thermal conductivity of 170 . The DBC ceramic layer is attached to the surface of the copper-based cooling plate through a thermally conductive silicone layer with a thickness of 0.10mm, forming a direct heat conduction path from the chip to the cooling liquid. After assembly, temperature cycle testing is performed, with a test condition of -40℃ to 150℃ cycle, a single cycle time of 60 minutes, including 15 minutes of heating, 15 minutes of high temperature holding, 20 minutes of cooling, and 10 minutes of low temperature holding. After 5000 cycles, the thermal resistance of the power module increases by 3.2%, the silver sintering layer does not show obvious cracks or delamination, and the electrical performance remains stable. In actual vehicle testing, the chip junction temperature of the power module under high-speed working conditions is stable below 120℃, completely eliminating the phenomenon of over-temperature protection, and the continuous output power capability of the vehicle driving system is significantly improved.

[0104] The present application realizes real-time adjustment of sintering process parameters through silver sintering interface cavity online detection technology, avoids the problem of batch rejection caused by the failure of traditional offline detection method to discover defects in time. The interface thermal stress rapid prediction model is based on intrinsic orthogonal decomposition and neural network proxy technology, which shortens the finite element analysis which originally takes several hours to sub-second level, so that the iterative optimization of material thickness ratio is feasible in engineering practice. The micro-channel flow and heat transfer multi-scale simulation optimization adopts adaptive grid reconstruction algorithm, which significantly reduces the calculation resource consumption while ensuring the calculation accuracy of hot spot area, and realizes the rapid design and optimization of complex flow channel structure. The direct cooling without substrate structure omits the solder layer and independent cooling plate between the traditional DBC substrate and copper bottom plate, shortens the series thermal resistance link in the heat conduction path, and reduces the total thermal resistance between the chip and the cooling liquid from the physical mechanism, which is an essential improvement that cannot be achieved by traditional indirect cooling methods.

[0105] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A method for manufacturing a substrate-free power module with direct cooling, characterized in that, This includes preparing an embedded microchannel cooling plate, processing a matrix flow channel structure inside the copper-based cooling plate, and performing a hydrophilic modification treatment on the surface of the matrix flow channel structure; Online detection of voids at the silver sintering interface was performed. A power chip was placed on a copper-based cooling plate after coating the silver nanoparticle paste with it. An ultrasonic transmitter scanned the interface of the silver nanoparticle paste, acquiring the time-domain signal of the reflected wave and calculating the acoustic resonance spectrum characteristic values. Sintering process parameters were adjusted in real time based on the acoustic resonance spectrum characteristic values. A rapid prediction model for interface thermal stress was constructed, and the thickness ratios of the chip's silicon layer, silver sintering layer, direct copper-clad ceramic layer, and thermally conductive medium layer were modeled with reduced order. The principal modes of the temperature field were extracted through intrinsic orthogonal decomposition, and a neural network surrogate model was trained to calculate the interface shear stress distribution. The material thickness ratio was adjusted based on the interface shear stress distribution. Multi-scale simulation optimization of microchannel flow heat transfer was performed. The fabrication of the direct-cooled substrate-free power module was completed.

2. The manufacturing method of the direct-cooling substrate-free power module according to claim 1, characterized in that, The processing of the matrix flow channel structure specifically involves processing a matrix flow channel structure with a width of 0.5 mm and a depth of 0.8 mm inside the copper-based cooling plate, with a flow channel spacing of 1.2 mm.

3. The manufacturing method of the direct-cooling substrate-free power module according to claim 2, characterized in that, The acoustic resonance spectrum characteristic value refers to the frequency domain amplitude distribution of the reflected wave time domain signal generated by ultrasound at the multi-layer interface of the silver sintered layer after fast Fourier transform.

4. The manufacturing method of the direct-cooling substrate-free power module according to claim 3, characterized in that, The correspondence between the acoustic resonance spectrum characteristic values ​​and the void ratio was established through a calibration experiment. In the calibration experiment, silver sintered samples with known void ratios were prepared, the acoustic resonance spectrum characteristic values ​​of the silver sintered samples were measured, and the linear relationship equation was obtained by fitting using the least squares method.

5. The manufacturing method of the direct-cooling substrate-free power module according to claim 4, characterized in that, The step of adjusting the sintering process parameters in real time according to the acoustic resonance spectrum characteristic value is specifically to increase the sintering pressure from 10 MPa to 15 MPa and extend the holding time by 5 minutes when the void ratio corresponding to the acoustic resonance spectrum characteristic value exceeds 0.5%, while adjusting the sintering temperature from 240 degrees Celsius to 260 degrees Celsius.

6. The method for manufacturing a direct-cooling substrate-free power module according to claim 5, characterized in that, The intrinsic orthogonal decomposition is a reduced-order modeling technique that extracts the temperature field mode with the largest contribution rate as the basis function by performing singular value decomposition on a large number of finite element simulation results during temperature cycling.

7. The method for manufacturing a direct-cooling substrate-free power module according to claim 6, characterized in that, The neural network proxy model adopts a three-layer hidden layer structure. The input layer includes the thickness of the chip silicon layer, the thickness of the silver sintered layer, the thickness of the direct copper-clad ceramic layer, the thickness of the thermally conductive medium layer, the thickness of the copper-based cooling plate, and the thermal expansion coefficient and elastic modulus of the corresponding materials. The output layer is the peak value and peak position coordinates of the interface shear stress distribution.

8. The method for manufacturing a direct-cooling substrate-free power module according to claim 7, characterized in that, The step of adjusting the material thickness ratio according to the interfacial shear stress distribution specifically involves increasing the thickness of the silver sintered layer from 50 micrometers to 80 micrometers when the peak value of the interfacial shear stress distribution exceeds 150 MPa, and adjusting the thickness of the direct copper-clad ceramic layer from 0.38 mm to 0.32 mm.

9. The method for manufacturing a direct-cooling substrate-free power module according to claim 8, characterized in that, The material thickness ratio is obtained through iterative optimization using a neural network surrogate model. During the iterative optimization process, the objective function is to minimize the peak value of the interfacial shear stress distribution, and a genetic algorithm is used to search for the optimal material thickness ratio.

10. The method for manufacturing a direct-cooling substrate-free power module according to claim 9, characterized in that, The steps for performing multi-scale simulation optimization of microchannel flow heat transfer specifically involve using a fine mesh with an accuracy of 0.05 mm in the hot spot area of ​​the power chip and a coarse mesh with an accuracy of 0.2 mm in the peripheral area of ​​the power chip, and calculating the temperature field distribution through an adaptive reconstruction algorithm for the heat conduction path.

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