Semiconductor package including mark frame and mark pattern defined by mark frame and method of manufacturing same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate; a semiconductor chip on the substrate; a molding layer covering the semiconductor chip on the substrate, the molding layer including a package body and a mark pattern on the package body; and a mark frame on the package body of the molding layer, the mark frame including a removable portion for defining a mark area when removed. The mark pattern is in the mark area and is connected to the package body. The marking frame includes a metal material.

Description

TECHNICAL FIELD

[0001] Some example embodiments of the present disclosure relate to the field of semiconductor packaging, and more particularly, to a semiconductor package and / or a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of the electronic industry, there is an increasing demand for electronic components with higher performance and / or more compactness. To meet this demand, there is a need for semiconductor devices or semiconductor packages that are relatively thin and / or more reliable.

[0003] Generally, a semiconductor package includes characters or patterns representing information such as a trademark, a model, a performance parameter, etc. thereof, which can be referred to as a mark pattern. In the existing marking process, a method of burning and etching a molding layer using a laser is used to form a mark pattern in a semiconductor package. The depth of the mark pattern thus formed is difficult to control to be small, and thus the overall thickness of the semiconductor package cannot be effectively reduced. SUMMARY

[0004] To solve the above problems, some example embodiments of the present disclosure provide a semiconductor package having a mark frame to reduce thickness and / or a manufacturing method thereof.

[0005] In addition, some example embodiments of the present disclosure also provide a semiconductor package having a mark frame to shield electromagnetic interference (EMI) and / or a manufacturing method thereof.

[0006] In addition, some example embodiments of the present disclosure also provide a semiconductor package having a mark frame to prevent warpage and / or a manufacturing method thereof.

[0007] According to example embodiments of the present disclosure, a semiconductor package includes a substrate, a semiconductor chip on the substrate, a molding layer covering the semiconductor chip on the substrate, the molding layer including a package body and a mark pattern on the package body, and a mark frame on the package body of the molding layer, the mark frame including a removable portion to define a mark region when removed. The mark pattern is in the mark region and connected to the package body. The mark frame includes a metal material.

[0008] Further, an upper surface of the mark frame and an upper surface of the mark pattern can be coplanar.

[0009] Further, the upper surface of the mark pattern can be a smooth upper surface.

[0010] Further, a depth of the mark pattern can be the same as a depth of the mark frame.

[0011] Further, the depth of the mark pattern can be 5 μm.

[0012] Further, the marking frame can include copper.

[0013] Further, a side surface of the marking frame can be aligned with a side surface of the package body.

[0014] Further, the package body and the marking pattern can be integral.

[0015] Further, the semiconductor chip can be located on the base with an active surface facing up and electrically connected to the base via the bond wire.

[0016] Further, the package body can cover an upper surface of the bond wire and the semiconductor chip, and the marking frame can not be in contact with the bond wire.

[0017] According to an example embodiment of the present disclosure, a method of manufacturing a semiconductor package includes: providing a marking unit including a preliminary marking frame and a separation carrier disposed below the preliminary marking frame; removing a portion of the preliminary marking frame to form a marking area, a remaining portion of the preliminary marking frame forming a marking frame; providing a chip unit including a base and a semiconductor chip located on the base; performing a molding process on the marking unit and the chip unit to form a molding layer including a package body covering the semiconductor chip on the base and a marking pattern disposed on the package body; and removing the separation carrier to expose an upper surface of the marking frame and an upper surface of the marking pattern. The marking pattern fills the marking area and is connected to the package body. The marking frame includes a metal material.

[0018] Further, the upper surface of the marking frame and the upper surface of the marking pattern can be coplanar.

[0019] Further, the upper surface of the marking pattern can be a smooth upper surface.

[0020] Further, a depth of the marking pattern can be the same as a depth of the marking frame.

[0021] Further, the depth of the marking pattern can be 5 pm.

[0022] Further, the marking frame can include copper.

[0023] Further, a side surface of the marking frame can be aligned with a side surface of the package body.

[0024] Further, the step of performing the molding process can include: placing the marking unit in a lower cavity of a mold with the marking area facing up, and placing the chip unit in an upper cavity of the mold with the semiconductor chip facing down; closing the mold and injecting an encapsulation material; and cooling and solidifying the encapsulation material to form the molding layer, and the package body and the marking pattern can be formed simultaneously in the mold via the molding process.

[0025] Further, the separate carrier of the marking unit can be placed on a release film in the lower cavity of the mold.

[0026] Further, the semiconductor chip can be disposed on the substrate with an active surface facing upward and electrically connected to the substrate via the bonding wire.

[0027] Further, the encapsulation body can cover the bonding wire and an upper surface of the semiconductor chip, and the marking frame can not be in contact with the bonding wire.

[0028] According to example embodiments of the present disclosure, a semiconductor package includes a substrate, a semiconductor chip disposed on the substrate, a bonding wire electrically connecting the semiconductor chip to the substrate, a molding layer encapsulating the semiconductor chip and the bonding wire, the molding layer having an upper surface, and a metal marking frame disposed on the upper surface of the molding layer, the metal marking frame having a marking area defined therein. The molding layer includes a marking pattern filling the marking area. The metal marking frame is configured to provide electromagnetic interference shielding. The metal marking frame is spaced apart from the bonding wire.

[0029] Further, the metal marking frame includes copper.

[0030] Further, an encapsulation body of the molding layer and the marking pattern are integrally formed.

[0031] Further, an upper surface of the metal marking frame and an upper surface of the marking pattern are coplanar and form a substantially smooth surface.

[0032] Further, a depth of the marking pattern is equal to a thickness of the metal marking frame.

[0033] Further, the depth of the marking pattern is about 5 pm.

[0034] Further, the semiconductor chip has an active surface facing upward, and the bonding wire extends from the active surface to the substrate.

[0035] Further, the metal marking frame has a side surface aligned with a side surface of the molding layer.

[0036] Further, the semiconductor package further includes an external connection terminal disposed on a lower surface of the substrate.

[0037] According to an example embodiment of the present disclosure, a semiconductor package includes a substrate, a semiconductor chip mounted on an upper surface of the substrate, bonding wires electrically connecting the semiconductor chip to the substrate, external connection terminals provided on a lower surface of the substrate, a molding layer covering the semiconductor chip and the bonding wires, the molding layer including a package body and a mark pattern on the package body, and a mark frame having a removable portion defining a mark area on the package body of the molding layer. The mark pattern is provided in the mark area. The mark frame includes a metal material. An upper surface of the mark frame and an upper surface of the mark pattern are coplanar. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above and other aspects of the present disclosure will become more apparent by describing in detail some example embodiments thereof with reference to the attached drawings. In the drawings:

[0039] Figure 1 is a schematic view of a semiconductor package according to a comparative example.

[0040] Figure 2 is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure.

[0041] Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure.

[0042] Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 are cross-sectional views of intermediate stages of a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure.

[0043] Figures 9A to 9C is a schematic view of a display mark pattern according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] Hereinafter, various example embodiments of the present disclosure will be fully described with reference to the accompanying drawings, in which various example embodiments are illustrated. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the example embodiments set forth herein.

[0045] Further, since the sizes and / or thicknesses of portions, regions, members, units, layers, films, substrates, etc. shown in the drawings can be arbitrarily shown for better understanding and ease of explanation, the present disclosure is not limited to the shown sizes and / or thicknesses. In the drawings, the thicknesses of portions, regions, members, units, layers, films, substrates, etc. can be exaggerated or enlarged for convenience of explanation and / or easy illustration.

[0046] For ease of description, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for describing an element's relationship to another element as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then an element described as "below" or "beneath" another element or step would then be oriented "above" the other element or step. The term "below" can encompass both "above" and "below". Thus, the terms "below" and "above" can encompass both orientations of the device in use or operation.

[0047] Although the term "same" is used in the description of example embodiments, it will be understood that there can be some inaccuracy. Thus, when an element is referred to as being the same as another element, it will be understood that the element is the same as the other element within a desired range of manufacturing tolerances (e.g., ±10%).

[0048] When the term "about" or "substantially" is used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing tolerances around the stated numerical value (e.g., ±10%). Additionally, when the words "generally" and "substantially" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required but that the limits of the shape are within the disclosed range. Furthermore, whether a numerical value or a shape is modified as "about" or "substantially", it will be understood that these values and shapes should be interpreted to include manufacturing or operational tolerances around the stated numerical value or shape (e.g., ±10%).

[0049] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.

[0050] Figure 1 is a schematic view of a semiconductor package according to a comparative example.

[0051] Referring to Figure 1 The semiconductor package 1000 can include a substrate SUB, a semiconductor chip 1002 disposed on the substrate SUB, and a molding layer 1003 encapsulating the semiconductor chip 1002.

[0052] The semiconductor chip 1002 can be electrically connected to the substrate SUB via the bonding wire 1004. As an example, the substrate SUB can be a printed circuit board (PCB), but is not limited thereto. The semiconductor package 1000 can further include an external connection terminal 1005 disposed on a lower surface of the substrate SUB.

[0053] In a conventional semiconductor packaging process, a marking process can be performed after a molding process of forming the molding layer 1003. Specifically, the marking process can include engraving on the molding layer 1003 (e.g., epoxy molding compound (EMC)) using a laser burning method to form a marking pattern. The marking pattern can include characters or patterns representing information of a trademark, a model number, a performance parameter, etc. of the semiconductor package 1000.

[0054] When using the conventional marking process, since the laser burning method is used, the marking depth can be relatively deep (e.g., about 10 micrometers (μm) to about 50 μm) and the characteristics of the marking are unstable, e.g., a large burning penetration depth, a rough edge, etc. When the thickness of the molding layer 1003 is thin, the relatively deep marking pattern formed by the laser burning method can easily contact the bonding wire 1004 in the molding layer 1003, which can cause the bonding wire 1004 to be not tightly encapsulated, thus exposed to the outside, resulting in a short circuit or corrosion. In addition, when the thickness of the molding layer 1003 is thin, the marking pattern can easily extend downward along the vertical direction to form a crack, resulting in a decrease in reliability of the semiconductor package 1000. Thus, it is desired to ensure that the overall thickness of the semiconductor package 1000 is formed to be large enough, making it difficult to make the semiconductor package 1000 thinner and / or lighter.

[0055] In addition, a coefficient of thermal expansion (CTE) mismatch between the epoxy molding compound (EMC) forming the molding layer 1003 and the printed circuit board (PCB) forming the substrate SUB can cause a package warpage problem, thus affecting the reliability of the semiconductor device.

[0056] Hereinafter, a semiconductor package according to an example embodiment of the present disclosure will be described in detail with reference to different example embodiments shown in the accompanying drawings.

[0057] Figure 2 is a cross-sectional view of a semiconductor package according to an example embodiment of the present disclosure.

[0058] Referring to Figure 2The semiconductor package 2000 can include a substrate SUB, a semiconductor chip 2002 on the substrate SUB, a molding layer 2003 covering the semiconductor chip 2002 on the substrate SUB, and a marking frame 2005. The molding layer 2003 includes a package body (a first portion of the molding layer) and a marking pattern 2004 (e.g., a second portion of the molding layer) disposed on the package body. The marking frame 2005 is on the package body of the molding layer 2003. A portion of the marking frame 2005 is removed to form a marking area. The marking pattern 2004 fills the marking area and is connected to the package body. The marking frame 2005 includes a metal material.

[0059] Unlike a conventional laser burning process, the semiconductor package 2000 according to this example embodiment of the disclosure includes the marking pattern 2004 defined by the marking frame 2005 and formed by a portion of the molding layer 2003. Since the thickness of the marking frame 2005 can be easily formed to be relatively thin, the depth of the marking pattern 2004 can be controlled to be relatively small, so that the thickness of the molding layer 2003 can be correspondingly reduced, thereby achieving a reduction in the overall thickness of the semiconductor package 2000.

[0060] Meanwhile, the marking frame 2005 including the metal material can have an electromagnetic interference (EMI) shielding function, which can improve the signal processing accuracy of the semiconductor package 2000, thereby improving the operation speed of the semiconductor package 2000 to improve the performance of the device.

[0061] In addition, since the marking frame 2005 includes the metal material, the marking frame 2005 has rigidity. When the rigid marking frame 2005 is disposed on the upper portion of the molding layer 2003 of the semiconductor package 2000, warping of the semiconductor package 2000 can be suppressed, thereby improving the yield and / or reliability of the product.

[0062] In an example embodiment, the substrate SUB can have a first surface (e.g., an upper surface) and a second surface (e.g., a lower surface) opposite the first surface. The substrate SUB can include a first pad disposed on the first surface of the substrate SUB and a second pad disposed on the second surface of the substrate SUB. As an example, the substrate SUB can be a printed circuit board (PCB), but is not limited thereto.

[0063] In an example embodiment, the semiconductor package 2000 may further include an external connection terminal 2007 disposed on a second surface of the substrate SUB. The external connection terminal 2007 may be disposed on a second pad on the second surface of the substrate SUB. The semiconductor chip 2002 may be electrically connected to the external connection terminal 2007 disposed on the second surface of the substrate SUB via the substrate SUB. As an example, the external connection terminal 2007 may be a solder ball or solder, etc., but is not limited thereto.

[0064] In an example embodiment, the semiconductor chip 2002 may have an active surface and a passive surface opposite to the active surface. For example, the semiconductor chip 2002 may be mounted upright on a substrate SUB or flip-chip on a substrate SUB.

[0065] In example embodiments, such as Figure 2 As shown, when the semiconductor chip 2002 is mounted on the substrate SUB, the semiconductor chip 2002 can be disposed on the substrate SUB with its active surface facing upwards, and the passive surface of the semiconductor chip 2002 can face the substrate SUB (e.g., the first surface of the substrate SUB). In this case, the semiconductor chip 2002 can be electrically connected to the substrate SUB (e.g., electrically connected to a first pad on the first surface of the substrate SUB) via bonding leads 2006.

[0066] Although not shown, the semiconductor chip 2002 can be flip-chip mounted on the substrate SUB. In this case, the semiconductor chip 2002 can be disposed on the substrate SUB with its active surface facing down, and the active surface of the semiconductor chip 2002 can face the substrate SUB (e.g., the first surface of the substrate SUB). However, the mounting form of the semiconductor chip 2002 on the substrate SUB is not limited to the above-described upright or flip-chip configurations.

[0067] although Figure 2 A semiconductor chip 2002 is shown, but the semiconductor package 2000 may include multiple stacked semiconductor chips.

[0068] In an example embodiment, the molding layer 2003 may cover at least a portion of the semiconductor chip 2002 on the substrate SUB. For example, as Figure 2 As shown, the molding layer 2003 can cover the upper surface and side surfaces of the semiconductor chip 2002. The molding layer 2003 can be a cured epoxy molding compound (e.g., cured epoxy resin).

[0069] The molding layer 2003 can include a package body and a marking pattern 2004 disposed on the package body. In an example embodiment, the marking pattern 2004 and the package body included in the molding layer 2003 can be integrally formed in the same process and connected to each other. In other words, the marking pattern 2004 and the package body included in the molding layer 2003 and connected to each other can be disposed as one body. For example, the marking pattern 2004 and the package body can be simultaneously formed in a mold via a molding process (to be described below with reference to Figure 6 and Figure 7 the detailed description). In a conventional semiconductor packaging process, an additional marking process can be performed after a molding process for forming the molding layer 1003 is performed. In contrast, according to some example embodiments of the present disclosure, the marking pattern can be formed at the same time as the molding process is performed, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0070] In an example embodiment, the marking pattern 2004 and the package body can contain the same material, for example, an epoxy molding compound (EMC). In this case, the package body in the molding layer 2003 can cover the semiconductor chip 2002 and the bonding leads 2006 to protect the semiconductor chip 2002 and the bonding leads 2006 from the external environment or external impact. The marking pattern 2004 in the molding layer 2003 can identify information such as a trademark, a model number, a performance parameter, etc.

[0071] A portion of the marking frame 2005 is removed to form a marking area. In an example embodiment, the marking area can pass through the marking frame 2005 in a vertical direction. When viewed from a cross-sectional view, the marking areas can be arranged in a horizontal direction and spaced apart from each other. In this case, the marking pattern 2004 can fill the marking areas formed by removing the portion of the marking frame 2005. The marking pattern 2004 and the remaining marking frame 2005 can be located on an upper surface of the package body of the molding layer 2003.

[0072] In an example embodiment, an upper surface of the marking frame 2005 and an upper surface of the marking pattern 2004 can be substantially coplanar. In this case, a depth of the marking pattern 2004 can be substantially the same as a depth of the marking frame 2005.

[0073] As Figure 2As shown, the upper surfaces of the marking frame 2005 and the marking pattern 2004 can be exposed after the separation carrier, which will be described below, is removed or peeled off. Since the separation carrier can protect the marking frame 2005 and the marking pattern 2004 during the various stages of the process, the marking frame 2005 and the marking pattern 2004 can have substantially flat or smooth upper surfaces after the separation carrier is removed. Therefore, a substantially flat and / or smooth upper surface can save the need for surface planarization processes (e.g., chemical mechanical polishing (CMP)) that would otherwise have to be performed in subsequent processes. In other words, a substantially flat and / or smooth upper surface makes surface planarization processes that would otherwise be performed in subsequent processes unnecessary. When no subsequent processes need to be performed, a substantially flat and / or smooth upper surface allows the product information represented by the marking pattern 2004 to be clearly identifiable. The product information represented by the marking pattern 2004 can be clearly identifiable without any subsequent processes due to the substantially flat and / or smooth upper surface.

[0074] In example embodiments, such as Figure 2 As shown, the side surface of the marking frame 2005 can be substantially aligned with the side surface of the package body. For example, the outer surface of the semiconductor package 2000 can be formed by the outer surface of the marking frame 2005 and the outer surface of the package body. The marking pattern 2004 can be formed in the central region of the upper surface of the semiconductor package 2000 to prevent the product information represented by the marking pattern 2004 from being worn or damaged.

[0075] In the example embodiment, the metal material of the marking frame 2005 may be copper (Cu), but the example embodiments of this disclosure are not limited to this, and other metal materials or alloys may be used to form the marking frame 2005. In the example embodiment, the thickness of the marking frame 2005 may be substantially the same as the depth of the marking pattern 2004. For example, the depth of the marking pattern 2004 may be approximately 5 μm. Considering reasonable tolerances in the manufacturing process, reasonable values ​​slightly larger or slightly smaller than 5 μm fall within the scope of the inventive concept.

[0076] According to exemplary embodiments of this disclosure, since a marking frame 2005 with a desired (or optionally, predetermined) depth is used and the depth of the marking pattern 2004 can be substantially the same as the depth of the marking frame 2005, the depth of the marking pattern 2004 can be controlled within a relatively stable expected range (e.g., approximately 5 μm). In other words, the depth of the marking pattern 2004 in exemplary embodiments of this disclosure can be relatively small and stable, thus facilitating the realization of thin semiconductor packages.

[0077] Below, we will refer to Figures 3 to 8 The following describes in detail the formation process of a semiconductor package according to an example embodiment of the present disclosure.Figure 3 is a flowchart of a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure. Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 are cross-sectional views of intermediate stages of a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure.

[0078] Referring to Figure 3 , a method of manufacturing a semiconductor package according to an example embodiment of the present disclosure can include steps S100 to S500.

[0079] Referring to Figure 4 , a marking unit is provided in step S100, where the marking unit can include a preliminary marking frame 100P and a separation carrier 200 disposed below the preliminary marking frame 100P. In an example embodiment, the separation carrier 200 can be a photosensitive material or a thermosensitive material with adhesion. For example, when the separation carrier 200 is irradiated with ultraviolet light or heated, the separation carrier 200 can lose adhesion and can be peeled off. However, example embodiments of the present disclosure are not limited thereto, and the separation carrier 200 can also be removed via a chemical etching, mechanical grinding, and / or chemical mechanical polishing process, etc.

[0080] Referring to Figure 5 , a portion of the preliminary marking frame 100P is removed to form a marking area 300 in step S200. The remaining portion of the preliminary marking frame 100P forms a marking frame 100. In an example embodiment, the separation carrier 200 can be located below the marking frame 100. The separation carrier 200 can not be removed. The marking area 300 can expose at least a portion of an upper surface of the separation carrier 200. In one example, a portion of the preliminary marking frame 100P can be removed by an etching process.

[0081] When viewed in a cross-sectional view, the marking frame 100 can include a plurality of portions arranged in a horizontal direction and spaced apart from each other. The plurality of portions can have different horizontal widths from each other. When viewed in a plan view, the marking area 300 can include text or patterns representing information of a trademark, a model number, a performance parameter, etc. of a semiconductor package to be manufactured.

[0082] Referring to Figure 6The chip unit is provided in step S300, where the chip unit can include a substrate SUB and a semiconductor chip 2002 disposed on the substrate SUB. The semiconductor chip 2002 can be electrically connected to the substrate SUB via bonding wires 2006. The semiconductor chip 2002 can be mounted on the substrate SUB in a face-up manner or in a flip-chip manner as described above, which will not be repeated here. In addition, other ways of disposing the semiconductor chip 2002 on the substrate SUB are also feasible.

[0083] Referring to Figure 6 and Figure 7 A molding process is performed on the marking unit in step S100 and the chip unit in step S300 to form a molding layer 2003 in step S400. The molding layer 2003 can include a package body covering the semiconductor chip 2002 on the substrate SUB and a marking pattern 2004 disposed on the package body.

[0084] In an example embodiment, the steps of the molding process can include: placing the marking unit in the lower cavity 602 of the mold with the marking area 300 facing upwards, and placing the chip unit in the upper cavity (not shown) of the mold with the semiconductor chip 2002 facing downwards; closing the mold and injecting the encapsulation material 601; and cooling and solidifying the encapsulation material 601 to form the molding layer 2003. In addition, the separation carrier 200 can be placed on a release film 603 in the lower cavity 602 of the mold.

[0085] In an example embodiment, the release film 603 can be pre-placed in the lower cavity of the mold. When the marking unit is placed into the lower cavity of the mold, the lower surface of the separation carrier 200 can contact the release film 603. The release film 603 can facilitate the separation of the separation carrier 200 from the mold, so that the semiconductor package can be easily taken out of the mold after the encapsulation material 601 is cooled and solidified. Although not shown, a release film can also be present in the upper cavity of the mold.

[0086] As Figure 7 indicated in the above, the package body and the marking pattern 2004 included in the molding layer 2003 can be formed simultaneously and integrally via the molding process. In addition, the marking frame 2005 formed can not be in contact with the bonding wires 2006, thereby reducing or preventing short-circuit failure.

[0087] After the molding process is completed, external connection terminals 2007 can be formed on the second surface (e.g., the lower surface) of the substrate SUB.

[0088] Referring to Figure 8In step S500, the structure obtained in step S400 is inverted by removing or peeling off the separation carrier 200 to expose the upper surface of the marking frame 2005 and the upper surface of the marking pattern 2004. The upper surface of the marking frame 2005 and the upper surface of the marking pattern 2004 can be substantially coplanar and substantially flat or smooth.

[0089] Figures 9A to 9C is a schematic view of a display marking pattern according to example embodiments of the present disclosure.

[0090] Figure 9A shows a separation carrier and a marking frame, wherein a portion of the marking frame has been removed and forms a marking area. Figure 9A may correspond to the structure obtained after performing steps S100 and S200.

[0091] Figure 9B shows a separation carrier, a marking frame, and a molding layer formed by the EMC. At this time, the upper portion of the molding layer can fill the marking area to form a marking pattern, and the formed marking pattern can identify information such as a trademark, a model number, a performance parameter, etc. of the semiconductor package. Figure 9B may correspond to the structure obtained after performing steps S300 and S400.

[0092] Figure 9C shows a marking frame and a molding layer including a package body and a marking pattern. Figure 9C may correspond to the structure obtained after performing step S500.

[0093] In summary, the semiconductor package according to some example embodiments of the present disclosure can have a reduced overall thickness and / or improved device reliability while achieving a desired controllable and / or relatively small marking depth. For example, the semiconductor package according to example embodiments of the present disclosure includes a marking frame including a metal material located on a package body of a molding layer and a marking pattern defined by an upper portion of the molding layer filling a marking area where a portion of the marking frame is removed. In this case, the depth of the marking pattern can be reduced so that the overall thickness of the semiconductor package can be reduced to achieve a thinner and / or lighter device.

[0094] In addition, the marking frame of the semiconductor package according to some example embodiments of the present disclosure can also function as an electromagnetic interference (EMI) shield. At the same time, since the marking frame itself has rigidity, disposing it at the upper portion of the molding layer can effectively suppress warping of the semiconductor package to improve the yield and / or reliability of the device.

[0095] In addition, the method of manufacturing a semiconductor package according to some example embodiments of the present disclosure can form a mark pattern while performing a molding process. Thus, a separate process for forming a mark pattern is no longer required, thereby simplifying the manufacturing process and reducing manufacturing costs.

[0096] While some example embodiments of the present disclosure have been illustrated and described herein, it will be clear to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as defined in the claims.

Claims

1. A semiconductor package, the semiconductor package comprising: Base; Semiconductor chips are located on a substrate; A molding layer covers a semiconductor chip on a substrate. The molding layer includes a package body and a marking pattern located on the package body. as well as A marking frame, on the encapsulation body of the molding layer, includes a removable portion for defining a marking area upon removal. The marking pattern is located in the marking area and connected to the encapsulation body, and The marking frame includes a metallic material.

2. The semiconductor package according to claim 1, wherein, The upper surface of the marking frame and the upper surface of the marking pattern are coplanar.

3. The semiconductor package according to claim 2, wherein, The upper surface of the marking pattern is a smooth surface.

4. The semiconductor package according to claim 2, wherein, The depth of the marking pattern is the same as the depth of the marking frame.

5. A semiconductor package, comprising: Base; Semiconductor chips are mounted on a substrate; Connect the leads to electrically connect the semiconductor chip to the substrate; A molding layer encapsulates a semiconductor chip and bonding leads; the molding layer has an upper surface. as well as A metal marking frame is disposed on the upper surface of the molding layer, and a marking area is defined within the metal marking frame. The molding layer includes a marking pattern that fills the marking area. The metal marking frame is configured to provide electromagnetic interference shielding, and The metal marking frame is spaced apart from the bonding leads.

6. The semiconductor package according to claim 5, wherein, The metal marker frame is made of copper.

7. The semiconductor package according to claim 5, wherein, The encapsulation body and marking pattern of the molding layer are formed as one piece.

8. A semiconductor package, comprising: Base; Semiconductor chips are mounted on the upper surface of a substrate; Connect the leads to electrically connect the semiconductor chip to the substrate; External connection terminals are disposed on the lower surface of the substrate; A molding layer covers the semiconductor chip and bonding leads. The molding layer includes a package body and a marking pattern located on the package body. as well as The marking frame, on the encapsulation body of the molded layer, has a removable portion that defines the marking area. The marking pattern is set in the marking area. The marking frame includes a metal material, and The upper surface of the marking frame and the upper surface of the marking pattern are coplanar.

9. A method for manufacturing a semiconductor package, the method comprising: A marking unit is provided, which includes a preliminary marking frame and a separation carrier disposed below the preliminary marking frame; A portion of the initial marking frame is removed to form the marking area, and the remaining portion of the initial marking frame forms the marking frame; A chip unit is provided, the chip unit comprising a substrate and a semiconductor chip located on the substrate; A molding process is performed on the marking cells and chip cells to form a molding layer, the molding layer including a package body covering a semiconductor chip on a substrate and a marking pattern disposed on the package body; as well as Remove the separation carrier to expose the upper surface of the marker frame and the upper surface of the marker pattern. The marking pattern fills the marking area and connects to the encapsulation body, and The marking frame includes a metallic material.

10. The method according to claim 9, wherein, The steps involved in performing the molding process include: The marking unit is placed in the lower cavity of the mold with the marking area facing upwards, and the chip unit is placed in the upper cavity of the mold with the semiconductor chip facing downwards; Close the mold and inject the encapsulating material; and Cool and solidify the encapsulating material to form a molded layer. The main body of the package and the marking pattern are formed simultaneously in the mold through a molding process.

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