Packaging structure of low-stress TVS discrete device

Abstract

The invention discloses a packaging structure of a low-stress TVS discrete device. A surface mount device, structure, and associated methods. The apparatus includes a housing, a lead frame at least partially enclosed by the housing, wherein the lead frame includes a chip mounting surface having a chip mounting pad and a chip mounting platform disposed on the chip mounting pad. The apparatus includes another lead frame at least partially encapsulated by the housing. The other lead frame is coupled to the clip and to the semiconductor chip. The semiconductor chip is coupled to the chip mounting platform.

Description

Technical Field

[0001] This disclosure relates generally to the field of power semiconductor discrete devices, and particularly to surface mount packages, including package structures for transient voltage suppressor (TVS) devices. Background Technology

[0002] Discrete semiconductors are devices designed to perform basic electronic functions and cannot be divided into multiple independent components, each with its own function. Power semiconductors are used as switches or rectifiers in power electronic devices. Diodes, transistors, thyristors, and rectifiers are all examples of discrete power semiconductors. Discrete power semiconductors exist in a wide variety of environments, from very low power systems to very high power systems.

[0003] Transient voltage suppression (TVS) diodes are electronic components designed to protect sensitive electronic devices from high-voltage transients. TVS diodes respond to overvoltage events faster than most other types of circuit protection devices and are available in a variety of surface mount and through-hole board mounting formats. TVS diodes are commonly used to protect against electrical overloads, such as those caused by lightning strikes, inductive load switching, and electrostatic discharge (ESD) associated with transmissions on data lines and electronic circuits.

[0004] Packaging integrated circuits is typically the final stage of the semiconductor device manufacturing process. During packaging, the semiconductor die, representing the core of the semiconductor device, is encapsulated in a housing that protects it from physical damage and corrosion. For example, semiconductor dies are typically mounted on a copper substrate using solder alloy reflow, conductive epoxy resin, etc. The mounted semiconductor die is then usually encapsulated in plastic or epoxy compound.

[0005] Currently, TVS device packages are typically characterized by small size and high power. Examples of TVS device packages include surface mounting type B (SMB) packages, which are used in many different technical fields, such as multi-point data transmission systems. Typically, multi-point data transmission systems require the use of asymmetric TVS devices, where the SMB package provides protection for electronic components on the printed circuit board from the effects of electrostatic discharge (ESD), electrical fast transients (EFT), lightning, etc. However, current SMB packages for TVS devices are inadequate in addressing damage to the semiconductor chip during manufacturing and / or packaging. Summary of the Invention

[0006] The following summary is provided to introduce a selection of concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0007] In some embodiments, the present subject matter relates to an apparatus (e.g., a surface mount device and / or package structure). The apparatus may include a housing, a lead frame at least partially enclosed by the housing, wherein the lead frame may include a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads. The apparatus may include another lead frame at least partially enclosed by the housing, wherein the other lead frame may be coupled to a clip and coupled to a semiconductor chip. The semiconductor chip may be coupled to the chip mounting platform.

[0008] In some implementations, the present subject may include one or more of the following optional features. The semiconductor chip may be configured to be coupled to chip mounting pads using conductive solder.

[0009] In some implementations, the clip may be completely enclosed by a housing. The semiconductor chip may include a semiconductor chip working region disposed on the top surface of the semiconductor chip. The clip may be configured to be coupled to the semiconductor chip working region.

[0010] In some implementations, the clamp may be configured to include one or more support bars that extend laterally through the clamp.

[0011] In some embodiments, the clip may include a flat plate for coupling to a semiconductor chip. The clip may include one or more grooves positioned between the flat plate and one or more support rods. The clip may include a raised portion configured to extend away from the flat plate and the semiconductor chip when the clip is coupled to the semiconductor chip.

[0012] In some implementations, the lead frame may include stress-reducing openings located close to the chip mounting surface.

[0013] In some embodiments, a leadframe may include leadframe terminal ends, and another leadframe may include another leadframe terminal ends. The leadframe terminal ends and the other leadframe terminal ends may be configured to be coupled to at least one of: a substrate, a printed circuit board, and any combination thereof.

[0014] In some embodiments, the housing may be made of at least one of the following materials: epoxy compounds, plastics, and any combination thereof.

[0015] In some embodiments, the device can be configured as a surface-mount device.

[0016] In some implementations, the device may be a transient voltage suppression device.

[0017] In some embodiments, the present subject relates to a method that may include providing a housing; a lead frame at least partially enclosed by the housing, the lead frame including a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads; and another lead frame at least partially enclosed by the housing, the other lead frame being coupled to a clip and coupled to a semiconductor chip; wherein the semiconductor chip is coupled to the chip mounting platform. The method may further include coupling the clip and the other lead frame; coupling the semiconductor chip to the lead frame and the clip; forming a housing to enclose the lead frame, the other lead frame, the clip, and the semiconductor chip, wherein at least a portion of each of the lead frame and the other lead frame is configured to extend outside the housing.

[0018] Details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, as well as from the claims. Attached Figure Description

[0019] The following overview is provided to introduce the selection of concepts in a simplified form, which will be further described in the detailed description below. This overview is not intended to identify key or essential features of the claimed subject matter, nor is it intended to assist in determining the scope of the claimed subject matter.

[0020] Figures 1A-1C Exemplary surface mount packaging structures according to some embodiments of the present topic are shown;

[0021] Figure 2 The internals of the encapsulation structure according to some embodiments of the current topic are shown;

[0022] Figures 3A-3D Further details of the first and second leads of the package structure according to some embodiments of the present topic are shown;

[0023] Figures 4A-4B Further details of the clip of the encapsulation structure according to some embodiments of the present topic are shown;

[0024] Figures 5A-5C Chips with package structures according to some embodiments of the present topic are shown; and

[0025] Figure 6 Example methods for manufacturing semiconductor surface mount structures (e.g., package structures) according to some embodiments of the present topic are shown.

[0026] The accompanying drawings are not necessarily drawn to scale. The drawings are merely illustrative and not intended to depict specific parameters of this disclosure. The drawings are intended to depict exemplary embodiments of the present subject matter and should therefore not be considered as limiting in scope. In the drawings, similar numbers denote similar elements.

[0027] Furthermore, for clarity, certain elements in some figures may be omitted and / or not shown to scale. Sectional views may be in the form of "slice-off" and / or "close-up" sectional views, and for clarity, certain background lines that would otherwise be visible in the "true" sectional view have been omitted. Additionally, for clarity, some reference numerals may be omitted in some figures. Detailed Implementation

[0028] Various methods according to this disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the systems and methods are illustrated. Devices, systems, components, etc., may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present subject matter to those skilled in the art.

[0029] To address these and other potential shortcomings of currently available solutions, one or more embodiments of the present subject matter relate to methods, systems, articles of manufacture, etc., which, among other possible advantages, can provide package structures for transient voltage suppressor devices, and in some example embodiments, surface mount (e.g., Type A (SMA), Type B (SMB), Type C (SMC), etc.) package structures for transient voltage suppressor devices.

[0030] As mentioned above, transient voltage suppressor (TVS) semiconductor devices can be used to protect electronic components from transient voltages, overvoltages, etc. TVS chips are typically used as the core component of TVS semiconductor devices. Examples of TVS chips are shown in... Figures 5A-5C As shown in the image.

[0031] Voltage transients are defined as short-duration surges in electrical energy, resulting from the sudden release of previously stored energy and / or energy induced by other means, such as heavy inductive loads, lightning, etc. Voltage transients can be classified as predictable or repeatable transients and random transients. In electrical or electronic circuits, this energy can be released in a predictable manner via controlled switching actions or randomly induced into the circuit from external sources. Repeatable transients are often caused by the operation of motors, generators, and / or the switching of reactive power circuit components. On the other hand, random transients are typically caused by electrostatic discharge (ESD) and lightning, which usually occur unpredictably.

[0032] ESD is characterized by a very fast rise time and very high peak voltage and current, which may result from an imbalance of positive and negative charges between objects. ESD generated by everyday activities can exceed the vulnerability threshold of standard semiconductor technology. In the case of lightning, even though a direct strike is destructive, the voltage transients caused by lightning are not the result of the direct strike. When lightning strikes, the event can generate a magnetic field, which in turn can cause significant voltage transients in nearby electrical cables. For example, cloud-to-cloud impacts will affect not only overhead cables but also buried cables. Even a strike from 1 mile away (1.6 km) can generate 70 volts in electrical cables. The voltage transient effect is significantly greater in cloud-to-ground impacts.

[0033] In some cases, TVS chips can be packaged using surface mount (SMA, SMB, SMC) packages, which offer high power while maintaining a small overall size. For example, SMB packages can be used in printed circuit boards (PCBs) to protect various electronic components from ESD, electrical fast transients (EFT), lightning, and / or any other transients. SMB packages allow for surface mounting of electronic components and optimization of space on the PCB (on which these components can be mounted). It can also be characterized by a small profile, improved clamping capability, and other enhanced features.

[0034] Figures 1A-1C An exemplary surface mount package structure 100 according to some embodiments of the present topic is shown. Figure 1A A top perspective view of the package structure 100 is shown. Figure 1B A side cutout view of the package structure 100 is shown. Figure 1C A transparent view of the top portion of the encapsulation structure 100 is shown.

[0035] Package structure 100 may include an encapsulation or housing 102 (hereinafter referred to as “housing”), a semiconductor and / or TVS chip 104, a clip 106, a first lead 108, a second lead 110, and a chip support or mounting (terms used interchangeably herein) pad 112 (which may be disposed on the second lead 110, as will be discussed below).

[0036] The housing 102 may be configured to receive and / or encapsulate at least a portion of the chip 104, clip 106, and first lead 108 and second lead 110, including chip support pads 112. The first lead 108 and second lead 110 may be configured to extend from the housing 102 for conductive coupling to other electronic components and / or printed circuit board 128. The housing 102 may be configured to be made of epoxy compounds, plastics, and / or any other suitable material.

[0037] The first lead 108 may include a first end 114 and a second end 116. The first end 114 of the first lead may be coupled to a substrate and / or printed circuit board (PCB) 128 and / or any other electronic component using any known mechanism (e.g., solder, welding, etc.). The second end 116 of the first lead may be coupled to a clip 106 using conductive solder 132. Specifically, the second end 116 of the first lead may be coupled to the first end 120 of the clip 106. Although... Figures 1A-1C The first lead 108 is shown as having a curved shape, but it will be understood that the first lead 108 may have any desired shape and / or its shape may be modified to suit various circuit structures and / or positioning.

[0038] The second lead 110 may include a first end 124 and a second end 126. The first end 124 of the second lead may be coupled to the PCB 128 and / or any other electronic component using any known mechanism (e.g., solder, welding, etc.). Similarly, although Figures 1A-1C The second lead 110 is shown as having a curved shape, but it is understood that the second lead 100 may have any desired shape and / or its shape may be modified to suit various circuit structures and / or positioning.

[0039] In some embodiments, the first lead 108 and the second lead 110 may be made of conductive materials, such as, but not limited to, copper, copper alloys, silver, metal alloys, and / or any combination thereof. Leads 108 and 110 may also be configured to provide an electrical connection between the TVS chip 104 and the package structure 100 to which circuitry (e.g., PCB 128) may be connected.

[0040] The second end 126 of the second lead may include a chip support pad 112 disposed close to the second end 126 of the second lead. The chip support pad 112 may include a chip platform 134, which may be coupled to the chip 104 using conductive solder 130. The chip platform 134 may be raised from the chip support pad 112 to create a raised surface for coupling the chip 104. The chip support pad 112 and the chip platform 134 may be configured to form an integral structure. Alternatively or additionally, the chip platform 134 may be coupled to the chip support pad 112 using any known mechanism (e.g., solder, bonding, etc.). The chip platform 134 (in itself and / or in combination with other features of the package structure 100) may be configured to reduce stress on the chip 104 during the manufacture, packaging, and / or operation of the package structure 100, and to prevent the chip 104 from cracking, being damaged, etc. The chip platform 134 may be made of a conductive material (e.g., copper, copper alloys, silver, metal alloys, etc.). In some embodiments, conductive solder, such as conductive solder 130, may be configured to be placed on the chip support pad 112 and surrounding the chip platform 134 on one or more sides of the chip platform 134, thereby creating additional support for the chip 104 when the chip 104 is positioned on the chip platform 134. The chip platform 134 may be configured to have any desired shape, such as circular, square, rectangular, etc. Furthermore, the chip platform 134 may be positioned on the chip support pad 112 at any desired location and may have any desired size. In some embodiments, the chip platform 134 may have a smaller surface area than the bottom surface and / or bottom working surface of the chip support pad 112 and / or the chip 104. Alternatively or additionally, the chip platform 134 may have a surface area equal to and / or larger than the bottom surface and / or bottom working surface of the chip support pad 112 and / or the chip 104.

[0041] In some example embodiments, the first lead 108 and the second lead 110 may include various structural features (including a chip platform 134) that can be configured to assist in the manufacturing and / or use processes of the package structure 100. In particular, such structural features can reduce manufacturing stress and reduce and / or prevent stress damage to the chip 104 during use. For example, for these purposes, in addition to the chip platform 134 disposed on the second lead 110, the first lead 108 may include stress protection and / or release levers 204 (such as…). Figure 2 (as shown in more detail below), and the second lead 110 may include a stress-reducing opening 138 of the lead frame and one or more stress-reducing grooves 136a, 136b of the lead frame.

[0042] In some exemplary, non-limiting embodiments, the first lead 108 may be configured as a cathode and the second lead 110 may be configured as an anode, or vice versa. As will be understood, any other implementation of leads 108 and 110 is possible.

[0043] like Figures 1A-1C As shown, chip 104 can be coupled to clip 106. The coupling between chip 104 and clip 106 can occur within housing 102. Furthermore, the top working panel of chip 104 can be configured to be electrically coupled to the second end 122 of clip using conductive solder 132. Additionally, the bottom working panel of chip 104 can be configured to be electrically coupled to chip support pad 112 using conductive solder 130.

[0044] In some embodiments, clip 106 may be made of a conductive material, such as, but not limited to, copper, copper alloys, silver, metal alloys, and / or any combination thereof. Clip 106 may be configured to provide an electrical path between PCB 128, chip 104, and first and second leads 108, 110. Clip 106 may be configured to have a curved shape, a portion of which may be configured to extend away from the first lead 108 and chip 104. As will be understood, clip 106 may have any desired shape.

[0045] Clip 106 can be configured to absorb more solder during the assembly process of package structure 100 and can further enhance the reliability of package structure 100 during operation. Furthermore, clip 106 can include various structural features that can be configured to package chip 104 (e.g., recessed features of the clip, as discussed in further detail below).

[0046] like Figures 1A-1C As shown, the housing 102 may have a generally parallelepiped shape. As will be understood, the housing may have any other desired shape.

[0047] Figure 2 The interior of the encapsulation structure 100 according to some embodiments of the present topic is shown. In particular, Figure 2 Further details of the first lead 108, the second lead 110, the clip 106, and the chip 104 are shown. Figure 2 As shown, chip 104 can be positioned between second lead 110 and clip 106. Specifically, chip 104 can be positioned on top of second lead 110 and below clip 106. Second lead 110 may include chip support pad 112, and chip 104 can be positioned on top of chip support pad 112, and specifically, on chip platform 134 (e.g., Figures 1A-1C As shown), and soldered using conductive solder 130 (as shown). Figures 1A-1C (As shown). The surface area of ​​the chip support pad 112 can be larger than the surface area of ​​the chip 104.

[0048] The clip 106 may include a plate 202 disposed near a second end 122 of the clip. The plate 202 of the clip 106 may be positioned on top of a top working panel 206 of the chip 104 and may be soldered to the panel 206 using conductive solder 118. The plate 202 may be configured to extend at least partially over the top working panel 206 of the chip. Figure 2 As shown, the surface area of ​​the plate 202 of the clip 106 can be smaller than the surface area of ​​the top working panel 206 of the chip. The first end 120 of the clip can be configured to be coupled to the second end 116 of the first lead. Figures 1A-1C As shown, conductive solder 132 can be used for the first end 120 of the coupling clip and the second end 116 of the first lead.

[0049] In some exemplary, non-limiting embodiments, the clip 106 may include a clamping bar 204, which can be used to provide stress relief and / or damage protection to the clip 106 and / or the chip 104 and / or any other component of the package structure 100. The clamping bar 204 may be disposed between the plate 202 of the clip 106 and the first end 120 of the clip. In some embodiments, the clamping bar 204 may be disposed near the stress-reducing grooves 208a and 208b of the clip, the stress-reducing grooves 208a and 208b being positioned between the clamping bar 204 and the plate 202, such as... Figure 2 As shown.

[0050] The stress-reducing grooves 208a and 208b of the clips can be configured to reduce mechanical, thermal, and / or any other stresses and / or pressures on the chip 104 and / or any other component of the package structure 100 that may occur during the manufacture, assembly, and / or use of the package structure 100. Some of these stresses may cause the chip 104 to crack and / or fail. In some embodiments, additional stress reduction and / or moisture, heat, and / or temperature release may be provided by the clip 106, and particularly by the first end 120 of the clip. The first end 120 of the clip may be made wider and higher. The wider first end 120 of the clip may be configured to provide a larger coupling area for coupling between the clip 106 and the first lead 108. The greater height of the first end 120 of the clip can be configured to raise at least a portion of the first end 120 of the clip (and in particular the clip bar 204) above the first lead 108 and the chip 104, thereby creating a curved shape of the clip 106 and thus providing additional space between the clip 106 and the chip 104, such as Figure 2As shown. This space increases the dissipation of heat from chip 104 and / or any other component of package structure 100 during the manufacture, assembly and / or use of package structure 100.

[0051] In some embodiments, to further enable the reduction of moisture and / or heat dissipation from chip 104 and / or any other component of package structure 100, the first lead 108 may be configured to include one or more dehumidification recesses 212. The dehumidification recesses 212 of the first lead may be located near the second end 116 of the first lead and near the coupling position between the second end 116 of the first lead and the first end 120 of the clip. The dehumidification recesses 212 of the first lead may be configured to traverse the second end 116 of the first lead and may be located on one or more surfaces of the first lead 108 (e.g., on one side and / or the opposite side where the clip 106 is coupled to the first lead 108). Any number of dehumidification recesses 212 of the first lead may be present. The recesses 212 may be configured to traverse the entire first lead 108 and / or at least a portion of the first lead 108.

[0052] Similarly, the second lead 110 can be configured to include one or more dehumidifying recesses 214a, 214b for the second lead. Recess 214 can be similar to recess 212 and can be configured to enable reduction of moisture and / or dissipation of heat from the chip 104 and / or any other component of the package structure 100. Recess 214 can be located close to the chip support pad 112 of the second lead 110. Figure 2 As shown, the groove 214 can be configured to traverse the second lead 110, and particularly between the stress-reducing grooves 136a and 136b of the lead frame. The dehumidification grooves 214a and 214b of the second lead can be separated by stress-reducing openings 138 of the lead frame that can be positioned between them. The stress-reducing openings 138 of the lead frame can be configured to also provide reduction of moisture and / or heat dissipation from the chip 104 and / or any other component of the package structure 100. Similar to groove 212, groove 214 can be provided on one or more surfaces of the second lead 110 (e.g., on one side and / or the opposite side where the chip 104 is coupled to the chip support pad 112). Any number of grooves 214 can be present. Figure 2 As shown, the groove 214 can be configured to extend across the entire first lead 108 and / or at least a portion of the second lead 110.

[0053] Figures 3A-3D Further details (in an exploded view) of the first lead 108 and the second lead 110 of the package structure 100 according to some embodiments of the present topic are shown. Specifically, Figure 3AA top perspective view of leads 108, 110 together with chip 104 is shown. Figure 3B A top perspective view of leads 108 and 110 is shown, revealing chip support pads 112 and chip platform 134. Figure 3C A top view of leads 108 and 110 is shown, revealing chip support pads 112 and chip platform 134 along with other stress and moisture reduction features. Figure 3D A side view of the first lead 108 and the second lead 110 is shown.

[0054] like Figures 3A-3D As shown, the first lead 108 may have a curved shape. As will be understood, the first lead 108 may have any desired shape and / or its shape may be modified to accommodate various circuit structures and / or positioning. As discussed above, the first lead 108 may include one or more dehumidification recesses 212, which may be disposed near the second end 116 of the first lead 108. The lead recesses 212 may be configured to provide heat and / or moisture release during the manufacture and / or use of the package structure 100, as in combination with... Figures 1A-1C and Figure 2 As shown and discussed.

[0055] Similar to the first lead 108, the second lead 110 may have a curved shape. As can be understood, the second lead 110 may have any desired shape and / or its shape may be modified to accommodate various circuit structures and / or positioning. Furthermore, the second lead 110, and particularly its chip support pad 112, may be configured to accommodate the positioning of the chip 104, where the bottom working panel of the chip ( Figures 3A-3D (Not shown) can be coupled (e.g., soldered, etc.) to chip support pad 112, and in particular its chip platform 134, while the top working panel 206 of the chip can be positioned relative to the chip platform 134.

[0056] Chip platform 134 and conductive solder 118 (e.g.) Figures 1A-1C and Figure 2 The use of (shown) can be configured to allow chip 104 to be more tightly positioned and coupled to the second lead 110 (and specifically the bottom working panel of the chip and the chip support pad 112). As stated herein, conductive solder 118 can be used to couple the bottom working panel of the chip to the second lead 110, wherein conductive solder 118 can be positioned and / or distributed on the pad boundary 302 of the chip support pad 112 to fill any gaps between the bottom working panel of the chip and the chip support pad 112.

[0057] In some embodiments, the chip platform 134 of the chip support pad 112 can be configured to protrude from a surface remote from the chip support pad 112, such as Figure 3D As shown. This allows the chip 104 to be positioned at a predetermined height above the chip support pad 112. The height can vary for each specific package structure 100 and / or the use of the package structure 100. This elevated positioning of the chip 104 above the chip support pad 112 and the positioning of the conductive solder 118 (as shown) on the pad boundary 302 Figures 1A-1C and Figure 2 The use of (shown) allows for an increased contact area between chip 104 and the second lead 110, and provides enhanced damage and / or thermal and / or moisture protection to chip 104 during manufacturing, packaging and / or use of package structure 100.

[0058] Figures 4A-4B Further details of the clip 106 of the encapsulation structure 100 according to some embodiments of the present topic are shown. Specifically, Figure 4A A top view of clip 106 is shown, and Figure 4B A side view of clip 106 is shown.

[0059] In some embodiments, clip 106 may be made of a conductive material, such as, but not limited to, copper, copper alloys, silver, metal alloys, and / or any combination thereof. Clip 106 may be configured to provide an electrical path between PCB 128, chip 104, and first and second leads 108, 110. Clip 106 may be configured to have a curved shape, with a portion (e.g., the protrusion 404 of the clip) configured to extend away from the first lead 108 and chip 104. Clip 106 may include various structural features (e.g., clip bar 204 as discussed herein) that may be configured to improve and accelerate heat dissipation during the manufacture, assembly, and / or operation of package structure 100.

[0060] Near the first end 120 of the clamp, the clamp 106 may further include a clamping bar 204, which may include clamping bar ends 402a and 402b that can be disposed on opposite sides of each other. The clamping bar ends 402a and 402b of the clamping bar 204 may be configured to extend beyond the width of the plate 202 of the clamp 106. The clamping bar 204 may have any desired length, which may be selected according to the manufacture, use and / or any other requirements of the package structure 100. The clamping bar 204 may be used to reduce and / or alleviate stress that the package structure 100 and / or its chip 104 may experience during manufacture, use and / or operation.

[0061] As discussed herein, clip 106 may include one or more stress-reducing recesses 208a and 208b of the clip, which may be positioned close to the clamping bar 204. Specifically, stress-reducing recess 208a may be positioned close to the clamping bar end 402a, and stress-reducing recess 208b may be positioned close to the clamping bar end 402b. The use of recesses 208 can be configured to reduce the width of clip 106 between recesses 208. This can be configured to improve the heat dissipation performance of the package structure 100.

[0062] In some embodiments, the clip 106 may include a protrusion 404 that may be positioned at an elevated position relative to the flat plate 202 of the clip 106 and the first lead 108 to which the clip 106 is coupled (e.g., Figure 1A-Figure 2 (As shown). The protrusion 404 of this clip can further improve the heat dissipation characteristics of the package structure 100, as well as provide protection for the chip 104 and / or other components of the package structure 100.

[0063] like Figures 4A-4B As shown, the clip's plate 202 can have a basic rectangular shape (e.g., a square), and its size can be selected to fit the chip 104. Figures 4A-4B Positioning of (not shown) and / or any other components. For example, the length and width of the plate 202 can be selected to be less than the length of the clamp 204, but greater than the length and / or width dimensions of the chip 104. As will be understood, any desired shape, size, dimension, etc. of various components of the package structure 100 can be used.

[0064] Figures 5A-5B Chip 104 with a package structure 100 according to some embodiments of the present topic is shown. Specifically, Figure 5A A top perspective view of chip 104 is shown; Figure 5B A bottom perspective view of chip 104 is shown; and Figure 5C A side view of chip 104 is shown.

[0065] like Figures 5A-5B As shown, chip 104 may include a top working panel 206, a bottom working panel 502, a top edge 504, a bottom edge 506, a top center portion 510, and a bottom center portion 512. The top center portion 510 may be surrounded by the top edge 504. The bottom center portion 512 may be surrounded by the bottom edge 506. The top edge 504 and bottom edge 506 may serve as protection for the chip and may be coupled to the respective top center portion 510 and bottom center portion 512 (e.g., using soldering, welding, etc., and / or manufactured as a whole chip).

[0066] like Figure 5A As shown, the top working panel 206 of the chip may include a top central portion 510 and a top edge 504 of the chip. The top working panel 206 of the chip can be used to position and / or couple various electronic components associated with the chip 104.

[0067] refer to Figure 5B The bottom working panel 502 of the chip may include a bottom center portion 512 and a bottom edge 506 of the chip. The bottom working panel 502 of the chip may also be used to position and / or couple various electronic components associated with the chip 104.

[0068] like Figures 5A-5C The illustrated chip 104 can be used in various electronic applications, such as multipoint data transmission devices, systems, telecommunications, data communication equipment, etc., wherein the chip 104 can be configured to provide protection against peak current pulses. In some example, non-limiting embodiments, the chip 104 can be a TVS semiconductor device (e.g., available from Littelfuse, Inc., Chicago, Illinois, USA), and can be used to suppress overvoltage transients in various electronic devices.

[0069] Furthermore, chip 104 can be packaged using a surface mount (e.g., SMC) package (as discussed herein), which provides high power while maintaining a small overall size. For example, an SMC package can be used on a printed circuit board (PCB) to protect various electronic components from ESD, electrical fast transients (EFT), lightning, and / or any other transients. The SMC package allows for surface mounting of electronic components and optimization of space on the PCB (on which these components can be mounted). It can also feature a small profile, improved clamping capabilities, and other enhanced features.

[0070] As will be understood, the subject matter is not limited to TVS semiconductor devices. For example, chip 104 can be a thyristor and / or any other type of chip. Chip 104 can be any device that can be used to prevent voltage transients that are harmful to the operation of various electronic components.

[0071] Figure 6 An example method 600 for manufacturing a semiconductor surface mount structure (e.g., package structure 100) according to some embodiments of the present subject is shown. Method 600 can be used to manufacture... Figures 1A-5C The packaging structure 100 shown is shown.

[0072] At 602, a housing (e.g., housing 102) and a lead frame (e.g., a second lead 110) at least partially enclosed by the housing are provided. The lead frame may include a chip mounting surface having chip mounting pads (e.g., chip support pads 112) and a chip mounting platform (e.g., chip platform 134) disposed on the chip mounting pads. Additionally, another lead frame (e.g., a first lead 108) at least partially enclosed by the housing may be provided. This additional lead frame may be coupled to a clip (e.g., clip 106) and a semiconductor chip (e.g., chip 104). The semiconductor chip may be coupled to the chip mounting platform.

[0073] At 604, the clip can be coupled to the lead frame (e.g., the second lead 110).

[0074] At 606, the semiconductor chip can be coupled to a lead frame (e.g., second lead 110) and a clip (e.g., clip 106).

[0075] At 608, the housing (e.g., housing 102) may be formed to encapsulate lead frames, other lead frames, clips, and semiconductor chips. At least a portion of each of the lead frames may be configured to extend outside the housing.

[0076] The components and features of the aforementioned devices can be implemented using any combination of discrete circuit systems, application-specific integrated circuits (ASICs), logic gates, and / or single-chip architectures. Furthermore, where appropriate, microcontrollers, programmable logic arrays, and / or microprocessors, or any combination thereof, can be used to implement the features of the devices. Note that hardware, firmware, and / or software elements may be collectively referred to herein or individually as “logic” or “circuit”.

[0077] It will be appreciated that the exemplary devices shown in the block diagrams above may represent one example of a functional description of many potential implementations. Therefore, the division, omission, or inclusion of block functions depicted in the figures does not imply that hardware components, circuits, software, and / or elements used to implement these functions will necessarily be divided, omitted, or included in the embodiments.

[0078] Some embodiments may be described using the expressions “one embodiment” or “embodiment,” “implementation” or “some implementations,” together with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. The appearance of the phrase “in one embodiment” (or its derivatives) in various places in the specification does not necessarily refer to the same embodiment. Furthermore, unless otherwise stated, the foregoing features are considered to be used in any combination. Thus, any feature discussed individually may be used in combination with each other unless it is noted that these features are incompatible with each other.

[0079] It is emphasized that this abstract of the disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. The abstract is to be understood as not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the foregoing detailed description, various features are combined in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be construed as reflecting an intention to claim more features than expressly recited in each claim. Rather, as reflected in the following claims, the inventive subject matter lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are incorporated herein by reference, wherein each claim stands independently as a separate embodiment. In the appended claims, the terms “including” and “in which” are used as concise English equivalents to the corresponding terms “comprising” and “wherein”, respectively. Furthermore, the terms “first,” “second,” “third,” and the like are used merely as labels and are not intended to impose numerical requirements on their objects. Moreover, the use of “including,” “comprising,” or “having,” and variations thereof herein, means to cover the items listed below and their equivalents, as well as additional items. Therefore, the terms “including,” “comprising,” or “having,” and their variations, are open-ended expressions and can be used interchangeably in this document.

[0080] For convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” “crossing,” “radial,” “inner,” “outer,” “left,” and “right” may be used throughout this document to describe the relative placement and orientation of features and components, each relative to the geometry and orientation of other features and components appearing in the perspective, exploded perspective, and cross-sectional views provided herein. The terms are not intended to be limiting and include specifically mentioned words, derived words therein, and words with similar meanings.

[0081] The above description includes examples of the disclosed architecture. It is certainly impossible to describe every conceivable combination of components and / or methods, but those skilled in the art will recognize that many further combinations and permutations are possible. Therefore, the novel architecture is intended to encompass all such changes, modifications, and variations falling within the spirit and scope of the appended claims.

[0082] In one aspect, an apparatus may include: a housing; a lead frame at least partially enclosed by the housing, the lead frame including a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads; and another lead frame at least partially enclosed by the housing, the other lead frame being coupled to a clip and coupled to a semiconductor chip; wherein the semiconductor chip is coupled to the chip mounting platform.

[0083] The device may also include a semiconductor chip configured to be coupled to a chip mounting pad using conductive solder.

[0084] The device may also include a clamp that is completely enclosed by a housing.

[0085] The device may also include a semiconductor chip working area disposed on the top surface of the semiconductor chip.

[0086] The device may also include clips configured to be coupled to the working area of ​​a semiconductor chip.

[0087] The device may also include a clamp configured to include one or more support rods extending laterally through the clamp.

[0088] The device may also include a clip comprising a plate for coupling to a semiconductor chip.

[0089] The device may also include a clamp comprising one or more grooves positioned between a plate and one or more support rods.

[0090] The device may also include a raised portion in which the clip includes a portion configured to extend away from the flat plate and the semiconductor chip when the clip is coupled to the semiconductor chip.

[0091] The device may also include a lead frame comprising stress-reducing openings positioned close to the chip mounting surface.

[0092] The device may also include a lead frame including a lead frame terminal end, and another lead frame including another lead frame terminal end.

[0093] The device may also include a lead frame terminal end and another lead frame terminal end configured to be coupled to at least one of: a substrate, a printed circuit board, and any combination thereof.

[0094] The device may also include a housing made of at least one of the following materials: epoxy compounds, plastics, and any combination thereof.

[0095] The device may also include a surface-mount device configured therein.

[0096] The device may also include transient voltage suppression devices.

[0097] In one aspect, a method may include providing a housing, a lead frame at least partially enclosed by the housing, the lead frame including a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads; and another lead frame at least partially enclosed by the housing, the other lead frame being coupled to a clip and coupled to a semiconductor chip; wherein the semiconductor chip is coupled to the chip mounting platform; coupling the clip and the other lead frame; coupling the semiconductor chip to the lead frame and the clip; forming the housing to enclose the lead frame, the other lead frame, the clip, and the semiconductor chip, wherein at least a portion of each of the lead frame and the other lead frame is configured to extend outside the housing.

[0098] For purposes of illustration and description, the foregoing description of exemplary embodiments has been presented. It is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Many modifications and variations are possible based on this disclosure. The scope of this disclosure is not intended to be limited by this detailed description, but rather by the appended claims. Future applications claiming priority to this application may claim the disclosed subject matter in different ways and may generally include one or more sets of limitations as differently disclosed or otherwise shown herein.

[0099] All directional references (e.g., proximal, distal, upper, lower, upward, downward, left, right, lateral, longitudinal, front, rear, top, bottom, above, below, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are used solely for identifiable purposes to aid the reader's understanding of this disclosure and do not impose limitations, particularly regarding the location, orientation, or use of this disclosure. Unless otherwise indicated, connection references (e.g., attachment, coupling, connection, and joining) should be interpreted broadly and may include intermediate members between sets of elements and relative movement between elements. Therefore, connection references do not necessarily imply that two elements are directly connected and in a fixed relationship with each other.

[0100] Furthermore, the designations (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority, but are used to distinguish one feature from another. These figures are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the accompanying figures may vary.

[0101] This disclosure is not limited in scope to the specific embodiments described herein. In fact, various other embodiments and modifications of this disclosure, besides those described herein, will be apparent to those skilled in the art from the foregoing description and drawings. Therefore, these other embodiments and modifications are intended to fall within the scope of this disclosure. Furthermore, this disclosure has been described herein in the context of specific embodiments for specific purposes and in specific environments. Those skilled in the art will recognize that its usefulness is not limited thereto, and that this disclosure can be advantageously practiced for any purpose in any number of environments. Therefore, the claims set forth below should be interpreted in light of the full breadth and spirit of this disclosure as described herein.

Claims

1. An apparatus comprising: case; A lead frame, at least partially enclosed by the housing, the lead frame including a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads; as well as Another lead frame, at least partially enclosed by the housing, is coupled to the clip and to the semiconductor chip; The semiconductor chip is coupled to the chip mounting platform.

2. The apparatus according to claim 1, wherein, The semiconductor chip is configured to be coupled to the chip mounting pads using conductive solder.

3. The apparatus according to claim 1, wherein, The clip is completely enclosed by the housing.

4. The apparatus according to claim 3, wherein, The semiconductor chip includes a semiconductor chip working area disposed on the top surface of the semiconductor chip.

5. The apparatus according to claim 4, wherein, The clip is configured to be coupled to the working area of ​​the semiconductor chip.

6. The apparatus according to claim 1, wherein, The clamp is configured to include one or more support rods that extend laterally through the clamp.

7. The apparatus according to claim 1, wherein, The clip includes a flat plate for coupling to the semiconductor chip.

8. The apparatus according to claim 7, wherein, The clamp includes one or more grooves positioned between the plate and one or more support rods.

9. The apparatus according to claim 8, wherein, The clip includes a raised portion configured to extend away from the plate and the semiconductor chip when the clip is coupled to the semiconductor chip.

10. The apparatus according to claim 1, wherein, The lead frame includes stress-reducing openings located close to the chip mounting surface.

11. The apparatus according to claim 1, wherein, The lead frame includes lead frame terminal ends, and the other lead frame includes another lead frame terminal ends.

12. The apparatus according to claim 11, wherein, The lead frame terminal end and another lead frame terminal end are configured to be coupled to at least one of: a substrate, a printed circuit board, and any combination thereof.

13. The apparatus according to claim 1, wherein, The shell is made of at least one of the following materials: epoxy compounds, plastics, and any combination thereof.

14. The apparatus according to claim 1, wherein, The device is configured as a surface-mount device.

15. The apparatus according to claim 1 further includes a transient voltage suppression device.

16. A method comprising: supply case; A lead frame, at least partially enclosed by the housing, the lead frame including a chip mounting surface having chip mounting pads and a chip mounting platform disposed on the chip mounting pads; as well as Another lead frame, at least partially enclosed by the housing, is coupled to the clip and to the semiconductor chip; The semiconductor chip is coupled to the chip mounting platform; Couple the clip to the other lead frame; The semiconductor chip is coupled to the lead frame and the clip; and The housing is formed to enclose the lead frame, the other lead frame, the clip, and the semiconductor chip, wherein at least a portion of each of the lead frame and the other lead frame is configured to extend outside the housing.

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