Plastic packaging method of chip

Abstract

The invention discloses a plastic packaging method of a chip. The plastic packaging method comprises the following steps: performing wafer thinning, scribing, chip bonding and lead bonding treatment on a circuit to be processed to obtain a semi-finished circuit subjected to lead bonding; the semi-finished circuit subjected to lead bonding is subjected to glue dispensing treatment, glue is coated on the surface of a chip, the chip, a bonding wire and an inner pin are expanded and covered by the glue through structural constraint of a lead frame, and then a stress buffer layer wrapping the chip, the bonding wire and the inner pin is formed through baking and curing; and packaging, electroplating, printing and separating the dispensed chip to obtain a finished circuit. According to the method, the low-modulus glue is introduced as the stress buffer layer, so that the mechanical stress in the plastic packaging process is effectively dispersed, the problem of output parameter drift of a high-precision chip is solved, and the precision and reliability of a device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit packaging and testing technology, and specifically to a chip encapsulation method. Background Technology

[0002] In the manufacturing of semiconductor leadframe-type plastic-encapsulated devices, standard packaging processes are mature and widely used in various general-purpose chips, covering multiple stages from wafer thinning to forming and cutting. The encapsulation process uses high-temperature injection molding to form a plastic package with multiple protective properties, and the reliability and yield stability of its materials and process parameters have been verified in mass production. High-precision chips such as low-power, low-offset dual-channel operational amplifiers are extremely sensitive to packaging stress. The stress generated by the curing shrinkage of conventional molding compounds and thermal mismatch during cooling can be transmitted to the chip through specific paths, causing micro-strain in the silicon-based active region, which in turn leads to the degradation of circuit performance.

[0003] Currently, the standard molding process used for general-purpose chips relies on high-temperature injection molding to fill the mold cavity with molten epoxy resin, encapsulating the chip, bonding wires, and part of the lead frame. After curing, a molded enclosure is formed to provide mechanical protection, moisture resistance, and thermal stability. However, the material system and process parameters of the existing standard molding process are only suitable for conventional chips and cannot solve the stress sensitivity problem of high-precision chips. It cannot suppress stress transmission paths, easily leading to performance issues such as transistor threshold voltage drift and excessive output voltage deviation. There is a lack of effective solutions that address the stress effects at the source of the packaging process without altering the chip structure. Summary of the Invention

[0004] This invention addresses the issue of insufficient output parameter drift accuracy in conventional plastic encapsulation of some high-precision chips. It reliably optimizes the encapsulation process and provides a chip plastic encapsulation method. Before encapsulation, adhesive is applied to the chip, covering it with the adhesive. The adhesive's extremely low modulus and low stress characteristics buffer the stress generated during encapsulation, thereby reducing the stress on the chip surface, resolving the output parameter drift problem, and improving the device's output accuracy. Furthermore, this method employs a suitable leadframe design and adhesive coating process to achieve adhesive coverage of the chip, internal leads, and bonding wires, avoiding reliability risks caused by bonding wires crossing the interface between the adhesive and the encapsulating material.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a method for encapsulating a chip, comprising the following steps: The circuit to be processed is subjected to wafer thinning, dicing, die bonding and wire bonding to obtain a wire-bonded semi-finished circuit. The pre-wire bonded semi-finished circuit is subjected to a dispensing process, which involves applying adhesive to the chip surface and using the structural constraints of the lead frame to extend and cover the chip, bonding wires, and internal pins. The circuit is then baked and cured to form a stress buffer layer that covers the chip, bonding wires, and internal pins. The chips that have been glued are then encapsulated, electroplated, printed, and separated to obtain the finished circuit.

[0006] Furthermore, the lead frame is a recessed lead frame, with the inner pins at the same horizontal height as the carrier, and the outer pins of the lead frame higher than the inner pins.

[0007] Furthermore, the lead frame is a non-drilled lead frame, with the inner pins, outer pins, and carrier all at the same horizontal height, and the inner pins having semi-etched holes or through holes.

[0008] Furthermore, there are gaps between the carrier and the inner pins of the lead frame, and between the inner pins themselves, with the width of the gaps not exceeding 200 μm.

[0009] Furthermore, the adhesive used in the dispensing process includes silicone rubber and fluorosilicone rubber.

[0010] Furthermore, the dispensing locations for the adhesive dispensing process are the chip surface and the outer side of the inner pins. The dispensing method for the chip is single-point diffusion or multi-point arrangement on the surface, while the dispensing method for the inner pins is rectangular dispensing on the outer side of the inner pins; the amount of adhesive dispensed each time is 1mm. 3 ~1.5mm 3 .

[0011] Furthermore, before dispensing the adhesive, the semi-finished circuit is subjected to plasma cleaning. Argon gas is used for plasma cleaning, with a cleaning power of 250~350W and a cleaning time of 8~12 seconds.

[0012] Furthermore, the thickness of the adhesive is 100~250μm.

[0013] Furthermore, the baking and curing temperature is 100~200℃, and the baking time is 0.5~4h.

[0014] Furthermore, the viscosity of the adhesive is between 3000 and 10000 mPa·s, and the elastic modulus after curing is less than 100 MPa.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves complete encapsulation of critical structures by coating adhesive onto the chip surface and constraining it with a lead frame structure to extend and cover the chip, bonding wires, and internal leads. A stress-buffered layer is formed by baking and curing, effectively dispersing the mechanical stress generated by the curing shrinkage of the epoxy molding compound during encapsulation, utilizing the adhesive's extremely low modulus. The chip, after adhesive application, is then encapsulated, electroplated, printed, and separated, ensuring the continuity of the packaging process. This design significantly reduces stress transmission on the chip surface, avoiding output parameter drift caused by molding stress in high-precision chips. Simultaneously, the complete encapsulation of the bonding wires and internal leads by the adhesive eliminates the reliability risks associated with bonding wires crossing different material interfaces, improving the device's output accuracy and long-term stability. Ultimately, this method achieves a comprehensive improvement in the reliability of high-precision chip packaging through process optimization without altering the chip structure design. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0017] Figure 1 This is a top view of the semi-finished circuit structure using a recessed lead frame in an embodiment of the present invention; Figure 2 This is a side view of the semi-finished circuit structure using a recessed lead frame in an embodiment of the present invention. Figure 3 This is a top view of the semi-finished circuit structure using a non-recessed lead frame in an embodiment of the present invention; Figure 4 This is a side view of the semi-finished circuit structure using a non-recessed lead frame in an embodiment of the present invention. Figure 5 This is a top view of the semi-finished circuit structure after dispensing, which uses a recessed lead frame in an embodiment of the present invention. Figure 6 This is a side view of the semi-finished circuit structure after dispensing, using a recessed lead frame in an embodiment of the present invention. Figure 7 This is a top view of the semi-finished circuit structure after dispensing, using a non-recessed lead frame in an embodiment of the present invention. Figure 8 This is a side view of the semi-finished circuit structure after dispensing, using a non-recessed lead frame in an embodiment of the present invention. In the diagram: 1. Chip; 2. Bonding wire; 3. Carrier; 4. Internal pin; 5. Dent position; 6. Half-etched hole or through hole; 7. Adhesive; 8. Lead frame. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can typically be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of the embodiments of this application, it should be noted that if terms such as "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this application is in use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of the embodiments of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following drawings indicate similar items; therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] The conventional packaging process for leadframe-type plastic-encapsulated devices for semiconductor integrated circuits includes wafer thinning, dicing, die bonding, plasma cleaning, wire bonding, encapsulation, electroplating, marking, and molding / cutting separation.

[0026] (1) Wafer thinning: The thickness of wafers manufactured by wafer fabs is generally 600-700μm. Due to the thickness of plastic-encapsulated devices, wafers of this thickness cannot be used directly and must be ground and thinned to meet the requirements of the packaging process. The commonly used wafer thickness is 200-300μm. For thin plastic-encapsulated devices, some products even need to be thinned to below 100μm. Before wafer thinning, a protective film needs to be pasted on the front side of the wafer to prevent damage to the wafer surface pattern.

[0027] (2) Dicing: Dicing is mainly to completely separate each chip on the wafer for subsequent chip assembly processes. First, a dicing blue film is attached to the back of the wafer. The wafer is then cut using a circular dicing blade on a dicing machine. After cutting, the chips are arranged neatly on the blue film.

[0028] (3) On-chip bonding: The individual chip is fixed on the lead frame with adhesive materials, such as conductive glue, insulating glue, DAF film, solder, solder paste, semi-nano silver paste, etc.

[0029] (4) Plasma cleaning: Plasma cleaning is a common process to improve the cleanliness of material surfaces and enhance interfacial bonding strength. Plasma cleaning performed after die bonding and before wire bonding can effectively remove residual contaminants from previous processes, greatly improve wire bonding strength, and effectively reduce the probability of failure. Plasma cleaning performed before encapsulation can increase the bonding force between the lead frame and the molding compound, improving product reliability.

[0030] (5) Wire bonding: Wire bonding is the process of connecting the chip pads and the pins of the lead frame using bonding wires to transmit the chip's circuit signals to the outside world. The bonding wires used typically include gold wire, copper wire, aluminum wire, and silver alloy wire. Bonding methods generally include thermoforming, ultrasonic bonding, and thermo-ultrasonic bonding.

[0031] (6) Encapsulation: The epoxy molding compound, which carries the chip, is pre-placed in the mold cavity. Molten epoxy resin, at high temperature, flows through the lead frame using injection molding technology, encapsulating part of the lead frame, chip, bonding wires, and other structures within it. This process does not cause significant deformation of the chip's internal structure, thus protecting and supporting the chip. The epoxy molding compound undergoes a polymerization reaction during and after encapsulation. This polymerization reaction gives the finished product good mechanical stability, moisture resistance, and heat resistance, protecting the electronic components from environmental influences.

[0032] (7) Electroplating: Electroplating is the process of applying a thin metal film to the surface of the lead frame using the principle of electrolysis. The main component of the lead frame is copper alloy, which is prone to oxidation. Usually, a protective plating layer (pure tin or tin-lead) is electroplated on the surface of the outer pins of the frame to improve the conductivity, solderability and oxidation resistance of the outer pins of the plastic packaged device.

[0033] (8) Marking: Use a laser marking machine to engrave words on the surface (front or back) of the plastic seal to distinguish different products and batches.

[0034] (9) Molding Separation / Cutting Separation: The outer leads are pressed into a predetermined shape, and the pre-packaged plastic devices on the entire lead frame are separated into independent devices. Leaded plastic devices are separated by a stamping system, while leadless plastic devices are separated by equipment similar to wafer dicing.

[0035] The above processes can be optimized, such as... Figure 5-8 As shown, this invention proposes a chip encapsulation method, comprising the following steps: The circuit to be processed is subjected to wafer thinning, dicing, die bonding and wire bonding to obtain a wire-bonded semi-finished circuit. The semi-finished circuit with wire bonding is subjected to dispensing treatment. The dispensing treatment involves applying glue 7 to the surface of chip 1 and constraining it with lead frame 8 to extend and cover chip 1, bonding wire 2 and inner pin 4. Then, it is baked and cured to form a stress buffer layer covering chip 1, bonding wire 2 and inner pin 4. The chip 1, after adhesive dispensing, is encapsulated, electroplated, printed, and separated to obtain the finished circuit.

[0036] This invention provides a high-reliability molding and encapsulation method for high-precision chips. Without altering the chip's structural design, it adds an adhesive dispensing process between wire bonding and encapsulation, allowing the adhesive to cover the chip, bonding wires, and internal leads in an approximately hemispherical shape. The adhesive acts as a stress buffer layer between the chip and the molding compound, reducing stress on the chip surface, resolving output parameter drift issues in high-precision products, and improving device output accuracy. Simultaneously, the lead frame structure is optimized, and the adhesive coverage is improved to achieve full adhesive coverage of the chip, internal leads, and bonding wires, avoiding reliability risks arising from bonding wires crossing the adhesive-molding compound interface.

[0037] In some specific embodiments, such as Figure 1-2 As shown, the lead frame 8 is a recessed lead frame. The inner lead 4 is at the same horizontal height as the carrier 3. The outer lead of the lead frame is higher than the inner lead 4. The recessed position 5 is where the outer lead is higher than the inner lead 4, and the recessed position 5 restricts the spread of adhesive. Figure 3-4 As shown, the lead frame 8 is a non-drilled lead frame. The inner pin 4, outer pin, and carrier 3 are all at the same horizontal height. The inner pin 4 has a semi-etched hole or through hole 6. By optimizing the structure of the lead frame 8, the range of adhesive spread is limited, so that it completely covers the surface of the chip 1, the bonding wire 2, and the top of the inner pin 4, forming a continuous and complete stress buffer layer; avoiding the risks of insufficient stress buffering and exposed bonding wires caused by excessively thin adhesive layers in some areas.

[0038] In some specific embodiments, there are gaps between the carrier 3 and the inner pin 4 of the lead frame 8, and between the inner pins 4 themselves, with the gap width not exceeding 200 μm. A suitable gap width prevents adhesive from flowing down along the gaps, ensuring that the amount of adhesive applied to the surface of the chip 1 is retained to the maximum extent within the target coverage area.

[0039] In some specific embodiments, the adhesive used for dispensing includes silicone rubber and fluorosilicone rubber; the thickness of the adhesive is 100~250μm. The viscosity of the adhesive is 3000-10000mPa·s, and the elastic modulus after curing is less than 100 MPa. Utilizing the low elastic modulus and controllable rheological properties of the adhesive, a stress buffer layer is formed on the surface of chip 1 through baking and curing. This buffer layer can effectively isolate the stress generated during the curing shrinkage of the epoxy molding compound and the thermal cycling process, thereby solving the degradation problems of key performance parameters of high-precision chips caused by molding stress, such as output voltage drift, input offset voltage deviation, and increased gain error.

[0040] The dispensing process involves applying adhesive to both the surface of chip 1 and the outer side of the inner pin 4. Under gravity, the adhesive on both surfaces radiates outwards from the center and fuses together, completely covering chip 1, bonding wire 2, and inner pin 4. The dispensing method for chip 1 is either single-point diffusion or multi-point arrangement on its surface, while the dispensing method for the inner pin 4 is a rectangular application of adhesive to the outer side of the inner pin. Each dispensing step involves approximately 1 mm of adhesive. 3 ~1.5mm 3 Do not apply too much adhesive at once, as this may result in an excessively thick adhesive layer.

[0041] In some specific embodiments, the semi-finished circuit is subjected to plasma cleaning before dispensing. Argon gas is used for plasma cleaning, with a cleaning power of 250-350W and a cleaning time of 8-12 seconds. Plasma cleaning improves the wettability of the adhesive, increases the adhesive spreading area, and ensures complete coverage of the chip 1, bonding wire 2, and internal pins 4.

[0042] In some specific embodiments, the baking and curing temperature is 100~200℃, and the baking time is 0.5~4h.

[0043] To make the technical problem to be solved, the technical solution, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0044] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under standard conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications in the art, unless otherwise stated.

[0045] Example 1 For a high-precision bandgap reference voltage source product, the chip size is 1.91mm*1.62mm, the thickness is 300μm, and it adopts the SOP8L package form. Its external dimensions are 4.9mm*3.9mm*1.4mm, and the external lead pitch is 1.27mm. The specific implementation of the method of the present invention is as follows: Step 1: The circuit to be processed is thinned and diced on a wafer. The die is then attached and wire bonded onto a recessed SOP8L lead frame to obtain a semi-finished circuit with wire bonds ready for adhesive application. The carrier 3 of the recessed lead frame has dimensions of 2.29mm x 3.04mm, and its inner leads 4 are at the same horizontal height as the carrier 3.

[0046] Step 2: The wire-bonded circuit is first subjected to plasma cleaning using pure argon gas at a power of 300W for 10 seconds. Within six hours of plasma cleaning, adhesive dispensing is performed using Wacker 988 silicone rubber. The adhesive is applied from chip 1 outwards to the recessed area of ​​the lead frame 8, completely covering chip 1, bonding wire 2, and inner leads 4. At this point, the adhesive morphology is approximately hemispherical with a thickness of 200μm. After dispensing, the circuit is baked at 150℃ for 30 minutes.

[0047] Step 3 involves encapsulating, electroplating, printing, and separating the dispensing-coated circuit to obtain the final finished circuit.

[0048] Example 2 For a certain high-precision bilateral amplifier product, the chip size is 3.38mm*1.95mm, the thickness is 150μm, and it adopts the QFN28L package form. Its external dimensions are 5mm*5mm*0.75mm and the external lead pitch is 0.5mm. The specific implementation of the method of the present invention is as follows: Step 1: The circuit to be processed is thinned and diced on a wafer. On a QFN28L lead frame, the core is attached and wire bonded to obtain a semi-finished circuit with wire bonded leads ready for adhesive application. The QFN28L lead frame is not recessed; its inner pins 4 are at the same horizontal level as the carrier 3 of the lead frame. The inner pins 4 have semi-etched holes 6. The carrier 3 has dimensions of 3.9mm x 3.9mm.

[0049] Step 2: The wire-bonded circuit is first subjected to plasma cleaning using pure argon gas at a power of 300W for 10 seconds. Six hours after plasma cleaning, adhesive dispensing is performed using Wacker 927F fluorosilicone rubber. The adhesive is applied from chip 1 outwards to the half-etched hole 6 of inner lead 4, completely covering chip 1, bonding wire 2, and inner lead 4. At this point, the adhesive morphology is approximately hemispherical with a thickness of 200μm. After dispensing, baking curing is performed at 175℃ for 1 hour.

[0050] Step 3 involves encapsulating, electroplating, printing, and cutting / separating the circuit after adhesive dispensing to obtain the final finished circuit.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can still make modifications or equivalent substitutions to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the claims of the present invention pending approval.

Claims

1. A method for encapsulating a chip, characterized in that, Includes the following steps: The circuit to be processed is subjected to wafer thinning, dicing, die bonding and wire bonding to obtain a wire-bonded semi-finished circuit. The semi-finished circuit with wire bonding is subjected to dispensing treatment. The dispensing treatment is to apply glue to the surface of the chip (1) and extend it to cover the chip (1), bonding wire (2) and inner pin (4) by the structural constraint of the lead frame (8). Then, it is baked and cured to form a stress buffer layer covering the chip (1), bonding wire (2) and inner pin (4). The chip (1) after dispensing is encapsulated, electroplated, printed and separated to obtain the finished circuit.

2. The chip encapsulation method according to claim 1, characterized in that, The lead frame (8) is a recessed lead frame, with the inner pin (4) and the carrier (3) at the same horizontal height, and the outer pin of the lead frame (8) being higher than the inner pin (4).

3. The chip encapsulation method according to claim 1, characterized in that, The lead frame (8) is a non-drilled lead frame. The inner pin (4), the outer pin, and the carrier (3) are all at the same horizontal height. The inner pin (4) is provided with a semi-etched hole or a through hole (6).

4. The chip encapsulation method according to claim 1, characterized in that, There are gaps between the carrier (3) and the inner pin (4) of the lead frame (8), and between the inner pin (4) and the inner pin (4), and the width of the gap does not exceed 200μm.

5. The chip encapsulation method according to claim 1, characterized in that, The adhesives used in the dispensing process include silicone rubber and fluorosilicone rubber.

6. The chip encapsulation method according to claim 1, characterized in that, The dispensing locations for the dispensing process are the surface of the chip (1) and the outer side of the inner pin (4). The dispensing method for the chip (1) is single-point diffusion or multi-point arrangement on the surface, and the dispensing method for the inner pin (4) is rectangular dispensing on the outer side of the inner pin. The amount of adhesive dispensed each time is 1 mm. 3 ~1.5mm 3 .

7. The chip encapsulation method according to claim 1, characterized in that, Before dispensing, the semi-finished circuit is subjected to plasma cleaning. Argon gas is used for plasma cleaning, with a cleaning power of 250~350W and a cleaning time of 8~12 seconds.

8. The chip encapsulation method according to claim 1, characterized in that, The thickness of the adhesive is 100~250μm.

9. The chip encapsulation method according to claim 1, characterized in that, The baking and curing temperature is 100~200℃, and the baking time is 0.5~4h.

10. The chip encapsulation method according to claim 1, characterized in that, The viscosity of the adhesive is 3000~10000 mPa·s, and the elastic modulus after curing is less than 100 MPa.

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