Semiconductor device and power conversion device

Abstract

The invention provides a semiconductor device and a power conversion device with improved reliability. A device (10) is provided on a semiconductor substrate (1). The metal wiring (4) is provided on the upper surface of the semiconductor substrate (1) and is connected to the device (10). The passivation film (5) is an inorganic insulating film covering the corners of the metal wiring (4), and has an opening (6) provided in the upper surface of the metal wiring (4). The organic protective film (7) covers the metal wiring (4) exposed from the opening (6).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and power conversion devices. Background Technology

[0002] In a semiconductor device, a passivation film covers metal wiring disposed on a semiconductor substrate (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 04-348523

[0004] Previously, passivation films were formed to uniformly cover the metal wiring, making them susceptible to damage from thermal stress. Furthermore, since an organic protective film is placed on top of the passivation film, if the metal wiring is exposed from the passivation film, an organic protective film and interface are formed. However, at the interface between the corners of the metal wiring where the electric field is concentrated and the organic protective film, the organic protective film reacts and deteriorates, leading to reduced reliability issues such as moisture resistance and durability. Summary of the Invention

[0005] This disclosure is made to solve the aforementioned problems, and its purpose is to obtain semiconductor devices and power conversion devices that can improve reliability.

[0006] The semiconductor device disclosed herein is characterized by comprising: a semiconductor substrate on which a device is disposed; a metal wiring disposed on the upper surface of the semiconductor substrate and connected to the device; a passivation film, which is an inorganic insulating film covering the corners of the metal wiring and having an opening disposed on the upper surface of the metal wiring; and an organic protective film covering the metal wiring exposed from the opening.

[0007] In this disclosure, an opening is provided in the passivation film on the upper surface of the metal wiring. This allows the passivation film to mitigate thermal stress from the metal wiring and suppress cracking. Furthermore, the passivation film covers the corners of the metal wiring. Consequently, the electric field concentration areas of the metal wiring do not come into contact with the organic protective film, thus suppressing degradation of the organic protective film at the interface between the organic protective film and the metal wiring. Therefore, peeling of the organic protective film can be prevented, improving moisture resistance. As a result, reliability, such as durability, can be improved. Attached Figure Description

[0008] Figure 1 This is a top view showing the semiconductor device of Embodiment 1.

[0009] Figure 2 Is Figure 1 The top view of the organic protective film is omitted.

[0010] Figure 3 It is along Figure 1A cross-sectional view of the outer periphery of the chip in the direction of the short side of section I-II.

[0011] Figure 4 It is along Figure 1 A sectional view of the corner section of III-IV.

[0012] Figure 5 This is an enlarged top view of a portion of a variation of the semiconductor device of Embodiment 1.

[0013] Figure 6 This is a top view showing the semiconductor device of Embodiment 2.

[0014] Figure 7 This is a top view showing the semiconductor device of Embodiment 3.

[0015] Figure 8 This is a top view of a portion of the semiconductor device in Embodiment 3, magnified.

[0016] Figure 9 This is a top view showing the semiconductor device of Embodiment 4.

[0017] Figure 10 It is along Figure 9 Sectional view I-II.

[0018] Figure 11 This is an enlarged top view of a portion of a modified example of the semiconductor device of Embodiment 4.

[0019] Figure 12 This is a top view showing the semiconductor device of Embodiment 5.

[0020] Figure 13 This is a top view showing the semiconductor device of Embodiment 6.

[0021] Figure 14 This is an enlarged top view of a portion of a modified example 1 of the semiconductor device according to embodiment 6.

[0022] Figure 15 This is a magnified top view of a portion of a variation 2 of the semiconductor device of Embodiment 6.

[0023] Figure 16 This is a top view showing the semiconductor device of Embodiment 7.

[0024] Figure 17 It is along Figure 16 Sectional view I-II.

[0025] Figure 18 This is a block diagram showing the structure of the power conversion system of the power conversion device according to embodiment 8.

[0026] Explanation of reference numerals in the attached figures: 1...semiconductor substrate; 2...source electrode (metal wiring); 4...gate wiring (metal wiring); 5...passivation film; 6...opening; 7...organic protective film; 10...device; 23...residual area; 200...power conversion device; 201...main conversion circuit; 202...drive circuit; 203...control circuit. Detailed Implementation

[0027] The semiconductor device and power conversion device of the embodiments will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and sometimes repeated descriptions are omitted.

[0028] Implementation Method 1

[0029] Figure 1 This is a top view showing the semiconductor device of Embodiment 1. Figure 2 Is Figure 1 The top view of the organic protective film is omitted. A source electrode 2 is disposed at the center of the upper surface of the semiconductor substrate 1. A gate pad 3 and a gate wiring 4 connected thereto are disposed in the outer peripheral region around the source electrode 2 on the upper surface of the semiconductor substrate 1. The aforementioned source electrode 2, gate pad 3, and gate wiring 4 are metal wirings.

[0030] A passivation film 5 is disposed on the semiconductor substrate 1, the outer periphery of the source electrode 2, the outer periphery of the gate pad 3, and the gate wiring 4. The passivation film 5 is, for example, a nitride film. The passivation film 5 covers the metal wiring at the termination portion to protect the termination area. An opening 6 is provided on the passivation film 5 at the outermost periphery of the gate pad 3 and on the gate wiring 4.

[0031] An organic protective film 7 is disposed on the semiconductor substrate 1, the passivation film 5, and the gate wiring 4. The organic protective film 7 protects the semiconductor substrate 1 by covering the areas without the passivation film 5. The passivation film 5 and the organic protective film 7 provide waterproofing and oxidation protection. In addition, in order to achieve electrical contacts such as wire bonding, the central portion of the gate pad 3 and the central portion of the source electrode 2 are exposed instead of being covered by the passivation film 5.

[0032] Figure 3 It is along Figure 1A cross-sectional view of the chip along the short side of the outer periphery of section I-II. In the semiconductor substrate 1, an outer peripheral region 9 is formed to surround the active region 8 through which the main current flows. A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is disposed in the active region 8 as a device 10. However, this is not a limitation; a Schottky diode, an IGBT (Insulated Gate Bipolar Transistor), or other similar device may also be disposed as device 10.

[0033] In semiconductor substrate 1, in N － A P-type layer 12 is disposed on top of the P-type drift layer 11. An N-type source region 13 is disposed on a portion of the P-type layer 12. An N-type source region 13 is located in the outer peripheral region 9 of the semiconductor substrate 1. － A P-type pressure-resistant retaining structure 14 is provided above the drift layer 11. In the N... － An N-type channel stopping region 15 is provided on the outermost periphery above the drift layer 11. － N is set below the drift layer 11 + Type 16 drain layer.

[0034] In the active region 8 of the semiconductor substrate 1, a gate electrode 18 is formed on the P-type layer 12 via a gate insulating film 17. An insulating oxide film 19 is disposed on the outer peripheral region 9 of the semiconductor substrate 1, covering a portion of the P-type withstand voltage holding structure 14 and the N-type channel stop region 15 to protect the semiconductor substrate 1. An insulating oxide film 20 is disposed such that it covers the semiconductor substrate 1, the gate electrode 18, and the insulating oxide film 19. The insulating oxide films 19 and 20 are, for example, silicon oxide films.

[0035] In the active region 8, a source electrode 2 is disposed on the insulating oxide film 20 via a barrier metal 21. The source electrode 2 passes through an opening in the insulating oxide film 20 and is connected to the N-type source region 13. In the peripheral region 9, a gate wiring 4 is disposed on the insulating oxide film 20 via a barrier metal 21. The gate wiring 4 passes through an opening in the insulating oxide film 20 and is connected to the lead-out portion of the gate electrode 18 that is led out onto the insulating oxide film 19. Therefore, the gate wiring 4 and the source electrode 2 disposed on the upper surface of the semiconductor substrate 1 are electrically connected to the device 10. In addition, the drain electrode 22 is disposed on the lower surface of the semiconductor substrate 1 and connected to the N-type source region 13. + Type 16 drain layer.

[0036] A passivation film 5 covers the semiconductor substrate 1, the gate wiring 4, and the source electrode 2. An opening 6 is formed along the gate wiring 4 on the upper surface of the passivation film 5. The passivation film 5 covers the side surfaces of the gate wiring 4 and the outer edge of the upper surface of the gate wiring 4. Multiple openings 6 may also be formed on the gate wiring 4. The lateral width of the opening 6 is smaller than the lateral width of the gate wiring 4. An organic protective film 7 covers the gate wiring 4 exposed through the opening 6 for protection.

[0037] The passivation film 5 has a thickness of 0.5 μm to 2 μm. The passivation film 5 is formed, for example, by CVD. A resist film is coated on the passivation film 5, and an etching process is performed after overlapping photomasks and photosensitive treatment, thereby forming the opening 6 of the passivation film 5.

[0038] Figure 4 It is along Figure 1 A cross-sectional view of the corner portion of III-IV. The structure of the corner portion of semiconductor substrate 1 is basically the same as... Figure 3 Similarly, but the area between the outer end of the insulating oxide film 20 and the end of the semiconductor substrate 1 is larger than that between the outer end of the insulating oxide film 20 and the end of the semiconductor substrate 1. Figure 3 The corners are wide. Therefore, they are easily affected by the thermal stress of the passivation film 5 and the adhesive strength of the organic protective film 7.

[0039] The larger the area of ​​the continuous passivation film 5, the greater the thermal stress experienced by the gate wiring 4. Therefore, in this embodiment, an opening 6 is provided in the passivation film 5 on the upper surface of the gate wiring 4. As a result, the passivation film 5 can mitigate the thermal stress experienced by the gate wiring 4 during environmental changes or driving, and suppress the formation of cracks in the passivation film 5. In addition, the shape of the organic protective film 7 entering the opening 6 provides an anchoring effect, improving the adhesion of the organic protective film 7.

[0040] Furthermore, the electric field is concentrated at the corner between the upper surface and the side surface of the gate wiring 4. Therefore, the passivation film 5 covers the corner of the gate wiring 4. As a result, the electric field concentration area of ​​the gate wiring 4 does not come into contact with the organic protective film 7, thus suppressing the degradation of the organic protective film 7 at the interface between the organic protective film 7 and the gate wiring 4. Therefore, the peeling of the organic protective film 7 can be prevented, thereby improving moisture resistance. As a result, reliability such as durability can be improved.

[0041] Furthermore, it is preferable that the lateral width w of the finest portion of the passivation film 5 covering the outer edge of the upper surface of the gate wiring 4 is greater than the thickness of the passivation film 5. This prevents the opening 6 from reaching the corner of the gate wiring 4 and exposing the corner of the gate wiring 4.

[0042] When viewed from above, the gate wiring 4 is disposed along the outer periphery of the semiconductor substrate 1 in the outer peripheral region 9. Therefore, when viewed from above, the opening 6 disposed on the upper surface of the gate wiring 4 is disposed along the outer periphery of the semiconductor substrate 1 in the outer peripheral region 9. As a result, the thermal stress on the passivation film 5 can be mitigated over a large area. In addition, the opening 6 is disposed only on the upper surface of the gate wiring 4. As a result, the contact area between the semiconductor substrate 1 and the organic protective film 7 is reduced, thereby suppressing the deterioration of the contact interface.

[0043] The passivation film 5 is, for example, a nitride film, but it can be an inorganic insulating film. If the passivation film 5 is a silicon nitride film, it can ensure moisture resistance, suppress the influence of electric fields, and suppress the reduction of the interface strength with the organic protective film 7.

[0044] Figure 5 This is an enlarged top view of a portion of a modified example of the semiconductor device according to Embodiment 1. When viewed from above, the opening 6 of the passivation film 5 is wavy. Therefore, the planar shape of the opening 6 does not have an acute angle of less than 90 degrees. This eliminates stress concentration areas, further reducing the load on the passivation film 5, and thus further improving reliability.

[0045] Implementation Method 2

[0046] Figure 6 This is a top view showing the semiconductor device according to Embodiment 2. An opening 6 is provided only at the corner of the semiconductor substrate 1 on the passivation film 5 above the gate wiring 4. By providing the opening 6 at the corner where stress easily concentrates, the generation of cracks in the passivation film 5 can be suppressed. Furthermore, since the gate wiring 4 outside the corner is covered by the passivation film 5, the area covered by the passivation film 5 and protecting the gate wiring 4 can be increased. Other structures and effects are the same as in Embodiment 1.

[0047] Implementation Method 3

[0048] Figure 7 This is a top view showing the semiconductor device of Embodiment 3. Figure 8 This is a magnified top view of a portion of the semiconductor device according to Embodiment 3. An opening 6 is provided along the gate wiring 4 in the passivation film 5. Multiple residual regions 23 of the passivation film 5 are present inside the opening 6.

[0049] By providing multiple residual regions 23, the area covered and protected by the passivation film 5 can be expanded. Furthermore, the organic protective film 7 enters the opening 6 where the multiple residual regions 23 exist, exerting an anchoring effect and further improving the adhesion of the organic protective film 7. Other structures and effects are the same as in Embodiment 1.

[0050] Implementation Method 4

[0051] Figure 9 This is a top view showing the semiconductor device of Embodiment 4. Figure 10 It is along Figure 9 The cross-sectional view is shown in section I-II. This embodiment differs from Embodiment 1 in the location of the opening 6. The passivation film 5 covers the outer periphery of the source electrode 2. When viewed from above, the opening 6 is located along the outer periphery of the source electrode 2. Therefore, the passivation film 5 can mitigate thermal stress from the source electrode 2 during environmental changes or driving, and suppress the formation of cracks in the passivation film 5. Furthermore, the shape of the organic protective film 7 entering the opening 6 provides an anchoring effect, improving the adhesion of the organic protective film 7.

[0052] Furthermore, the electric field is concentrated at the corner between the upper surface and the side surface of the source electrode 2. Therefore, the passivation film 5 covers the corner of the source electrode 2. As a result, the electric field concentration area of ​​the source electrode 2 does not come into contact with the organic protective film 7, thus suppressing the degradation of the organic protective film 7 at the interface where the electric field is concentrated. Therefore, peeling of the organic protective film 7 can be prevented, thereby improving moisture resistance. As a result, reliability such as durability can be improved.

[0053] Figure 11 This is an enlarged top view of a portion of a modified example of the semiconductor device according to Embodiment 4. When viewed from above, the opening 6 of the passivation film 5 is wavy. Therefore, the planar shape of the opening 6 does not have an acute angle of less than 90 degrees. This eliminates stress concentration areas, further reducing the load on the passivation film 5, and thus further improving reliability.

[0054] Implementation Method 5

[0055] Figure 12 This is a top view of the semiconductor device according to Embodiment 5. An opening 6 is provided only at the corner of the source electrode 2 in the passivation film 5 covering the outer periphery of the source electrode 2. By providing the opening 6 at the corner where stress easily concentrates, the generation of cracks in the passivation film 5 can be suppressed. Furthermore, since the source electrode 2 outside the corner is covered by the passivation film 5, the area covered and protected by the passivation film 5 can be increased. Other structures and effects are the same as in Embodiment 4.

[0056] Implementation Method 6

[0057] Figure 13 This is a top view showing the semiconductor device according to Embodiment 6. An opening 6 is provided in the passivation film 5 at the outer periphery of the source electrode 2. Multiple residual regions 23 of the passivation film 5 are present inside the opening 6.

[0058] By providing multiple residual regions 23, the area covered and protected by the passivation film 5 on the outer periphery of the source electrode 2 can be expanded. Furthermore, the organic protective film 7 enters the opening 6 where the multiple residual regions 23 exist, exerting an anchoring effect and further improving the adhesion of the organic protective film 7. Other structures and effects are the same as in embodiment 4.

[0059] Figure 14 This is an enlarged top view of a portion of a modified example 1 of the semiconductor device according to embodiment 6. The remaining region 23 is quadrilateral. Figure 15 This is an enlarged top view of a portion of a variation 2 of the semiconductor device according to Embodiment 6. The residual region 23 is triangular. However, if there are sharp parts in the residual region 23, stress will concentrate in those parts. Therefore, it is preferable to assign R to all the angles of the residual region 23. That is, the residual region 23 is preferably a polygon or a circle without sharp angles.

[0060] Implementation Method 7

[0061] Figure 16 This is a top view showing the semiconductor device of Embodiment 7. Figure 17 It is along Figure 16 The diagram shows a cross-sectional view along line I-II. Openings 6 are located on both the upper surface of the gate wiring 4 and the outer periphery of the source electrode 2. The anchoring effect on both sides further improves the adhesion of the organic protective film 7, and the large openings 6 further alleviate the thermal stress on the passivation film 5 and suppress crack formation in the passivation film 5. Furthermore, the shapes of the openings 6 on both sides can be identical or a combination of different shapes.

[0062] Furthermore, the semiconductor substrate 1 is not limited to being formed of silicon; it can also be formed of a wide-bandgap semiconductor with a larger bandgap than silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, or diamond. Semiconductor devices formed from such wide-bandgap semiconductors exhibit high voltage withstand capability and allowable current density, thus enabling miniaturization. By using this miniaturized semiconductor device, semiconductor modules assembled with it can also be miniaturized and highly integrated. Additionally, due to the high heat resistance of the semiconductor device, the heat sink can be miniaturized, and the water-cooling section can be air-cooled, further enabling miniaturization of the semiconductor module. Furthermore, the low power loss and high efficiency of the semiconductor device allow for high efficiency in the semiconductor module.

[0063] Implementation Method 8

[0064] This embodiment applies the semiconductor device from any of the embodiments 1 to 7 described above to a power conversion device. Although this disclosure is not limited to a specific power conversion device, the following describes, as embodiment 8, the application of this disclosure to a three-phase inverter.

[0065] Figure 18 This is a block diagram illustrating the structure of a power conversion system using the power conversion device of Embodiment 8. The power conversion system includes a power source 50, a power conversion device 200, and a load 300. The power source 50 is a DC power source, supplying DC power to the power conversion device 200. The power source 50 can be composed of various components, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 50 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0066] The power conversion device 200 is a three-phase inverter connected between the power supply 50 and the load 300, which converts the DC power supplied from the power supply 50 into AC power and supplies AC power to the load 300. The power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals to drive the switching elements of the main conversion circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0067] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. Furthermore, load 300 is not limited to a specific application, but can be a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or for air conditioning equipment.

[0068] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and circulating diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power source 50 into AC power and supplies it to the load 300. Although the specific circuit structure of the main conversion circuit 201 can vary, in this embodiment, the main conversion circuit 201 is a two-level three-phase full-bridge circuit with six switching elements and six circulating diodes connected in anti-parallel to each switching element. Each switching element of the main conversion circuit 201 uses a semiconductor device from any of the embodiments 1 to 7 described above. In the six switching elements, every two switching elements are connected in series to form upper and lower branches, and each upper and lower branch constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower branch, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0069] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, based on the control signal from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is held on, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is held off, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0070] The control circuit 203 controls the switching elements of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, it calculates the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on-time of the switching elements according to the output voltage. Furthermore, a control command (control signal) is output to the drive circuit 202 so that an on signal is output for each switching element that is in the on state at each time, and an off signal is output for each switching element that is in the off state. The drive circuit 202 outputs an on or off signal to the control electrode of each switching element as a drive signal according to the control signal.

[0071] In the power conversion device of this embodiment, a semiconductor device from any of the embodiments 1 to 7 is used as the switching element of the main conversion circuit 201, thereby improving reliability.

[0072] This embodiment describes an example of applying the present disclosure to a 2-level three-phase inverter, but the present disclosure is not limited thereto and can be applied to various power conversion devices. Although this embodiment describes a 2-level power conversion device, it can also be a 3-level or multi-level power conversion device, and the present disclosure can also be applied to a single-phase inverter when supplying power to a single-phase load. In addition, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter when supplying power to a DC load, etc.

[0073] Furthermore, the power conversion device disclosed herein is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machines, induction heating regulators, or contactless power supply systems, and can also be used as a power regulator for solar power generation systems or energy storage systems.

[0074] While the preferred embodiments have been described in detail above, the present invention is not limited to these embodiments. Various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. Hereinafter, various aspects of this disclosure will be described in detail as appendices.

[0075] (Note 1) A semiconductor device, characterized in that it comprises:

[0076] A semiconductor substrate on which devices are disposed;

[0077] Metal wiring is disposed on the upper surface of the semiconductor substrate and connected to the device;

[0078] A passivation film, which is an inorganic insulating film covering the corners of the metal wiring, having an opening on the upper surface of the metal wiring; and

[0079] An organic protective film covers the metal wiring exposed from the opening.

[0080] (Note 2) The semiconductor device according to Note 1 is characterized in that,

[0081] The metal wiring includes gate wiring disposed in the outer peripheral region of the semiconductor substrate.

[0082] The opening is located on the upper surface of the gate wiring.

[0083] (Note 3) The semiconductor device according to Note 2 is characterized in that,

[0084] When viewed from above, the opening is only located at the corner of the semiconductor substrate.

[0085] (Note 4) The semiconductor device according to Note 1 is characterized in that,

[0086] The metal wiring has a source electrode.

[0087] The passivation film covers the outer periphery of the source electrode.

[0088] The opening is located on the outer periphery of the source electrode.

[0089] (Note 5) The semiconductor device according to Note 4 is characterized in that,

[0090] When viewed from above, the opening is only located at the corner of the source electrode.

[0091] (Note 6) The semiconductor device according to Note 1 is characterized in that,

[0092] The metal wiring has a gate wiring and a source electrode.

[0093] The passivation film covers the outer periphery of the gate wiring and the source electrode.

[0094] The opening is located on both the upper surface of the gate wiring and the outer periphery of the source electrode.

[0095] (Appendix 7) The semiconductor device according to any one of Appendices 1 to 6, characterized in that,

[0096] Multiple residual regions of the passivation film exist inside the opening.

[0097] (Note 8) The semiconductor device according to Note 7 is characterized in that,

[0098] The residual area is a polygon or circle without acute angles.

[0099] (Appendix 9) The semiconductor device according to any one of Appendices 1 to 8, characterized in that,

[0100] The lateral width of the thinnest portion of the passivation film covering the outer edge of the upper surface of the metal wiring is greater than the thickness of the passivation film.

[0101] (Note 10) The semiconductor device according to any one of Notes 1 to 9, characterized in that,

[0102] The planar shape of the opening does not have an acute angle of less than 90 degrees.

[0103] (Note 11) The semiconductor device according to any one of Notes 1 to 10, characterized in that,

[0104] The opening is only provided on the upper surface of the metal wiring.

[0105] (Note 12) The semiconductor device according to any one of Notes 1 to 11, characterized in that,

[0106] The passivation film is a silicon nitride film.

[0107] (Note 13) The semiconductor device according to any one of Notes 1 to 12, characterized in that,

[0108] The semiconductor substrate is formed of a wide-bandgap semiconductor.

[0109] (Appendix 14) A power conversion device, characterized in that it comprises:

[0110] A main conversion circuit having a semiconductor device as described in any one of Appendices 1 to 13, which converts and outputs the input power;

[0111] A driving circuit that outputs a driving signal to the semiconductor device; and

[0112] The control circuit outputs control signals to the drive circuit.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate on which devices are disposed; Metal wiring is disposed on the upper surface of the semiconductor substrate and connected to the device; A passivation film is an inorganic insulating film that covers the corners of the metal wiring and has an opening on the upper surface of the metal wiring. as well as An organic protective film covers the metal wiring exposed from the opening.

2. The semiconductor device according to claim 1, characterized in that, The metal wiring includes gate wiring disposed in the outer peripheral region of the semiconductor substrate. The opening is located on the upper surface of the gate wiring.

3. The semiconductor device according to claim 2, characterized in that, When viewed from above, the opening is only located at the corner of the semiconductor substrate.

4. The semiconductor device according to claim 1, characterized in that, The metal wiring has a source electrode. The passivation film covers the outer periphery of the source electrode. The opening is located on the outer periphery of the source electrode.

5. The semiconductor device according to claim 4, characterized in that, When viewed from above, the opening is only located at the corner of the source electrode.

6. The semiconductor device according to claim 1, characterized in that, The metal wiring has a gate wiring and a source electrode. The passivation film covers the outer periphery of the gate wiring and the source electrode. The opening is located on both the upper surface of the gate wiring and the outer periphery of the source electrode.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, Multiple residual regions of the passivation film exist inside the opening.

8. The semiconductor device according to claim 7, characterized in that, The residual area is a polygon or circle without acute angles.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that, The lateral width of the thinnest portion of the passivation film covering the outer edge of the upper surface of the metal wiring is greater than the thickness of the passivation film.

10. The semiconductor device according to any one of claims 1 to 6, characterized in that, The planar shape of the opening does not have an acute angle of less than 90 degrees.

11. The semiconductor device according to any one of claims 1 to 6, characterized in that, The opening is only provided on the upper surface of the metal wiring.

12. The semiconductor device according to any one of claims 1 to 6, characterized in that, The passivation film is a silicon nitride film.

13. The semiconductor device according to any one of claims 1 to 6, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.

14. A power conversion device, characterized in that, have: A main conversion circuit having a semiconductor device as described in any one of claims 1 to 6, which converts and outputs the input power; A driving circuit that outputs a driving signal to the semiconductor device; as well as The control circuit outputs control signals to the drive circuit.

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