Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof, and the structure comprises a substrate which comprises a front surface and a back surface opposite to the front surface, the substrate is provided with a groove, and the front surface of the substrate is exposed out of the groove; the electronic component is arranged in the groove, and the electronic component is electrically connected with the substrate; the chip is arranged on the front surface of the substrate, and the chip is electrically connected with the front surface of the substrate; the bottom filling layer is arranged on the front surface of the substrate and covers the side wall of the chip and the top surface and the side wall of the electronic component; the heat dissipation body structure is arranged on the substrate and surrounds the electronic component and the chip, the inner wall of the heat dissipation body structure and the front face of the substrate define a containing cavity, the inner wall of the heat dissipation body structure makes contact with the chip, and the electronic component and the chip are both located in the containing cavity. The risk that the material overflowed by melting of the heat sink structure in a high-temperature process is in contact with an electronic component can be reduced, and the reliability of the packaging structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a packaging structure and a method for forming the same. Background Technology

[0002] With the rapid development of electronic information technology, semiconductor packaging technology continues to evolve towards higher density, higher performance, and miniaturization. Under this trend, flip-chip packaging structures are widely used due to their excellent electrical performance and high integration density. To meet the increasing heat dissipation demands, enhanced heat dissipation solutions using metal thermal interface materials and heat sinks have become a common choice for high-performance packaging designs. Meanwhile, to achieve system-level functionality, passive electronic components such as capacitors, resistors, and inductors are typically integrated with the chip on the same front side of a substrate, forming a more compact system-in-package or heterogeneous integrated module.

[0003] In existing packaging architectures, electronic components are usually surface-mounted on the front of the substrate and together with the chip form a circuit functional unit. To ensure the stability of the components in subsequent processes and service, a protective dielectric layer is often formed on their surface. At the same time, the heat dissipation module is usually composed of a metal thermal interface material located above the chip and a heat dissipation cover surrounding the chip. The heat dissipation cover is fixed to the substrate by adhesive material and together with the substrate surface forms a package structure that accommodates the chip and components.

[0004] Currently, the reliability of the packaging structure still needs to be improved. Summary of the Invention

[0005] The problem addressed by this disclosure is to provide a packaging structure and a method for forming the same, which improves both the performance and integration density of the packaging structure. To address the aforementioned issues, this disclosure provides a packaging structure comprising: a substrate, the substrate having a front side and a back side opposite to it, a groove being provided in the substrate, and the front side of the substrate exposing the groove; an electronic component disposed in the groove and electrically connected to the substrate; a chip disposed on the front side of the substrate and electrically connected to the front side of the substrate; a bottom filler layer disposed on the front side of the substrate and covering the sidewalls of the chip and the top surface and sidewalls of the electronic component; and a heat sink structure disposed on the substrate and surrounding the electronic component and the chip, the inner wall of the heat sink structure forming a receiving cavity with the front side of the substrate, the inner wall of the heat sink structure contacting the chip, and both the electronic component and the chip being located within the receiving cavity.

[0006] Optionally, the number of grooves can be one or more.

[0007] Optionally, the number of electronic components disposed in the groove may be one or more.

[0008] Optionally, the top of the electronic components is lower than the front side of the substrate.

[0009] Optionally, electronic components include one or more of capacitors, resistors, inductors, and chips.

[0010] Optionally, the horizontal distance between the side edge of the chip and the side edge of the electronic component is less than 4 mm.

[0011] Optionally, one or more circuit layers are formed in the substrate, and the top circuit layer is exposed on the front side of the substrate; the packaging structure further includes: a first conductive bump disposed on the front side of the chip, and the first conductive bump is electrically connected to the circuit layer.

[0012] Optionally, the bottom filler layer is also disposed between the chip and the substrate, and the bottom filler layer also covers the first conductive bump.

[0013] Optionally, the bottom filler layer also fills the recesses where electronic components are exposed.

[0014] Optionally, the material for the bottom filler layer may include epoxy resin.

[0015] Optionally, the heat sink structure includes: a thermally conductive layer located on the chip; and a heat sink cover located on the substrate and surrounding the electronic components and the chip, with the inner wall of the heat sink cover in contact with the top surface of the thermally conductive layer.

[0016] Optionally, the packaging structure further includes: an adhesive layer located on the substrate and surrounding the electronic components and chips; a heat sink located on the adhesive layer, and the inner wall of the heat sink, the inner wall of the adhesive layer, and the front side of the substrate forming a receiving cavity.

[0017] Optionally, one or more circuit layers are formed in the substrate, and the bottom circuit layer is exposed on the back side of the substrate; the packaging structure further includes: a second conductive bump located on the back side of the substrate, and the second conductive bump is electrically connected to the bottom circuit layer.

[0018] Accordingly, this disclosure also provides a method for forming a package structure, comprising: providing a substrate, the substrate including a front side and a back side opposite to it, a groove formed in the substrate, and the front side of the substrate exposing the groove; disposing electronic components in the groove, and the electronic components being electrically connected to the substrate; disposing a chip on the front side of the substrate, and the chip being electrically connected to the front side of the substrate; after forming the electronic components and the chip, forming a bottom filling layer on the front side that covers the sidewalls of the chip and the top surface and sidewalls of the electronic components; after forming the bottom filling layer, disposing a heat sink structure surrounding the electronic components and the chip on the substrate, the inner wall of the heat sink structure and the front side of the substrate forming a receiving cavity, the inner wall of the heat sink structure contacting the chip, and both the electronic components and the chip being located within the receiving cavity.

[0019] Optionally, the process of placing electronic components in the groove includes a mounting process.

[0020] Optionally, after setting the electronic components in the groove, the chip is set on the front side of the substrate.

[0021] Optionally, the process of setting the chip on the front side of the substrate includes flip-chip technology.

[0022] Optionally, in the step of setting the chip on the front side of the substrate, the horizontal distance between the side edge of the chip and the side edge of the electronic component is less than 4 mm.

[0023] Optionally, in the step of providing the substrate, one or more circuit layers are formed in the substrate, and the top circuit layer is exposed on the front side of the substrate; the step of setting the chip on the front side of the substrate includes: providing the chip, a first conductive bump being formed on the back side of the chip; facing the back side of the chip toward the front side of the substrate, and soldering the first conductive bump to the front side of the substrate, wherein the first conductive bump is electrically connected to the circuit layer.

[0024] Optionally, in the step of forming the underfill layer, the underfill layer is also formed between the chip and the substrate, and the underfill layer also covers the first conductive bump.

[0025] Optionally, the process of setting the chip on the front side of the substrate includes flip-chip technology.

[0026] Optionally, the step of setting a heat sink structure on the substrate includes: setting a thermally conductive layer on the chip; setting a heat sink cover on the substrate that surrounds the electronic components and the chip, wherein the inner wall of the heat sink cover is in contact with the top surface of the thermally conductive layer.

[0027] Optionally, the step of setting a heat sink on the substrate includes: setting an adhesive layer surrounding the electronic components and chips on the substrate; setting a heat sink on the adhesive layer, wherein the inner wall of the heat sink, the inner wall of the adhesive layer, and the front side of the substrate form a receiving cavity.

[0028] Optionally, in the step of providing the substrate, one or more circuit layers are formed in the substrate, and the bottom circuit layer is exposed on the back side of the substrate; after the heat sink structure is provided, the forming method further includes: forming a second conductive bump on the back side of the substrate, and the second conductive bump is electrically connected to the bottom circuit layer.

[0029] Compared with the prior art, the technical solution of the present disclosure has the following advantages: The packaging structure provided in this embodiment includes a groove in the substrate, with the groove exposed on the front side of the substrate. Electronic components are disposed in the groove and electrically connected to the substrate. A bottom filler layer is disposed on the front side of the substrate and covers the sidewalls of the chip and the top and sidewalls of the electronic components. The bottom filler layer protects the electronic components in the groove and the chip on the front side of the substrate. During the heat sink structure construction, the risk of material from the heat sink melting and overflowing during high-temperature processes coming into contact with the electronic components is reduced, thus reducing the risk of short circuits in the electronic components. Furthermore, the bottom filler layer covering the top and sidewalls of the electronic components eliminates the need for separate application of insulating adhesive to the electronic components, avoiding the risk of uneven coating and bubble inclusions in the insulating adhesive applied to the electronic components, thereby improving the reliability of the packaging structure.

[0030] The method for forming a packaging structure provided in this disclosure includes a substrate with a front side and a back side opposite to it. A groove is formed in the substrate, and the groove is exposed on the front side of the substrate. Electronic components are disposed in the groove and electrically connected to the substrate. After the electronic components and chip are formed, a bottom filling layer is formed on the front side to cover the sidewalls of the chip and the top surface and sidewalls of the electronic components. The bottom filling layer protects the electronic components in the groove and the chip on the front side of the substrate. In the subsequent process of setting the heat sink structure, it can reduce the risk of the material from the heat sink structure melting and overflowing during the high-temperature process coming into contact with the electronic components, thereby reducing the risk of short circuits in the electronic components. Furthermore, the bottom filling layer covering the top surface and sidewalls of the electronic components eliminates the need to separately coat the electronic components with insulating adhesive, avoiding the risk of uneven coating and bubble inclusions in the insulating adhesive coated on the electronic components, and improving the reliability of the packaging structure. Attached Figure Description

[0031] Figure 1 A schematic diagram of the packaging structure is shown. Figure 2 This is a schematic diagram of the packaging structure of one embodiment of the present disclosure; Figure 3 This is a flowchart of the steps corresponding to one embodiment of the method for forming the packaging structure according to this disclosure; Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming the packaging structure according to an embodiment of the present disclosure. Detailed Implementation

[0032] Currently, the reliability of packaging structures still needs to be improved. This paper analyzes the reasons why the reliability of a particular packaging structure still needs to be improved.

[0033] in, Figure 1A schematic diagram of one type of packaging structure is shown.

[0034] The packaging structure includes: a substrate 10; a chip 16 disposed on the top surface of the substrate 10 and electrically connected to the substrate 10; an electronic component 22 disposed on the exposed top surface of the substrate 10 of the chip 16 and electrically connected to the substrate 10; an insulating layer 24 located on the top surface of the substrate 10 and covering the electronic component 22; a thermally conductive layer 20 located on the top surface of the chip 16; and a heat sink 18 disposed on the substrate 10 and surrounding the electronic component 22 and the chip 16. The inner wall of the heat sink 18 and the front surface of the substrate 10 form a receiving cavity, and the inner wall of the heat sink 18 is in contact with the thermally conductive layer 20. Both the electronic component 22 and the chip 16 are located within the receiving cavity.

[0035] Research has revealed that the thermal conductive layer 20 undergoes a melting-liquefaction process during the mounting of the heat sink 18 or its subsequent high-temperature processes. In its liquid state, driven by the pressure of the heat sink 18, the thermal conductive layer 20 exhibits inherent fluidity and overflows from the interface gap between the top surface of the chip 16 and the heat sink 18. During the process of setting the insulating layer 24 covering the electronic components 22, the filling space for forming the insulating layer 24 is too small due to product size limitations. This leads to uneven coating, incomplete coverage, or the presence of air bubbles in the insulating layer 24 during actual processing. The overflowing liquid thermal conductive layer 20 material flows to the defective areas of the insulating layer 24, increasing the probability of the overflowing liquid thermal conductive layer 20 material coming into contact with the electronic components 22, leading to a risk of short circuit in the electronic components 22 and thus affecting the reliability of the packaging structure.

[0036] To address the aforementioned technical problems, this disclosure provides a packaging structure, comprising: a substrate, the substrate having a front side and a back side opposite to it, a groove being provided in the substrate, and the front side of the substrate exposing the groove; an electronic component disposed in the groove and electrically connected to the substrate; a chip disposed on the front side of the substrate and electrically connected to the front side of the substrate; a bottom filler layer disposed on the front side of the substrate and covering the sidewalls of the chip and the top surface and sidewalls of the electronic component; and a heat sink structure disposed on the substrate and surrounding the electronic component and the chip, the inner wall of the heat sink structure and the front side of the substrate forming a receiving cavity, the inner wall of the heat sink structure contacting the chip, and both the electronic component and the chip being located within the receiving cavity.

[0037] The packaging structure provided in this embodiment includes a groove in the substrate, with the groove exposed on the front side of the substrate. Electronic components are disposed in the groove and electrically connected to the substrate. A bottom filler layer is disposed on the front side of the substrate and covers the sidewalls of the chip and the top and sidewalls of the electronic components. The bottom filler layer protects the electronic components in the groove and the chip on the front side of the substrate. During the heat sink structure construction, the risk of material from the heat sink melting and overflowing during high-temperature processes coming into contact with the electronic components is reduced, thus reducing the risk of short circuits in the electronic components. Furthermore, the bottom filler layer covering the top and sidewalls of the electronic components eliminates the need for separate application of insulating adhesive to the electronic components, avoiding the risk of uneven coating and bubble inclusions in the insulating adhesive applied to the electronic components, thereby improving the reliability of the packaging structure.

[0038] To make the above-mentioned objects, features and advantages of the embodiments of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0039] Figure 2 A schematic diagram of the corresponding structure in one embodiment of the packaging structure disclosed herein is shown.

[0040] The packaging structure includes: a substrate 200, which includes a front side 210 and a back side 211 opposite to it. A groove is provided in the substrate 200, and the front side 210 of the substrate 200 exposes the groove; an electronic component 201, which is disposed in the groove and is electrically connected to the substrate 200; a chip 298, which is disposed on the front side 210 of the substrate 200 and is electrically connected to the front side 210 of the substrate 200; a bottom filler layer 226, which is disposed on the front side 210 of the substrate 220 and covers the sidewalls of the chip 298 and the top surface and sidewalls of the electronic component 201; and a heat sink structure 236, which is disposed on the substrate 200 and surrounds the electronic component 201 and the chip 298. The inner wall of the heat sink structure 236 and the front side 210 of the substrate 200 form a receiving cavity. The inner wall of the heat sink structure 236 is in contact with the chip, and both the electronic component 201 and the chip 298 are located within the receiving cavity.

[0041] It should be noted that a groove is provided in the substrate 200, and the front side 210 of the substrate 200 exposes the groove. The electronic component 201 is disposed in the groove and is electrically connected to the substrate 200. The bottom filling layer 226 is disposed on the front side 210 of the substrate 200 and covers the sidewalls of the chip 298 as well as the top surface and sidewalls of the electronic component 201. The bottom filling layer 226 protects the electronic component 201 in the groove and the chip 298 on the front side 210 of the substrate 200. A heat sink is provided. In the process of structure 236, the risk of material from the heat sink structure 236 melting and overflowing during high-temperature processes coming into contact with electronic components 201 can be reduced, thereby reducing the risk of short circuits in electronic components 201. Furthermore, the bottom filling layer 226 covers the top surface and sidewalls of electronic components 201, eliminating the need for a separate step of applying insulating adhesive to electronic components 201. This avoids the risk of uneven coating and bubble inclusions in the insulating adhesive applied to electronic components 201, thus improving the reliability of the packaging structure.

[0042] The substrate 200 provides a process platform for setting electronic components 201, chips 298 and heat sink structure 236. At the same time, the electronic components 201 and chips 298 are set on the substrate 200, so that the electronic components 201 and chips 298 can transmit electrical signals and optical signals through the circuit inside the substrate 200.

[0043] In some embodiments, substrate 200 is a packaging substrate.

[0044] In some embodiments, the substrate 200 includes a front side 210 and a back side 211 opposite thereto.

[0045] Specifically, the front side 210 of the substrate 200 is used to carry the electronic components 201, the chip 298 and the heat sink structure 236, and to interconnect with the electronic components 201 and the chip 298, while the back side 211 of the substrate 200 is used to electrically connect with the subsequently provided second conductive bump, thereby realizing that the package structure is electrically connected to the external circuit board through the second conductive bump.

[0046] It should be noted that the groove provides space for the electronic component 201. By embedding the electronic component 201 inside the substrate 200, the overall thickness of the packaging structure is effectively reduced, thereby significantly improving the product integration of the packaging structure. At the same time, by embedding the electronic component 201 inside the substrate 200, key process conditions are created for the bottom filling layer 226 to achieve seamless coverage of the electronic component 201.

[0047] Specifically, the key process conditions refer to the following: during the formation of the bottom filler layer 226, since the electronic component 201 is embedded inside the substrate 200, the filler adhesive can flow naturally into the groove and cover the top and sidewalls of the electronic component 201.

[0048] In some embodiments, one or more circuit layers are formed in the substrate 200, and the top circuit layer is exposed on the front side 210 of the substrate 200.

[0049] It should be noted that by forming one or more circuit layers in the substrate 200, it is possible to bypass areas where wiring is not possible (such as grooves), thereby achieving a higher degree of integration and better electrical performance.

[0050] It should also be noted that the top layer of the circuit layer is exposed on the front side 210 of the substrate 200, providing an electrical connection point for the chip 298 and the substrate 200. This allows the conductive bumps on the back side 211 of the chip 298 to be electrically connected to the top layer of the circuit layer exposed on the front side 210, thereby connecting the chip 298 to the substrate 200.

[0051] In some embodiments, the back side 211 of the substrate 200 exposes the bottommost circuit layer.

[0052] Specifically, the back surface 211 of the substrate 200 exposes the bottommost circuit layer, providing electrical connection points for setting conductive bumps on the back surface 211 of the substrate 200. This allows the conductive bumps on the back surface 211 of the substrate 200 to be electrically connected to the bottommost circuit layer exposed on the back surface 211, thereby enabling the packaging structure to be electrically connected to the external circuit board through the conductive bumps on the back surface 211 of the substrate 200.

[0053] In some embodiments, the material of the circuit layer includes one or both of copper and aluminum.

[0054] In some embodiments, the number of grooves is set to one or more.

[0055] It should be noted that a single recess can be used to integrate specific functions or position-sensitive critical components, while multiple recesses allow electronic components 201 of different types, sizes and functions to be partitioned and distributed in the optimal position of the substrate 200. This not only achieves a higher integration density of the package structure and avoids signal interference, but also ensures that the electronic components 201 in each recess can be effectively covered by the bottom filling layer 226, thereby improving the integration of the package structure and the high reliability of the package structure.

[0056] Specifically, by placing the electronic component 201 in the recess and electrically connecting it to the substrate 200, the power supply circuit and signal path can be significantly shortened, effectively suppressing power supply noise, improving signal integrity, and providing stable decoupling, filtering, and impedance matching functions for the chip 298, thereby improving the overall circuit performance of the package structure. At the same time, the layout of the electronic component 201 embedded in the recess avoids the space occupied by laying it flat on the front side 210 of the substrate 200, further improving the integration of the package structure.

[0057] It should be noted that the electronic component 201 is disposed in the groove. In the process of forming the bottom filling layer 226, the filling adhesive can flow smoothly and naturally into the groove and cover the top and side walls of the electronic component 201, so that the bottom filling layer 226 can protect the electronic component 201.

[0058] In some embodiments, the top of the electronic component 201 is lower than the front side 210 of the substrate 200.

[0059] Specifically, the top of the electronic component 201 is lower than the front side 210 of the substrate 200. During the formation of the bottom filler layer 226, the bottom filler adhesive can continuously form a uniform and bubble-free bottom filler layer 226 when it flows and covers. This reduces the risk of the material from the heat sink structure 236 melting and overflowing during the high-temperature process coming into contact with the electronic component 201, thus reducing the risk of short circuits in the electronic component 201. At the same time, it avoids defects such as local thinning or local breaks in the bottom filler layer 226 caused by the protrusion of the electronic component 201, thereby significantly improving the reliability of the packaging structure.

[0060] In some embodiments, the number of electronic components 201 disposed in the groove is one or more.

[0061] It should be noted that setting a single electronic component 201 in the groove can achieve precise performance optimization of the electronic component 201, while setting multiple electronic components 201 in the groove can achieve high-density integration within a single groove. The coordinated layout of the electronic components 201 forms a complete functional unit, which not only significantly improves the utilization rate of local space, but also ensures that all components can be completely covered by the bottom filling layer 226 through the unified constraint of the groove.

[0062] It should also be noted that when there are multiple electronic components 201 in the groove, the multiple electronic components 201 are arranged in parallel with intervals in the groove.

[0063] In some embodiments, electronic component 201 includes one or more of capacitors, resistors, inductors, and chips.

[0064] In some embodiments, the specific type of chip 298 can be selected according to actual needs. For example, the chip may include one or more of the following: ASIC (Application-Specific Integrated Circuit) chip, HBM (High Bandwidth Memory) chip, CPU (Central Processing Unit) chip, GPU (Graphics Processing Unit) chip, and FPGA (Field-Programmable Gate Array) chip. As the core functional unit in the package structure, chip 298 actively processes and controls electrical signals through electrical connections on the front side 210 of substrate 200. It serves as a carrier for computation, storage, or communication functions, responsible for performing core logic operations, data storage, and signal transmission of the electronic system. It also efficiently interacts with and supplies power to the electronic components 201 within the recess and the external circuit board through the circuit layer inside substrate 200, thereby driving the entire package structure to achieve its predetermined functions.

[0065] In some embodiments, chip 298 is bonded to the front side 210 of substrate 200 using a flip chip process, thereby improving the communication speed between chips.

[0066] It should be noted that the horizontal distance between the side edge of chip 298 and the side edge of electronic component 201 should not be too large. If the horizontal distance between the side edge of chip 298 and the side edge of electronic component 201 is too large, in the method of forming the bottom filler layer 226, the bottom filler adhesive forming the bottom filler layer 226 may not be able to flow naturally into the groove under capillary action, causing the bottom filler layer 226 to fail to cover the top surface and sidewalls of electronic component 201. This results in the bottom filler layer 226 failing to protect the electronic component 201, thereby increasing the risk of short circuits in the electronic component 201 and affecting the performance and reliability of the packaging structure. Therefore, in some embodiments, the horizontal distance between the side edge of chip 298 and the side edge of electronic component 201 is less than 4 mm.

[0067] In some embodiments, the packaging structure further includes a first conductive bump 220 disposed on the front side 210 of the chip 298, and the first conductive bump 220 is electrically connected to the circuit layer.

[0068] Specifically, chip 298 is electrically connected to the circuit layer via the first conductive bump 220.

[0069] In some embodiments, the first conductive bump 220 may be made of a material with good conductivity, for example, it may include one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0070] It should be noted that the bottom filler layer 226 is disposed on the front side 210 of the substrate 200 and covers the sidewalls of the chip 298 and the top and sidewalls of the electronic component 201. The bottom filler layer 226 protects the electronic component 201 in the groove and the chip 298 on the front side 210 of the substrate 200. During the setting of the heat sink structure 236, the risk of the material of the heat sink structure 236 melting and overflowing in the high-temperature process coming into contact with the electronic component 201 is reduced, thereby reducing the risk of short circuit of the electronic component 201. In addition, the bottom filler layer 226 covers the top and sidewalls of the electronic component 201, which also eliminates the step of separately coating the electronic component 201 with insulating glue, avoiding the risk of uneven coating and bubble inclusions in the insulating glue coated on the electronic component 201, and improving the reliability of the packaging structure.

[0071] It should also be noted that in the method of forming the bottom filler layer 226, the bottom filler layer 226 is formed by bottom filler adhesive. As a low viscosity and high wettability liquid, the bottom filler adhesive will automatically flow into the gap between the chip 298 and the front side 210 of the substrate 200 due to capillary action. At the same time, under the driving force of continuous flow and surface tension, the bottom filler adhesive will flow further forward to the groove area adjacent to the chip 298. Since the depth of the groove is greater than the height of the electronic component 201, the inlet structure of the groove has very little resistance to the flow of the bottom filler adhesive, so that the bottom filler adhesive can cover the sidewalls and top surface of the electronic component 201, and finally form a complete bottom filler layer 226. The bottom filler layer 226 plays a complete protective role for the electronic component 201.

[0072] In some embodiments, the bottom filler layer 226 is also disposed between the chip 298 and the substrate 200, and the bottom filler layer 226 also covers the first conductive bump 220.

[0073] Specifically, after the bottom filler layer 226 fills the slit between the chip 298 and the substrate 200 and wraps the first conductive bump 220, it can effectively disperse the periodic thermal stress caused by the mismatch of the thermal expansion coefficients of the chip 298 and the substrate 200, significantly reducing the risk of solder joint fatigue failure. At the same time, it consolidates multiple independent first conductive bumps 220 into a whole, greatly enhancing the mechanical strength and impact resistance of the first conductive bumps 220, thereby comprehensively improving the service life and reliability of the packaging structure.

[0074] In some embodiments, the bottom filler layer 226 also fills the recesses exposed by the electronic components 201.

[0075] It should be noted that the bottom filler layer 226 also fills the grooves exposed by the electronic components 201. During the setting of the heat sink structure 236, it can completely prevent the material that melts and overflows from the heat sink structure 236 during the high-temperature process from entering the grooves, which could lead to short circuits between the circuit layers of the substrate 200. Furthermore, the bottom filler layer 226 fills the grooves completely, which significantly improves the mechanical strength of the packaging structure, effectively suppresses microcracks and displacement caused by thermal expansion coefficient mismatch or external impact, and eliminates the hidden danger of residual air expanding and forming bubbles at high temperatures, thereby improving the reliability of the packaging structure.

[0076] In some embodiments, the material of the bottom filler layer 226 includes epoxy resin.

[0077] Specifically, epoxy resin, with its excellent flowability and high wettability on the surfaces of the substrate 200 and the electronic component 201, can seamlessly fill the gap between the chip 298 and the substrate 200 through capillary action, and naturally flow into the groove to cover the electronic component 201. At the same time, the cured epoxy resin not only effectively disperses thermal stress and protects the first conductive bump 220, but also prevents the material that melts and overflows from the heat sink structure 236 during the high-temperature process from contacting the electronic component 201, thereby comprehensively improving the performance of the packaging structure.

[0078] It should be noted that the heat sink structure 236 forms a sealed cavity with the front side 210 of the substrate 200 through its inner wall, and the inner wall of the heat sink structure 236 is in contact with the chip 298, providing a large-area heat conduction path for the chip 298, ensuring that the heat generated by the chip 298 in the working state is quickly dissipated through the heat sink structure 236.

[0079] It should also be noted that the heat sink structure 236 enhances the mechanical rigidity of the package structure and provides a physical barrier against external stress and environmental pollution for the electronic components 201 and chip 298 inside the cavity, thereby improving the reliability of the package structure.

[0080] In some embodiments, the heat sink structure 236 includes: a thermally conductive layer 230 located on the chip 298; and a heat sink cover 231 located on the substrate 200 and surrounding the electronic components 201 and the chip 298, wherein the inner wall of the heat sink cover 231 is in contact with the top surface of the thermally conductive layer 230.

[0081] Specifically, the thermal conductive layer 230 covers the chip 298 and acts as a high thermal conductivity interface between the chip 298 and the heat sink 231. It is responsible for diffusing the heat generated by the chip 298 laterally and conducting it vertically to the heat sink 231. The heat sink 231 is in close contact with the top surface of the thermal conductive layer 230 through its inner wall. On the one hand, it dissipates the heat transferred by the thermal conductive layer 230 to the environment through a larger surface area. On the other hand, the surrounding structure of the heat sink 231 provides a sealed environment and protection for the chip 298 and the electronic components 201 in the groove.

[0082] In some embodiments, the material of the thermally conductive layer 230 includes one or more of indium, indium alloys, copper, silver, and tin.

[0083] It should be noted that indium, indium alloys, copper, silver, and tin are all materials with high thermal conductivity, which can serve as a heat conduction channel between chip 298 and heat sink 231, ensuring that the heat generated by the chip can be quickly dissipated.

[0084] In some embodiments, the material of the heat sink 231 includes one or more of high thermal conductivity metal materials, high thermal conductivity non-metal materials, and metal matrix composite materials.

[0085] In some embodiments, the packaging structure further includes an adhesive layer 232, located on the substrate 200 and surrounding the electronic components 201 and the chip 298.

[0086] Specifically, the adhesive layer 232 reliably fixes the heat sink 231 onto the substrate 200 and seals the cavity, providing structural support and vibration buffer for the heat sink 231, while effectively preventing external moisture and contaminants from entering the cavity and affecting the electronic components 201 and the chip 298.

[0087] In some embodiments, the heat dissipation cover 231 is located on the adhesive layer 232, and the inner wall of the heat dissipation cover 231, the inner wall of the adhesive layer 232, and the front side 210 of the substrate 200 form a receiving cavity.

[0088] In some embodiments, the material of the adhesive layer 232 includes a thermally conductive adhesive material.

[0089] Specifically, the adhesive layer 232 is made of a thermally conductive adhesive material. In addition to fixing the heat sink 231 to the substrate 200, it can also provide an additional heat dissipation path from the substrate 200 to the heat sink 231, thereby further improving the heat dissipation performance of the packaging structure.

[0090] In some embodiments, the packaging structure further includes a second conductive bump 292 located on the back side 211 of the substrate 200, and the second conductive bump 292 is electrically connected to the bottommost line layer.

[0091] It should be noted that the second conductive bump 292 is used to enable the package structure to be electrically connected to the external circuit board, and to lead the electrical signals of the chip 298 and electronic components 201 to the external circuit board via the second conductive bump 292.

[0092] In some embodiments, the second conductive bump 292 may be made of a material with good conductivity, for example, it may include one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0093] Accordingly, this disclosure also provides a method for forming an encapsulation structure.

[0094] Figure 3 This is a flowchart of the steps corresponding to one embodiment of the method for forming the packaging structure according to this disclosure.

[0095] In this embodiment, the method for forming the packaging structure includes the following basic steps: Step S1: Provide a substrate, which includes a front side and a back side opposite to it, and a groove is formed in the substrate, with the front side of the substrate exposing the groove. Step S2: Place electronic components in the groove, and electrically connect the electronic components to the substrate; Step S3: Place the chip on the front side of the substrate, and electrically connect the chip to the front side of the substrate. Step S4: After forming the electronic components and chips, a bottom filler layer is formed on the front side to cover the chip sidewalls and the top and sidewalls of the electronic components; Step S5: After forming the bottom filling layer, a heat sink structure is set on the substrate to surround the electronic components and chips. The inner wall of the heat sink structure is in contact with the chip, and the inner wall of the heat sink structure and the front side of the substrate form a receiving cavity, and the electronic components and chips are located in the receiving cavity.

[0096] in, Figures 4 to 11 The diagram shows a schematic representation of the structure of the packaging structure in one embodiment of the present disclosure.

[0097] refer to Figure 4 A substrate 100 is provided, the substrate 100 includes a front side 110 and a back side 111 opposite thereto, a groove 199 is formed in the substrate 100, and the front side 110 of the substrate 100 exposes the groove 199.

[0098] Specifically, the substrate 100 provides a process platform for the subsequent installation of electronic components, chips, and heat sink structures. At the same time, the subsequent electronic components and chips are installed on the substrate 100, enabling the electronic components and chips to transmit electrical and optical signals through the circuits inside the substrate 100.

[0099] In some embodiments, substrate 100 is a packaging substrate.

[0100] In some embodiments, the substrate 100 includes a front side 110 and a back side 111 opposite thereto.

[0101] Specifically, the front side 110 of the substrate 100 is used to subsequently support electronic components, chips and heat sink structures, and to interconnect with electronic components and chips, while the back side 111 of the substrate 100 is used to electrically connect with the subsequently provided second conductive bump, thereby realizing that the package structure is electrically connected to the external circuit board through the second conductive bump.

[0102] It should be noted that the groove 199 provides space for subsequent placement of electronic components. By embedding the electronic components inside the substrate 100, the overall thickness of the packaging structure is effectively reduced, thereby significantly improving the product integration of the packaging structure. At the same time, by embedding the electronic components inside the substrate 100, key process conditions are created for the bottom filling layer to achieve seamless coverage of the electronic components.

[0103] Specifically, the key process condition refers to the following: during the subsequent formation of the bottom filler layer, as the electronic components are embedded inside the substrate 100, the filler adhesive can naturally flow into the groove 199 and cover the top and sidewalls of the electronic components.

[0104] In some embodiments, during the step of providing the substrate 100, one or more circuit layers are formed in the substrate 100, and the top circuit layer is exposed on the front side 110 of the substrate 100.

[0105] It should be noted that by forming one or more circuit layers in the substrate 100, it is possible to bypass areas where wiring is not possible (such as the groove 199), thereby achieving a higher degree of integration and better electrical performance.

[0106] It should also be noted that the top layer of the circuit layer is exposed on the front side 110 of the substrate 100, providing an electrical connection point for the chip and the substrate 100 to be installed subsequently. This allows the conductive bumps installed on the back side 111 of the chip to be electrically connected to the top layer of the circuit layer exposed on the front side 110, thereby making the chip electrically connected to the substrate 100.

[0107] In some embodiments, the back side 111 of the substrate 100 exposes the bottommost circuit layer.

[0108] Specifically, the back side 111 of the substrate 100 exposes the bottommost circuit layer, providing electrical connection points for the subsequent setting of conductive bumps on the back side 111 of the substrate 100. This allows the conductive bumps on the back side 111 of the substrate 100 to be electrically connected to the bottommost circuit layer exposed on the back side 111, thereby enabling the packaging structure to be electrically connected to the external circuit board through the conductive bumps on the back side 111 of the substrate 100.

[0109] In some embodiments, the material of the circuit layer includes one or both of copper and aluminum.

[0110] In some embodiments, the number of grooves 199 is one or more.

[0111] It should be noted that a single recess 199 can be used to integrate specific functions or position-sensitive critical components, while multiple recesses 199 allow for the partitioning and distribution of electronic components of different types, sizes and functions in optimal positions on the substrate 100. This not only achieves higher integration density of the package structure and avoids signal interference, but also ensures that the electronic components in each recess 199 can be effectively covered by the bottom filler layer, thereby improving the integration of the package structure and its high reliability.

[0112] refer to Figure 5 An electronic component 101 is disposed in the groove 199 and is electrically connected to the substrate 100.

[0113] Specifically, by placing the electronic component 101 in the recess 199 and electrically connecting the electronic component 101 to the substrate 100, the power supply circuit and signal path can be significantly shortened, power supply noise can be effectively suppressed, signal integrity can be improved, and stable decoupling, filtering and impedance matching functions can be provided for the chip, thereby improving the overall circuit performance of the package structure. At the same time, the layout of the electronic component 101 embedded in the recess 199 avoids the space occupied by laying it flat on the front side 110 of the substrate 100, further improving the integration of the package structure.

[0114] It should be noted that the electronic component 101 is disposed in the groove 199. During the subsequent formation of the bottom filling layer, the filling adhesive can flow smoothly and naturally into the groove 199 and cover the top and side walls of the electronic component 101, so that the bottom filling layer can protect the electronic component 101.

[0115] In some embodiments, the top of the electronic component 101 is lower than the front side 110 of the substrate 100.

[0116] Specifically, the top of the electronic component 101 is lower than the front side 110 of the substrate 100. During the subsequent formation of the bottom filler layer, the bottom filler adhesive can continuously form a uniform and bubble-free bottom filler layer when it flows and covers. This reduces the risk of the material from the heat sink structure melting and overflowing during the high-temperature process coming into contact with the electronic component 101, thus reducing the risk of short circuits in the electronic component 101. At the same time, it avoids defects such as localized thinness or localized breaks in the bottom filler layer caused by the protrusion of the electronic component 101, thereby significantly improving the reliability of the packaging structure.

[0117] In some embodiments, the number of electronic components 101 disposed in the groove 199 is one or more.

[0118] It should be noted that setting a single electronic component 101 in the groove 199 can achieve precise performance optimization of the electronic component 101, while setting multiple electronic components 101 in the groove 199 can achieve high-density integration within a single groove 199. The coordinated layout of the electronic components 101 forms a complete functional unit, which not only significantly improves the utilization rate of local space, but also ensures that all components can be completely covered by the bottom filling layer through the unified constraint of the groove 199.

[0119] It should also be noted that when there are multiple electronic components 101 in the groove 199, the multiple electronic components 101 are arranged in parallel at intervals in the groove 199.

[0120] In some embodiments, electronic components 101 include one or more of capacitors, resistors, inductors, and chips.

[0121] In some embodiments, the process of setting the electronic component 101 in the groove 199 includes a mounting process.

[0122] It should be noted that by placing the electronic component 101 in the groove 199 through the mounting process, high-precision and high-efficiency integration of the electronic component 101 and the substrate 100 is achieved. The electronic component 101 is picked up and precisely placed in the predetermined pad position in the groove 199 using a high-precision placement equipment. Reliable electrical connection is then achieved through reflow soldering or curing with conductive adhesive. The mounting process not only makes full use of the physical limiting effect of the groove 199 to improve the mounting alignment accuracy, but also creates process conditions for the subsequent bottom filler layer by embedding the electronic component 101 inside the substrate 100.

[0123] refer to Figure 6 A chip 198 is disposed on the front side 110 of the substrate 100, and the chip 198 is electrically connected to the front side 110 of the substrate 100.

[0124] Specifically, the chip 198, as the core functional unit in the package structure, actively processes and controls electrical signals through the electrical connection of the front side 110 of the substrate 100. It serves as a carrier for computing, storage, or communication functions, and is responsible for performing the core logic operations, data storage, and signal transmission of the electronic system. It also achieves efficient data interaction and power supply through the circuit layer inside the substrate 100, the electronic components 101 in the groove 199, and the external circuit board, thereby driving the entire package structure to achieve its predetermined function.

[0125] The specific type of chip 198 can be selected according to actual needs. For example, chip 198 may include one or more of the following: ASIC (Application-Specific Integrated Circuit) chip, HBM (High Bandwidth Memory) chip, CPU (Central Processing Unit) chip, GPU (Graphics Processing Unit) chip, and FPGA (Field-Programmable Gate Array) chip.

[0126] In some embodiments, the process of setting the chip 198 on the front side 110 of the substrate 100 includes a flip chip process, wherein the chip 198 is bonded to the front side 110 of the substrate 100 by a flip chip process, thereby improving the communication speed between the chips 198.

[0127] It should be noted that the horizontal distance between the side edge of chip 198 and the side edge of electronic component 101 should not be too large. If the horizontal distance between the side edge of chip 198 and the side edge of electronic component 101 is too large, during the subsequent formation of the bottom filler layer, the bottom filler adhesive forming the bottom filler layer may not be able to flow naturally into the groove 199 under capillary action. This would prevent the bottom filler layer from covering the top surface and sidewalls of electronic component 101, thus failing to protect electronic component 101 and increasing the risk of short circuits in electronic component 101, affecting the performance and reliability of the packaging structure. Therefore, in some embodiments, during the step of setting chip 198 on the front side 110 of substrate 100, the horizontal distance between the side edge of chip 198 and the side edge of electronic component 101 is less than 4 mm.

[0128] In some embodiments, after the electronic component 101 is disposed in the groove 199, the chip 198 is disposed on the front side 110 of the substrate 100.

[0129] Specifically, by first setting the electronic components 101 in the groove 199, a larger operating space is provided for setting the electronic components 101, thereby improving the packaging yield of the packaging structure.

[0130] In some embodiments, the step of setting chip 198 on the front side 110 of substrate 100 includes: providing chip 198, wherein a first conductive bump is formed on the back side 111 of chip 198; facing the back side 111 of chip 198 toward the front side 110 of substrate 100, and soldering the first conductive bump to the front side 110 of substrate 100, wherein the first conductive bump is electrically connected to the circuit layer.

[0131] Specifically, chip 198 is electrically connected to the circuit layer via a first conductive bump.

[0132] In some embodiments, the first conductive bump may be made of a material with good conductivity, for example, it may include one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0133] refer to Figure 7 After forming the electronic component 101 and the chip 198, a bottom filling layer 126 is formed on the front side 110 to cover the sidewalls of the chip 198 and the top and sidewalls of the electronic component 101.

[0134] It should be noted that the bottom filler layer 126 is disposed on the front side 110 and covers the sidewalls of the chip 198 and the top surface and sidewalls of the electronic component 101. The bottom filler layer 126 protects the electronic component 101 in the groove 199 and the chip 198 on the front side 110 of the substrate 100. In the subsequent process of setting the heat sink structure, it can reduce the risk of the material that melts and overflows from the heat sink structure in the high-temperature process coming into contact with the electronic component 101, thereby reducing the risk of short circuit of the electronic component 101. In addition, the bottom filler layer 126 covers the top surface and sidewalls of the electronic component 101, which also eliminates the step of separately coating the electronic component 101 with insulating glue, avoiding the risk of uneven coating and bubble inclusions in the insulating glue coated on the electronic component 101, and improving the reliability of the packaging structure.

[0135] It should also be noted that in the method of forming the bottom filler layer 126, the bottom filler layer 126 is formed by bottom filler adhesive. As a low viscosity and high wettability liquid, the bottom filler adhesive will automatically flow into the gap between the chip 198 and the front side 110 of the substrate 100 due to capillary action. At the same time, under the driving force of continuous flow and surface tension, the bottom filler adhesive will flow further forward to the groove 199 area adjacent to the chip 198. Since the depth of the groove 199 is greater than the height of the electronic component 101, the inlet structure of the groove 199 has very little resistance to the flow of the bottom filler adhesive, so that the bottom filler adhesive can cover the sidewalls and top surface of the electronic component 101, and finally form a complete bottom filler layer 126. The bottom filler layer 126 plays a complete protective role for the electronic component 101.

[0136] In some embodiments, a bottom filler layer 126 is also formed between the chip 198 and the substrate 100, and the bottom filler layer 126 also covers the first conductive bump.

[0137] Specifically, after the bottom filler layer 126 fills the slit between the chip 198 and the substrate 100 and wraps the first conductive bump, it can effectively disperse the periodic thermal stress caused by the mismatch of the thermal expansion coefficients of the chip 198 and the substrate 100, significantly reducing the risk of solder joint fatigue failure. At the same time, it consolidates multiple independent first conductive bumps into a whole, greatly enhancing the mechanical strength and impact resistance of the first conductive bumps, thereby comprehensively improving the service life and reliability of the packaging structure.

[0138] In some embodiments, during the step of forming the bottom fill layer 126, the bottom fill layer 126 also fills the recess 199 exposed by the electronic component 101.

[0139] It should be noted that the bottom filler layer 126 also fills the groove 199 exposed by the electronic component 101. During the subsequent setting of the heat sink structure, it can completely prevent the material that melts and overflows from the heat sink structure during the high-temperature process from entering the groove 199, which could lead to a short circuit between the circuit layers of the substrate 100. Furthermore, the bottom filler layer 126 fills the groove 199 completely, which significantly improves the mechanical strength of the packaging structure, effectively suppresses microcracks and displacement caused by thermal expansion coefficient mismatch or external impact, and eliminates the hidden danger of residual air expanding and forming bubbles at high temperatures, thereby improving the reliability of the packaging structure.

[0140] In some embodiments, the material of the bottom filler layer 126 includes epoxy resin.

[0141] Specifically, epoxy resin, with its excellent flowability and high wettability on the surfaces of the substrate 100 and the electronic component 101, can seamlessly fill the gap between the chip 198 and the substrate 100 through capillary action, and naturally flow into the groove 199 to cover the electronic component 101. At the same time, the cured epoxy resin not only effectively disperses thermal stress and protects the first conductive bump, but also prevents the material that melts and overflows from the heat sink structure during the high-temperature process from contacting the electronic component 101, thereby comprehensively improving the performance of the packaging structure.

[0142] refer to Figures 8 to 10 After the bottom filling layer 126 is formed, a heat sink structure 136 is provided on the substrate 100 to surround the electronic components 101 and the chip 198. The inner wall of the heat sink structure 136 is in contact with the chip 198, and the inner wall of the heat sink structure 136 and the front side 110 of the substrate 100 form a receiving cavity, and the electronic components 101 and the chip 198 are both located in the receiving cavity.

[0143] It should be noted that the heat sink structure 136 forms a sealed cavity with the front side 110 of the substrate 100 through its inner wall, and the inner wall of the heat sink structure 136 is in contact with the chip 198, providing a large area of ​​heat conduction path for the chip 198, ensuring that the heat generated by the chip 198 in the working state is quickly dissipated through the heat sink structure 136.

[0144] It should also be noted that the heat sink structure 136 also enhances the mechanical rigidity of the package structure and provides a physical barrier against external stress and environmental pollution for the electronic components 101 and chip 198 inside the cavity, thereby improving the reliability of the package structure.

[0145] In some embodiments, the step of providing a heat sink structure 136 on the substrate 100 includes: providing a thermally conductive layer 130 on the chip 198; and providing a heat sink cover 131 surrounding the electronic component 101 and the chip 198 on the substrate 100, wherein the inner wall of the heat sink cover 131 is in contact with the top surface of the thermally conductive layer 130.

[0146] Specifically, the thermal conductive layer 130 covers the chip 198 and acts as a high thermal conductivity interface between the chip 198 and the heat sink 131. It is responsible for diffusing the heat generated by the chip 198 laterally and conducting it vertically to the heat sink 131. The heat sink 131 is in close contact with the top surface of the thermal conductive layer 130 through its inner wall. On the one hand, it dissipates the heat transferred by the thermal conductive layer 130 to the environment through a larger surface area. On the other hand, the surrounding structure of the heat sink 131 provides a sealed environment and protection for the chip 198 and the electronic components 101 in the groove 199.

[0147] In some embodiments, the material of the thermally conductive layer 130 includes one or more of indium, indium alloys, copper, silver, and tin.

[0148] It should be noted that indium, indium alloys, copper, silver, and tin are all materials with high thermal conductivity, which can serve as a heat conduction channel between chip 198 and heat sink 131, ensuring that the heat generated by chip 198 can be quickly dissipated.

[0149] In some embodiments, the material of the heat sink 131 includes one or more of high thermal conductivity metal materials, high thermal conductivity non-metal materials, and metal matrix composite materials.

[0150] In some embodiments, the step of providing a heat dissipation cover 131 on the substrate 100 includes: providing an adhesive layer 132 surrounding the electronic components 101 and the chip 198 on the substrate 100; providing a heat dissipation cover 131 on the adhesive layer 132, wherein the inner wall of the heat dissipation cover 131, the inner wall of the adhesive layer 132, and the front surface 110 of the substrate 100 form a receiving cavity.

[0151] Specifically, the adhesive layer 132 reliably fixes the heat sink 131 onto the substrate 100 and seals the cavity, providing structural support and vibration buffer for the heat sink 131, while effectively preventing external moisture and contaminants from entering the cavity and affecting the electronic components 101 and the chip 198.

[0152] In some embodiments, the material of the adhesive layer 132 includes a thermally conductive adhesive material.

[0153] Specifically, the adhesive layer 132 is made of a thermally conductive adhesive material. In addition to fixing the heat sink 131 to the substrate 100, it can also provide an additional heat dissipation path from the substrate 100 to the heat sink 131, thereby further improving the heat dissipation performance of the package structure.

[0154] In some embodiments, during the process of setting the heat sink structure 136 on the substrate 100, the heat sink structure 136 needs to be subjected to high temperature treatment so that the adhesive layer 132 can be fully cured, thereby forming a cured and sealed receiving cavity with the substrate 100.

[0155] refer to Figure 11 After setting the heat sink structure 136, the forming method further includes: forming a second conductive bump 192 on the back side 111 of the substrate 100, and the second conductive bump 192 is electrically connected to the bottommost circuit layer.

[0156] It should be noted that the second conductive bump 192 is used to enable the package structure to be electrically connected to the external circuit board, and to lead the electrical signals of the chip 198 and electronic components 101 to the external circuit board via the second conductive bump 192.

[0157] In some embodiments, the second conductive bump 192 may be made of a material with good conductivity, for example, it may include one or more of copper, aluminum, gold, nickel, silver, palladium and tin.

[0158] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A package structure, characterized by, The package structure comprises: a substrate, the substrate comprising a front surface and a back surface opposite to the front surface, the substrate being provided with a recess, and the front surface of the substrate exposing the recess; an electronic component disposed in the recess, and the electronic component being electrically connected with the substrate; a chip disposed on the front surface of the substrate, and the chip being electrically connected with the front surface of the substrate; a bottom filling layer disposed on the front surface of the substrate and covering the sidewall of the chip and the top surface and sidewall of the electronic component; a heat sink structure disposed on the substrate and surrounding the electronic component and the chip, the inner wall of the heat sink structure and the front surface of the substrate forming a receiving cavity, the inner wall of the heat sink structure being in contact with the chip, and the electronic component and the chip being located in the receiving cavity.

2. The package structure of claim 1, wherein, The number of the recesses is one or more.

3. The package structure of claim 1, wherein, The number of the electronic components disposed in the recesses is one or more.

4. The package structure of claim 1, wherein, The top of the electronic component is lower than the front surface of the substrate.

5. The package structure of claim 1, wherein, The electronic component comprises one or more of a capacitor, a resistor, an inductor and a chip.

6. The package structure of claim 1, wherein, The distance between the side edge of the chip and the side edge of the electronic component in the horizontal direction is less than 4 mm.

7. The package structure of claim 1, wherein, The substrate is formed with one or more circuit layers, and the front surface of the substrate exposes the topmost circuit layer. The package structure further comprises a first conductive bump disposed on the front surface of the chip, and the first conductive bump is electrically connected with the circuit layer.

8. The package structure of claim 7, wherein, The bottom filling layer is further disposed between the chip and the substrate, and the bottom filling layer further covers the first conductive bump.

9. The package structure of claim 1, wherein, The bottom filling layer is further filled in the recess exposed by the electronic component.

10. The package structure of claim 1, wherein, The material of the bottom filling layer comprises epoxy resin.

11. The package structure of claim 1, wherein, The heat sink structure comprises a heat conductive layer located on the chip; a heat dissipation cover located on the substrate and surrounding the electronic component and the chip, the inner wall of the heat dissipation cover being in contact with the top surface of the heat conductive layer.

12. The package structure of claim 11, wherein, The package structure further comprises a sticking layer located on the substrate and surrounding the electronic component and the chip; the heat dissipation cover is located on the sticking layer, and the inner wall of the heat dissipation cover, the inner wall of the sticking layer and the front surface of the substrate form a receiving cavity.

13. The package structure of claim 1, wherein, The substrate is formed with one or more circuit layers, and the back surface of the substrate exposes the bottommost circuit layer. The package structure further comprises a second conductive bump located on the back surface of the substrate, and the second conductive bump is electrically connected with the bottommost circuit layer.

14. A method of forming a package structure, comprising: The package structure comprises: providing a substrate, the substrate comprising a front surface and a back surface opposite to the front surface, the substrate being provided with a recess, and the front surface of the substrate exposing the recess; disposing an electronic component in the recess, and the electronic component being electrically connected with the substrate; disposing a chip on the front surface of the substrate, and the chip being electrically connected with the front surface of the substrate; forming a bottom filling layer on the front surface of the substrate after forming the electronic component and the chip, the bottom filling layer covering the sidewall of the chip and the top surface and sidewall of the electronic component; After the underfill layer is formed, a heat sink structure is provided on the substrate to surround the electronic components and the chip, an inner wall of the heat sink structure is in contact with the chip, an inner wall of the heat sink structure and the front surface of the substrate form a receiving cavity, and the electronic components and the chip are located in the receiving cavity.

15. The method of forming a package structure of claim 14, wherein, The process of providing the electronic components in the recess includes a mounting process.

16. The method of forming a package structure of claim 14, wherein, After the electronic components are provided in the recess, the chip is provided on the front surface of the substrate.

17. The method of forming a package structure of claim 14, wherein, The process of providing the chip on the front surface of the substrate includes a flip process.

18. The method of forming a package structure of claim 14, wherein, In the step of providing the chip on the front surface of the substrate, a horizontal distance between a side edge of the chip and a side edge of the electronic components is less than 4 mm.

19. The method of forming a package structure of claim 14, wherein, In the step of providing the substrate, one or more circuit layers are formed in the substrate, and a topmost circuit layer is exposed on the front surface of the substrate. The step of providing the chip on the front surface of the substrate includes: providing a chip, a back surface of the chip is formed with a first conductive bump. The back surface of the chip faces the front surface of the substrate, and the first conductive bump is welded to the front surface of the substrate, and the first conductive bump is electrically connected to the circuit layer.

20. The method of forming a package structure of claim 23, wherein, In the step of forming the underfill layer, the underfill layer is also formed between the chip and the substrate, and the underfill layer also covers the first conductive bump.

21. The method of forming a package structure of claim 14, wherein, The process of providing the chip on the front surface of the substrate includes a flip process.

22. The method of forming a package structure of claim 14, wherein, The step of providing the heat sink structure on the substrate includes: providing a heat-conducting layer on the chip; A heat sink cover is provided on the substrate to surround the electronic components and the chip, an inner wall of the heat sink cover is in contact with a top surface of the heat-conducting layer.

23. The method of forming a package structure of claim 22, wherein, The step of providing the heat sink cover on the substrate includes: providing a bonding layer on the substrate to surround the electronic components and the chip; The heat sink cover is provided on the bonding layer, and an inner wall of the heat sink cover, an inner wall of the bonding layer, and the front surface of the substrate form a receiving cavity.

24. The method of forming a package structure of claim 14, wherein, In the step of providing the substrate, one or more circuit layers are formed in the substrate, and a bottommost circuit layer is exposed on the back surface of the substrate; After the heat sink structure is provided, the forming method further includes: forming a second conductive bump on the back surface of the substrate, and the second conductive bump is electrically connected to the bottommost circuit layer.

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