Storage device

Abstract

A storage device having a novel structure is provided. The memory device includes a first sense amplifier section, a second sense amplifier section, a word line driving circuit section, a sense amplifier driving circuit section, and a controller section. The sense amplifier driving block control signal is a signal for causing the plurality of sense amplifier driving blocks to control the state of the first sense amplifier block. The word line driving block control signal is a signal for causing the plurality of word line driving blocks to be in a state of outputting a word signal to a memory cell connected to the first sense amplifier block. The second sense amplifier control signal is a signal that causes one second sense amplifier block to be in a state in which data read out by the first sense amplifier block through the second bit line is accessed.

Description

Technical Field

[0001] This manual describes storage devices, etc.

[0002] Note that one aspect of the present invention is not limited to the above-described technical fields. Examples of technical fields for one aspect of the present invention disclosed in this specification include semiconductor devices, imaging devices, display devices, light-emitting devices, energy storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, or manufacturing methods thereof. Background Technology

[0003] In recent years, the importance of measures to combat global warming has increased. Energy consumption continues to rise, and carbon dioxide emissions, one of the causes of global warming, have not yet been reduced. Simply reducing energy consumption can sometimes lead to a decrease in convenience. Therefore, low-power technologies have become crucial for reducing energy consumption without compromising convenience.

[0004] As a technology applicable to low power consumption, for example, storage devices that use transistors containing oxide semiconductors (also known as OS transistors) to retain data are known (see, for example, Patent Document 1). The storage device described in Patent Document 1 can reduce the frequency of refresh operations and thus achieve low power consumption by using the characteristics of OS transistors, which have extremely low current flow when in the off state, for data retention.

[0005] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] U.S. Patent Application Publication No. 2015 / 0294710. Summary of the Invention

[0006] The technical problem that the invention aims to solve The memory device described in Patent Document 1 uses OS transistors, but the time required for writing and reading memory cells is longer than that of silicon-based transistors (Si transistors) such as DRAM (Dynamic Random Access Memory). In this structure, when the memory bandwidth (or memory bandwidth) is increased, the time required for writing and reading can be shortened by adding an activated read amplifier (a read amplifier capable of both writing and reading).

[0007] However, as the number of simultaneously activated sense amplifiers increases, the current flowing through the storage device also increases, sometimes causing a drop in the voltage of the power supply lines supplying the sense amplifiers. Furthermore, when outputting data read by the activated sense amplifiers to the outside of the storage device, it is sometimes necessary to output data corresponding to the width of the external bus.

[0008] One objective of this invention is to provide a low-power storage device. Another objective is to provide a miniaturized storage device. Another objective is to provide a storage device capable of reducing the time required for writing and reading. Another objective is to provide a storage device capable of suppressing voltage drops on the power lines supplying the sense amplifier. Another objective is to provide a storage device capable of outputting data corresponding to the width of an external bus. Finally, another objective is to provide a storage device with a novel structure.

[0009] Note that one embodiment of the present invention does not need to achieve all of the above objectives; achieving at least one objective is sufficient. Furthermore, the description of the above objectives does not preclude the existence of other objectives. Objectives other than those described above can be readily apparent from the description, claims, drawings, etc.

[0010] means of solving technical problems One aspect of the present invention is a storage device, comprising: a first sense amplifier section including a plurality of first sense amplifier blocks electrically connected to a storage cell via first bit lines; a second sense amplifier section including a plurality of second sense amplifier blocks electrically connected to the first sense amplifier blocks via second bit lines; a word line driving circuit section including a plurality of word line driving blocks that output word signals to the storage cell; a sense amplifier driving circuit section including a plurality of sense amplifier driving blocks that drive the first sense amplifier blocks; and a controller section that outputs a sense amplifier driving block control signal for controlling the sense amplifier driving blocks and a word line driving block control signal for controlling the word line driving blocks, wherein the sense amplifier driving block control signal is a signal that causes the plurality of sense amplifier driving blocks to be in a state that controls the first sense amplifier block, and the word line driving block control signal is a signal that causes the plurality of word line driving blocks to be in a state that outputs word signals to the storage cell connected to the first sense amplifier block.

[0011] One aspect of the present invention is a storage device, comprising: a first sense amplifier section including a plurality of first sense amplifier blocks electrically connected to a storage cell via first bit lines; a second sense amplifier section including a plurality of second sense amplifier blocks electrically connected to the first sense amplifier blocks via second bit lines; a word line driving circuit section including a plurality of word line driving blocks that output word signals to the storage cell; a sense amplifier driving circuit section including a plurality of sense amplifier driving blocks that drive the first sense amplifier blocks; and a controller section that outputs a sense amplifier driving block control signal for controlling the sense amplifier driving blocks, a word line driving block control signal for controlling the word line driving blocks, and a second sense amplifier control signal for controlling the second sense amplifier blocks, wherein the sense amplifier driving block control signal is a signal that enables the plurality of sense amplifier driving blocks to be in a state of controlling the first sense amplifier block, the word line driving block control signal is a signal that enables the plurality of word line driving blocks to be in a state of outputting word signals to the storage cell connected to the first sense amplifier block, and the second sense amplifier control signal is a signal that enables one of the second sense amplifier blocks to be in a state of accessing data read by the first sense amplifier block via the second bit lines.

[0012] One aspect of the present invention is a storage device, comprising: a first sense amplifier section including a plurality of first sense amplifier blocks electrically connected to a storage cell via first bit lines; a second sense amplifier section including a plurality of second sense amplifier blocks electrically connected to the first sense amplifier blocks via second bit lines; a word line driving circuit section including a plurality of word line driving blocks that output word signals to the storage cell; a sense amplifier driving circuit section including a plurality of sense amplifier driving blocks that drive the first sense amplifier blocks; and a sense amplifier driving block control signal for controlling the sense amplifier driving blocks and a word line driving block control signal for controlling the word line driving blocks, wherein the sense amplifier driving block control signal is a signal that causes one or more sense amplifier driving blocks to be in a state that controls the first sense amplifier blocks, and the word line driving block control signal is a signal that causes one or more word line driving blocks to be in a state that outputs word signals to the storage cell connected to the first sense amplifier block.

[0013] In one aspect of the present invention, the memory cell preferably includes a first transistor, and the first transistor includes a first semiconductor layer comprising an oxide semiconductor in the channel forming region.

[0014] In one aspect of the storage device of the present invention, when viewed in cross-section in the channel width direction, the first semiconductor layer preferably has a fin-like shape.

[0015] In one embodiment of the storage device of the present invention, it is preferred that the controller unit has the function of outputting a second read amplifier control signal to control the second read amplifier block, and the second read amplifier control signal is a signal that enables a second read amplifier block to access data read by the first read amplifier block through the second bit line.

[0016] Note that other aspects of the present invention are described in the following description and accompanying drawings.

[0017] Invention Effects According to one aspect of the present invention, a low-power storage device can be provided. Additionally, according to one aspect of the present invention, a miniaturized storage device can be provided. Furthermore, according to one aspect of the present invention, a storage device capable of shortening the time required for writing and reading can be provided. Furthermore, according to one aspect of the present invention, a storage device capable of suppressing voltage drop on the power supply line supplying the sense amplifier can be provided. Furthermore, according to one aspect of the present invention, a storage device capable of outputting data corresponding to the width of an external bus can be provided. Furthermore, according to one aspect of the present invention, a storage device with a novel structure can be provided.

[0018] The description of multiple effects does not preclude the existence of each other's effects. Furthermore, one aspect of the invention does not necessarily require all of the aforementioned effects. In one aspect of the invention, objectives, effects, and novel features beyond the foregoing can be readily understood from the description and drawings herein. Brief description of the attached figures Figure 1A and Figure 1B This is a diagram illustrating an example of the structure of a storage device.

[0019] Figure 2A and Figure 2B This is a diagram illustrating an example of the structure of a storage device.

[0020] Figure 3A and Figure 3B This is a diagram illustrating an example of the structure of a storage device.

[0021] Figure 4A and Figure 4B This is a diagram illustrating an example of the structure of a storage device.

[0022] Figures 5A to 5C This is a diagram illustrating an example of the structure of a storage device.

[0023] Figure 6A and Figure 6B This is a diagram illustrating an example of the structure of a storage device.

[0024] Figure 7A and Figure 7BThis is a diagram illustrating an example of the structure of a storage device.

[0025] Figure 8A and Figure 8B This is a diagram illustrating an example of the structure of a storage device.

[0026] Figure 9A and Figure 9B This is a diagram illustrating an example of the structure of a storage device.

[0027] Figure 10A and Figure 10B This is a diagram illustrating an example of the structure of a storage device.

[0028] Figures 11A to 11C This is a diagram illustrating an example of the structure of a storage device.

[0029] Figures 12A to 12G This is a diagram illustrating an example of the structure of a storage device.

[0030] Figures 13A to 13C This is a diagram illustrating an example of the structure of a storage device.

[0031] Figures 14A to 14C This is a diagram illustrating an example of the structure of a storage device.

[0032] Figure 15 This is a cross-sectional view illustrating an example of the structure of a storage device.

[0033] Figure 16A This is a diagram illustrating an example of the structure of transistors included in a storage device. Figure 16B It is a diagram illustrating the equivalent circuit of a memory cell.

[0034] Figures 17A to 17C This is a cross-sectional view illustrating an example of the structure of the transistors included in a storage device.

[0035] Figure 18A This is a plan view illustrating an example of the structure of transistors included in a storage device. Figures 18B to 18D This is a cross-sectional view illustrating an example of the structure of the transistors included in a storage device.

[0036] Figure 19A This is a plan view illustrating an example of the structure of transistors included in a storage device. Figures 19B to 19D This is a cross-sectional view illustrating an example of the structure of the transistors included in a storage device.

[0037] Figure 20 This is a cross-sectional view illustrating an example of the structure of a storage device.

[0038] Figure 21A This is a diagram illustrating an example of the structure of transistors included in a storage device. Figure 21B It is a diagram illustrating the equivalent circuit of a memory cell.

[0039] Figure 22A and Figure 22B This is a plan view showing an example of the structure of transistors included in a storage device. Figure 22C This is a cross-sectional view showing an example of the structure of the transistors included in a storage device.

[0040] Figure 23A and Figure 23B This is a cross-sectional view showing an example of the structure of the transistors included in a storage device.

[0041] Figure 24 This is a cross-sectional view showing an example of the structure of the transistors included in a storage device.

[0042] Figure 25A and Figure 25B This is a schematic diagram illustrating an example of the structure of transistors included in a storage device.

[0043] Figure 26A and Figure 26B This is a plan view showing an example of the structure of transistors included in a storage device. Figure 26C and Figure 26D This is a cross-sectional view showing an example of the structure of the transistors included in a storage device.

[0044] Figures 27A to 27D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention.

[0045] Figures 28A to 28D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention.

[0046] Figure 29A and Figure 29B This is a diagram showing an example of an electronic component.

[0047] Figures 30A to 30D This is a diagram illustrating an example of an electronic component.

[0048] Figure 31A and Figure 31B This is a diagram illustrating an example of an electronic device.

[0049] Figures 32A to 32C This is a diagram illustrating an example of an electronic device.

[0050] Figure 33 This is a diagram illustrating an example of a large computer. Methods of implementing the invention The embodiments will now be described. Note that one embodiment of the present invention is not limited to the following description, and those skilled in the art will readily understand that its manner and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, one aspect of the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0051] Note that in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Furthermore, these ordinal numbers do not limit the order of the constituent elements. Additionally, for example, in this specification, a constituent element referred to by "first" in one embodiment may be designated as a constituent element referred to by "second" in other embodiments or claims. Furthermore, for example, in this specification, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0052] In the accompanying drawings, the same symbol is sometimes used to represent the same element or elements with the same function, elements made of the same material or elements formed at the same time, and sometimes repeated descriptions are omitted.

[0053] In this specification, the power supply potential VDD is sometimes simply referred to as potential VDD, VDD, etc. The same applies to other components (e.g., signals, voltages, circuits, components, electrodes, and wiring).

[0054] In addition, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as “_1”, “_2”, “[n]”, “[m,n]” are sometimes added to the symbol for identification. For example, the second wiring GL is represented as wiring GL[2].

[0055] (Implementation Method 1) The structure and operation of a storage device according to one aspect of the present invention will be described.

[0056] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are also types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., sometimes include semiconductor devices.

[0057] <Structural Example of Storage Device 100> Figure 1A This is a schematic diagram illustrating one aspect of the storage device 100 of the present invention.

[0058] Storage device 100 includes a component layer 10 and a component layer 40 stacked on the component layer 10. Figure 1A In the schematic diagram shown, the component layer 10 and component layer 40 are shown separately to facilitate understanding of the configuration of the various components constituting the storage device 100. Furthermore, the component layer is a layer in which semiconductor components such as transistors or capacitors are disposed.

[0059] In addition to the global sense amplifier section 11, which is configured with multiple global sense amplifier blocks (GSABs), component layer 10 also includes a data sense amplifier section 12, a global sense amplifier driver circuit section 13, a column line driver circuit section 14, a word line driver circuit section 15, and a controller section 16. Note that the global sense amplifier section 11 is sometimes referred to as the first sense amplifier section. The global sense amplifier block (GSAB) is sometimes referred to as the first sense amplifier block. The global sense amplifier driver circuit section 13 is sometimes referred to as the first sense amplifier driver circuit section. The data sense amplifier section 12 is sometimes referred to as the second sense amplifier section.

[0060] exist Figure 1A In the schematic diagrams shown, to illustrate the configuration of each structure, the direction perpendicular or substantially perpendicular to the surface of component layer 10 (e.g., the surface where an interlayer insulating layer is provided) is defined as the Z-axis direction. Furthermore, for ease of understanding, the Z-axis direction is sometimes referred to as the direction perpendicular to the surface of component layer 10 in the specification. Note that "substantially perpendicular" refers to a configuration at an angle of 85 degrees or more but less than 95 degrees.

[0061] Note that, in order to illustrate the configuration of the various components, the X, Y, and Z directions are sometimes specified in this specification and accompanying drawings. For example, in Figure 1A In the schematic diagram shown, the X, Y, and Z directions are sometimes specified to illustrate the arrangement of the constituent elements constituting the storage device 100. The X, Y, and Z directions are each perpendicular or substantially perpendicular to each other.

[0062] The device layer 10 includes a silicon transistor (Si transistor) contained in a semiconductor layer having a channel formation region. The device layer 10 is a device layer in which a semiconductor layer having a channel formation region is disposed within a silicon substrate, or a device layer formed by attaching a silicon semiconductor layer having a channel formation region to a silicon substrate.

[0063] Although the case where a portion of the substrate in element layer 10 is a silicon substrate has been described, this embodiment is not limited to this. Note that a silicon substrate refers to a substrate with silicon as the semiconductor material, such as a single-crystal silicon substrate. Furthermore, it is not limited to silicon; materials containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., may also be used as the substrate.

[0064] The Si transistors included in the element layer 10 are made of highly crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. Because the element layer 10 contains highly crystalline silicon, high field-effect mobility can be achieved, enabling higher-speed operation. Therefore, in addition to the global sense amplifier section 11, the data sense amplifier section 12, the global sense amplifier drive circuit section 13, the column line drive circuit section 14, the word line drive circuit section 15, and the controller section 16 can be integrated into the element layer 10.

[0065] Component layer 40 includes a memory cell array 42 having a plurality of memory cells 41. Component layer 40 includes oxide semiconductor transistors (OS transistors) in a semiconductor layer having a channel formation region. Memory cells 41 are memory cells including OS transistors. Memory devices including memory cells with OS transistors are sometimes referred to as "OS memories".

[0066] Component layer 40, including OS transistors, can be stacked on component layer 10. By placing component layer 40 on component layer 10, the transistor density per unit area can be increased.

[0067] Examples of metal oxides used in OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). In-Zn oxide can also be used as a metal oxide for OS transistors. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, element M is preferably selected from one or more of aluminum, gallium, yttrium, and tin.

[0068] Figure 1B This is a block diagram illustrating the global sense amplifier section 11, data sense amplifier section 12, global sense amplifier drive circuit section 13, column line drive circuit section 14, word line drive circuit section 15, and controller section 16 configured with a global sense amplifier block GSAB.

[0069] In the global sense amplifier section 11, multiple global sense amplifier blocks GSAB are arranged in a column direction (Y direction in the figure). Each global sense amplifier block GSAB includes multiple global sense amplifiers GSA. Sometimes, the global sense amplifiers GSA are referred to as first sense amplifiers. The global sense amplifiers GSA are connected to the memory cell 41 via bit lines BL and inversion bit lines BLB provided in the Z direction.

[0070] Note that sometimes the bit line BL and the inverted bit line BLB are referred to as the bit line pair BL-BLB. Sometimes only the bit line BL is shown and the inverted bit line BLB is omitted. Sometimes the bit line BL is referred to as the first bit line.

[0071] The data readout amplifier section 12 includes multiple data readout amplifier blocks DSAB. The data readout amplifier blocks DSAB amplify the potential difference between the data bit line DBL and the inverted data bit line DBLB (not shown) corresponding to the input write data. The data readout amplifier blocks DSAB amplify the potential difference between the data bit line DBL and the inverted data bit line DBLB (not shown) and output it as readout data. Sometimes, the data readout amplifier block DSAB is referred to as the second readout amplifier block.

[0072] Note that, although Figure 1B The Global Sense Amplifier (GSAB) block is shown as a separate block for each row of the data bit lines DBL, but the Global Sense Amplifier (GSA) connected to multiple rows, such as two rows of the data bit lines DBL, can also be considered as the Global Sense Amplifier (GSAB) block.

[0073] The Data Readout Amplifier Block (DSAB) and the Global Readout Amplifier Block (GSAB) both include readout amplifiers on each row. Sometimes, the readout amplifiers included in the Data Readout Amplifier Block (DSAB) are referred to as the second readout amplifiers.

[0074] Note that sometimes the data bit line DBL and the inverted data bit line DBLB are referred to as the data bit line pair DBL-DBLB. For example... Figure 1B As shown, sometimes only the data bit line DBL is shown, while the inverted data bit line DBLB is omitted. Sometimes the data bit line DBL is referred to as the second bit line.

[0075] The data bit line pair (DBL-DBLB) is used for bidirectional data input / output routing between the data sense amplifier block (DSAB) and the global sense amplifier block (GSAB). Note that when the data input / output from the data bit line to the DBL-DBLB is multi-bit, there are also multiple routing steps.

[0076] The global sense amplifier driver circuit section 13 includes multiple sense amplifier driver blocks SADB. Each sense amplifier driver block SADB is located within a global sense amplifier block GSAB. The sense amplifier driver block SADB outputs a sense amplifier control signal SAEN to the global sense amplifier block GSAB. The sense amplifier control signal SAEN is used to control the global sense amplifiers GSA included in the global sense amplifier block GSAB corresponding to the sense amplifier driver block SADB.

[0077] The column line drive circuit section 14 supplies a column selection signal CSE to the global sense amplifier GSA included in the global sense amplifier block GSAB via the column line CSEL. The column selection signal CSE is a signal that causes the global sense amplifier GSA included in the global sense amplifier block GSAB to be in a selected state or a non-selected state. The column line CSEL is connected to the column line drive circuit section 14. Furthermore, the column line CSEL is connected to the global sense amplifier GSA included in the global sense amplifier block GSAB in the direction in which the column line CSEL extends (Y direction).

[0078] The word line driver circuit section 15 includes multiple word line driver blocks (WDBs). The multiple word line driver blocks (WDBs) are disposed in each global sense amplifier block (GSAB). The multiple word line driver blocks (WDBs) output word signals (SWL). The word signals (SWL) are output to a memory cell 41, which is connected to a global sense amplifier (GSA) included in the global sense amplifier block (GSAB) corresponding to the word line driver block (WDB).

[0079] The global sense amplifier GSA is connected to the memory cell 41 via the bit line BL and the inverted bit line BLB located in the Z direction. The global sense amplifier GSA is controlled by the sense amplifier control signal SAEN and the column select signal CSE.

[0080] The global sense amplifier (GSA) can write and read data from the memory cell 41 connected to it using the word signal SWL from the word line driver block WDB corresponding to the global sense amplifier block GSAB and the sense amplifier control signal SAEN from the sense amplifier driver block SADB. For example, the memory cell 41 is selected by outputting the word signal SWL from the word line driver block WDB of the word line driver circuit section 15. The selected memory cell 41 can be written and read by activating the global sense amplifier GSA using the sense amplifier control signal SAEN. The data being written and read is bidirectionally input and output between the column select signal CSE and the data sense amplifier block DSAB via the data bit line DBL. Specifically, the global sense amplifier GSA selected by the column select signal CSE can output the data held in the memory cell 41 to the data sense amplifier block DSAB. In addition, the global sense amplifier GSA selected by the column select signal CSE can input and write data from the data sense amplifier block DSAB.

[0081] The controller unit 16 outputs a sense amplifier driver block control signal SADB_EN ​​to control the output of the sense amplifier driver block SADB of the global sense amplifier block GSAB, which corresponds to data writing or reading. Additionally, the controller unit 16 outputs a word line driver block control signal WDB_EN ​​to control the output of the word signal SWL of the word line driver block WDB of the global sense amplifier block GSAB, which corresponds to data writing or reading. Furthermore, the controller unit 16 outputs a data sense amplifier block control signal DSAB_EN to perform data writing and reading within the data sense amplifier block DSAB of the global sense amplifier block GSAB, which corresponds to data writing or reading.

[0082] The word line drive circuit 15 can use the word line drive block control signal WDB_EN ​​to simultaneously select the word lines of memory cells 41 connected to one or more global sense amplifier blocks GSAB. The global sense amplifier drive circuit 13 can use the sense amplifier drive block control signal SADB_EN ​​to select one or more global sense amplifier blocks GSAB to activate the sense amplifiers included in the global sense amplifier GSA. Therefore, the global sense amplifier GSA, including the activated sense amplifier, can simultaneously read the data of the selected memory cells 41. The data sense amplifier unit 12 can use the data sense amplifier block control signal DSAB_EN to activate the sense amplifiers included in a data sense amplifier block DSAB. Therefore, the data sense amplifier block DSAB, including the activated sense amplifier, can be in a state of accessing the data read by the corresponding global sense amplifier block GSAB.

[0083] Note that in the activated data sense amplifier block DSAB, the state of accessing data read by the corresponding global sense amplifier block GSAB refers to the state where data can be read from the global sense amplifier GSA via the data bit line DBL. For example, it refers to the state where the data sense amplifier block control signal DSAB_EN, which switches the DSAB's operating state, can amplify the signal from the global sense amplifier block GSAB and output it. Alternatively, it refers to the state where the switch between the data bit line pair DBL-DBLB and the data sense amplifier block DSAB is turned on using the data sense amplifier block control signal DSAB_EN.

[0084] In a storage device 100 according to one aspect of the present invention, a plurality of global sense amplifier blocks (GSABs) are arranged in the lower layer of the storage cell 41. This allows for miniaturization and reduced power consumption by suppressing the increase in circuit area.

[0085] Furthermore, according to one aspect of the present invention, the storage device 100 has a structure that selects one or more global sense amplifier blocks (GSABs) to control the sense amplifier driver block (SADB) and the word line driver block (WDB) to read data. Therefore, the sense amplifiers included in the selected global sense amplifier block (GSAB) can be activated simultaneously, thereby increasing memory bandwidth. In addition, by simultaneously reading data from the selected memory cell 41 to the activated sense amplifiers, the time required for writing and reading can be shortened. Furthermore, by activating the global sense amplifier blocks (GSABs) one by one, the current flowing through the storage device as the number of activated sense amplifiers increases can be adjusted, thereby reducing the voltage drop across the power lines.

[0086] Furthermore, the storage device 100 according to one embodiment of the present invention can be configured to select a data readout amplifier block DSAB and access data read by a global readout amplifier block GSAB. Therefore, data simultaneously read by global readout amplifiers GSA included in the global readout amplifier block GSAB can be sequentially output according to the external bus width of the storage device 100. Additionally, by sequentially activating the data readout amplifier blocks DSAB, the current flowing through the storage device as the number of activated readout amplifiers increases can be suppressed, thereby reducing voltage drop across the power supply lines.

[0087] Figure 2A This is a schematic diagram illustrating an example of the structure of the memory cell 41 and the global sense amplifier GSA. Figure 2A Shown in Figure 1B The structure described above the area containing the global sense amplifier GSA and the data bit line pairs DBL-DBLB includes a component layer 40 containing memory cell 41. Memory cell 41 is connected to the global sense amplifier GSA via bit line pairs BL-BLB.

[0088] Figure 2B This is an explanation Figure 1A The schematic diagram shown depicts transistor 51 disposed in component layer 10 and transistor 53 disposed in component layer 40, representing a stacked component layer 10. Additionally, Figure 2B Show connection Figure 2A The storage cell 41 shown is paired with the bit line BL-BLB of the global sense amplifier GSA.

[0089] The semiconductor layer 52 included in transistor 51 is made of oxide semiconductor (metal oxide), thereby forming the memory cell 41 composed of OS transistors as described above.

[0090] By using silicon as the semiconductor layer 54 included in transistor 53, a global sense amplifier GSA can be provided in the element layer 10 composed of the aforementioned Si transistors.

[0091] By configuring the component layer 40 containing the storage unit 41 on the component layer containing the global sense amplifier GSA, the storage capacity, i.e. the number of storage units 41, can be increased compared to the case where the storage unit 41 and the global sense amplifier GSA are configured on the same layer.

[0092] Figure 3A The storage device 100A shown is Figure 2A A modified example of the storage device 100 shown. Figure 3A The diagram shown illustrates multiple stacked layers. Figure 2A An example of component layer 40. Specifically, Figure 3A The middle layer contains component layer 40_1 and component layer 40_2.

[0093] Figure 3A The storage device 100A shown includes a component layer 40_1 and a component layer 40_2, each configured with a plurality of storage cells 41. By employing this structure, the same manufacturing process using a photomask can be used in the plurality of component layers 40_1 and 40_2. Therefore, the same manufacturing process can be reused in the vertical direction to manufacture the storage cells 41, thereby reducing manufacturing costs.

[0094] Figure 3B It is set to include Figure 3A The diagram shows component layers 40_1 to 40_n (n is an integer of 2 or more) of component layers 40_1 and 40_2. Additionally, Figure 3B Show connection Figure 3A The memory cell 41 shown is paired with the bit line BL-BLB of the global sense amplifier GSA. (As shown...) Figure 3B As shown, in the storage device 100A, multiple element layers 40_1 to 40_n are stacked on the element layer 10 in a direction perpendicular or substantially perpendicular to the surface of the element layer 10. By adopting this structure, the number of storage cells 41 disposed per unit area can be increased. As a result, the storage density can be improved.

[0095] exist Figure 3B In this structure, the wiring distance between the memory cells 41 connected to the bit line pair BL-BLB can be shortened while increasing the number of memory cells 41 connected to the global sense amplifier GSA. By stacking the component layer 40, the wiring distance can be shortened, reducing parasitic capacitance generated in the bit line pair BL-BLB, thereby achieving low power consumption. Furthermore, the number of data bits can be increased while simultaneously reading data from the memory cells 41 to the global sense amplifier GSA at high speed.

[0096] Figure 4AThis is a block diagram used to illustrate the sense amplifier driver block control signal SADB_EN, word line driver block control signal WDB_EN, and data sense amplifier block control signal DSAB_EN output by the controller section 16.

[0097] exist Figure 4A In this example, the global sense amplifier section 11 includes eight global sense amplifier blocks (GSAB[1] to GSAB[8]). Additionally, in Figure 4A In the diagram, a memory cell array 42 is shown on the global sense amplifier blocks GSAB[1] to GSAB[8]. Although the diagram is omitted, the memory cell array 42 is provided with memory cells 41 connected to the global sense amplifiers GSA included in the global sense amplifier blocks GSAB[1] to GSAB[8].

[0098] Furthermore, as data sense amplifier blocks DSAB, eight data sense amplifier blocks DSAB corresponding to global sense amplifier blocks GSAB[1] to GSAB[8] are shown (in Figure 4A (See attached [1] to [8]). The controller section 16 supplies the data readout amplifier block control signal DSAB_EN to each of the eight data readout amplifier blocks DSAB for selecting and controlling each block.

[0099] Furthermore, as sense amplifier driver blocks SADB, eight sense amplifier driver blocks SADB corresponding to global sense amplifier blocks GSAB[1] to GSAB[8] are shown (in Figure 4A (See attached [1] to [8]). The controller section 16 supplies the SADB_EN ​​control signal to each of the eight sense amplifier driver blocks SADB for selecting and controlling each block.

[0100] Furthermore, as word line driver blocks (WDBs), eight word line driver blocks (WDBs) corresponding to global sense amplifier blocks (GSAB[1] to GSAB[8]) are shown (in... Figure 4A (See attached [1] to [8]). The controller section 16 supplies each of the eight word line drive blocks WDB with the word line drive block control signal WDB_EN ​​for selecting and controlling each block.

[0101] When selecting one or more blocks from among the aforementioned data readout amplifier block DSAB, readout amplifier driver block SADB, and word line driver block WDB, for example... Figure 4B As shown, the control signal IN_EN and the control signal B_EN from the controller section 16 can be combined and input into the AND gate 17, and control can be performed according to the obtained signal OUT_EN.

[0102] For example, Figure 5AThe following structure is shown: When one or more data readout amplifier blocks DSAB[1] to DSAB[8] are selected, the input data readout amplifier control signal DSA_EN and data readout amplifier block control signals DSAB_EN[1] to DSAB_EN[8] are input to AND gate 17 connected to the data readout amplifier blocks DSAB[1] to DSAB[8] respectively for control. The data readout amplifier control signal DSA_EN is a signal that makes the data readout amplifier block DSAB in a state of accessing data read by the global readout amplifier block GSAB. By adopting this structure, the data readout amplifier block DSAB selected by the data readout amplifier block control signals DSAB_EN[1] to DSAB_EN[8] can be made to access data read by the global readout amplifier block GSAB.

[0103] For example, Figure 5B The following structure is shown: When one or more of the sense amplifier driver blocks SADB[1] to SADB[8] are selected, the input sense amplifier driver control signal SAD_EN and sense amplifier block control signals SADB_EN[1] to SADB_EN[8] are input to AND gate 17 connected to sense amplifier driver blocks SADB[1] to SADB[8] respectively for control. The sense amplifier driver control signal SAD_EN is a signal used to output the sense amplifier control signal SAEN from the sense amplifier driver block SADB to activate the global sense amplifier GSA. By adopting this structure, the sense amplifier driver block SADB selected by the sense amplifier driver block control signals SADB_EN[1] to SADB_EN[8] can output the sense amplifier control signal SAEN to activate the global sense amplifier GSA included in the corresponding global sense amplifier block GSAB.

[0104] For example, Figure 5C The following structure is shown: When one or more word line driver blocks WDB[1] to WDB[8] are selected, the input word line driver control signal WD_EN and word line driver block control signals WDB_EN[1] to WDB_EN[8] are input to AND gate 17 connected to word line driver blocks WDB[1] to WDB[8] respectively for control. The word line driver control signal WD_EN is a signal used to output the word signal SWL from the word line driver block WDB and select the memory cell 41. By adopting this structure, the memory cell 41 connected to the global sense amplifier GSA included in the corresponding global sense amplifier block GSAB can be selected by outputting the word signal SWL from the word line driver block WDB selected by the word line driver block control signals WDB_EN[1] to WDB_EN[8].

[0105] <Example of operation of storage device 100> exist Figures 6A to 10B In the middle, refer to Figures 4A to 5C The structural examples described illustrate the operation of the storage device 100. Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A Shown in Figure 4A The blocks selected by the controller unit 16 in the block diagram are shown with shading added to the selected blocks (where the readout amplifier is activated).

[0106] in addition, Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B They correspond to Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A The timing diagram shows the state. Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B The timing diagram shows Figures 5A to 5C The data readout amplifier control signals DSA_EN, readout amplifier driver block control signals SADB_EN[1] to SADB_EN[8], word line drive control signals WD_EN, word line driver block control signals WDB_EN[1] to WDB_EN[8], data readout amplifier control signals DSA_EN, and data readout amplifier block control signals DSAB_EN[1] to DSAB_EN[8] are described below. Note that the cases where each control signal is selected at H level and deselected at L level are explained.

[0107] exist Figures 6A to 10B This section describes the case where the global sense amplifier block GSAB, sense amplifier driver block SADB, word line driver block WDB, and data sense amplifier block DSAB each consist of eight blocks. Note that the number of blocks is not limited to eight; preferably, there are two or more. By having multiple global sense amplifier blocks GSAB, sense amplifier driver blocks SADB, word line driver blocks WDB, and data sense amplifier blocks DSAB, the number of blocks controlled by the control signal can be switched. The number of controlled blocks can be multiple or one.

[0108] Figure 6A and Figure 6BThe diagram illustrates the operation and timing when a global sense amplifier block, such as global sense amplifier block GSAB[1], is selected. When data is read out by activating the sense amplifiers included in global sense amplifier block GSAB[1], as shown... Figure 6B The control signals are set as shown. Specifically, the data readout amplifier control signal DSA_EN, the word line drive control signal WD_EN and the data readout amplifier control signal DSA_EN are set to H level, and the readout amplifier drive block control signal SADB_EN[1] and the word line drive block control signal WDB_EN[1] corresponding to the global readout amplifier block GSAB[1] are set to H level.

[0109] By adopting this structure, in the memory cell array 42, the memory cell 41 connected to the read amplifier included in the global read amplifier block GSAB[1] is selected by the word signal SWL output by the corresponding word line driver block control signal WDB_EN[1]. In addition, the read amplifier included in the global read amplifier block GSAB[1] is activated by the read amplifier control signal SAEN output by the corresponding read amplifier driver block SADB[1].

[0110] In addition, Figure 6A and Figure 6B During period T1, the data readout amplifier block control signal DSAB_EN[1] is set to level H. By adopting this structure, the data readout amplifier block DSAB[1] becomes capable of accessing the data read by the readout amplifiers included in the global readout amplifier block GSAB[1], thereby reading data from the readout amplifiers included in the global readout amplifier block GSAB[1] selected by the column selection signal CSE.

[0111] Figures 7A to 8B The diagram illustrates the operation and timing when two global sense amplifier blocks, such as global sense amplifier blocks GSAB[1] and GSAB[2], are selected. When data is read out by activating the sense amplifiers included in global sense amplifier blocks GSAB[1] and GSAB[2], as shown... Figure 7B and Figure 8B The control signals are set as shown. Specifically, the data sense amplifier control signal DSA_EN, the word line drive control signal WD_EN and the data sense amplifier control signal DSA_EN are set to H level, and the sense amplifier drive block control signals SADB_EN[1] and SADB_EN[2] corresponding to the global sense amplifier blocks GSAB[1] and GSAB[2] and the word line drive block control signals WDB_EN[1] and WDB_EN[2] are set to H level.

[0112] By adopting this structure, in the memory cell array 42, the memory cell 41 connected to the read amplifiers included in the global read amplifier blocks GSAB[1] and GSAB[2] is simultaneously selected by the word signal SWL output by the corresponding word line driver block control signals WDB_EN[1] and WDB_EN[2]. In addition, the read amplifiers included in the global read amplifier blocks GSAB[1] and GSAB[2] are simultaneously activated by the read amplifier control signal SAEN output by the corresponding read amplifier driver blocks SADB[1] and SADB[2].

[0113] In addition, Figure 7A and Figure 7B During period T2-1, the data readout amplifier block control signal DSAB_EN[1] is set to level H. By adopting this structure, the data readout amplifier block DSAB[1] becomes capable of accessing the data read by the readout amplifiers included in the global readout amplifier block GSAB[1], thereby reading data from the readout amplifiers included in the global readout amplifier block GSAB[1] selected by the column selection signal CSE.

[0114] Next, in Figure 8A and Figure 8B During period T2-2, the data readout amplifier block control signal DSAB_EN[2] is set to level H. By adopting this structure, the data readout amplifier block DSAB[2] becomes capable of accessing the data read by the readout amplifiers included in the global readout amplifier block GSAB[2], thereby reading data from the readout amplifiers included in the global readout amplifier block GSAB[2] selected by the column selection signal CSE.

[0115] Figures 9A to 10B The diagram illustrates the operation and timing when all eight global sense amplifier blocks, such as global sense amplifier blocks GSAB[1] and GSAB[8], are selected. When data is read out by activating the sense amplifiers included in global sense amplifier blocks GSAB[1] to GSAB[8], as shown... Figure 9B and Figure 10B The control signals are set as shown. Specifically, the data sense amplifier control signal DSA_EN, the word line drive control signal WD_EN and the data sense amplifier control signal DSA_EN are set to H level, and the sense amplifier drive block control signals SADB_EN[1] to SADB_EN[8] and the word line drive block control signals WDB_EN[1] to WDB_EN[8] corresponding to the global sense amplifier blocks GSAB[1] to GSAB[8] are set to H level.

[0116] By adopting this structure, in the memory cell array 42, the memory cell 41 connected to the read amplifiers included in the global read amplifier blocks GSAB[1] to GSAB[8] is simultaneously selected by the word signal SWL output by the corresponding word line driver block control signals WDB_EN[1] to WDB_EN[8]. In addition, the read amplifiers included in the global read amplifier blocks GSAB[1] to GSAB[8] are simultaneously activated by the read amplifier control signal SAEN output by the corresponding read amplifier driver blocks SADB[1] to SADB[8].

[0117] In addition, Figure 9A and Figure 9B During period T3-1, the data readout amplifier block control signal DSAB_EN[1] is set to level H. By adopting this structure, the data readout amplifier block DSAB[1] becomes capable of accessing the data read by the readout amplifiers included in the global readout amplifier block GSAB[1], thereby reading data from the readout amplifiers included in the global readout amplifier block GSAB[1] selected by the column selection signal CSE.

[0118] Additionally, although the explanation is omitted, the data readout amplifier block control signals DSAB_EN[2] to DSAB_EN[7] are sequentially set to H level (equivalent to periods T3-2 to T3-7). By adopting this structure, the data readout amplifier blocks DSAB[2] to DSAB[7] are sequentially configured to access the data read by the readout amplifiers included in the global readout amplifier blocks GSAB[2] to GSAB[7], thereby allowing data to be read sequentially from the readout amplifiers included in the global readout amplifier blocks GSAB[2] to GSAB[7] selected by the column selection signal CSE.

[0119] Next, in Figure 10A and Figure 10B During period T3-8, the data readout amplifier block control signal DSAB_EN[8] is set to level H. By adopting this structure, the data readout amplifier block DSAB[8] becomes capable of accessing the data read by the readout amplifiers included in the global readout amplifier block GSAB[8], thereby reading data from the readout amplifiers included in the global readout amplifier block GSAB[8] selected by the column selection signal CSE.

[0120] According to one aspect of the present invention, a storage device 100 has a structure that selects one or more global sense amplifier blocks (GSABs) to control a sense amplifier driver block (SADB) and a word line driver block (WDB) to read data. Therefore, the sense amplifiers included in the selected global sense amplifier block (GSAB) can be activated simultaneously, thereby increasing memory bandwidth. Furthermore, by simultaneously reading data from the selected memory cell 41 to the activated sense amplifiers, the time required for writing and reading can be shortened. Additionally, by activating the global sense amplifier blocks (GSABs) one by one, the current flowing through the storage device as the number of activated sense amplifiers increases can be adjusted, thereby reducing voltage drop across the power lines.

[0121] Furthermore, the storage device 100 according to one embodiment of the present invention can be configured to select a data readout amplifier block DSAB and access data read by a global readout amplifier block GSAB. Therefore, data simultaneously read by global readout amplifiers GSA included in the global readout amplifier block GSAB can be sequentially output according to the external bus width of the storage device 100. Additionally, by sequentially activating the data readout amplifier blocks DSAB, the current flowing through the storage device as the number of activated readout amplifiers increases can be suppressed, thereby reducing voltage drop across the power supply lines.

[0122] <Structure example of storage unit 41> Next, an example of a circuit structure that can be used as a memory cell 41 will be described. Alternatively, memory cell 41 can be a memory cell including an OS transistor. A memory that includes a memory cell with an OS transistor is sometimes referred to as an "OS memory".

[0123] The off-state current of the OS transistor is extremely small. Therefore, the charge corresponding to the data written to the memory cell 41 can be maintained for a long time. In other words, the written data can be retained in the memory cell 41 for a long time. Therefore, the frequency of data refresh can be reduced, thereby reducing the power consumption of the memory device 100 according to one aspect of the present invention.

[0124] Figure 11A This is a diagram illustrating a memory cell array 42 that includes multiple memory cells 41. Figure 11A The diagram shows word lines WL_1 to WL_m and bit lines BL_1 to BL_n arranged side-by-side in an m-row, n-column configuration (where m and n are natural numbers greater than 2). Additionally, a memory cell 41 connected to each word line WL and bit line BL is also shown.

[0125] Figure 11BThis is a circuit diagram illustrating an example of a circuit structure that can be applied to memory cell 41. Memory cell 41 includes a transistor M1 and a capacitor C1 (also called a capacitor). Transistor M1 is connected to word line WL, bit line BL, and capacitor C1. Additionally, capacitor C1 is connected to wiring PL, which serves as a capacitor line. For example, wiring PL is connected to the input voltage GND (a low-level power supply potential). Furthermore, Figure 11C It corresponds to Figure 11B The circuit blocks in the circuit diagram.

[0126] Figure 11B The shown memory cell 41 can be a 1T (transistor) 1C (capacitor) type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is RAM that includes 1T 1C type memory cells. DOSRAM is DRAM formed using OS transistors, and DOSRAM is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors. DOSRAM is a 1T 1C type memory cell, therefore a memory cell array 42 with a large storage capacity can be realized. Furthermore, by using OS transistors, the data retention period can be extended compared to DRAM that includes Si transistors.

[0127] The circuit structure that can be used in storage cell 41 is not limited to Figure 11B The 1T1C type DOSRAM. For example. Figure 12A Other structural examples of 1T1C type memory cells that can be used as DOSRAM are shown. Figure 12A The storage cell 41A shown is Figure 11B The difference in the shown memory cell 41 is that, in the former, transistor M1 is an OS transistor including a back gate connected to wiring BGL. By including wiring BGL, transistor M1 can be a transistor with improved electrical characteristics.

[0128] The memory cell 41, including the OS transistor, can be NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory). NOSRAM memory cells are either two-transistor (2T) gain cells or three-transistor (3T) gain cells. NOSRAM rewrites data using the charging and discharging of capacitors, thus theoretically having no limit on the number of rewrites and low energy consumption. Therefore, NOSRAM is a high-speed, low-power, and highly rewrite-tolerant memory. Furthermore, NOSRAM allows for non-destructive reading of written data, making it suitable for long-term data retention.

[0129] Figure 12B The illustrated memory cell 41B is a circuit equivalent to a 2T type NOSRAM. In memory cell 41B, transistors M1 and M2, including transistor M1, transistor M2, and capacitor C1, are respectively a write transistor and a read transistor. Transistors M1 and M2 can be OS transistors with semiconductor layers arranged in different layers, or OS transistors with semiconductor layers arranged in the same layer. Memory cell 41B is shown as an example connected to the write bit line WBL, the read bit line RBL, the write word line WWL, the read word line RWL, and the source line SL.

[0130] Figure 12C The shown memory cell 41C is a circuit equivalent to a 3T type NOSRAM. Memory cell 41C includes transistors M1, M2, and M3, and a capacitor C1. Transistors M1, M2, and M3 are the write transistor, read transistor, and select transistor, respectively. Transistors M1, M2, and M3 can be OS transistors with semiconductor layers configured on different layers, or they can be OS transistors with semiconductor layers configured on the same layer.

[0131] Since the write transistor is composed of an OS transistor, the charge corresponding to the data can be maintained by turning off the write transistor. Therefore, memory cells 41B and 41C do not consume power while holding data. Thus, memory cells 41B and 41C can retain data for extended periods and can be used as low-power memory cells. Note that the gate of the read transistor serves as a node for holding the charge corresponding to the data. The read transistor is a transistor that allows current to flow according to the potential of the node holding the charge corresponding to the data. The select transistor is a transistor that controls the current flowing through the read transistor.

[0132] Figure 12D Other structural examples of the 2T type gain unit are shown. Figure 12D The storage cell 41D shown is Figure 12BThe difference in the shown memory cell 41B is that, in the former, transistors M1 and M2 are both OS transistors including a back gate, and the back gate is connected to the wiring BGL. For example, the wiring BGL is connected to the input voltage GND (low-level side power supply potential). By including the wiring BGL, transistors M1 and M2 can be transistors with improved electrical characteristics.

[0133] Figure 12E Other structural examples of the 3T type gain unit are shown. Figure 12E The storage cell 41E shown is Figure 12C The difference in the shown memory cell 41C is that, in the former, transistors M1, M2, and M3 are all OS transistors including a back gate, and this back gate is connected to the wiring BGL. For example, the wiring BGL is connected to the input voltage GND (low-level side power supply potential). By including the wiring BGL, transistors M1, M2, and M3 can be transistors with improved electrical characteristics.

[0134] Figure 12F Other structural examples of the 2T type gain unit are shown. Figure 12F The storage cell 41F shown is Figure 12B The difference in the memory cell 41B shown is that, in the former, capacitor C1 is omitted by using the gate capacitor of the read transistor; and wiring PL is omitted.

[0135] Figure 12F The transistors M1 and M2 included in the 2T-type gain unit shown are preferably vertical transistors, wherein the source and drain electrodes are located at different heights. For example, a vertical transistor corresponds to the one described later. Figure 20 or Figure 21A Transistor M1 shown in Figure 22, transistor VM1 shown in Figure 22, Figure 24 The transistor VM2 shown Figures 26A to 26D Transistors VT1 and VT2, as shown, flow in the vertical direction (height direction) of the channel formation region in the semiconductor layer. In other words, the channel length direction can be said to include a component in the height direction (vertical direction). Therefore, these vertical transistors can also be called VFETs (Vertical Field Effect Transistors), vertical channel transistors, or simply vertical transistors.

[0136] Compared to lateral transistors (also known as planar structures or planar transistors) where the source and drain electrodes are at the same height, vertical transistors have a structure in which at least a portion of the source region, channel formation region, and drain region overlap when viewed from above, thus reducing the occupied area (also known as the footprint). Furthermore, because they have a structure that allows for a shorter channel length and a wider channel width, the on-state resistance can be reduced (increasing the on-state current).

[0137] Figure 12G Other structural examples of the 3T type gain unit are shown. Figure 12G The storage cell 41G shown is Figure 12C The difference in the memory cell 41C shown is that, in the former, capacitor C1 is omitted by using the gate capacitor of the read transistor; and wiring PL is omitted. Figure 12G The transistors M1, M2, and M3 included in the 3T-type gain unit shown can reduce the occupied area and reduce the on-state resistance (increase the on-state current) by using vertical transistors with the source and drain electrodes located at different heights.

[0138] <Example of Global Sensing Amplifier (GSA) Structure> An example of the circuit structure of the Global Sensing Amplifier (GSA) is provided. Figure 13A This is the circuit diagram of the Global Readout Amplifier (GSA). Figure 13B The circuit blocks corresponding to this circuit diagram are shown. Additionally, Figure 13C Show combination Figure 11C The circuit block of the storage unit 41 shown is... Figure 13B The diagram shows an example of the circuit block structure of the Global Sense Amplifier (GSA).

[0139] Figure 13A The global sense amplifier (GSA) shown includes a sense amplifier 61, a precharge circuit 62, a precharge circuit 63, and a switching circuit 64. The sense amplifier 61, the precharge circuit 62, the precharge circuit 63, and the switching circuit 64 are connected to the bit line pair BL-BLB, respectively.

[0140] The sense amplifier 61 has the function of supplying a predetermined potential to the bit line BL to output a potential corresponding to one of the two data values, and to output a potential corresponding to the other of the two data values ​​to the inverted bit line BLB. The sense amplifier 61 includes transistors 61_1, 61_2, 61_3, and 61_4. Transistors 61_1 and 61_2 are p-channel transistors. Transistors 61_3 and 61_4 are n-channel transistors. Transistors 61_1 and 61_3 form an inverter circuit with the inverted bit line BLB as input, the bit line BL as output, the bit line SAP as a high-potential power supply line, and the bit line SAN as a low-potential power supply line. Transistors 61_2 and 61_4 form an inverter circuit with the bit line BL as input, the bit line BLB as output, the bit line SAP as a high-potential power supply line, and the bit line SAN as a low-potential power supply line.

[0141] The pre-charge circuit 62 has the function of pre-charging the bit line pair BL-BLB to potential VPRE according to the signal EQB. Specifically, the pre-charge circuit 62 includes transistors 62_1, 62_2, and 62_3. Transistors 62_1, 62_2, and 62_3 are all p-channel transistors. Transistor 62_1 has the function of switching to an on or off state between itself and the bit line pair BL-BLB according to the signal EQB. Transistor 62_2 has the function of pre-charging the bit line BL to potential VPRE according to the signal EQB. Transistor 62_3 has the function of pre-charging the inverted bit line BLB to potential VPRE according to the signal EQB.

[0142] The pre-charge circuit 63 has the function of pre-charging the bit line pair BL-BLB to potential VPRE according to the signal EQ. Specifically, the pre-charge circuit 63 includes transistors 63_1, 63_2, and 63_3. Transistors 63_1, 63_2, and 63_3 are all n-channel transistors. Transistor 63_1 has the function of switching between an on and off state with the bit line pair BL-BLB according to the signal EQ. Transistor 63_2 has the function of pre-charging the bit line BL to potential VPRE according to the signal EQ. Transistor 63_3 has the function of pre-charging the inverted bit line BLB to potential VPRE according to the signal EQ.

[0143] The switching circuit 64 has the function of turning the bit line pair BL-BLB and the data bit line pair DBL-DBLB into an on or off state according to the column select signal CSE. Specifically, the switching circuit 64 includes transistors 64_1 and 64_2. Both transistors 64_1 and 64_2 are n-channel transistors. Transistor 64_1 has the function of turning the bit line BL and the data bit line DBL into an on or off state according to the column select signal CSE. Transistor 64_2 has the function of turning the data bit line pair DBL-DBLB and the bit line pair BL-BLB into an on or off state according to the column select signal CSE.

[0144] Figure 13B Showing the corresponding Figure 13A The circuit block diagram of the Global Sense Amplifier (GSA) is explained. Additionally, Figure 13C Show combination Figure 13B The circuit block of the global sense amplifier GSA shown is... Figure 11C The circuit block structure of the storage unit 41 shown is an example.

[0145] Signals such as EQ and EQB that control the Global Sensing Amplifier (GSA) are equivalent to the sensing amplifier control signal SAEN. Furthermore, the sensing amplifier control signal SAEN can also include the potentials of the wiring SAP and wiring SAN. For example, when the GSA is driven, potentials from the wiring SAP and wiring SAN are supplied. Conversely, when the GSA is stopped, the potentials from the wiring SAP and wiring SAN are cut off. Therefore, the signals controlling the GSA can also include the potentials of the wiring SAP and wiring SAN.

[0146] exist Figures 13A to 13C In the structure of the global sense amplifier GSA shown, by reading data from memory cell 41, the potential difference between bit line BL and the inverted bit line BLB, which are affected by charge fluctuations held in memory cell 41, can be amplified, and output to the data bit line pair DBL-DBLB according to the column select signal CSE. Furthermore, in Figures 13A to 13C In the structure of the global sense amplifier GSA shown, the amplified potential difference can be written into the memory cell 41 connected to the bit line pair BL-BLB by applying the potential difference of the data bit line pair DBL-DBLB to the bit line pair BL-BLB according to the column select signal CSE.

[0147] <Example of the structure of a Data Readout Amplifier Block (DSAB)> An example of the circuit structure of the data readout amplifier block (DSAB) is provided. Figure 14A This is the circuit diagram of the Data Readout Amplifier (DSAB). Figure 14BThe circuit blocks corresponding to this circuit diagram are shown. Additionally, Figure 14C Show combination Figure 11C The circuit block of the storage unit 41 shown and Figure 13B The circuit block of the global sense amplifier GSA shown is... Figure 14B The diagram shows an example of the circuit block structure of the data readout amplifier block DSAB.

[0148] Figure 14A The data readout amplifier block (DSAB) shown includes a precharge circuit 65, a readout amplifier 66, a switching circuit 67, a transistor 68, an AND gate 69, and a latch circuit 70. Additionally, Figure 14A The data readout amplifier block DSAB shown includes Figure 4B and Figure 5A AND gate 17 is shown. The precharge circuit 65, the readout amplifier 66, and the switch circuit 67 are respectively connected to the data bit line pair DBL-DBLB.

[0149] Figure 14A The diagram shows an AND gate 17 positioned in the gate of transistor 68, but other structures are also possible. For example, a structure could be used where the data sense amplifier block control signal DSAB_EN supplied to AND gate 17 controls the signals input to the precharge circuit 65, sense amplifier 66, switching circuit 67, AND gate 69, and latch circuit 70. In this case, the inactive data sense amplifier block DSAB can be more reliably kept in a non-operating state, thereby achieving low power consumption. Alternatively, a structure could be used where a separate switch is provided between the data sense amplifier block DSAB and the data bit line pair DBL-DBLB, and the switch is controlled to open or close according to the data sense amplifier block control signal DSAB_EN. In this case, the current flowing through the data bit line pair DBL-DBLB and the data sense amplifier block DSAB can be more reliably reduced, thereby achieving low power consumption.

[0150] The precharge circuit 65 functions to precharge the data bit lines DBL-DBLB to the potential of the wiring DSAP according to the signal DEQ_ENB. The wiring DSAP is a high-potential power supply line. Specifically, the precharge circuit 65 includes transistors 65_1, 65_2, and 65_3. Transistors 65_1, 65_2, and 65_3 are all p-channel transistors. Transistor 65_1 functions to switch the data bit line DBL and the inverted data bit line DBLB to an on or off state according to the signal DEQ_ENB. Transistor 65_2 functions to precharge the data bit line DBL to the potential of the wiring DSAP according to the signal DEQ_ENB. Transistor 65_3 functions to precharge the inverted data bit line DBLB to the potential of the wiring DSAP according to the signal DEQ_ENB.

[0151] The sense amplifier 66 has the function of supplying a predetermined potential to the data bit line DBL corresponding to one of the two data values ​​and to the inverted data bit line DBLB corresponding to the other of the two data values ​​by supplying a predetermined potential to the wiring DSAP and wiring DSAN. The sense amplifier 66 includes transistors 66_1, 66_2, 66_3, and 66_4. Transistors 66_1 and 66_2 are p-channel transistors. Transistors 66_3 and 66_4 are n-channel transistors. Transistors 66_1 and 66_3 form an inverter circuit with the inverted data bit line DBLB as input, the data bit line DBL as output, wiring DSAP as a high-potential power supply line, and wiring DSAN as a low-potential power supply line. Transistors 66_2 and 66_4 form an inverter circuit with the data bit line DBL as input, the inverted data bit line DBLB as output, wiring SAP as a high-potential power supply line, and wiring SAN as a low-potential power supply line.

[0152] The potential of the DSAN supply wiring to the sense amplifier 66 is controlled by the data sense amplifier control signal DSA_EN supplied to transistor 68. The data sense amplifier control signal DSA_EN controls the state of the sense amplifier 66. When the data sense amplifier control signal DSA_EN turns transistor 68 on, the sense amplifier 66 is activated; when the data sense amplifier control signal DSA_EN turns transistor 68 off, the sense amplifier 66 is deactivated.

[0153] Switching circuit 67 controls the supply of write data W to data bit lines DBL-DBLB according to write control signals WE and WEB. DATA W DATA The function of _B. The write control signal WEB is the inverted version of the write control signal WE. Write data W DATA _B is the data to be written (W). DATA The switching circuit 67 includes transistors 67_1 to 67_4. Transistors 67_1 and 67_3 are n-channel transistors. Transistors 67_2 and 67_4 are p-channel transistors. Transistors 67_1 and 67_2 are used to control the supply of write data W to the inverted data bit line DBLB. DATA The analog switch of _B. Transistors 67_3 and 67_4 are used to control the supply of write data W to the data bit line DBL. DATA Analog switch.

[0154] AND gate 69 has the function of outputting the potential of the data bit line DBL to latch circuit 70 according to the control of signal RE. Signal RE is the read control signal. In addition, latch circuit 70 has the function of reading the output signal of AND gate 69 according to the latch signal DLAT and using it as the read data R. DATA Output function.

[0155] Figure 14B Showing the corresponding Figure 14A The circuit diagram for the DSAB (Data Readout Amplifier Block) is described below. Additionally, Figure 14C Show combination Figure 14B The circuit block shown is the DSAB data readout amplifier block. Figure 13C The diagram shows an example of the structure of the memory cell 41 and the global sense amplifier GSA circuit block.

[0156] exist Figures 14A to 14C The data readout amplifier block DSAB shown in the diagram amplifies the potential difference between the data bit lines and DBL-DBLB, which varies due to the column select signal CSE, and uses this difference as the readout data R based on the signal RE and the latch signal DLAT. DATA Output. Additionally, in Figures 14A to 14C In the structure of the data readout amplifier block DSAB shown, the data bit line pair DBL-DBLB can be amplified by controlling the write control signals WE and WEB, which supply the written data W. DATA W DATA The potential difference at time _B, controlled by the column select signal CSE, can apply the potential of the data bit line pair DBL-DBLB to the bit line pair BL-BLB, and write the potential difference amplified by the global sense amplifier GSA as data into the memory cell 41 connected to the bit line pair BL-BLB.

[0157] As described above, according to one aspect of the present invention, a storage device controls a read amplifier driver block and a word line driver block to select one or more global read amplifier blocks and read data. Therefore, switching can be performed between simultaneously activating or sequentially activating the read amplifiers included in the selected global read amplifiers. This allows for switching of memory bandwidth for output.

[0158] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0159] (Implementation Method 2) In this embodiment, an example of a cross-sectional structure having a stacked OS transistor element layer that can be used in storage devices, etc., will be described. In this embodiment, an example of a cross-sectional schematic diagram that can be used in circuit structures such as NOSRAM and DOSRAM will be described.

[0160] <Example structure 1 of NOSRAM> Figure 15 Shows an example of a cross-sectional structure when adopting the circuit structure of a three-transistor type NOSRAM. Figure 15 Shows an example of a case where the element layer UF[1] to the element layer UF[3] are stacked on the element layer LF. In addition, Figure 16A Shows an example of the cross-sectional structure of the element layer UF[k]. In addition, Figure 16B is Figure 16A the equivalent circuit diagram.

[0161] The element layer LF is the element layer 10 described in the above Embodiment 1. Elements such as Si transistors are provided in the element layer LF. The element layer UF is the element layer 40 described in the above Embodiment 1. Elements such as OS transistors are provided in the element layer UF.

[0162] In addition, Figure 15 Shows an example of the transistor 550 included in the element layer LF. The transistor 550 is provided on the substrate 311 and includes a conductive layer 316 used as a gate electrode, an insulating layer 315, a semiconductor region 313 formed by a part of the substrate 311, and low-resistance regions 314a and 314b used as source regions or drain regions.

[0163] In addition, the transistor 550 can be either a p-channel transistor or an n-channel transistor.

[0164] In the low-resistance regions 314a and 314b, in addition to the semiconductor material applied to the semiconductor region 313, elements such as arsenic and phosphorus that impart n-type conductivity or an element such as boron that imparts p-type conductivity are also included.

[0165] In addition, Figure 15 The shown transistor 550 is just an example, and appropriate transistors can be used according to the circuit structure or driving method without being limited to its structure.

[0166] Between the element layer LF and the element layer UF or between the k-th layer element layer UF and the (k + 1)-th layer element layer UF, a wiring layer provided with an interlayer film, wirings, plugs, etc. can also be provided. In addition, in this embodiment etc., the k-th layer element layer UF is sometimes denoted as the element layer UF[k], and the (k + 1)-th layer element layer UF is denoted as the element layer UF[k + 1]. Here, k is an integer of 1 or more and N or less. In addition, in this embodiment etc., when denoted as "k + α (α is an integer of 1 or more)" or "k - α", the solutions of "k + α" and "k - α" are each an integer of 1 or more and N or less.

[0167] Furthermore, the wiring layer can be configured as multiple layers depending on the design. Additionally, in this specification and other materials, wiring and connectors for connecting to wiring can also be considered components. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a connector.

[0168] For example, in transistor 550, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322. Furthermore, conductive layers 330 are embedded in insulating layers 324 and 326. Furthermore, conductive layers 328 and 330 are used as contact plugs or wiring.

[0169] Alternatively, a wiring layer can be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 15 In this structure, insulating layers 350, 357, 352, and 354 are sequentially stacked on insulating layer 326 and conductive layer 330. Furthermore, a conductive layer 356 is formed within insulating layers 350, 357, and 352. The conductive layer 356 is used as a contact plug or wiring.

[0170] An insulating layer 514, characteristic of the component layer UF, is provided on the insulating layer 354. Furthermore, a conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 is used as a contact plug or wiring. For example, wiring used as bit lines is connected to the transistor 550 via conductive layers 358, 356, and 330.

[0171] like Figure 16A As shown, Figure 15 The storage cell 41E shown includes transistors M2, M3 and M1 on the insulating layer 514.

[0172] also, Figure 15 and Figure 16A Transistors M2 and M3 shown share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 is used as the channel formation region for transistor M2, and another portion is used as the channel formation region for transistor M3. Furthermore, the source of transistor M2 and the drain of transistor M3, or vice versa, are shared. Therefore, compared to the case where transistors M2 and M3 are disposed independently, the transistors occupy a smaller area.

[0173] Note that in Figure 15 and Figure 16AThe memory cell 41E shown can be configured without transistor M1. The memory cell 41E with the configuration of not having transistor M1 can be a dual-transistor type NOSRAM, which is equivalent to... Figure 12D The storage unit 41D shown is shown.

[0174] Here, refer to Figures 17A to 17C Explain the OS transistor. Figure 17A and Figure 17B This is a cross-sectional schematic diagram of transistor 500, which can be used as transistors M1 to M3.

[0175] like Figure 17A and Figure 17B As shown, an insulating layer 516 is disposed on an insulating layer 514. The transistor 500 includes: a conductive layer 503 disposed in the insulating layer 516; an insulating layer 522 disposed on the insulating layer 516 and the conductive layer 503; an insulating layer 524 disposed on the insulating layer 522; a semiconductor layer 530 disposed on the insulating layer 524; conductive layers 542a and 542b disposed on the semiconductor layer 530 spaced apart from each other; an insulating layer 580 disposed on the conductive layers 542a and 542b and having an opening overlapping between the conductive layers 542a and 542b; an insulating layer 545 disposed on the bottom and side surfaces of the opening; and a conductive layer 560 disposed on the forming surface of the insulating layer 545. The conductive layer 560 includes a conductive layer 560a disposed inside the insulating layer 545 and a conductive layer 560b disposed inside the conductive layer 560a.

[0176] In addition, such as Figure 17A and Figure 17B As shown, insulating layer 544 is disposed between semiconductor layer 530, conductive layer 542a and conductive layer 542b and insulating layer 580. Furthermore, insulating layer 574 is disposed on insulating layer 580, conductive layer 560 and insulating layer 545, and insulating layer 581 is disposed on insulating layer 574.

[0177] Here, in transistor 500, conductive layer 560 is used as the gate electrode, insulating layer 545 is used as the gate insulating film, and conductive layers 542a and 542b are used as the source electrode or drain electrode, respectively. Conductive layer 560 is sometimes used as the first gate electrode. Conductive layer 503 is sometimes used as the second gate electrode. Insulating layers 522 and 524 are used as the second gate insulating film.

[0178] In addition, Figure 17A and Figure 17BIn the transistor 500, insulating layer 522 and insulating layer 524 are shown as the second gate insulating film, which is a two-layer stacked structure. However, the second gate insulating film may also have a single-layer structure or a stacked structure of three or more layers. In this case, it is not limited to using a stacked structure made of the same material, and a stacked structure made of different materials may also be used.

[0179] In transistor 500, an oxide semiconductor layer is preferably used as the semiconductor layer 530 including the channel formation region. The oxide semiconductor layer that can be used as semiconductor layer 530 will be described in Embodiment 3 described later.

[0180] In the channel formation region of a transistor where an oxide semiconductor is used as the semiconductor layer, it is preferable that, compared to the source and drain regions, there are fewer oxygen vacancies (hereinafter, sometimes referred to as V0). O The concentration of impurities such as hydrogen, nitrogen, and metal elements is low. Additionally, hydrogen near oxygen vacancies sometimes forms defects (hereinafter sometimes referred to as V0) that allow hydrogen to enter oxygen vacancies. O H) generates electrons that become charge carriers, so V is generated in the channel formation region. O H is also preferably reduced. Thus, the channel formation region of the transistor is a high-resistivity region with low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0181] Furthermore, the source and drain regions of transistors using oxide semiconductors as semiconductor layers are as follows: Due to the higher number of oxygen vacancies compared to the channel formation region, V... O High concentrations of impurities such as hydrogen, nitrogen, and metals increase carrier concentration, resulting in lower resistance. In other words, compared to the channel region, the source and drain regions of a transistor are n-type regions with higher carrier concentration and lower resistance.

[0182] The bandgap of the oxide semiconductor is preferably 2 eV or higher, more preferably 2.5 eV or higher. By using an oxide semiconductor with a large bandgap as the semiconductor layer, the off-state current of the transistor can be reduced. By using transistors with low off-state current in the memory cells, the stored content can be retained for a long time. In other words, refresh operations are not required or the refresh frequency is extremely low, thereby significantly reducing the power consumption of the memory device.

[0183] Figure 17A and Figure 17B The semiconductor layer 530 is shown as a single layer, but the invention is not limited thereto. For example, the semiconductor layer 530 may also be a stacked structure of two or more layers.

[0184] When an oxide semiconductor is used as the semiconductor layer 530, such as Figure 17AAs shown, sometimes a region 543a is formed at and near the interface between the semiconductor layer 530 and the conductive layer 542a as a low-resistance region. Similarly, sometimes a region 543b is formed at and near the interface between the semiconductor layer 530 and the conductive layer 542b as a low-resistance region. In this case, regions 543a and 543b are used as source regions or drain regions, respectively. Furthermore, a channel forming region is formed in the region sandwiched between regions 543a and 543b.

[0185] Note that the semiconductor material that can be used for semiconductor layer 530 is not limited to oxide semiconductor. Semiconductor materials other than oxide semiconductors can also be used as semiconductor layer 530. Other semiconductor materials that can be used for semiconductor layer 530 will be described later in the section on [Other Semiconductor Materials].

[0186] exist Figure 17A The conductive layer 542a and conductive layer 542b are single-layer structures, but the present invention is not limited thereto. For example, the conductive layer 542a and conductive layer 542b can also be a stacked structure of two or more layers.

[0187] exist Figure 17A and Figure 17B The conductive layer 560 and the conductive layer 503 are two-layer structures, but the present invention is not limited thereto. For example, the conductive layer 560 and the conductive layer 503 can also be single-layer structures or stacked structures of three or more layers.

[0188] The insulating layer 580 is preferably disposed on the conductive layers 542a and 542b, with the insulating layer 544 as a buffer. The opening of the insulating layer 580 is formed to overlap with the area between the conductive layers 542a and 542b. Thus, the conductive layer 560 is disposed such that it is embedded in the opening of the insulating layer 580 and sandwiched in the area between the conductive layers 542a and 542b.

[0189] When an oxide semiconductor is used as the semiconductor layer 530, an insulator containing oxygen (hereinafter sometimes referred to as excess oxygen) that has been removed by heating is preferably used as the insulating layer 580. By heat-treating the insulating layer 580 containing excess oxygen, oxygen can be supplied from the insulating layer 580 to the channel formation region of the semiconductor layer 530, thereby reducing oxygen vacancies and Vo. O H. This allows the electrical characteristics of transistor 500 to be stabilized, thereby improving its reliability.

[0190] exist Figure 17A and Figure 17B The insulating layer 545 is a single-layer structure, but the present invention is not limited thereto. For example, the insulating layer 545 may also be a stacked structure of two or more layers.

[0191] The insulating layer 544 is provided to cover the conductive layers 542a and 542b. The insulating layer 544 preferably has oxygen-barrier properties. By employing this structure, oxidation of the conductive layers 542a and 542b can be suppressed.

[0192] An insulating layer 571a is disposed on a conductive layer 542a, and an insulating layer 571b is disposed on a conductive layer 542b. By providing insulating layers 571a and 571b, over-etching of the ends of conductive layers 542a and 542b can be prevented when the semiconductor film that will become semiconductor layer 530 and the conductive films that will become conductive layers 542a and 542b are processed into island shapes in one step. As a result, miniature transistors can be fabricated with high precision.

[0193] The insulating layer 574 preferably has the function of suppressing the diffusion of impurities such as hydrogen. Furthermore, the insulating layer 574 preferably has the function of trapping or fixing impurities such as hydrogen. By employing this structure, hydrogen diffusion into the semiconductor layer 530 can be suppressed. In addition, the hydrogen concentration in the semiconductor layer 530 can be reduced.

[0194] A conductive layer 540a is disposed in the openings of insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is disposed in the openings of insulating layers 581, 574, 580, 544, and 571b. The conductive layers 540a and 540b are disposed opposite to each other with a conductive layer 560 between them. The conductive layers 540a and 540b are used as through holes, contact plugs, or wiring.

[0195] exist Figure 17A The conductive layer 540a and conductive layer 540b are two-layer stacked structures, but the present invention is not limited thereto. For example, the conductive layer 540a and conductive layer 540b can be single-layer structures or stacked structures of three or more layers, respectively.

[0196] Figure 17A and Figure 17B The structure of transistor 500 shown is just an example and is not limited to the structure described above. Appropriate transistors can be used depending on the circuit structure, driving method, etc.

[0197] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 17A and Figure 17B The transistor 500 is shown. For example, it can also be used... Figure 17C The transistor 500 is shown in the diagram. Figure 17C The transistor 500 shown is Figure 17A and Figure 17BThe difference of the transistor 500 shown is that, in the former, the conductive layer 542a and the conductive layer 542b are stacked; and the insulating layer 520 and the insulating layer 555 are provided.

[0198] exist Figure 17C In the transistor 500 shown, conductive layer 542a has a stacked structure of conductive layer 542a1 and conductive layer 542a2 on conductive layer 542a1, and conductive layer 542b has a stacked structure of conductive layer 542b1 and conductive layer 542b2 on conductive layer 542b1. As conductive layers 542a1 and 542b1 that contact the semiconductor layer 530, conductive materials such as metal nitrides that are not easily oxidized are preferably used. This prevents excessive oxidation of conductive layers 542a and 542b due to oxygen contained in the semiconductor layer 530. Furthermore, conductive layers 542a2 and 542b2 are preferably used as conductive materials with higher conductivity than conductive layers 542a1 and 542b1. Therefore, conductive layers 542a and 542b can be used as highly conductive wiring or electrodes. Thus, a storage device can be provided having conductive layers 542a and 542b, which serve as wiring or electrodes, disposed in a manner that contacts the top surface of the semiconductor layer 530.

[0199] like Figure 17C As shown, when viewed in cross-section along the channel length of transistor 500, the distance between conductive layers 542a1 and 542b1 is smaller than the distance between conductive layers 542a2 and 542b2. By employing this structure, the distance between the source and drain can be further shortened, and correspondingly, the channel length can be shortened. Therefore, the frequency characteristics of transistor 500 can be improved. Thus, by miniaturizing the memory device, a memory device with increased operating speed can be provided.

[0200] The insulating layer 555 is disposed in contact with the sides of the conductive layer 542a2 and the sides of the conductive layer 542b2. The insulating layer 555 preferably has the function of inhibiting oxygen diffusion. By employing this structure, oxidation of the sides of the conductive layer 542a2 and the sides of the conductive layer 542b2 can be suppressed.

[0201] The insulating layer 520 preferably has hydrogen-barrier properties. This can suppress hydrogen diffusion into the semiconductor layer 530 and reduce the hydrogen concentration in the semiconductor layer 530.

[0202] By adopting this structure, it is possible to miniaturize or highly integrate memory devices that use transistors containing oxide semiconductors.

[0203] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 17A and Figure 17C The transistor 500 is shown. Figures 18A to 18D Explanation and Figures 17A to 17C The transistors shown have different structures. Figure 18A This is a plan view of transistor 500A, which can be used in transistors M1 to M3 mentioned above. Furthermore, Figures 18B to 18D This is a cross-sectional view of the 500A transistor.

[0204] Figure 18B It is along Figure 18A The cross-sectional view of the section with dotted lines A1-A2 is also a cross-sectional view of the channel width direction of transistor 500A. Figure 18C It is along Figure 18A The cross-sectional view of the dashed lines A3-A4 in the figure is equivalent to the cross-sectional view of the transistor 500A in the channel width direction. Figure 18D It is along Figure 18A The cross-sectional view of the section marked with dotted lines A5-A6 is also a cross-sectional view along the channel length of transistor 500A. Here, the dotted lines A5-A6 are orthogonal to the dotted lines A1-A2 and A3-A4, and the dotted lines A1-A2 are parallel to the dotted lines A3-A4. Note that in... Figure 18A In the plan view, for clarity, some constituent elements are omitted and shown in a transparent manner.

[0205] Transistor 500A includes an insulating layer 516 on a substrate (not shown), an insulator 521 on the insulating layer 516, an insulating layer 522 on the insulator 521, a semiconductor layer 530 on the insulating layer 522, conductive layers 542a and 542b on the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 on the semiconductor layer 530, and conductive layers 560 (conductive layers 560a and 560b) on the insulating layer 545. Note that conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542 below.

[0206] An insulator 575 is disposed on the conductive layer 542, and an insulating layer 580 is disposed on the insulator 575. The insulating layer 545 and the conductive layer 560 are disposed inside an opening disposed in the insulating layer 580 and the insulator 575. This opening reaches the semiconductor layer 530, and the insulating layer 545 is in contact with the semiconductor layer 530 within this opening. In addition, an insulating layer 574 is disposed on the insulating layer 580 and the conductive layer 560. Furthermore, an insulator 583 is disposed on the insulating layer 574. In addition, an insulator 515 is disposed below the insulating layer 516.

[0207] An insulator 541a is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulator 541b is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Hereinafter, conductive layers 540a and 540b are sometimes collectively referred to as conductive layer 540. Furthermore, insulators 541a and 541b are sometimes collectively referred to as insulator 541.

[0208] Semiconductor layer 530 has a region serving as a channel formation region for transistor 500A. Additionally, conductive layer 560 has a region serving as a first gate electrode (upper gate electrode) for transistor 500A. Insulating layer 545 has a region serving as a first gate insulator for transistor 500A.

[0209] Conductive layer 542a has a region that serves as one of the source and drain electrodes of transistor 500A. Conductive layer 540a is used as a connector to conductive layer 542a. Conductive layer 542b has a region that serves as the other of the source and drain electrodes of transistor 500A. Conductive layer 540b is used as a connector to conductive layer 542b.

[0210] The semiconductor layer 530 is formed in contact with the insulating layer 522. The semiconductor layer 530 has a high aspect ratio shape when viewed in cross-section along the channel width direction (a shape where the length (H) in the height direction is greater than or equal to the length (W) of the base). The semiconductor layer 530 with its high aspect ratio shape can sometimes be described as having a fin-like shape.

[0211] Here, the aspect ratio of the semiconductor layer 530 when viewed in cross-section along the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range that will not cause the semiconductor layer 530 to collapse during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H is at least greater than the width L. The height H of the semiconductor layer 530 can also be set to be greater than 1 to 400 times the width L, preferably more than 2 times and less than 100 times, more preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. Alternatively, for example, the height H can also be more than 2 times and less than 10 times the width L. For example, the width L can also be set to 5 nm or more and less than 100 nm, preferably more than 5 nm and less than 50 nm, more preferably more than 10 nm and less than 30 nm. Alternatively, for example, the height H can be set to 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less. Furthermore, for example, the height H can also be 50 nm or more and 100 nm or less.

[0212] Furthermore, when viewed in cross-section along the channel width, the angle formed by the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or substantially perpendicular. For example, the angle formed by the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably 80 degrees or more and 100 degrees or less, more preferably 85 degrees or more and 95 degrees or less.

[0213] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the high aspect ratio semiconductor layer 530 described above. In the transistor 500A, a portion of the insulating layer 545 and the conductive layer 560 are provided in a folded state, sandwiching the semiconductor layer 530. Thus, when viewed in cross-section along the channel width direction, the semiconductor layer 530 and the conductive layer 560 are disposed opposite each other, sandwiching the insulating layer 545 on the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 are all used as channel formation regions. Therefore, compared to the case where the semiconductor layer 530 is formed as a flat plate, the channel width of the transistor 500A is increased by the size of the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0214] As described above, increasing the channel width improves the on-state current, transconductance, and frequency characteristics of transistor 500A. This allows for the provision of a transistor with high operating speed. Furthermore, it increases the operating speed of memory devices using this transistor. Additionally, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without expanding the area occupied by transistor 500A. This enables miniaturization or high integration of semiconductor devices. Moreover, by adopting the above structure, the relative area of ​​conductive layer 560 and semiconductor layer 530 is increased, thus allowing control of the threshold voltage to keep transistor 500A in a normally off state.

[0215] Note that normally off refers to the state where the current flowing through the source and drain of the transistor is extremely small when the gate-source voltage is 0V. Specifically, for example, in the case where the semiconductor layer of the transistor contains oxides containing indium (In), gallium (Ga), and zinc (Zn), the current flowing through each channel width of 1 μm between the source and drain when the transistor is normally off is 1 × 10⁻⁶ at room temperature. -20 Below A, at 85℃, it is 1×10 -18 A and below or at 125℃, 1×10 -16 Below A.

[0216] Furthermore, the upper part of the semiconductor layer 530 may also have a curved shape. By having this curved shape, defects such as voids can be prevented from forming in the insulating layer 545 and the conductive layer 542 near the upper part of the semiconductor layer 530.

[0217] Since the semiconductor layer 530 has a high aspect ratio shape, it is preferably formed as a sidewall on the side of the pillar made of insulator. Therefore, the semiconductor layer 530 is preferably formed using an atomic layer deposition (ALD) method with good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to deposit at least one layer using the ALD method, preferably the layer in contact with the pillar.

[0218] The semiconductor layer 530 is formed into a sidewall shape by contacting the sides of multiple pillars, such as... Figure 18A As shown, multiple semiconductor layers 530 can be formed simultaneously. Thus, by forming multiple semiconductor layers 530, the distance between each semiconductor layer 530 can be set according to the size and shape of the pillar. This reduces the distance between the semiconductor layers 530 and decreases the area occupied by the transistor 500A, thereby achieving high integration of the transistor.

[0219] Because the semiconductor layer 530 is formed as a sidewall in a manner that contacts the pillar, thus... Figure 18AAs shown, the top surface of semiconductor layer 530 has a circumferential shape (also referred to as a frame, ring, donut, or closed curve) with both ends aligned. Alternatively, semiconductor layer 530 can be described as having a shape including an opening in the central portion. Note that in... Figure 18A In this invention, the top surface of semiconductor layer 530 has a linearly symmetrical shape centered on A1-A2, but the invention is not limited to this. For example, the top surface of semiconductor layer 530 can also be an asymmetrical shape.

[0220] exist Figure 18A In the structure shown, two pillars are arranged along the dotted line A1-A2, and a circumferential semiconductor layer 530 is formed in contact with the side of each pillar. For example... Figure 18A As shown, the semiconductor layer 530 preferably overlaps with the conductive layer 560 in two or more locations when viewed from above. That is, the structure has two or more regions where the semiconductor layer 530 and the conductive layer 560 overlap. By adopting this structure, as... Figure 18B As shown, multiple fin-shaped semiconductor layers 530 are formed when viewed in cross-section along the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 serves as a channel formation region. In other words, transistor 500A is used as a multi-channel transistor. Therefore, the channel width can be further increased in transistor 500A.

[0221] In addition, such as Figures 19A to 19D The transistor 500B shown in the figure can be used for Figures 18A to 18D The structure of transistor 500A of transistors M1 to M3 described above can also be a structure in which a conductive layer 503 is provided under the insulator 521. The conductive layer 503 has a region that serves as the second gate electrode (lower gate electrode) of transistor 500B. Furthermore, the insulating layer 522 and the insulator 521 each have a region that serves as the second gate insulator of transistor 500B. Here, Figures 19A to 19D Corresponding to Figures 18A to 18D Therefore, for details about the structure, please refer to the above description.

[0222] In transistor 500B, conductive layer 503 is disposed in a manner that overlaps with semiconductor layer 530 and conductive layer 560. Here, conductive layer 503 is preferably disposed in a manner that embeds it within an opening in insulating layer 516. Furthermore, as... Figure 19A and Figure 19B As shown, the conductive layer 503 is preferably provided extending in the channel width direction. By adopting this structure, the conductive layer 503 is used as wiring when multiple transistors are disposed.

[0223] like Figure 19B and Figure 19DAs shown, the conductive layer 503 preferably includes a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is disposed in contact with the bottom surface and sidewall of the opening. The conductive layer 503b is disposed in a recess of the conductive layer 503a formed along the opening. Here, the height of the top surface of the conductive layer 503 is the same as or approximately the same as the height of the top surface of the insulating layer 516.

[0224] Here, the conductive layer 503a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0225] By using a conductive material with hydrogen diffusion suppression function as conductive layer 503a, impurities such as hydrogen contained in conductive layer 503b can be prevented from diffusing to semiconductor layer 530 through insulating layer 516 and the like. Furthermore, by using a conductive material with oxygen diffusion suppression function as conductive layer 503a, oxidation of conductive layer 503b and reduction in conductivity can be prevented. Examples of conductive materials with oxygen diffusion suppression function include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Conductive layer 503a can have a single-layer structure or a multilayer structure of the above-mentioned conductive materials. For example, conductive layer 503a preferably contains titanium nitride.

[0226] Furthermore, the conductive layer 503b preferably uses a conductive material with tungsten, copper, or aluminum as its main components. For example, the conductive layer 503b preferably contains tungsten.

[0227] The conductive layer 503 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500B can be controlled by independently changing the potential applied to the conductive layer 503 without linking it to the potential applied to the conductive layer 560. In particular, by applying a negative potential to the conductive layer 503, the Vth of the transistor 500B can be further increased, thereby reducing the off-state current. Therefore, compared to not applying a negative potential to the conductive layer 503, applying a negative potential to the conductive layer 503 can reduce the drain current when the potential applied to the conductive layer 560 is 0V.

[0228] Furthermore, the resistivity of the conductive layer 503 is designed taking into account the potential applied to the conductive layer 503 as described above, and the thickness of the conductive layer 503 is set according to this resistivity. Additionally, the thickness of the insulating layer 516 is approximately the same as that of the conductive layer 503. Here, it is preferable to reduce the thickness of both the conductive layer 503 and the insulating layer 516 within the design limits of the conductive layer 503. By reducing the thickness of the insulating layer 516, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, thus suppressing the diffusion of these impurities into the semiconductor layer 530.

[0229] Note that in the above structure, a stacked structure of the conductive layer 503a and the conductive layer 503b is shown, but the present invention is not limited thereto. The conductive layer 503 can have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 503 has a stacked structure of three layers, the stacked structure of the conductive layer 503a and the conductive layer 503b described above can be adopted, and a conductive layer containing the same material as the conductive layer 503a can also be provided on the conductive layer 503b. At this time, the above-mentioned conductor can also be formed in such a manner that the top surface of the conductive layer 503b is lower than the uppermost part of the conductive layer 503a and is embedded in the recess formed by the conductive layer 503a and the conductive layer 503b.

[0230] <Structural example of DOSRAM> Figure 20 An example of a cross-sectional structure when a circuit structure using DOSRAM is shown. Figure 20 An example showing a case where the element layer UF[1] to the element layer UF[3] are stacked on the element layer LF. In addition, Figure 21A An example of a cross-sectional structure of the element layer UF[k] is shown. In addition, Figure 21B is Figure 21A an equivalent circuit diagram.

[0231] In Figure 20 each of the plurality of element layers UF includes a plurality of memory cells 41. Figure 20 An example showing that one bit line BL is electrically connected to two memory cells 41 in each of the element layers UF[1] to the element layer UF[3] is shown. Figure 20 The memory cell 41 shown includes a transistor M1 and a capacitor C1. In Figure 20 In the memory cell 41 shown, the capacitor C1 is provided below the transistor M1. As the transistor M1, an OS transistor can be used.

[0232] In addition, the conductive layer 363a, the conductive layer 363b, and the conductive layer 363c are embedded in the interlayer film between the element layer LF and the element layer UF[1]. In addition, in each of the plurality of element layers UF, the conductive layer 365 is embedded in the insulating layer 180 described later. In addition, in each of the plurality of element layers UF, the conductive layer 366 is embedded in the insulating layer 180 and the insulating layer 280 described later. In addition, in each of the plurality of element layers UF, the conductive layer 367 is embedded in the semiconductor layer 270, the insulating layer 250, and the insulating layer 285 described later. The conductive layer 363a, the conductive layer 363b, the conductive layer 363c, the conductive layer 365, the conductive layer 366, and the conductive layer 367 are used as through holes, contact plugs, or wirings.

[0233] Figure 20 The transistor 550 included in the element layer LF shown can adopt the above-mentioned Figure 15 The structure of transistor 550 is described. Note that the transistor that can be used as the Si transistor in Embodiment 1 is not limited to transistor 550, and other structures can also be used. For example, it is preferable to use a transistor with a gate surrounding the channel, such as a FinFET. By adopting this structure, a transistor with fast switching speed and high current density can be used as a Si transistor. Furthermore, the transistor can be used as a transistor M1 included in the element layer UF. Figures 17A to 18D The OS transistors surrounding the gate-surrounded channel, as described, enable miniaturized and highly integrated memory devices.

[0234] Next, the explanation Figure 20 The diagram shows a structural example of the storage unit 41 included in the multiple element layers UF.

[0235] Figure 22A This is a plan view showing an example of the structure of the memory cells 41 included in each of the multiple element layers UF and their vicinity. Figure 22B It is an omission Figure 22A A plan view of a portion of the constituent elements shown. Figure 22C It is along Figure 22A The cross-sectional view shown is the dotted-dotted line A1-A2. Note, for example, in... Figure 22A In the diagram, some components of transistor VM1, such as the insulating layer 250, are omitted. Furthermore, in subsequent transistor planar diagrams, some components such as the insulating layer are also omitted.

[0236] exist Figures 22A to 22C In the diagram, transistor VM1 is equivalent to... Figure 20 In the transistor M1, capacitor VC1 is equivalent to Figure 20 Capacitor C1 in the middle.

[0237] exist Figure 22C In the figure, insulating layer 160 is disposed on substrate (not shown), insulating layer 180 is disposed on insulating layer 160, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0238] A conductive layer 110 is disposed on the insulating layer 160. As an example, the conductive layer 110 may be a wiring PL extending in the Y direction.

[0239] An opening 601 is provided in the region where the insulating layer 180 overlaps with the conductive layer 110. A conductive layer 115 is provided in contact with the bottom surface and sidewalls of the opening 601. That is, the conductive layer 115 has a region in the opening 601 that contacts the top surface of the conductive layer 110 and a region that contacts the side surface of the insulating layer 180. Note that in Figure 22C The intermediate conductive layer 115 has a region that contacts the top surface of the insulating layer 180.

[0240] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. Furthermore, a conductive layer 220 is provided on the insulating layer 130. The conductive layer 220 is provided in a manner that it is embedded in the opening 601.

[0241] The capacitor VC1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0242] In capacitor VC1, conductive layer 115 is used as one of a pair of electrodes, conductive layer 220 is used as the other of a pair of electrodes, and insulating layer 130 is used as a dielectric material sandwiched between the pair of electrodes.

[0243] A transistor VM1 is disposed above the capacitor VC1. The transistor VM1 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0244] In transistor VM1, conductive layer 260 is used as the gate electrode, and insulating layer 250 is used as the gate insulating film. Conductive layers 220 and 240 are used as the source electrode and drain electrode, respectively. Note that, as mentioned above, conductive layer 220 is also used as the other of a pair of electrodes in capacitor VC1.

[0245] In semiconductor layer 270, the entire area between the source electrode and the drain electrode, separated by a gate insulating film and opposite to the gate electrode, is used as a channel forming region. Furthermore, in semiconductor layer 270, the region in contact with the source electrode is used as the source region, and the region in contact with the drain electrode is used as the drain region.

[0246] Insulating layer 280 can be used as an interlayer insulating layer. Here, interlayer insulating layer can refer to the interlayer film used to separate the source electrode and the gate electrode in transistor VM1.

[0247] An insulating layer 280 is provided with a conductive layer 240. The insulating layer 280 is provided with an opening 602 that reaches the conductive layer 220. The conductive layer 240 is provided with an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0248] exist Figure 22A The conductive layer 220, conductive layer 240, conductive layer 260, opening 602, and opening 603 are shown as components of transistor VM1. Here, Figure 22B Shown in Figure 22A The structural example shown omits the conductive layer 260 in the constituent elements. That is to say, Figure 22B The conductive layer 220, conductive layer 240, opening 602, and opening 603 are shown.

[0249] Figure 22Aand Figure 22B An example is shown where the shapes of openings 602 and 603 are both circular when viewed from a planar perspective. By making the planar shapes of openings 602 and 603 circular, the processing precision during their formation can be improved, allowing for the formation of finer openings 602 and 603. This enables miniaturization or high integration of the memory cell. Note that in this specification, the circle is not limited to a perfect circle. For example, the planar shapes of openings 602 and 603 can also be elliptical or curved. Alternatively, they can be polygonal or polygonal with rounded corners.

[0250] The description of the shapes of openings 602 and 603 can be applied to opening 601.

[0251] The conductive layer 240 is preferably not disposed inside the opening 602. That is, the conductive layer 240 preferably does not contact the side of the insulating layer 280 on the side of the opening 602. By adopting this structure, the opening 603 and the opening 602 can be formed in one step, thereby simplifying the process.

[0252] Figure 22C An example is shown where the bottom end of the conductive layer 240 in the opening 603 coincides with or substantially coincides with the top end of the insulating layer 280 in the opening 602. Note that in this specification, the bottom surface of the conductive layer 240 refers to the surface on one side of the insulating layer 280. The top surface of the insulating layer 280 refers to the surface on one side of the conductive layer 240.

[0253] Note that "end-to-end alignment" or "approximate alignment" can also be described as "end-to-end alignment" or "approximate alignment." In cases of end-to-end alignment or approximate alignment, and in cases of consistent or approximate planar shapes, it can be said that, when viewed from the plane, at least a portion of the edges overlap between the stacked layers. For example, this includes cases where the upper and lower layers are processed from the same mask pattern or a portion thereof. However, there are actually cases where the edges do not overlap, sometimes with the upper layer located inside or outside the lower layer; in these cases, it can also be described as "approximately aligned ends" or "approximately consistent planar shapes."

[0254] Hereinafter, the opening including opening 602 and opening 603 will sometimes be referred to as opening 290. That is, the insulating layer 280 and the conductive layer 240 are provided with opening 290 that leads to the conductive layer 220. Furthermore, opening 602 is a part of opening 290 and opening 603 is another part of opening 290.

[0255] At least a portion of the semiconductor layer 270 is disposed in the opening 290. The semiconductor layer 270 has a region in the opening 290 that contacts the side surface of the conductive layer 240, a region that contacts the side surface of the insulating layer 280, and a region that contacts the top surface of the conductive layer 220. The semiconductor layer 270 has a region that contacts the top surface of the conductive layer 240.

[0256] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is disposed on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region that contacts the top surface of the semiconductor layer 270, a region that contacts the side surface of the semiconductor layer 270, a region that contacts the side surface of the conductive layer 240, and a region that contacts the top surface of the insulating layer 280.

[0257] A conductive layer 260 is disposed on an insulating layer 250 and has a region that contacts the top surface of the insulating layer 250. The conductive layer 260 is disposed such that it is embedded in an opening 290. The conductive layer 260 is disposed such that it is embedded in a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270 across the insulating layer 250.

[0258] Figure 22C An example is shown where the conductive layer 260 overlaps with the conductive layer 240 across the insulating layer 250 and the semiconductor layer 270, but the invention is not limited thereto. For example, the conductive layer 260 may also be disposed without overlapping the conductive layer 240. By employing this structure, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operating speed of the memory cell can be further improved.

[0259] Transistor VM1 has the following structure: the direction of the channel length is not approximately parallel to the substrate (not shown) but along the sidewall of the opening 602 provided in the insulating layer 280. In this specification and the like, this type of transistor is sometimes referred to as a longitudinal transistor.

[0260] Vertical transistors have a structure that allows at least a portion of the source region, channel formation region, and drain region to overlap when viewed from a plane, thus reducing the occupied area. Furthermore, because they have a structure that allows for a shorter channel length and a wider channel width, the on-state resistance can be reduced (and the on-state current increased).

[0261] Figure 22A An example is shown where the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260.

[0262] Here, Figure 23A Show Figure 22C An enlarged view of the semiconductor layer 270 and its vicinity is shown. Furthermore, Figure 23BA cross-sectional view of the XY plane including the conductive layer 240 is shown.

[0263] like Figure 23A As shown, the semiconductor layer 270 has region 270i, region 270na and region 270nb disposed in a manner that sandwiches region 270i.

[0264] Region 270na is the region in semiconductor layer 270 that contacts conductive layer 220. Region 270nb is the region in semiconductor layer 270 that contacts conductive layer 240. Regions 270na and 270nb each serve as the source or drain region of transistor VM1. Figure 23B As shown, the conductive layer 240 contacts the entire outer periphery of the semiconductor layer 270. Therefore, the source or drain region of the transistor VM1 may be formed on the entire outer periphery of the portion of the semiconductor layer 270 formed in the same layer as the conductive layer 240.

[0265] Region 270i is the region in semiconductor layer 270 sandwiched between regions 270na and 270nb. Region 270i is used as the channel formation region of transistor VM1. That is, the channel formation region of transistor VM1 is formed in a portion of semiconductor layer 270 located between conductive layer 220 and conductive layer 240. Alternatively, it can be said that the channel formation region of transistor VM1 is located in or near the region of semiconductor layer 270 that is in contact with insulating layer 280.

[0266] The channel length of transistor VM1 is the distance between the source and drain regions. In other words, the channel length of transistor VM1 can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220. Figure 23A In the diagram, the channel length L of transistor VM1 is represented by a dashed double arrow. Viewed in cross-section, the channel length L is the distance from the end of the region where semiconductor layer 270 contacts conductive layer 220 to the end of the region where semiconductor layer 270 contacts conductive layer 240. In other words, the channel length L is equivalent to the length of the side surface of the opening 602 of insulating layer 280 when viewed in cross-section.

[0267] In planar transistors, the channel length is determined based on the exposure limit of photolithography. However, in this invention, the channel length can be determined based on the thickness of the insulating layer 280. Therefore, the channel length of transistor VM1 can be set to a very fine structure below the exposure limit of photolithography (e.g., below 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm and above 1 nm or 5 nm and above). This increases the on-state current of transistor VM1, improving its frequency characteristics. Consequently, a high-speed memory device can be provided.

[0268] Furthermore, as described above, a channel forming region, a source region, and a drain region can be formed in the opening 290. Therefore, compared to a planar transistor where the channel forming region, source region, and drain region are respectively provided on the XY plane, the occupied area of ​​the transistor VM1 can be reduced. As a result, the memory device can be highly integrated, thus increasing the storage capacity per unit area.

[0269] In addition, with Figure 23B Similarly, on the XY plane including the channel formation region of semiconductor layer 270, semiconductor layer 270, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of semiconductor layer 270 across insulating layer 250. In other words, when viewed from above, the entire outer periphery of semiconductor layer 270 forms the channel formation region. At this time, for example, the channel width of transistor VM1 is determined by the length of the outer periphery of semiconductor layer 270. That is, the channel width of transistor VM1 is determined by the maximum width of opening 602. Figure 23A and Figure 23B In the diagram, the double-headed arrow with a double dotted line represents the maximum width D of the opening 602. Figure 23B The double-headed dotted arrow represents the channel width W of transistor VM1. By increasing the maximum width D of the opening 602, the channel width per unit area can be increased, thereby increasing the on-state current.

[0270] When forming the opening 602 using photolithography, the maximum width D of the opening 602 is set according to the exposure limit of the photolithography method. Furthermore, the maximum width D of the opening 602 is set according to the thickness of each of the semiconductor layer 270, insulating layer 250, and conductive layer 260 provided in the opening 602. The maximum width D of the opening 602 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and less than 100 nm, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the shape of the opening 602 in top view is circular, the maximum width D of the opening 602 is equivalent to the diameter of the opening 602, and the channel width W can be calculated as "D×π".

[0271] At this time, the maximum width D of the opening 602 can be appropriately calculated based on the shape of the opening 602 when viewed from the plane. For example, when the opening 602 is a quadrilateral when viewed from the plane, the maximum width of the opening 602 can be the length of the diagonal of the quadrilateral. Alternatively, for example, when the shape of the opening 602 when viewed from the plane is an ellipse, a polygon, or a shape in which the corners of the polygon are arc-shaped, the maximum width of the opening 602 can be the diameter of the smallest circle (also called the smallest containing circle) that encompasses the shape of the opening 602 when viewed from the plane.

[0272] Furthermore, in one embodiment of the memory device of the present invention, the channel length L of transistor VM1 is preferably at least smaller than the channel width W of transistor VM1. In one embodiment of the present invention, the channel length L of transistor VM1 is at least 0.1 times and less than 0.99 times the channel width W of transistor VM1, preferably at least 0.5 times and less than 0.8 times. By employing this structure, transistors with good electrical characteristics and high reliability can be realized.

[0273] Furthermore, by forming the opening 602 in a nearly circular manner when viewed from above, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the semiconductor layer 270 is approximately uniform, so a gate electric field can be applied to the semiconductor layer 270 approximately uniformly.

[0274] Note that in Figure 23A In the example, the opening 602 is provided such that the side surface of the opening 602 is perpendicular to the top surface of the conductive layer 220; however, the present invention is not limited to this. For example, the side surface of the opening 602 may also be tapered.

[0275] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface. For example, it is preferable to have an area with an inclined side surface and a substrate surface (also referred to as a tapered angle) of less than 90 degrees.

[0276] like Figure 22C As shown, a portion of the insulating layer 250 is located outside the opening 603, i.e., on the insulating layer 280. In this case, the insulating layer 250 preferably covers the side end of the conductive layer 240. This prevents a short circuit between the conductive layer 260 and the conductive layer 240.

[0277] As semiconductor layer 270, a single layer or a stack of semiconductors that can be used in semiconductor layer 530 can be used. Furthermore, the structure of semiconductor layer 270 can also refer to the structure of semiconductor layer 530 described above.

[0278] Semiconductor layer 270 preferably has layered crystals that are substantially parallel to the sides of insulating layer 280 in opening 602. By adopting this structure, the layered crystals of semiconductor layer 270 are substantially parallel to the channel length direction of transistor VM1, thus increasing the on-state current of transistor.

[0279] When the semiconductor layer 270 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, and region 270na of the semiconductor layer 270 is reduced in resistance. By reducing the resistance of the semiconductor layer 270 in contact with the conductive layer 220, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced. Similarly, when the semiconductor layer 270 contacts the conductive layer 240, region 270nb of the semiconductor layer 270 is reduced in resistance. This reduces the contact resistance between the semiconductor layer 270 and the conductive layer 240.

[0280] The conductive layer 240 can be a stacked structure of a first conductive layer and a second conductive layer on the first conductive layer. In this case, a highly conductive material can be used to form the first conductive layer, and an oxygen-containing conductive material can be used to form the second conductive layer. When an oxide semiconductor is used as the semiconductor layer 270, by using an oxygen-containing conductive material as the second conductive layer of the conductive layer 240 that contacts the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced, thereby suppressing the decrease in the on-state current of the transistor VM1 caused by this contact resistance. For example, it is preferable to use tungsten as the first conductive layer of the conductive layer 240 and indium tin oxide containing silicon as the second conductive layer of the conductive layer 240.

[0281] The conductive layer 220 has a recess at a position overlapping with the opening 602. Furthermore, the semiconductor layer 270 contacts the bottom and side surfaces of the recess in the conductive layer 220. Note that the recess in the conductive layer 220 can also be considered part of the opening 290.

[0282] By having a recess in the conductive layer 220 at the location overlapping with the opening 602, compared to the case without the recess, the height of the bottom surface of the insulating layer 250 and the bottom surface of the conductive layer 260 within the opening 290 can be lower than the height of the top surface of the conductive layer 220 that contacts the insulating layer 280, when the top surface of the insulating layer 160 is used as a reference. Here, the height of each surface can be determined based on the surface where the memory cell or transistor is formed. Here, the top surface of the insulating layer 160 is used as the reference. There is no particular limitation on the surface used as the reference; for example, the top surface of the substrate on which the memory cell or transistor is disposed can also be used as the reference.

[0283] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing their contact resistance. Consequently, the decrease in the on-state current of transistor VM1 caused by the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field can be easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of transistor VM1. Moreover, a gate electric field can also be easily applied to the region of the semiconductor layer 270 that contacts the conductive layer 220, thus increasing the on-state current of transistor VM1. Additionally, regardless of whether either the conductive layer 220 or the conductive layer 240 is used as the drain electrode, transistor VM1 can possess excellent electrical characteristics.

[0284] Furthermore, an oxygen-containing conductive material is preferably used as the conductive layer 220. When an oxide semiconductor is used as the semiconductor layer 270, the contact resistance between the semiconductor layer 270 and the conductive layer 220 can be reduced by using an oxygen-containing conductive material as the conductive layer 220.

[0285] Furthermore, the conductive layer 220 can be constructed by stacking tungsten beneath an oxygen-containing conductive material. This stacking of tungsten improves the conductivity of the conductive layer 220.

[0286] Insulating layers 280 and 285 are used as interlayer films, so their relative permittivity is preferably low. By using a material with a low relative permittivity for the interlayer film, the capacitance value of parasitic capacitance generated between the wirings can be reduced.

[0287] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 270.

[0288] Furthermore, the insulating layer 280 preferably uses an insulator containing excess oxygen. By heat-treating the insulating layer 280 containing excess oxygen, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, thereby reducing oxygen vacancies and V. O H. This stabilizes the electrical characteristics of transistor VM1 and improves its reliability.

[0289] Note that the transistors that can be used in this invention are not limited to those in the present invention. Figure 22C The transistor VM1 shown. For example, it can also be used Figure 24 The transistor VM2 is shown in the diagram. Figure 24 The transistor VM2 shown is Figure 22C The difference between the transistor VM1 shown is that the former has a conductive layer 215 and an insulating layer 225.

[0290] Figure 24 The structure shown is equivalent to Figure 6AThe storage unit 41A is shown. In Figure 24 In the storage cell 41A shown, transistor VM2 is positioned above capacitor VC1.

[0291] like Figure 24 As shown, a conductive layer 215 is provided on the insulating layer 280. Furthermore, an insulating layer 281 is disposed on both the insulating layer 280 and the conductive layer 215. Additionally, a conductive layer 240 is provided on the insulating layer 281.

[0292] An opening 604 leading to the conductive layer 220 is provided in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The opening 604 includes openings in the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240. The sidewalls of the opening 604 include the sidewalls of the insulating layer 280, conductive layer 215, insulating layer 281, and conductive layer 240.

[0293] At least a portion of each of the insulating layer 225, semiconductor layer 270, insulating layer 250, and conductive layer 220 is located in the opening 604. Specifically, the insulating layer 225 is disposed such that it covers a portion of the bottom and sidewalls of the opening 290; the semiconductor layer 270 is disposed such that it covers the remaining portion of the bottom of the opening 290 and the insulating layer 225; and the insulating layer 250 is disposed such that it covers the semiconductor layer 270. Furthermore, the conductive layer 260 is disposed such that it is embedded in a recess of the insulating layer 250 that reflects the shape of the opening 604.

[0294] The insulating layer 225 contacts a portion of the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 215, the side surface of the insulating layer 281, and the side surface of the conductive layer 240 in the opening 604.

[0295] exist Figure 24 In the transistor VM2 shown, semiconductor layer 270 is used as semiconductor layer, conductive layer 260 is used as first gate electrode, insulating layer 250 is used as first gate insulating film, conductive layer 215 is used as second gate electrode, insulating layer 225 is used as second gate insulating film, and conductive layer 220 and conductive layer 240 are used as source electrode or drain electrode, respectively.

[0296] By independently changing the potential applied to the conductive layer 215 without linking it to the potential applied to the conductive layer 260, the threshold voltage (Vth) of the transistor can be controlled. In particular, by applying a negative potential to the conductive layer 215, the Vth of the transistor can be further increased to reduce the off-state current. Therefore, compared with the case where no negative potential is applied to the conductive layer 215, the drain current when the potential applied to the conductive layer 260 is 0V can be reduced. In addition, the conductive layer 260 can also be used as the second gate electrode and the conductive layer 215 can be used as the first gate electrode.

[0297] In addition, the conductive layer 215 can also be connected to the conductive layer 260. By connecting the conductive layer 215 and the conductive layer 260 and applying the same potential to them, the on-state current can be increased, the initial characteristic deviation can be reduced, the deterioration of electrical characteristics under the negative GBT (Gate Bias-Temperature) stress test can be suppressed, and the variation of the rising voltage of the on-state current under different drain voltages can be suppressed.

[0298] As described above, Figure 24 the transistor VM2 shown includes a first gate electrode and a second gate electrode, whereby the electrical characteristics of the transistors included in the storage device can be improved.

[0299] <Example structure 2 of NOSRAM> Figure 25A and Figure 25B shows an example of the structure of a transistor that can be used for the circuit structure of a dual-transistor type NOSRAM. Figure 25A is an example of a perspective view of a storage device in which a plurality of memory cells 41F including transistors VT1 and VT2 arranged in a stacked manner are arranged. Both the transistor VT1 and the transistor VT2 are vertical transistors. The memory cell 41F is connected to the conductive layer 220a, the conductive layer 240a, the conductive layer 240b, and the conductive layer 210. Note that in Figure 25A for clarity, insulating layers such as interlayer films are not shown and the conductive layer 210 located at the top is represented by a dashed line.

[0300] Figure 25A The conductive layer 220a shown is used as Figure 12F the read bit line RBL shown, etc. Figure 25A The conductive layer 240a shown is used as Figure 12F the read word line RWL shown, etc. Figure 25A The conductive layer 240b shown is used as Figure 12F the write bit line WBL shown, etc. Figure 25A The conductive layer 210 shown is used as Figure 12F the write word line WWL shown, etc.

[0301] exist Figure 25A In the storage cell 41F shown, transistor VT2 is positioned above transistor VT1. Figure 25A The transistor VT2 shown is equivalent to Figure 12F The transistor M1 of the memory cell 41F shown. Figure 25A The transistor VT1 shown is equivalent to Figure 12F The transistor M2 of the memory cell 41F shown.

[0302] Notice, Figure 25A An example is shown in which the storage cells 41F are arranged at equal intervals in the X and Y directions. An interleaved configuration in which the storage cells 41F are arranged alternately can also be used.

[0303] Transistor VT1 includes conductive layers 220a, 240a, and 260a as constituent elements. Transistor VT2 includes conductive layers 260a, 240b, and 260b as constituent elements.

[0304] Next, an example of the structure of storage cell 41F will be described. Figure 25B This is a perspective view illustrating an example of the structure of memory cell 41F. Note that, for clarity, insulating layers such as interlayer films are not shown; portions of conductive layers 220a, 240a, 240b, and 210 are indicated by dashed lines.

[0305] Figure 25B The memory cell 41F shown has the following structure: In transistor VT1, a semiconductor layer 270a is disposed in the opening of conductive layer 240a, and the side of conductive layer 240a in the opening is in contact with semiconductor layer 270a.

[0306] Figure 26A This is a plan view illustrating transistor VT1. Figure 26B This is a plan view illustrating transistor VT2. Note that some components have been omitted in the plan view for clarity.

[0307] Figure 26C It is equivalent to Figure 26A and Figure 26B The diagram shows the cross-section of line segment A1-A2. Figure 26D It is equivalent to Figure 26A and Figure 26B The diagram shows the cross-section of line segment B1-B2.

[0308] The memory cell 41F includes an insulating layer 160 on a substrate (not shown), a transistor VT1 disposed on the insulating layer 160, and a transistor VT2 disposed on the transistor VT1. In addition, insulating layers 280a, 280b, and 285, which serve as interlayer films, can be disposed between the transistors and between various wirings.

[0309] Transistor VT1 includes a conductive layer 220a, a conductive layer 240a, a semiconductor layer 270a, an insulating layer 250a, and a conductive layer 260a. In transistor VT1, the semiconductor layer 270a is used as the semiconductor layer, the conductive layer 260a is used as the gate electrode, and the insulating layer 250a is used as the gate insulating film. Furthermore, the conductive layers 220a and 240a are used as the source electrode and drain electrode, respectively.

[0310] In other words, transistor VT1 has the same characteristics as... Figure 22C The diagram shows the structure corresponding to that of transistor VM1. Therefore, in the accompanying drawings, corresponding components in transistors VM1 and VT1 are generally assigned the same three-digit number as symbols. Furthermore, unless otherwise specified, transistor VT1 can be referred to in the description of transistor VM1.

[0311] Transistor VT2 includes a conductive layer 260a, a conductive layer 240b, a semiconductor layer 270b, an insulating layer 250b, and a conductive layer 260b. In transistor VT2, the semiconductor layer 270b is used as the semiconductor layer, the conductive layer 260b is used as the gate electrode, and the insulating layer 250b is used as the gate insulating film. Furthermore, the conductive layers 260a and 260b are used as either source or drain electrodes.

[0312] In other words, transistor VT2 has the same characteristics as... Figure 22C The structure shown corresponds to the structure of transistor VM1. Therefore, in the accompanying drawings, corresponding components in transistors VM1 and VT2 are generally assigned the same three-digit number as symbols. Furthermore, unless otherwise specified, transistor VT2 can be referred to in the description of transistor VM1. Note that conductive layer 260a corresponds to conductive layer 220 in transistor VM1. Therefore, conductive layer 260a can be referred to in the description of conductive layer 220 described above.

[0313] Note that you can Figure 24 The transistor VM1 shown is used as one or both of transistors VT1 and VT2.

[0314] The conductive layer 260a can be said to have a region that serves as both the gate electrode of transistor VT1 and one of the source and drain electrodes of transistor VT2.

[0315] The conductive layer 260b is connected to the conductive layer 210 formed on the conductive layer 260b. Note that the conductive layer 260b and the conductive layer 210 may also be formed as a single component.

[0316] The top surfaces of both conductive layers 260a and 260b are preferably approximately circular. This structure improves the integration density of the memory cell 41F. Note that the top surface shapes of conductive layers 260a and 260b can be referenced to the description of the shape of the opening 602, etc., described above.

[0317] In order to increase the overlap area of ​​transistor VT2 and transistor VT1, it is preferable that the top surface shape of the opening 290b has the same or similar shape as the top surface shape of the opening 290a forming transistor VT1.

[0318] <Materials Constructing Storage Devices> The following describes the materials that can be used to construct storage devices.

[0319] [Substrate] Substrates suitable for use in storage devices can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttrium-stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switches, light-emitting elements, and memory elements.

[0320] [Insulator] As insulators, there are oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, etc., which have insulating properties.

[0321] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced. On the other hand, by using a material with a low relative permittivity as the insulator used as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select the material based on the function of the insulator. Additionally, materials with a low relative permittivity are also materials with high dielectric strength.

[0322] Materials with relatively high permittivity (high-k) include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0323] Examples of materials with low relative permittivity include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride, as well as resins such as polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silicon oxide, carbon-containing silicon oxide, and silicon oxide containing both carbon and nitrogen. Additionally, porous silicon oxides can be cited. Moreover, these silicon oxides may also contain nitrogen.

[0324] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities and oxygen include single layers or stacks of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride, can be used as insulators that suppress the permeation of impurities and oxygen.

[0325] Furthermore, the insulating layer in contact with the semiconductor layer, or the insulating layer disposed near the semiconductor layer, such as a gate insulating film, preferably has regions containing excess oxygen. For example, when an insulating layer having regions containing excess oxygen is in contact with the semiconductor layer, or when an insulating layer having regions containing excess oxygen is disposed near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or porous silicon oxide.

[0326] In addition, examples of oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride are examples of oxides containing one or both of aluminum and hafnium.

[0327] In addition, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride are examples of insulators that have hydrogen-blocking properties.

[0328] An oxygen-blocking insulator and a hydrogen-blocking insulator can be described as an insulator that blocks one or both of oxygen and hydrogen.

[0329] Furthermore, as insulators capable of trapping or fixing hydrogen, examples include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. Moreover, these oxides are more preferably amorphous. Oxides with amorphous structures sometimes possess the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. Furthermore, while these metal oxides are preferably amorphous, some may also have crystalline regions.

[0330] Note that in this specification, etc., "barrier insulating film" refers to an insulating film with barrier properties. Furthermore, barrier property refers to the property that makes it difficult for the corresponding substance to diffuse (also referred to as the property that makes it difficult for the corresponding substance to pass through, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Additionally, the function of trapping or fixing (also called gettering) the corresponding substance can be referred to as barrier property. Furthermore, hydrogen, denoted as the corresponding substance, refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier property refers to the property that at least one of oxygen atoms, oxygen molecules, etc., does not readily diffuse.

[0331] [Conductor] As a conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. As an alloy containing the above-mentioned metallic elements, a nitride of the alloy or an oxide of the alloy may also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0332] Furthermore, conductive materials containing nitrogen, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, ruthenium nitrides, tantalum and aluminum nitrides, or titanium and aluminum nitrides; conductive materials containing oxygen, such as ruthenium oxide, strontium and ruthenium oxides, or lanthanum and nickel oxides; and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0333] In addition, conductive materials with tungsten, copper or aluminum as the main components have high conductivity and are therefore preferred.

[0334] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0335] Furthermore, when using oxide semiconductors in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0336] In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in the oxide semiconductor in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, can be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon can also be used. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the oxide semiconductor in which the channel is formed can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0337] [Other Semiconductor Materials] Semiconductor materials that can be used as semiconductor layers are not limited to oxide semiconductors. Semiconductor materials with band gaps (semiconductor materials that are not zero-bandgap semiconductors) can also be used as semiconductor layers. For example, it is preferable to use single-element semiconductors, compound semiconductors, or layered materials (also known as atomic layer materials, two-dimensional materials, etc.) as semiconductor materials.

[0338] In this specification and other materials, layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together by bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using materials that are semiconductors and have high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0339] Examples of semiconductors that can be used as single-element semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include, for instance, low-temperature polycrystalline silicon (LTPS).

[0340] Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride suitable for use in semiconductor layers preferably has an amorphous structure. Boron arsenide suitable for use in semiconductor layers preferably comprises crystals with a cubic crystal structure.

[0341] As layered materials, examples include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon, nitrogen, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen elements. Furthermore, chalcogen elements are a collective term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and protium. Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0342] As the semiconductor layer, transition metal chalcogenides, which are typically used as semiconductors, are preferred, for example. Examples of transition metal chalcogenides suitable for use in semiconductor layers include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By using the aforementioned transition metal chalcogenides in the semiconductor layer, a memory device with a large on-state current can be provided.

[0343] According to one aspect of the present invention, a novel transistor and a novel memory device can be provided. Furthermore, a memory device capable of miniaturization or high integration can be provided. Additionally, a memory device with excellent frequency characteristics can be provided. Furthermore, according to one aspect of the present invention, a memory device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a memory device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a low-power memory device can be provided. Furthermore, a memory device including transistors with high on-state current can be provided. Furthermore, a memory device with less transistor characteristic non-uniformity can be provided. Furthermore, according to one aspect of the present invention, a memory device with good electrical characteristics can be provided.

[0344] The configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments, etc.

[0345] (Implementation Method 3) In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer for a transistor is described.

[0346] [Oxide semiconductor layer] In one aspect of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures with crystalline metal oxides include the CAAC (c-axis aligned crystal) structure, the polycrystalline structure, and the nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect state density in the oxide semiconductor layer can be reduced. This improves the reliability of transistors using the oxide semiconductor layer of one aspect of the present invention, and consequently improves the reliability of memory devices including transistors.

[0347] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. A CAAC structure refers to a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are oriented along the c-axis and connected on the ab plane in a manner where the multiple microcrystals are not oriented. Furthermore, when a cross-section of the oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that the metal atoms are arranged in layers within the crystalline regions. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure with layered crystalline regions.

[0348] The crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, it can be analyzed by combining several of the above methods.

[0349] Furthermore, there are no particular restrictions on the crystallinity of the semiconductor material contained in the oxide semiconductor layer. For example, the oxide semiconductor layer may sometimes contain one or more of the following: amorphous semiconductor (semiconductor with an amorphous structure), single-crystal semiconductor (semiconductor with a single-crystal structure), and crystalline semiconductors other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in a portion thereof). When the oxide semiconductor layer is crystalline, it can sometimes suppress the degradation of transistor characteristics.

[0350] The metal oxide comprising the oxide semiconductor layer of one aspect of the present invention can include, for example, indium oxide, gallium oxide, and zinc oxide. Preferably, the metal oxide of one aspect of the present invention comprises at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. Additionally, element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one aspect of the present invention preferably comprises one or more elements selected from indium, gallium, and zinc. Note that in this specification and other documents, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification and other documents sometimes include half-metallic elements.

[0351] As one embodiment of the present invention, the metal oxide may be indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. In addition, examples include indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide), which contain silicon.

[0352] By increasing the proportion of indium atoms in a metal oxide relative to the total number of atoms of all metal elements, transistors can achieve large on-state current and high frequency characteristics.

[0353] In addition, metal oxides can also contain one or more of the periodically numbered metals in the periodic table instead of indium. Alternatively, metal oxides can contain one or more of the periodically numbered metals in the periodic table besides indium. There is a tendency that the greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including periodically numbered metals, the field-effect mobility of transistors can sometimes be improved. Examples of periodically numbered metals include those belonging to the fifth period and those belonging to the sixth period. Specific examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0354] In addition, metal oxides may also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0355] Furthermore, by increasing the proportion of zinc atoms relative to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0356] Furthermore, by increasing the proportion of element M atoms in the metal oxide relative to the total number of atoms of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. In addition, variations in the transistor's electrical characteristics are suppressed, thereby improving reliability.

[0357] In this embodiment, In-Ga-Zn oxides are sometimes used as examples to illustrate metal oxides.

[0358] In one embodiment of the present invention, the oxide semiconductor layer is crystalline. Furthermore, in another embodiment of the present invention, the oxide semiconductor layer preferably has a CAAC structure.

[0359] An oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using at least two deposition methods. For example, an oxide semiconductor layer according to one aspect of the present invention can be fabricated by forming a metal oxide using a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed using at least two deposition methods can also be referred to as a Hybrid OS.

[0360] An oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, and then forming a metal oxide as a second layer on the first layer using a second deposition method. In this case, as the first deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the second deposition method. When a deposition method that causes less damage to the surface to be formed is used as the first deposition method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on the surface to be formed of the oxide semiconductor layer can be suppressed. Furthermore, the incorporation of impurities such as silicon into the second layer can be suppressed, thereby improving the crystallinity of the oxide semiconductor layer.

[0361] Examples of first deposition methods include ALD, Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), and wet deposition. Examples of CVD methods include Plasma Enhanced CVD (PECVD), Thermal CVD, Photochemical CVD, and Metal-Organic CVD (MOCVD). Examples of wet deposition methods include spraying. Compared to sputtering methods described later, ALD and CVD methods can suppress damage to the surface being formed, making them suitable as first deposition methods.

[0362] Examples of ALD methods include thermal ALD (thermal ALD) which uses only thermal energy to react precursors and reactants, and plasma ALD (PEALD) which uses reactants excited by plasma.

[0363] The ALD method allows for atomic deposition layer by layer, resulting in advantages such as: extremely thin deposition; the ability to deposit on structures with high aspect ratios or surfaces with large steps; deposition with fewer defects such as pinholes; high coverage; and the ability to deposit at low temperatures. Furthermore, the PEALD method, utilizing plasma, allows for deposition at even lower temperatures, making it sometimes preferred. Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films deposited using the ALD method sometimes contain more carbon or chlorine than films deposited using other methods. It should be noted that the quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Furthermore, in a metal oxide deposition method according to one aspect of the present invention, the ALD method employs one or both of the following conditions: a high substrate temperature during deposition and an impurity removal process. Compared to the case where the ALD method is used without employing the aforementioned conditions and processes, the carbon and chlorine content in the film is sometimes lower.

[0364] Unlike deposition methods that deposit particles released from a target or similar material, the ALD (Advanced Layer Deposition) method forms a film through a reaction on the surface of the workpiece. Therefore, the ALD method is a deposition method with good step coverage, less affected by the shape of the workpiece. In particular, the ALD method exhibits good step coverage and thickness uniformity, making it suitable for covering surfaces with high aspect ratio openings, etc.

[0365] By utilizing plasma CVD, high-quality films can be obtained at relatively low temperatures. Furthermore, thermal CVD, because it does not use plasma, is a deposition method that reduces plasma damage to the workpiece. Moreover, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0366] Examples of secondary deposition methods include sputtering and pulsed laser deposition (PLD). Metal oxides formed using these secondary deposition methods tend to have a CAAC structure.

[0367] Furthermore, as the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, having a lower crystallinity than the CAAC structure, is sometimes formed. By forming a second layer with higher crystallinity on the first layer with lower crystallinity, or by performing heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. As a result, the crystallinity of the oxide semiconductor layer as a whole, including the interface with the surface to which it is formed, can be improved.

[0368] Furthermore, a third layer can also be formed on the second layer. Because the second layer has high crystallinity, the third layer can crystallize and grow using the crystals of the second layer as nuclei or seeds. Thus, even if the deposition method for the third layer does not utilize a deposition method that readily produces crystals, the third layer can still be crystallized. Here, for example, when the third layer is formed using a deposition method with higher coverage than the second layer, both high crystallinity and high coverage can be achieved throughout the oxide semiconductor layer.

[0369] As an example, an oxide semiconductor layer according to one aspect of the present invention can be manufactured by the following steps: forming a metal oxide as a first layer using a first deposition method, forming a metal oxide as a second layer using a second deposition method, and then forming a metal oxide as a third layer using the first deposition method. Specifically, the first deposition method can be the ALD method, and the second deposition method can be the sputtering method. Compared with the sputtering method, the ALD method is a deposition method with excellent coverage. When the ALD method is used as the deposition method for the first and third layers, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with high aspect ratios.

[0370] [Manufacturing method of oxide semiconductor layer] The oxide semiconductor 230 of the oxide semiconductor layer can be manufactured, for example, by the following steps: forming oxide semiconductor 230a on layer 229 of the surface to be formed using the ALD method, forming oxide semiconductor 230b on oxide semiconductor 230a using sputtering, and forming oxide semiconductor 230c on oxide semiconductor 230b using the ALD method. Furthermore, it is preferable to perform heat treatment after forming the oxide semiconductor 230. By performing heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. The heat treatment described herein is not limited to heating treatment. For example, it can also be heat applied during the manufacturing process.

[0371] The oxide semiconductor 230 can be used in the semiconductor layer 530 and semiconductor layer 270 described in the above embodiments. In addition, layer 229 is equivalent to the insulating layer 524, insulating layer 280, insulating layer 225 or conductive layer 220 described in the above embodiments.

[0372] Layer 229 may also be non-crystalline. Furthermore, if layer 229 is crystalline, it may have a crystal structure with low lattice integration with the metal oxide contained in the oxide semiconductor 230.

[0373] Reference Figures 27A to 28D An example illustrating the manufacturing method of oxide semiconductor 230.

[0374] First, oxide semiconductor 230a is formed on layer 229 using the ALD method (see reference). Figure 27A Next, oxide semiconductor 230b is formed on oxide semiconductor 230a using sputtering (see reference). Figure 27B ).

[0375] When depositing metal oxide films using sputtering, alloying sometimes occurs between the components contained in the metal oxide film and the components contained in the layer on the surface being formed, due to damage to the surface being formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even after the heat treatment described later. When using an oxide semiconductor layer with alloyed regions in a transistor, there are concerns about negatively impacting the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress the alloying between the components contained in the metal oxide film and the components contained in the layer on the surface being formed.

[0376] In one embodiment of the present invention, an oxide semiconductor layer manufacturing method is used to form an oxide semiconductor 230a between an oxide semiconductor 230b and a layer 229 using a deposition method that causes minimal damage to the surface to be formed. This suppresses the alloying of the components contained in the oxide semiconductor 230 with the components contained in the layer 229, thereby further improving the crystallinity of the oxide semiconductor 230.

[0377] By employing the above structure, the thickness of the alloyed region can be reduced to a point where it is not observable. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that... Figure 27A and Figure 27B An example is shown where no alloying region is formed between layer 229 and oxide semiconductor 230a.

[0378] Note that the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0379] For example, using the direction perpendicular to the surface to which the oxide semiconductor 230a is formed as the depth direction, a linear EDX analysis is performed on the aforementioned region and its surrounding area. Next, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth at which the quantitative value of a metal that is a major component of the oxide semiconductor 230a but not a major component of the layer forming the surface (here, layer 229) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element that is a major component of the layer forming the surface but not a major component of the oxide semiconductor 230a (e.g., Si) reaches half its value is defined as the depth (location) of the interface between the aforementioned region and the layer forming the surface. Through these steps, the thickness of the alloyed region can be calculated.

[0380] In one aspect of the oxide semiconductor layer of the present invention, when the thickness of the alloyed region is observed using EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0381] Additionally, for example, when using a silicon oxide layer as layer 229 and performing SIMS analysis on the oxide semiconductor 230 formed on layer 229, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration in layer 229, and the silicon concentration is reduced to 1.0 × 10⁻⁶. 21 atoms / cm 3 Preferably 5.0×10 20 atoms / cm 3 More preferably 1.0×10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t_s2. The thickness t_s2 is preferably less than 3 nm, and more preferably less than 2 nm.

[0382] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the range mentioned above.

[0383] Furthermore, by thinning the alloyed region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region in a substantially perpendicular direction that is greater than 0 nm and less than 3 nm from the surface to be formed of the oxide semiconductor 230, preferably greater than 0 nm and less than 2 nm, and more preferably more than 1 nm and less than 2 nm.

[0384] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when performing cross-sectional observation of oxide semiconductor 230 using high-resolution TEM, layered bright spots arranged in a direction parallel to the formed surface were identified near the formed surface.

[0385] Furthermore, when forming oxide semiconductor 230a using the ALD method, sometimes oxide semiconductor layers with microcrystalline or amorphous structures that have lower crystallinity than the CAAC structure are formed. That is, in Figure 27A In the manufacturing stages shown, oxide semiconductor 230a sometimes includes regions whose crystallinity is lower than that of oxide semiconductor 230b.

[0386] The oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure.

[0387] When forming the oxide semiconductor 230b using a sputtering method, a mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, due to sputtered particles during the formation of the oxide semiconductor 230b, or energy supplied to the substrate side by sputtered particles, small crystalline regions may sometimes form in the mixed layer 231. In subsequent heat treatment processes, at least a portion of the oxide semiconductor 230a may crystallize by using the mixed layer 231 or the small crystalline regions formed in the mixed layer 231 as nuclei.

[0388] When depositing oxide semiconductor 230b using sputtering, it is preferable to heat the substrate. When forming metal oxides, by increasing the substrate temperature (stage temperature) during metal oxide formation, it is sometimes possible to form highly crystalline metal oxides.

[0389] Next, oxide semiconductor 230c is formed on oxide semiconductor 230b using the ALD method (see reference). Figure 27C For the formation of oxide semiconductor 230c using the ALD method, please refer to the formation method of oxide semiconductor 230a.

[0390] When forming oxide semiconductor 230c on oxide semiconductor 230b having a CAAC structure using the ALD method, oxide semiconductor 230c is sometimes epitaxially grown with oxide semiconductor 230b as the core. Therefore, when forming oxide semiconductor 230c, oxide semiconductor 230c sometimes includes a region having a CAAC structure. Furthermore, this region having a CAAC structure is preferably formed throughout oxide semiconductor 230c.

[0391] Next, a heat treatment process can be performed. Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c is sometimes improved. Furthermore, after deposition using the ALD method, when this region is only formed below the oxide semiconductor 230c, it sometimes extends upwards due to this heat treatment process (see [reference]). Figure 27D In other words, by performing this heat treatment, regions with CAAC structures are sometimes formed throughout the oxide semiconductor 230c.

[0392] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a undergoes CAAC treatment via this heat treatment process (see reference). Figure 27D CAAC formation is expected to readily occur using the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of oxide semiconductor 230b as a core or seed. The CAAC formation region in the oxide semiconductor 230a is preferably large, and preferably extends to the vicinity of layer 229.

[0393] Furthermore, since CAAC formation occurs from the upper to the lower portion of the oxide semiconductor 230a, it is not limited by the material or crystallinity of layer 229 and can reach the vicinity of layer 229. For example, even if layer 229 has an amorphous structure, a highly crystalline oxide semiconductor 230a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one aspect of the present invention is particularly suitable for cases where the layer to be formed has an amorphous structure.

[0394] Notice, Figures 27A to 27D This is a cross-sectional view illustrating a method for depositing metal oxides according to one aspect of the present invention. Furthermore, Figures 27A to 27D This can also be viewed as a conceptual diagram illustrating a metal oxide deposition model of one aspect of the present invention. For example... Figures 27A to 27D As shown, oxide semiconductors 230a and 230c respectively enhance their crystallinity by using highly crystallinity oxide semiconductor 230b as a core or seed. Specifically, the crystallinity of oxide semiconductor 230a is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230b. Furthermore, the crystallinity of oxide semiconductor 230c is sometimes improved by heat treatment during or after the deposition of oxide semiconductor 230c. Note that the aforementioned heat treatment plays an auxiliary role in improving crystallinity.

[0395] Thus, in one aspect of the metal oxide deposition method of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductors 230a and 230c) can be improved by using a highly crystalline oxide semiconductor 230b (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using oxide semiconductor 230b as a nucleus or seed to grow the upper and lower oxide semiconductors in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, i.e., the CAAC film, can be referred to as axially grown CAAC (AG CAAC).

[0396] In oxide semiconductor 230, regions with CAAC structures are preferably widely present throughout the entire layer. Figure 28A The diagram shows a state where oxide semiconductors 230a, 230b, and 230c are all crystallized. In this state, sometimes the boundary between oxide semiconductors 230a and 230b is not observed. Furthermore, sometimes the boundary between oxide semiconductors 230b and 230c is not observed. Oxide semiconductor 230 can sometimes be described as a layer without a clearly observed interface. Oxide semiconductor 230 can sometimes be described as a single layer.

[0397] In addition, sometimes a portion of oxide semiconductor 230a or oxide semiconductor 230c is not crystallized. Figure 28B This illustrates the case where the interface between the oxide semiconductor 230a and layer 229 is not crystallized. Figure 28C This illustrates the case where the surface of an oxide semiconductor 230c is not crystallized. Figure 28D This illustrates the case where the area near the interface between oxide semiconductor 230a and layer 229, and the area near the surface of oxide semiconductor 230c, are not crystallized.

[0398] By improving the crystallinity of the oxide semiconductor layer, the increase in semiconductor layer resistance in transistors using oxide semiconductor layers is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby making it possible to realize transistors suitable for high-speed driving. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0399] In one embodiment of the present invention, the oxide semiconductor layer exhibits high overall crystallinity. Therefore, in oxide semiconductor 230, the boundaries between the stacked films in oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are sometimes not identified. In particular, after heat treatment, it is sometimes difficult to identify the boundaries between the stacked films. For example, the presence or absence of boundaries between the stacked films can be confirmed by cross-sectional observation using TEM, scanning transmission electron microscopy (STEM), etc.

[0400] As described above, using metal oxides with a high In content ratio in transistors can improve the transistor's field-effect mobility. On the other hand, oxide semiconductors with a high In content ratio tend to polycrystalline. When using metal oxides with polycrystalline structures in transistors, it negatively impacts the transistor's initial characteristics or reliability. Therefore, by using oxide semiconductors with a high In content ratio in one or both of oxide semiconductors 230a and 230c, forming a crystal that reflects the orientation of the crystals contained in oxide semiconductor 230b, polycrystalline formation can be suppressed.

[0401] Furthermore, the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is preferably small. Therefore, oxide semiconductor 230a or oxide semiconductor 230c can form a crystal that reflects the orientation of the crystal contained in oxide semiconductor 230b. At this time, for example, when observing a cross-section of oxide semiconductor 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in oxide semiconductor 230a or oxide semiconductor 230c.

[0402] There are no particular restrictions on the crystal structure of oxide semiconductor 230a or oxide semiconductor 230c, provided that the lattice mismatch between the crystal contained in oxide semiconductor 230b and the crystal contained in oxide semiconductor 230a or oxide semiconductor 230c is small. The crystal structure of oxide semiconductor 230a or oxide semiconductor 230c can also be any of the cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal crystal systems.

[0403] [Composition of the oxide semiconductor layer] As described above, the composition of the oxide semiconductor 230b is preferably suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed, for example, using a sputtering method. The oxide semiconductor 230b preferably contains zinc, for example. By including zinc, a highly crystalline metal oxide can be obtained. Furthermore, the oxide semiconductor 230b preferably contains element M in addition to zinc. By including element M in the oxide semiconductor 230b, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using the oxide semiconductor layer can be improved. Specifically, as an oxide semiconductor 230b, metal oxides with the following compositions can be used: In:M:Zn = 1:1:1 [atomic ratio] or similar, In:M:Zn = 1:1:1.2 [atomic ratio] or similar, In:M:Zn = 1:1:0.5 [atomic ratio] or similar, In:M:Zn = 1:1:2 [atomic ratio] or similar, In:M:Zn = 4:2:3 [atomic ratio] or similar, In:M:Zn = 1:3:2 [atomic ratio] or similar, In:M:Zn = 1:3:4 [atomic ratio] or similar. Note that "similar" includes a range of ±30% of the desired atomic ratio. Furthermore, one or more of gallium, aluminum, and tin are preferably used as element M.

[0404] The oxide semiconductor 230b may also not contain element M. For example, In-Zn oxide may be used. Specifically, it may be an In:Zn composition of 1:1 (atomic ratio) or near, In:Zn composition of 2:1 (atomic ratio) or near, or In:Zn composition of 4:1 (atomic ratio) or near. Alternatively, indium oxide may be used. Furthermore, it may contain trace amounts of element M. For example, it may be an In:Ga:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Ga:Zn composition of 2:0.1:1 (atomic ratio) or near. Additionally, it may be an In:Sn:Zn composition of 4:0.1:1 (atomic ratio) or near, or In:Sn:Zn composition of 2:0.1:1 (atomic ratio) or near.

[0405] Oxide semiconductors 230a and 230c can use metal oxides with a high In content. Oxide semiconductors 230a and 230c can be formed, for example, using the ALD method. Furthermore, metal oxides with a higher In content than element M are particularly preferred. By using metal oxides with a high In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics improved.

[0406] Alternatively, oxide semiconductors 230a and 230c may not contain element M. For example, In-Zn oxide may also be used. Specifically, it may be an In:Zn ratio of 1:1 or similar, an In:Zn ratio of 2:1 or similar, or an In:Zn ratio of 4:1 or similar. Alternatively, indium oxide may also be used. Furthermore, oxide semiconductors 230a and 230c may also contain trace amounts of element M. Specifically, it may be an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, an In:Sn:Zn ratio of 4:0.1:1 or similar, or an In:Sn:Zn ratio of 2:0.1:1 or similar.

[0407] Furthermore, oxide semiconductors 230a and 230c can use metal oxides with a higher proportion of In than oxide semiconductor 230b.

[0408] Furthermore, for example, metal oxides with a higher Ga content than oxide semiconductor 230b can be used as oxide semiconductors 230a and 230c. For example, oxide semiconductors 230a and 230c preferably use metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar. By increasing the Ga content, the band gap of oxide semiconductors 230a and 230c can sometimes be made larger than that of oxide semiconductor 230b. Thus, oxide semiconductor 230b is sandwiched between oxide semiconductors 230a and 230c with larger band gaps, and oxide semiconductor 230b is primarily used as a current path (channel). By sandwiching oxide semiconductor 230b between oxide semiconductors 230a and 230c, the trap levels at and near the interface of oxide semiconductor 230b can be reduced. This allows for the creation of buried-channel transistors with the channel located far from the insulating layer interface, thereby improving field-effect mobility.

[0409] Furthermore, in one embodiment of the oxide semiconductor layer of the present invention, even if the oxide semiconductors 230a and 230c employ a composition that makes it difficult to form a CAAC structure when forming a monolayer, the entire oxide semiconductor layer including oxide semiconductors 230a and 230c can have a CAAC structure by crystal growth with oxide semiconductor 230b as the nucleus. Alternatively, regions including at least a portion of each of oxide semiconductors 230a and 230c extending to the region of oxide semiconductor 230b can have a CAAC structure.

[0410] In particular, when the oxide semiconductors 230a and 230c employ a high In ratio, a crystallinity suitable for transistors can be obtained. In one embodiment of the oxide semiconductor layer of the present invention, while increasing the In ratio to improve the transistor's turn-on characteristics, reliability can be improved by employing a highly crystallinity CAAC structure.

[0411] Note that the composition of oxide semiconductor 230a can also be different from that of oxide semiconductor 230c.

[0412] In addition, oxide semiconductors 230a and 230c can also use metal oxides with the same composition as oxide semiconductor 230b.

[0413] By using the oxide semiconductor layer with CAAC structure formed by the above two deposition methods to form the channel region of the transistor, transistors with excellent characteristics can be realized (e.g., transistors with large on-state current, transistors with high field-effect mobility, transistors with small S-value, transistors with high frequency characteristics (also known as f-characteristics), transistors with high reliability, etc.).

[0414] The composition of the metal oxides used in oxide semiconductor 230 can be analyzed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these methods can be used. Note that the actual content ratio of elements with low abundance can differ from the analytically obtained ratio due to the limitations of analytical precision. For example, when the abundance ratio of element M is low, the analytically obtained content ratio of element M may sometimes be lower than the actual content ratio.

[0415] [c-axis orientation] One embodiment of the present invention has an oxide semiconductor layer with a CAAC structure. For example, crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0416] Crystal orientation can be obtained from TEM images by performing a Fast Fourier Transform (FFT). Specifically, the crystal axis orientation can be obtained from the FFT pattern. The FFT pattern obtained through FFT processing reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0417] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region over a certain area, a map showing the crystal orientation can be formed. Specifically, two high-intensity spots are observed in the FFT pattern of a region with layered crystals. The crystal axis orientation of this region can be obtained from the angle of the line segment connecting these two spots.

[0418] The degree of c-axis orientation can be calculated by determining the proportion of the c-axis orientation region in a diagram showing crystal orientation. Note that here, the c-axis orientation region refers to the region whose orientation coincides with the c-axis and whose difference from the c-axis is within 20 degrees.

[0419] In one embodiment of the present invention, the c-axis orientation rate can be calculated, for example, by performing cross-sectional or planar TEM observation of the oxide semiconductor layer. Furthermore, the region for performing the FFT (also called the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region for performing the FFT is not limited to a circle.

[0420] In one embodiment of the oxide semiconductor layer of the present invention, the c-axis orientation is preferably 60% or more, more preferably 70% or more, even more preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more.

[0421] Furthermore, the c-axis orientation degrees of the regions deposited as oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are Rc1, Rc2, and Rc3, respectively. Rc2 and Rc3 are preferably 60% or more, more preferably 70% or more, further preferably 80% or more, even more preferably 90% or more, and still more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Furthermore, Rc2 / Rc1 is preferably greater than 1.

[0422] Note that sometimes the boundaries of oxide semiconductors 230a, 230b and 230c are not clearly observed after the oxide semiconductor 230 is manufactured.

[0423] In one embodiment of the present invention, the oxide semiconductor 230 can be sequentially divided into three regions—a first region, a second region, and a third region—from one side of layer 229. Each region is a layered region.

[0424] The first, second, and third regions all have a CAAC structure. Furthermore, the c-axis orientation degree of the third region is preferably higher than that of the first region. Similarly, the c-axis orientation degree of the second region is preferably higher than that of the first region. Moreover, the c-axis orientation degree of both the second and third regions is preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0425] The first region is located 0 nm above and 3 nm below the top surface of layer 229, and the third region is located 0 nm above and 3 nm below the top surface of oxide semiconductor 230.

[0426] Alternatively, the thickness of the layers in each region may be approximately the same.

[0427] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0428] (Implementation Method 4) In this embodiment, electronic components, electronic devices, and mainframe computers that can use the storage devices described in the above embodiments will be described. Electronic components, electronic devices, and mainframe computers using a storage device according to one aspect of the present invention are highly effective in achieving high performance, such as low power consumption.

[0429] [Electronic Components] Figure 29A A perspective view of a substrate (circuit board 704) on which electronic components 709 are mounted is shown. Figure 29A The electronic component 709 shown includes a storage device 710 within the mold 711. Figure 29A In this text, a portion of the electronic component 709 is omitted to indicate its internal structure. The electronic component 709 includes a connecting pad 712 on the outside of the mold 711. The connecting pad 712 is connected to an electrode pad 713, which is connected to the storage device 710 via a lead 714. The electronic component 709 is mounted, for example, on a printed circuit board 702. By combining multiple such electronic components and connecting them individually on the printed circuit board 702, the circuit board 704 is completed.

[0430] Furthermore, the storage device 710 includes a layer 715 with a processing core and a layer 716 with memory. Note that the memory layer 716 has a structure with multiple memory cell arrays stacked on top of each other. The structure of the layer 715 with the processing core and the layer 716 with memory can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without through-hole electrode technologies such as TSVs (Through Silicon Vias) or bonding technologies such as Cu-Cu direct bonding. When the layer 715 with the processing core and the layer 716 with memory have a monolithic stacked structure, for example, a so-called on-chip memory structure where memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0431] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving memory bandwidth.

[0432] Furthermore, it is preferable to use OS transistors to form the multiple memory cell arrays included in the memory layer 716, and to stack these multiple memory cell arrays monolithically. When the multiple memory cell arrays adopt a monolithic stacked structure, one or both of the memory bandwidth and memory access latency can be improved. Note that bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between access and the start of data exchange. In addition, when Si transistors are used in the memory layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0433] Alternatively, the storage device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into small rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0434] then, Figure 29BA perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a storage device 735 and multiple storage devices 710 are provided on the interposer 731.

[0435] The packaging substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0436] The through-hole board 731 has multiple wirings and multiple integrated circuits with different spacing between their electrical connection terminals. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 732. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is electrically connected to the package substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0437] Furthermore, for example, HBM (High Bandwidth Memory) can be used in storage device 710 or storage device 735. In HBM, many wirings are required to achieve wide memory bandwidth. Therefore, to mount HBM, fine wirings need to be densely formed on the mounting board 731. Therefore, a silicon mounting board is preferably used as the mounting board for HBM.

[0438] Furthermore, in SiP and MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally side-by-side on the interposer.

[0439] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required for the width of these terminal pitches. Therefore, when the size of the electronic component 730 is to be reduced, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a memory cell array stacked monolithically can also be used.

[0440] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 have the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 710 and the storage device 735 have the same height.

[0441] In order to mount the electronic component 730 on other substrates, an electrode 733 may also be provided on the bottom of the package substrate 732. Figure 29B An example of forming electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrode 733 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0442] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0443] Figures 30A to 30D This is an explanation of the above. Figure 29A and Figure 29B The diagram shows different structural examples of electronic components 709 and 730. Figures 30A to 30D The electronic components 730A to 730D shown have the following structure: a layer 715 having a computing core and a layer 716 having a memory are provided in a mold 711 on a plate 731 on which the above-mentioned electrodes 733 are provided.

[0444] exist Figure 30A In the structure of the electronic component 730A shown, a layer 715 with a processing core is disposed on a connector 731 and connected to electrode pads (not shown) via leads 714. A memory layer 716 formed on the processing core layer 715 has the aforementioned monolithic stacked structure. In the monolithic stacked structure, the memory layer 716 is connected to the processing core layer 715. Therefore, since the leads 714 between the connector 731 and the processing core layer 715 can also serve as wiring between the memory layers 716 of each layer and the connector 731, the number of leads can be reduced.

[0445] Note that in Figure 30A The structural example illustrates a single monolithic stacked structure, but it's also possible to use a structure where monolithic stacked electronic components overlap with other electronic components. For example, as... Figure 30B As shown, the following structure can also be adopted: multiple layers 716A (containing memory) and 715A (containing computational core), as well as layers 716B (containing memory) and 715B (containing computational core), are stacked to form a monolithic stacked structure. The monolithic stacked structure, overlapping with other electronic components, is fixed to a resin sheet 744 by an adhesive layer 743. By adopting this structure, a structure can be realized that stacks multiple memory cell arrays with different circuit structures. By having different circuit structures, memory devices with different bandwidths and memory access delays can be realized, and this is preferably applied to structures with layered structures, such as cache memories.

[0446] also, Figure 30A The structural examples can be stacked with other electronic components. For example, such as... Figure 30C As shown, an electronic component 730C can be used, wherein the aforementioned electronic component 730A and a layer 715C containing a processing core, such as a processor, are stacked within a mold 711 located between insert plates 731A and 731B. The circuit layers are connected via conductive materials such as electrodes 733. This structure enables high-speed operation of the interface between the processor and memory. Furthermore, a gap (space) can be provided between the mold containing the processing core layer 715C and the mold containing the electronic component 730A, thereby preventing heat generated in the processing core layer 715C from easily transferring to the electronic component 730A.

[0447] In addition, Figure 30C In structural examples, a structure can also be adopted where a memory layer including OS transistors is set on the 715C layer containing processing cores such as processors. For example, as... Figure 30DAs shown, a layer 716C containing memory can be disposed on a layer 715C containing a computing core and stacked with an electronic component 730A. By adopting this structure, high-speed operation of the interface portion between a structure of so-called on-chip memory, in which memory is directly formed on the processor, and a structure of a memory device including stacked memory layers, can be achieved.

[0448] [Electronic Devices] Figure 31A This is an external image showing an example of a portable electronic device. Figure 31B This is a simplified diagram of data delivery within a portable electronic device. The portable electronic device 595 includes a printed circuit board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0449] In the portable electronic device 595, the aforementioned electronic component 709 can be mounted on the printed circuit board 596. By utilizing the electronic component 709, the portable electronic device 595 can process and analyze multiple data obtained through the speaker 597, camera 598, microphone 599, etc., thereby improving user convenience. Furthermore, the electronic component 709 can also be used in systems such as voice guidance and image retrieval.

[0450] In electronic component 709, the obtained image data is processed by artificial neural network (ANN) and other operations. For example, image resolution can be increased, image noise can be reduced, face recognition can be performed (for security purposes, etc.), object recognition can be performed (for autonomous driving purposes, etc.), image compression can be performed, image correction can be performed (wide dynamic range), image restoration of lensless image sensors can be performed, position alignment can be performed, text recognition can be performed, and reflection glare can be reduced.

[0451] Figure 32A The portable game console 1100 shown includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connector 1105, and operation keys 1107. Housings 1101, 1102, and 1103 are detachable. By mounting the connector 1105 provided on housing 1101 to housing 1108, the image output to display unit 1104 can be output to other video display devices. Alternatively, by mounting housings 1102 and 1103 to housing 1109, housings 1102 and 1103 can be integrated and used as an operation unit. The aforementioned electronic components 709 can be combined with chips or the like provided on the substrates of housings 1102 and 1103.

[0452] Figure 32BThis is a strip-shaped electronic device 1120 with USB (Universal Serial Bus) connectivity. The electronic device 1120 includes a housing 1121, a cover 1122, a USB connector 1123, and a substrate 1124. The substrate 1124 is housed within the housing 1121. For example, a memory chip 1125 and a control chip 1126 are mounted on the substrate 1124. The aforementioned electronic components 709 can be integrated with the controller chip 1126, etc., on the substrate 1124.

[0453] Figure 32C It is a humanoid robot 1130. Robot 1130 includes sensors 2101 to 2106 and control circuitry 2110. For example, the aforementioned electronic component 709 can be integrated into control circuitry 2110.

[0454] [Mainframe Computer] The aforementioned electronic component 709 can be used in a system 3000 that includes a large computer that communicates with the electronic device, without being housed within the electronic device. In this case, the electronic device and the large computer constitute a computing system. Figure 33 This shows a structural example of System 3000.

[0455] System 3000 consists of electronic device 3001 and mainframe computer 3002. Communication between electronic device 3001 and mainframe computer 3002 can be carried out via Internet cable 3003.

[0456] The mainframe computer 3002 has multiple racks 3004. Multiple substrates 3005 are arranged on these racks, and the electronic components 709 described in the above embodiments can be mounted on these substrates 3005. Thus, a neural network is formed in the mainframe computer 3002. Furthermore, the mainframe computer 3002 can perform neural network operations using data input from the electronic device 3001 via the Internet cable 3003. The operation results of the mainframe computer 3002 can be transmitted to the electronic device 3001 via the Internet cable 3003 as needed. This reduces the computational burden on the electronic device 3001.

[0457] This embodiment can be appropriately combined with descriptions of other embodiments.

[0458] <Notes regarding the contents of this instruction manual, etc.> Below, additional notes are added to the descriptions of the above embodiments and the structures in those embodiments.

[0459] The structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to constitute one aspect of the present invention. Furthermore, when multiple structural instances are shown in one embodiment, these structural instances can be appropriately combined.

[0460] Furthermore, the content (or a portion thereof) described in one embodiment may be applied, combined, or replaced with other content (or a portion thereof) described in that embodiment and / or content (or a portion thereof) described in one or more other embodiments.

[0461] The content described in the embodiments refers to the content described in each embodiment using various accompanying drawings or the content described in the instruction manual.

[0462] Furthermore, more figures can be formed by combining the figures (or portions thereof) shown in one embodiment with other portions of the figures, other figures (or portions thereof) shown in that embodiment, and / or figures (or portions thereof) shown in one or more other embodiments.

[0463] In this specification, components are categorized according to function and represented by independent boxes in block diagrams. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of boxes in block diagrams is not limited to the components described in the specification and may vary appropriately depending on the circumstances.

[0464] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not necessarily limited to the dimensions described above. The drawings are shown in arbitrary sizes for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, non-uniformity of signals, voltages, or currents caused by noise or timing deviations may be included.

[0465] In this specification and other documents, when describing the connection relationships of transistors, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. This is because the source and drain of a transistor are interchangeable depending on the transistor's structure or operating conditions. Note that, depending on the circumstances, the source and drain of a transistor may be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0466] Furthermore, in this specification and the like, the terms "electrode" or "wiring" do not limit the function of the constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0467] Furthermore, voltage and potential can be interchanged appropriately in this instruction manual and other documents. Voltage refers to the potential difference between the voltage and a reference potential. For example, when the reference potential is ground voltage (grounding voltage), voltage can be replaced with potential. Grounding potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied for wiring, etc., sometimes varies according to the reference potential.

[0468] In this specification and other materials, the terms "film" and "layer" may be interchanged depending on the situation or condition. For example, "conductive layer" may sometimes be replaced with "conductive film." Furthermore, "insulating film" may sometimes be replaced with "insulating layer."

[0469] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths.

[0470] In this specification, for example, the channel length of a planar transistor refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is turned on) and the gate electrode overlap or the region forming the channel in a planar view of the transistor.

[0471] In this specification, for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is turned on) and the gate electrode overlap, or the length of the portion of the region in which the source and drain electrodes of the channel are opposite each other.

[0472] In this specification and other materials, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, or impurity regions, depending on the circuit structure or device structure. Alternatively, terminals, wiring, etc., may also be referred to as nodes.

[0473] In this specification, "A connected to B" means that A and B are electrically connected. Here, "A connected to B" refers to a connection where an object (a switch, transistor, diode, or other component, or a circuit containing such an object and wiring) exists between A and B, allowing the transmission of electrical signals between them. Note that the case of an electrical connection between A and B includes the case of a direct connection between A and B. Here, a direct connection between A and B means a connection where A and B can transmit electrical signals between them via wiring (or electrodes) without passing through the aforementioned object. In other words, a direct connection is a connection that can be considered as the same circuit diagram when represented using equivalent circuits.

[0474] [Symbol Explanation] BL: Bit line, BLB: Inverted bit line, DBL: Data bit line, DBLB: Inverted data bit line, DSAB: Data sense amplifier block, GSA: Global sense amplifier, GSAB: Global sense amplifier block, SADB: Sense amplifier driver block, WDB: Word line driver block, 10: Component layer, 11: Global sense amplifier section, 12: Data sense amplifier section, 13: Global sense amplifier driver circuit section, 14: Column line driver circuit section, 15: Word line driver circuit section, 16: Controller section, 40: Component layer, 41: Memory cell, 42: Memory cell array.

Claims

1. A storage device, comprising: The first sense amplifier section includes a plurality of first sense amplifier blocks electrically connected to the memory cells via first bit lines; It includes a second sense amplifier section comprising a second sense amplifier block electrically connected to the first sense amplifier block via a second bit line; A word line driving circuit section including multiple word line driving blocks that output word signals to the memory cell; It includes a sense amplifier drive circuit section that drives multiple sense amplifier drive blocks that drive the first sense amplifier block; as well as A controller unit that outputs a sense amplifier driver block control signal to control the sense amplifier driver block and a word line driver block control signal to control the word line driver block. The sense amplifier driver block control signal is a signal that enables the plurality of sense amplifier driver blocks to control the state of the first sense amplifier block. Furthermore, the word line driver block control signal is a signal that enables the plurality of word line driver blocks to output the word signal to the memory cell connected to the first sense amplifier block.

2. The storage device according to claim 1, The memory cell includes a first transistor. The first transistor includes a first semiconductor layer comprising an oxide semiconductor in the channel forming region.

3. The storage device according to claim 2, When viewed in cross-section along the channel width, the first semiconductor layer has a fin-like shape.

4. A storage device, comprising: The first sense amplifier section includes a plurality of first sense amplifier blocks electrically connected to the memory cells via first bit lines; It includes a second sense amplifier section comprising a second sense amplifier block electrically connected to the first sense amplifier block via a second bit line; A word line driving circuit section including multiple word line driving blocks that output word signals to the memory cell; It includes a sense amplifier drive circuit section that drives multiple sense amplifier drive blocks that drive the first sense amplifier block; as well as A controller unit that outputs a sense amplifier driver block control signal to control the sense amplifier driver block, a word line driver block control signal to control the word line driver block, and a second sense amplifier control signal to control the second sense amplifier block. The sense amplifier driver block control signal is a signal that enables the plurality of sense amplifier driver blocks to control the state of the first sense amplifier block. The word line driver block control signal is a signal that enables the plurality of word line driver blocks to output the word signal to the memory cell connected to the first sense amplifier block. Furthermore, the second sense amplifier control signal is a signal that enables a second sense amplifier block to access data read by the first sense amplifier block via the second bit line.

5. The storage device according to claim 4, The memory cell includes a first transistor. The first transistor includes a first semiconductor layer comprising an oxide semiconductor in the channel forming region.

6. The storage device according to claim 5, When viewed in cross-section along the channel width, the first semiconductor layer has a fin-like shape.

7. A storage device, comprising: The first sense amplifier section includes a plurality of first sense amplifier blocks electrically connected to the memory cells via first bit lines; It includes a second sense amplifier section comprising a second sense amplifier block electrically connected to the first sense amplifier block via a second bit line; A word line driving circuit section including multiple word line driving blocks that output word signals to the memory cell; It includes a sense amplifier drive circuit section that drives multiple sense amplifier drive blocks that drive the first sense amplifier block; as well as A controller unit that outputs a sense amplifier driver block control signal to control the sense amplifier driver block and a word line driver block control signal to control the word line driver block. The sense amplifier driver block control signal is a signal that enables one or more sense amplifier driver blocks to control the state of the first sense amplifier block. Furthermore, the word line driver block control signal is a signal that enables one or more of the word line driver blocks to output the word signal to the memory cell connected to the first sense amplifier block.

8. The storage device according to claim 7, The memory cell includes a first transistor. The first transistor includes a first semiconductor layer comprising an oxide semiconductor in the channel forming region.

9. The storage device according to claim 8, When viewed in cross-section along the channel width, the first semiconductor layer has a fin-like shape.

10. The storage device according to claim 7, The controller unit has the function of outputting a second sense amplifier control signal to control the second sense amplifier block. Furthermore, the second sense amplifier control signal is a signal that enables a second sense amplifier block to access data read by the first sense amplifier block via the second bit line.

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