DC / DC converter

Abstract

In an H-bridge buck-boost DC / DC converter, when a lower side of an up-down range of a reference signal for buck is zero or less and an upper side of an up-down range of a reference signal for boost is zero or more at the start of one switching period, a control unit controls the buck-boost DC / DC converter in a predetermined period from the start of the one switching period. The fourth switching element is maintained in an off state. In the step-up / step-down DC / DC converter, an increase in loss caused by an unintended switching operation of a step-up circuit under the condition that operation should be performed only by a step-down operation instead of in an overlapping region is prevented.

Description

Technical Field

[0001] This disclosure relates to a DC / DC converter capable of buck-boosting. Background Technology

[0002] Among DC / DC converters, there exists an H-bridge buck-boost DC / DC converter capable of seamlessly switching between boost and buck operations (see, for example, Patent Document 1). H-bridge buck-boost DC / DC converters are frequently used for DC power supplies with fluctuating voltages, such as batteries and solar cells.

[0003] When using an H-bridge buck-boost DC / DC converter for buck operation, the general approach is as follows: the high-side switching element on the output side is fixed in the on state, and the low-side switching element is fixed in the off state, controlled by the ratio of the on-time to the off-time of the high-side switching element on the input side. Conversely, when using an H-bridge buck-boost DC / DC converter for boost operation, the general approach is as follows: the high-side switching element on the input side is fixed in the on state, and the low-side switching element is fixed in the off state, controlled by the ratio of the on-time to the off-time of the low-side switching element on the output side.

[0004] In H-bridge type buck-boost DC / DC converters, there exists a buck-boost DC / DC converter that has an overlapping region at the boundary between the region where buck operation is performed and the region where boost operation is performed. In the overlapping region, buck-boost operation that allows buck operation performed by the high-side switching element on the input side and boost operation performed by the low-side switching element on the output side to coexist is supported.

[0005] Prior art literature

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2000-166223 Summary of the Invention

[0008] When constructing an H-bridge buck-boost DC / DC converter with an overlap region set in peak current mode, under heavy load during buck operation, the current may be judged to be zero at the beginning of a switching cycle due to current detection delay, and the boost operation will also start, resulting in buck-boost operation. Although the buck operation will switch back to buck operation if current is detected, the situation of buck-boost operation at the beginning of a switching cycle is a useless switch and leads to losses.

[0009] The DC / DC converter of the present disclosure includes: a first arm including one of a first switching element and one of a second switching element and a second rectifying element, the one of the first switching element and the one of the second switching element and the second rectifying element being connected in series at a first connection point, and the first arm being connected in parallel with respect to a direct-current power supply; a second arm including one of a third switching element and a third rectifying element and a fourth switching element, the one of the third switching element and the third rectifying element being connected in series at a second connection point with the fourth switching element, and the second arm being connected in parallel with respect to a direct-current bus; a reactor connected to the first connection point of the first arm and the second connection point of the second arm; and a control unit that controls the first switching element, the second switching element, the third switching element, and the fourth switching element, or controls the first switching element and the fourth switching element. The control unit generates a sawtooth-shaped reference signal for step-up to which a slope compensation is applied to a difference between an output voltage or an output current with respect to the direct-current bus and a reference value, adds a sawtooth wave for step-down to the error signal, the sawtooth wave for step-down being obtained by shifting the reference signal for step-up upward, and having a certain overlap region with an upper side of the reference signal for step-up, at the start of one switching cycle, in a case where a current detection value obtained by detecting a current flowing through the reactor is within an upper and lower range of the reference signal for step-down, the first switching element is turned on, and thereafter, if the current detection value coincides with the reference signal for step-down, the first switching element is turned off, at the start of one switching cycle, in a case where the current detection value is within the upper and lower range of the reference signal for step-up, the fourth switching element is turned on, and thereafter, if the current detection value coincides with the reference signal for step-up, the fourth switching element is turned off, in a case where a lower side of the upper and lower range of the reference signal for step-down is below zero and an upper side of the upper and lower range of the reference signal for step-up is above zero at the start of one switching cycle, the fourth switching element is maintained in an off state for a given period from the start of one switching cycle.

[0010] According to the present disclosure, in the H-bridge type step-up / down DC / DC converter, an increase in loss due to unintended switching operation of the step-up circuit can be prevented in a condition where the operation is not performed in the overlap region and should be performed only by the step-down operation. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a diagram showing a structure example of the H-bridge type step-up / down DC / DC converter to which the embodiment relates.

[0012] Figure 2 This is a diagram showing an example of the circuit structure of the control unit involved in the comparative example (voltage mode).

[0013] Figure 3 This is a diagram illustrating an example of the circuit structure of the control unit involved in the implementation method (peak current mode).

[0014] Figure 4 This is a diagram illustrating an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first to fourth switching elements, used to explain the basic operation of the H-bridge buck-boost DC / DC converter according to the embodiment.

[0015] Figure 5 (a)-(b) are schematic diagrams illustrating the flow of current during the boost operation.

[0016] Figure 6 (a)-(b) are schematic diagrams illustrating the flow of current during the voltage reduction operation.

[0017] Figure 7 (a)-(b) are schematic diagrams illustrating the flow of reverse current from the output side to the input side.

[0018] Figure 8 This is an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltage of the first to fourth switching elements when the third switching element is always fixed in the off state.

[0019] Figure 9 This is an example of a timing diagram showing the current detection value, the reference signal for bucking, the reference signal for boosting, and the gate / source voltage of the first to fourth switching elements when a reverse current is generated during the boost operation.

[0020] Figure 10 This is an example of a timing diagram showing the current detection value, the reference signal for bucking, the reference signal for boosting, and the gate / source voltage of the first to fourth switching elements when a reverse current is generated during bucking operation.

[0021] Figure 11 This is a diagram illustrating an example of a timing diagram of the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltage of the first to fourth switching elements in the case where reverse current countermeasures are implemented according to the embodiment.

[0022] Figure 12This is an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first to fourth switching elements when there is no delay in the current detection value under light load during buck operation.

[0023] Figure 13 This is an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first to fourth switching elements under heavy load conditions during buck conversion without delay.

[0024] Figure 14 This is an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltage of the first to fourth switching elements when the current detection value is delayed under light load during buck operation.

[0025] Figure 15 This is an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltage of the first to fourth switching elements when the current detection value is delayed under heavy load during buck operation.

[0026] Figure 16 This is a first example of a timing diagram showing the current detection value, the reference signal for bucking, the reference signal for boosting, and the gate / source voltage of the first to fourth switching elements when the upper side of the upper and lower ranges of the reference signal for boosting is zero or higher during bucking operation.

[0027] Figure 17 This is a second example of a timing diagram showing the current detection value, the reference signal for bucking, the reference signal for boosting, and the gate / source voltage of the first to fourth switching elements when the upper side of the upper and lower ranges of the reference signal for boosting is zero or higher during bucking operation.

[0028] Figure 18 This is a diagram illustrating a structural example of a buck-boost DC / DC converter involving a variation. Detailed Implementation

[0029] Figure 1This diagram illustrates a structural example of the H-bridge buck-boost DC / DC converter 10 according to the embodiment. A DC power supply 1 is connected to the input side of the buck-boost DC / DC converter 10, and a DC bus Bdc is connected to the output side. A load 2 is connected to the DC bus Bdc. For example, the load 2 could be a server or storage device within a data center. The DC power supply 1 could also be a battery. In this case, the battery functions as a backup power source for the server or storage device.

[0030] The buck-boost DC / DC converter 10 includes a first capacitor C1, an inductor L1, first switching elements Q1 to fourth switching elements Q4, a second capacitor C2, first drive circuits dr1 to fourth drive circuits dr4, and a control unit 20. For the first capacitor C1 and the second capacitor C2, electrolytic capacitors can be used, for example. For the first switching elements Q1 to the fourth switching elements Q4, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) can be used.

[0031] A first smoothing capacitor C1 is connected between the positive and negative wirings of DC power supply 1. A first arm, comprising a first switching element Q1 and a second switching element Q2 connected in series, is connected in parallel with respect to DC power supply 1 and the first capacitor C1. A voltage sensor V1 and a second smoothing capacitor C2 are connected between the positive and negative wirings of DC bus Bdc. A second arm, comprising a third switching element Q3 and a fourth switching element Q4 connected in series, is connected in parallel with respect to DC bus Bdc and the second capacitor C2.

[0032] The first switching element Q1 serves as the high-side switching element for step-down, the second switching element Q2 serves as the low-side switching element for step-down, the third switching element Q3 serves as the high-side switching element for step-up, and the fourth switching element Q4 serves as the low-side switching element for step-up, thus each performing its respective function.

[0033] A reactor L1 is connected between the midpoint of the first arm (the connection point N1 where the first switching element Q1 and the second switching element Q2 are connected in series) and the midpoint of the second arm (the connection point N2 where the third switching element Q3 and the fourth switching element Q4 are connected in series).

[0034] In the case where the first switching element Q1 to the fourth switching element Q4 are respectively connected in reverse parallel, diodes D1 to D4 are formed or connected as body diodes. When using N-channel MOSFETs for the first switching element Q1 to the fourth switching element Q4, parasitic diodes formed from the source to the drain can be used as diodes D1 to D4. When using IGBTs for the first switching element Q1 to the fourth switching element Q4, external diodes are connected to serve as diodes D1 to D4.

[0035] The first drive circuit dr1 to the fourth drive circuit dr4 generate drive signals for the first switch element Q1 to the fourth switch element Q4 based on the control signals input from the control unit 20, respectively, to drive the first switch element Q1 to the fourth switch element Q4. When the switch element is a MOSFET, the drive circuit generates a gate / source voltage and applies it between the gate and source of the MOSFET.

[0036] Current sensor A1 detects the current flowing through reactor L1 and outputs it to control unit 20. Current sensor A1 may be composed, for example, of a shunt resistor and a current amplifier that amplifies the voltage across the shunt resistor and outputs the current. Alternatively, current sensor A1 may be composed of a Hall element and an amplifier that converts the magnetic field generated in the Hall element into a voltage. Figure 1 The image shows an example of a current sensor A1 being positioned in the positive wiring between the DC power supply 1 and the first switching element Q1, but it can also be positioned before or after the reactor L1.

[0037] Voltage sensor V1 detects the output voltage of buck-boost DC / DC converter 10 and outputs it to control unit 20. Voltage sensor V1 is, for example, constructed from a resistor divider circuit.

[0038] The control unit 20 performs PWM (Pulse Width Modulation) control on the first switching element Q1 to the fourth switching element Q4 based on the output voltage of the buck-boost DC / DC converter 10 and the current flowing through the reactor L1.

[0039] Figure 2 This is a diagram showing an example of the circuit structure of the control unit 20 involved in the comparative example (voltage mode). The voltage mode is a method that only provides feedback on the voltage error signal relative to the reference value. The error amplifier 21 amplifies and outputs the difference between the output voltage detected by the voltage sensor V1 and the reference voltage (target voltage) Vref.

[0040] The boost-side comparator 22 compares the error voltage output from the error amplifier 21 with the boost sawtooth wave (ramp) to determine the pulse width of the PWM signal controlling the fourth switching element Q4. When the error voltage is within the upper or lower range of the boost sawtooth wave, the boost-side comparator 22 outputs a high-level signal if the error voltage is lower than the boost sawtooth wave. If the error voltage becomes higher than the boost sawtooth wave, the boost-side comparator 22 outputs a low-level signal.

[0041] The buck-side comparator 23 compares the error voltage output from the error amplifier 21 with the buck sawtooth wave to determine the pulse width of the PWM signal controlling the first switching element Q1. When the error voltage is within the upper or lower range of the buck sawtooth wave, and the error voltage is higher than the buck sawtooth wave, the buck-side comparator 23 outputs a high-level signal. If the error voltage becomes lower than the buck sawtooth wave, the buck-side comparator 23 outputs a low-level signal.

[0042] Control logic circuit 24 outputs the PWM signal of the fourth switching element Q4 from boost-side comparator 22 to the fourth drive circuit dr4, and outputs a PWM signal with the opposite phase from the PWM signal of the fourth switching element Q4 from boost-side comparator 22 to the third drive circuit dr3. Control logic circuit 24 outputs the PWM signal of the first switching element Q1 from buck-side comparator 23 to the first drive circuit dr1, and outputs a PWM signal with the opposite phase obtained by inverting the PWM signal of the first switching element Q1 from buck-side comparator 23 to the second drive circuit dr2.

[0043] In the buck-boost DC / DC converter 10, by setting a certain overlap region for the sawtooth waves used for boost and buck, buck-boost operations that coexist with buck and boost operations can be performed in regions where the input and output voltages are close. This prevents chattering caused by frequent switching between buck and boost operations in regions where the input and output voltages are close, allowing for seamless switching between buck and boost operations. However, in the voltage mode described in the comparative example, bipolarity is generated by the LC filter, which consists of reactor L1 and the second capacitor C2, thus complicating phase compensation.

[0044] Figure 3 This is a diagram illustrating an example of the circuit structure of the control unit 20 according to the embodiment (peak current mode). Peak current mode is a method of feedback between the voltage error signal and the reactor current. The error amplifier 21 amplifies and outputs the difference between the output voltage detected by the voltage sensor V1 and the reference voltage Vref.

[0045] The buck-side adder 25 adds the buck sawtooth wave to the error voltage output from the error amplifier 21 and outputs it as a sawtooth wave-shaped reference signal for bucking. The boost-side adder 26 adds the boost sawtooth wave to the error voltage output from the error amplifier 21 and outputs it as a sawtooth wave-shaped reference signal for boosting. The buck and boost sawtooth waves are both right-falling (downslope) sawtooth waves. The buck sawtooth wave is obtained by shifting the boost sawtooth wave upwards, forming a certain overlap area on the lower side of the buck sawtooth wave and the upper side of the boost sawtooth wave. In these sawtooth waves, the rising edge and the subsequent falling slope constitute the switching cycle that causes the switching element to switch based on the PWM signal, and the switching cycle repeats repeatedly in the sawtooth waves.

[0046] The width of the overlap region can be set by the designer. The wider the overlap region, the wider the range of input and output voltages for buck-boost operation. For example, it can operate stably without switching operating modes when the input and output voltages change during buck-boost operation. However, if the width of the overlap region is set too wide, the efficiency of buck-boost operation becomes lower compared to buck-only or buck-only operation, thus widening the range of input and output voltages where efficiency decreases.

[0047] The buck-side comparator 27 compares the buck reference signal output from the buck-side adder 25 with the current value detected by the current sensor A1 (hereinafter also referred to as the current detection value) to determine the pulse width of the PWM signal controlling the first switching element Q1. When the current detection value is within the range of the buck reference signal, and is lower than the buck reference signal, the buck-side comparator 27 outputs a high-level signal. If the current detection value rises and matches the buck reference signal, the buck-side comparator 27 outputs a low-level signal.

[0048] The boost-side comparator 28 compares the boost reference signal output from the boost-side adder 26 with the current detection value to determine the pulse width of the PWM signal controlling the fourth switching element Q4. If the current detection value is within the range of the boost reference signal, and is lower than the boost reference signal, the boost-side comparator 28 outputs a high-level signal. If the current detection value rises and matches the boost reference signal, the boost-side comparator 28 outputs a low-level signal.

[0049] Control logic circuit 29 outputs the PWM signal of the first switching element Q1 from buck-side comparator 27 to the first drive circuit dr1, and outputs a PWM signal with opposite phase obtained by inverting the PWM signal of the first switching element Q1 from buck-side comparator 27 to the second drive circuit dr2. Control logic circuit 29 outputs the PWM signal of the fourth switching element Q4 from boost-side comparator 28 to the fourth drive circuit dr4, and in principle, outputs a PWM signal with opposite phase to the PWM signal of the fourth switching element Q4 from boost-side comparator 28 to the third drive circuit dr3. Additionally, it can control the PWM signal output to the third drive circuit dr3 to be fixed at a low level.

[0050] The reason for adding the sawtooth wave for buck or boost converter to the error voltage output from error amplifier 21 is to suppress low-order harmonic oscillations caused by a duty cycle of 50% or more when directly comparing the current detection value and the error voltage. When the duty cycle is 50% or more, the slope during the fall of the current detection value is larger than the slope during the rise, and the amplitude of the current detection value change between cycles gradually increases, leading to oscillations. In this implementation, slope compensation is performed by applying a falling slope to the error voltage. Even with a duty cycle of 50% or more, the increase in conduction time can be suppressed, preventing oscillations.

[0051] Figure 2 , Figure 3 The circuit functional block shown can also be implemented using microcontroller-based digital control. In this case, the output voltage detected by voltage sensor V1 and the current value detected by current sensor A1 need to be converted into digital values ​​using an A / D converter.

[0052] In the peak current mode described in the implementation, the bipolarity caused by the LC filter on the output side is not generated, thus simplifying phase compensation. Especially when using digital control, the computational load can be significantly reduced compared to voltage mode. Furthermore, the peak current mode has high responsiveness to rapid changes in DC power supply 1, making it suitable for discharge control from the battery with large voltage fluctuations.

[0053] Figure 4 This is a diagram illustrating an example of a timing diagram showing the current detection value, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first to fourth switching elements, used to explain the basic operation of the H-bridge buck-boost DC / DC converter 10 according to the embodiment. Figure 5 (a)-(b) are schematic diagrams illustrating the flow of current during the boost operation. Figure 6 (a)-(b) are schematic diagrams illustrating the flow of current during the voltage reduction operation.

[0054] The buck operation of the buck-boost DC / DC converter 10 (refer to...) Figure 6 In (a)-(b)), the control unit 20 fixes the fourth switching element Q4 in the off state, and in principle, fixes the third switching element Q3 in the on state. The control unit 20 causes the first switching element Q1 and the second switching element Q2 to perform complementary operations. When the first switching element Q1 is in the on state and the second switching element Q2 is in the off state, the reactor L1 is charged from the DC power supply 1, and power is simultaneously transferred to the output side (transfer state, see reference). Figure 4 (2) Figure 6 (a) When the first switching element Q1 is in the open state and the second switching element Q2 is in the closed state, the DC power supply 1 and the reactor L1 are disconnected, and the power stored in the reactor L1 is transferred to the output side (commutation state, see reference). Figure 4 During the period (3), Figure 6 (b)

[0055] At the beginning of a switching cycle, if the current detection value is within the upper or lower range of the reference signal for step-down, the control unit 20 turns on the first switching element Q1 and turns off the second switching element Q2 to control the system in a transmission state. Subsequently, if the current detection value matches the reference signal for step-down, the control unit 20 turns off the first switching element Q1 and turns on the second switching element Q2 to control the system in a commutation state, and this continues until the end of a switching cycle.

[0056] The boost operation of the buck-boost DC / DC converter 10 (refer to...) Figure 5 In (a)-(b)), the control unit 20 fixes the first switching element Q1 in the on state and the second switching element Q2 in the off state. In principle, the control unit 20 causes the third switching element Q3 and the fourth switching element Q4 to operate complementaryly. When the fourth switching element Q4 is in the on state and the third switching element Q3 is in the off state, power transmission from the input side to the output side stops, and the reactor L1 is charged from the DC power supply 1 (accumulation state, see reference). Figure 4 During the period (1), Figure 5 (a)). When the fourth switching element Q4 is in the off state and the third switching element Q3 is in the on state, power is transferred from both the DC power supply 1 and the reactor L1 to the output side (transfer state, refer to...). Figure 4 During the period (2), Figure 5 (b)

[0057] At the beginning of a switching cycle, if the current detection value is within the range of the reference signal for boosting, the control unit 20 turns on the fourth switching element Q4 and turns off the third switching element Q3 to control the system in an accumulation state. Afterwards, if the current detection value matches the reference signal for boosting, the control unit 20 turns off the fourth switching element Q4 and turns on the third switching element Q3 to control the system in a transmission state, and this continues until the end of a switching cycle.

[0058] The buck-boost operation of the buck-boost DC / DC converter 10 (refer to...) Figure 4 In this configuration, both buck and boost operations occur simultaneously. At the beginning of a switching cycle, if the current detection value is within the range of both the buck and boost reference signals, the control unit 20 turns on the first switching element Q1 and the fourth switching element Q4, and turns off the second switching element Q2 and the third switching element Q3. Subsequently, if the current detection value matches the boost reference signal, the control unit 20 turns off the fourth switching element Q4 and turns on the third switching element Q3, continuing this process until the end of a switching cycle. If the current detection value matches the buck reference signal, the control unit 20 turns off the first switching element Q1 and turns on the second switching element Q2, continuing this process until the end of a switching cycle.

[0059] Figure 7 (a)-(b) are schematic diagrams illustrating the flow of reverse current from the output side to the input side. Figure 7 (a) illustrates a state in which reverse current is generated during the transmission state of boost operation. In boost operation, the voltage of DC power supply 1 is lower than the voltage of DC bus Bdc, so reverse current may occur if the current from DC power supply 1 to DC bus Bdc decreases.

[0060] Figure 7 (b) shows the state where reverse current is generated during the commutation state of buck operation. In buck operation, the voltage of DC power supply 1 is higher than the voltage of the DC bus Bdc, so there should be virtually no reverse current. However, a second capacitor C2 is connected to the DC bus Bdc. From the perspective of the second capacitor C2, the first switching element Q1 and the second switching element Q2 can be considered as a boost converter. In the transmission state of buck operation (with...) Figure 7 Under (a) similar circumstances, there is a concern that power flows backward from both the second capacitor C2 and the reactor L1 to the input side.

[0061] Furthermore, even if the second capacitor C2 does not store a large amount of power, there is a concern that power may flow backward from the charger or the other step-up / step-down DC / DC converter when a charger is connected to the DC bus Bdc or when another step-up / step-down DC / DC converter is connected in parallel with the step-up / step-down DC / DC converter 10.

[0062] Reverse current flowing into the battery is a major cause of battery damage and deterioration, and therefore even a short period of time (milliseconds) should be avoided. Therefore, to prevent reverse current from the DC bus Bdc to the DC power supply 1, it is recommended to always keep the third switching element Q3 in an open position.

[0063] Figure 8 This diagram illustrates an example of the timing diagram for the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first to fourth switching elements Q1, with the third switching element Q3 always fixed in the off state. By fixing the gate / source voltage of the third switching element Q3 to a low level, the third switching element Q3 is always fixed in the off state. As a result, the lower limit of the current detection value Idet is clamped to 0A, preventing reverse current from the DC bus Bdc to the DC power supply 1.

[0064] With the third switching element Q3 always fixed in the off state, during both buck and boost transmission operations, current flows from at least one of the DC power supply 1 or reactor L1 through the third diode D3 to the DC bus Bdc. If the third diode D3 is a parasitic diode of the MOSFET, a large current flowing through it will generate significant heat, potentially causing smoke / fire. Furthermore, when current flows through the third diode D3 (diode rectification), power loss is greater and conversion efficiency decreases compared to when current flows through the third switching element Q3 in the on state (synchronous rectification). The larger the current flowing through the third diode D3, the greater the power loss generated by it.

[0065] Therefore, consider the following control: under heavy load conditions, keep the third switching element Q3 in the on state to maintain synchronous rectification, and under light load conditions, turn off the third switching element Q3 to switch to diode rectification. For example, consider the following control: set a current sensor on the output side of the buck-boost DC / DC converter 10 to detect the output current of the buck-boost DC / DC converter 10, and determine that the output current is small enough to turn off the third switching element Q3.

[0066] In this control system, if the output current increases and the third switching element Q3 is turned on again, there is a concern that the power stored in the second capacitor C2 may flow backward to the input side. This reverse current is particularly prone to occur under conditions of repeated rapid changes in the load 2.

[0067] Figure 9 This is an example of a timing diagram showing the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first switching element Q1 through the fourth switching element Q4, in the case of reverse current generation during boost operation. Figure 9 In the example shown, after switching from a light load mode (diode rectification mode) where the third switching element Q3 is always off to a normal mode (synchronous rectification mode) where the third switching element Q3 becomes the complementary operation of the fourth switching element Q4, the current detection value Idet enters the negative region.

[0068] Figure 10 This is an example of a timing diagram showing the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first switching element Q1 through the fourth switching element Q4, in the case of reverse current generation during buck operation. Figure 10 In the example shown, after switching from the light load mode (diode rectification mode) where the third switching element Q3 is always off to the normal mode (synchronous rectification mode) where the third switching element Q3 is always on, the current detection value Idet enters the negative region.

[0069] Therefore, in this embodiment, the control unit 20 switches from the light load mode to the normal mode based on a given current value or higher flowing through the reactor L1.

[0070] During boost or buck-boost operations, when the current detection value Idet is less than a certain value, the control unit 20 keeps the third switching element Q3 in an open state (light load mode). When the current detection value Idet is above a certain value, the third switching element Q3 performs a complementary operation relative to the fourth switching element Q4 (normal mode). The certain value is preset to ensure backflow prevention based on the results of experiments and simulations conducted by the designer.

[0071] During the voltage reduction operation, when the current detection value Idet is less than a certain value, the control unit 20 keeps the third switching element Q3 in the off state and the fourth switching element Q4 in the off state (light load mode). When the current detection value Idet is above a certain value, the control unit 20 keeps the third switching element Q3 in the on state and the fourth switching element Q4 in the off state (normal mode).

[0072] In any of the boost, buck, or buck-boost operations, if the current detection value Idet becomes zero when the third switching element Q3 is in the on state, the control unit 20 forces the third switching element Q3 to turn off.

[0073] Figure 11 This is a diagram illustrating an example of a timing diagram of the current detection value Idet, the reference signal for buck converter, the reference signal for boost converter, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4, under the condition that the reverse current countermeasure is implemented according to the embodiment.

[0074] When the current detection value (Idet) reaches a certain value, the light load mode is deactivated and the system switches to normal mode, thereby preventing reverse current from the output side. In normal mode, synchronous rectification is activated, which improves conversion efficiency while suppressing heat generation.

[0075] Furthermore, in peak current mode, the current flowing from DC power supply 1 to reactor L1 is constantly monitored, eliminating the need for a new current sensor to prevent reverse current flow. Therefore, no additional hardware cost is incurred. In contrast, in voltage mode, a new current sensor is required, resulting in additional hardware cost.

[0076] As described above, in the buck-boost DC / DC converter 10, offsets are set for the reference signals used for boosting and bucking, and a certain overlap area is established, thereby enabling smooth switching between boost and buck operations. In the buck-boost DC / DC converter 10, due to hardware factors, the current detection value Idet may sometimes be delayed relative to the reference signals used for boosting and bucking. This delay sometimes occurs, especially in digital control systems such as A / D converters in current sensing systems. During buck operation, under heavy loads and when the current detection value Idet is delayed relative to the reference signal, an unintentional temporary switch from buck to buck operation may sometimes occur.

[0077] Figure 12 This is an example of a timing diagram showing the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4, under light load conditions during buck conversion without delay. Figure 13 This is an example of a timing diagram showing the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4, under heavy load conditions during buck conversion without delay.

[0078] Figure 14This is an example of a timing diagram showing the current detection value Idet, the reference signal for bucking, the reference signal for boosting, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4 when the current detection value Idet is delayed under light load during buck operation. Figure 15 This is an example of a timing diagram showing the current detection value Idet, the reference signal for bucking, the reference signal for boosting, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4 when the current detection value Idet is delayed under heavy load during buck operation.

[0079] like Figure 13 As shown, when the current detection value Idet is not delayed, even under heavy load, the current rises as a whole while maintaining the relative relationship between the current detection value Idet, the reference signal for buck conversion, and the reference signal for boost conversion; therefore, the boost operation is not initiated. In contrast, as... Figure 15 As shown, if the load becomes heavy when the current detection value (Idet) is delayed, the current detection value (Idet) will not rise at the beginning of a switching cycle even if the reference signals for both the buck and boost voltages rise. Therefore, the current detection value (Idet) falls within the range of the boost voltage reference signal, and the boost operation is initiated. Subsequently, if the current detection value (Idet) is higher than the boost voltage reference signal, the boost operation transitions from the accumulation state to the transmission state. However, the boost operation at the beginning of this switching cycle is a useless switch, resulting in losses.

[0080] Therefore, in the buck operation, a blanking time is set for the boost operation for a given period starting from the beginning of a switching cycle. At the beginning of a switching cycle, if the lower side of the upper and lower ranges of the buck reference signal is below zero and the upper side of the upper and lower ranges of the boost reference signal is above zero, the control unit 20 keeps the fourth switching element Q4 in the off state for a given period starting from the beginning of a switching cycle to disable the boost operation.

[0081] Figure 16 This is a diagram illustrating a first example of a timing diagram of the current detection value Idet, the reference signal for buck conversion, the reference signal for boost conversion, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4 when the upper side of the upper and lower ranges of the reference signal for boost conversion is zero or higher during buck conversion. In this first example, at the beginning of a switching cycle, when the lower side of the upper and lower ranges of the reference signal for buck conversion is zero or lower and the upper side of the upper and lower ranges of the reference signal for boost conversion is zero or higher, the control unit 20 maintains the fourth switching element Q4 in an off state for the delay time spent detecting the current flowing through the reactor L1, i.e., the given period, from the beginning of a switching cycle.

[0082] Hereinafter, this delay time will be referred to as the first masking period M1. The designer pre-determines the delay time of the current detection system through experiments and simulations, and sets it as the first masking period M1. In the case of implementing buck-boost control through hardware control, in... Figure 3 In the control logic circuit 29 shown, an additional gate element is added. This gate element fixes the PWM signal of the fourth switching element Q4 to a low level and the PWM signal of the third switching element Q3 to a high level during the first masking period M1. In the case of implementing buck-boost control through digital control, the comparison process between the PWM signal of the fourth switching element Q4 and the current detection value Idet is stopped during the first masking period M1.

[0083] Figure 17 This is a second example of a timing diagram showing the current detection value Idet, the buck reference signal, the boost reference signal, and the gate / source voltages of the first switching element Q1 to the fourth switching element Q4 when the upper side of the upper and lower ranges of the boost reference signal is above zero during buck operation. In this second example, at the beginning of a switching cycle, when the lower side of the upper and lower ranges of the buck reference signal is below zero and the upper side of the upper and lower ranges of the boost reference signal is above zero, the control unit 20 keeps the fourth switching element Q4 in the off state from the beginning of a switching cycle until the upper side of the upper and lower ranges of the boost reference signal is below zero.

[0084] The period from the beginning of a switching cycle until the upper limit of the upper and lower limits of the reference signal used for boosting falls below zero will be referred to as the second masking period M2. The second masking period M2 is a variable value.

[0085] In this way, during buck operation, at the beginning of a switching cycle, if the upper limit of the reference signal used for boost is above zero, the boost operation is disabled for a given period. This prevents unintentional switching from buck to buck-boost operation at the beginning of a switching cycle. Consequently, unwanted losses during buck operation can be prevented.

[0086] When using the first shielding period M1, the shielding period can be set to the minimum. When using the second shielding period M2, the boost operation can be disabled until the reference signal for boosting is below zero, thus more reliably preventing switching to boost / buck operation.

[0087] The present disclosure has been described above based on the embodiments. The embodiments are illustrative, and those skilled in the art will understand that various modifications can be made to the combination of their constituent elements and processing procedures, and such modifications are also within the scope of the present disclosure.

[0088] Figure 18 This is a diagram illustrating a structural example of a buck-boost DC / DC converter according to a modified example. Without performing bidirectional operation, the second switching element Q2 can be replaced with a second diode D2 as a passive element, and the third switching element Q3 can be replaced with a third diode D3 as a passive element.

[0089] In the above embodiment, an example of CV discharge from a battery is envisioned. That is, error amplifier 21 amplifies the difference between the output voltage detected by voltage sensor V1 and the reference voltage to generate an error signal for generating a reference signal. In this regard, in the case of CC discharge from a battery, a current sensor is provided on the output side of the buck-boost DC / DC converter 10. Error amplifier 21 amplifies the difference between the detected value of the output current detected by this current sensor and the reference voltage corresponding to the target current, and generates an error signal corresponding to this difference for generating a reference signal. Subsequent processing is the same as in the CV discharge case.

[0090] Alternatively, the implementation method can also be determined by the following items.

[0091] [Project 1]

[0092] A DC / DC converter (10), wherein:

[0093] The first arm includes a first switching element (Q1), a second switching element (Q2), and a second rectifier element (D2). The first switching element (Q1) and one of the second switching element (Q2) and the second rectifier element (D2) are connected in series at a first connection point (N1). The first arm is connected in parallel with respect to the DC power supply (1).

[0094] The second arm includes one of a third switching element (Q3) and a third rectifier element (D3), and a fourth switching element (Q4), wherein the third switching element (Q3) and the third rectifier element (D3) are connected in series with the fourth switching element (Q4) at a second connection point (N2), and the second arm is connected in parallel with respect to the DC bus (Bdc).

[0095] The reactor (L1) is connected to the first connection point (N1) of the first arm and the second connection point (N2) of the second arm; and

[0096] The control unit (20) controls the first switching element (Q1), the second switching element (Q2), the third switching element (Q3) and the fourth switching element (Q4), or controls the first switching element (Q1) and the fourth switching element (Q4).

[0097] The control unit (20) performs the following processing:

[0098] A sawtooth-shaped reference signal for boosting is generated by applying slope compensation to the error signal between the output voltage or output current of the DC bus (Bdc) and the reference value.

[0099] The sawtooth wave used for bucking the voltage is added to the error signal to generate a sawtooth wave-shaped reference signal for bucking the voltage. The sawtooth wave used for bucking the voltage is obtained by shifting the reference signal used for boosting the voltage upward, and the lower side of the sawtooth wave used for boosting the voltage has a certain overlap with the upper side of the sawtooth wave used for boosting the voltage.

[0100] At the beginning of a switching cycle, if the current detection value obtained by detecting the current flowing through the reactor (L1) is within the upper and lower range of the reference signal for step-down, the first switching element (Q1) is turned on. Then, if the current detection value matches the reference signal for step-down, the first switching element (Q1) is turned off.

[0101] At the beginning of a switching cycle, if the current detection value is within the range of the reference signal for boosting, the fourth switching element (Q4) is turned on. Then, if the current detection value matches the reference signal for boosting, the fourth switching element (Q4) is turned off.

[0102] At the beginning of a switching cycle, if the lower side of the upper and lower ranges of the reference signal for bucking is below zero and the upper side of the upper and lower ranges of the reference signal for boosting is above zero, the fourth switching element (Q4) is maintained in the off state for a given period from the beginning of a switching cycle.

[0103] Therefore, it is possible to prevent switching from buck to buck-boost operation at the beginning of a switching cycle, and to prevent unwanted losses during buck operation.

[0104] [Project 2]

[0105] According to the DC / DC converter (10) described in Project 1, where,

[0106] At the beginning of a switching cycle, if the lower side of the upper and lower range of the reference signal for step-down is below zero and the upper side of the upper and lower range of the reference signal for step-up is above zero, the control unit (20) maintains the fourth switching element (Q4) in the off state during the delay time spent detecting the current flowing through the reactor (L1) from the beginning of a switching cycle.

[0107] Therefore, the period of ineffective boosting can be minimized.

[0108] [Project 3]

[0109] According to the DC / DC converter (10) described in Project 1, where,

[0110] At the beginning of a switching cycle, if the lower side of the upper and lower range of the reference signal for bucking is below zero and the upper side of the upper and lower range of the reference signal for boosting is above zero, the control unit (20) maintains the fourth switching element (Q4) in the off state from the beginning of a switching cycle until the upper side of the upper and lower range of the reference signal for boosting is below zero.

[0111] This allows for more reliable prevention of switching to boost / buck operation.

[0112] [Project 4]

[0113] According to any one of items 1 to 3, the DC / DC converter (10) described therein,

[0114] The control unit (20) sets the amplitude of the sawtooth wave of the reference signal for boosting voltage and the amplitude of the sawtooth wave of the reference signal for bucking voltage to different values.

[0115] Therefore, the width of the overlapping area can be adjusted arbitrarily.

[0116] Explanation of reference numerals in the attached figures

[0117] 1 DC power supply

[0118] 2. Load

[0119] 10. Buck-Boost DC / DC Converter

[0120] 20 Control Department

[0121] 21 Error Amplifier

[0122] 22 Boost-side comparator

[0123] 23. Buck-side comparator

[0124] 24 Control Logic Circuit

[0125] 25 Step-down side adder

[0126] 26. Boost-side adder

[0127] 27. Buck-side comparator

[0128] 28. Boost-side comparator

[0129] 29 Control Logic Circuit

[0130] Bdc DC bus

[0131] L1 reactor

[0132] Q1-Q4 switching elements

[0133] Diodes D1-D4

[0134] C1-C2 capacitors

[0135] dr1-dr4 drive circuit

[0136] A1 Current Sensor

[0137] V1 Voltage sensor.

Claims

1. A DC / DC converter, comprising: The first arm includes one of a first switching element, a second switching element, and a second rectifier element, wherein the first switching element and the second switching element and the second rectifier element are connected in series at a first connection point, and the first arm is connected in parallel with respect to the DC power supply. The second arm includes one of a third switching element and a third rectifier element, and a fourth switching element, wherein the third switching element and the third rectifier element are connected in series with the fourth switching element at a second connection point, and the second arm is connected in parallel with respect to the DC bus. A reactor is connected to the first connection point of the first arm and the second connection point of the second arm; The control unit controls the first switching element, the second switching element, the third switching element, and the fourth switching element, or controls the first switching element and the fourth switching element. The control unit performs the following processing: A sawtooth-shaped reference signal for boosting is obtained by applying slope compensation to the error signal corresponding to the difference between the output voltage or output current to the DC bus and the reference value. The sawtooth wave used for bucking the voltage is added to the error signal to generate a sawtooth wave-shaped reference signal for bucking the voltage. The sawtooth wave used for bucking the voltage is obtained by shifting the reference signal used for boosting the voltage upward, and the lower side of the sawtooth wave used for boosting the voltage has a certain overlap with the upper side of the sawtooth wave used for boosting the voltage. At the beginning of a switching cycle, if the current detection value obtained by detecting the current flowing through the reactor is within the upper and lower range of the reference signal for step-down, the first switching element is turned on. Then, if the current detection value matches the reference signal for step-down, the first switching element is turned off. At the beginning of a switching cycle, if the current detection value is within the range of the reference signal for boosting, the fourth switching element is turned on. Then, if the current detection value matches the reference signal for boosting, the fourth switching element is turned off. At the beginning of a switching cycle, if the lower side of the upper and lower ranges of the reference signal for buck conversion is below zero and the upper side of the upper and lower ranges of the reference signal for boost conversion is above zero, the fourth switching element is kept in the off state for a given period from the beginning of a switching cycle.

2. The DC / DC converter according to claim 1, wherein, At the beginning of a switching cycle, if the lower side of the upper and lower ranges of the reference signal for step-down is below zero and the upper side of the upper and lower ranges of the reference signal for step-up is above zero, the control unit maintains the fourth switching element in the off state for the delay time spent detecting the current flowing through the reactor from the beginning of a switching cycle.

3. The DC / DC converter according to claim 1, wherein, At the beginning of a switching cycle, if the lower side of the upper and lower ranges of the reference signal for bucking is below zero and the upper side of the upper and lower ranges of the reference signal for boosting is above zero, the control unit maintains the fourth switching element in the off state from the beginning of a switching cycle until the upper side of the upper and lower ranges of the reference signal for boosting is below zero.

4. The DC / DC converter according to any one of claims 1 to 3, wherein, The control unit sets the amplitude of the sawtooth wave of the reference signal used for boosting and the amplitude of the sawtooth wave of the reference signal used for bucking to different values.

Images