3D cell and array structure

Abstract

Various 3D cells, array structures, and processes are disclosed. In an embodiment, a memory cell array structure is provided. The memory cell array structure includes memory cells organized into a plurality of rows and a plurality of columns, input lines in which each input line is connected to a memory cell in a selected row, and the input lines form an input line group, and output lines in which each output line is connected to a memory cell in a selected column, and the output lines form an output line group. The array structure further includes a multiplexer having a multiplexer input and a multiplexer output such that the multiplexer input is connected to the set of output lines, and a neuron circuit connected to the multiplexer output, the array of memory cells simulating a neural network, wherein the input line simulates an input layer neuron of the neural network, and the output line simulates an output layer neuron of the neural network.

Description

[0001] Cross Reference to Related Applications

[0002] This application is a continuation-in-part (CIP) of U.S. Patent Application No. 18 / 424,700, filed January 26, 2024, and titled “3D Cell and Array Structures.”

[0003] This application claims priority under 35 U.S.C 119(e) to the following U.S. Provisional Patent Applications, all of which are incorporated by reference in their entirety:

[0004] Application No. Filing Date

[0005] 63 / 470,987 2023-06-05

[0006] 63 / 612,982 2023-12-20

[0007] 63 / 620,856 2024-01-14

[0008] 63 / 624,306 2024-01-24

[0009] 63 / 572,288 2024-03-31

[0010] 63 / 633,737 2024-04-13

[0011] 63 / 636,755 2024-04-20

[0012] 63 / 638,416 2024-04-25

[0013] 63 / 639,904 2024-04-29

[0014] 63 / 642,798 2024-05-05

[0015] 63 / 643,920 2024-05-08

[0016] 63 / 644,262 2024-05-08

[0017] 63 / 644,391 2024-05-08

[0018] 63 / 645,713 2024-05-10

[0019] This application 18 / 424,700 claims priority under 35 U.S.C 119 (e) to U.S. Provisional Patent Application No. 63 / 444,928, filed February 11, 2023, and titled “3D Cell and Array Structures,” U.S. Provisional Patent Application No. 63 / 445,299, filed February 14, 2023, and titled “3D Cell and Array Structures,” U.S. Provisional Patent Application No. 63 / 446,101, filed February 16, 2023, and titled “3D Cell and Array Structures,” U.S. Provisional Patent Application No. 63 / 446,570, filed February 17, 2023, and titled “3D Cell and Array Structures,” and U.S. Provisional Patent Application No. 63 / 447,875, filed February 23, 2023, and titled “3D Cell and Array Structures,” which are incorporated by reference in their entireties. TECHNICAL FIELD

[0020] Exemplary embodiments of the present invention relate generally to the field of memory, and more particularly to memory cell and array structures and associated processes. BACKGROUND

[0021] As the complexity and density of electronic circuits increase, the size, complexity, and cost of memory are important considerations. One method of increasing memory capacity is to use three-dimensional (3D) array structures. 3D array structures have been successfully used today for NAND flash memory. However, for dynamic random access memory (DRAM), cost-effective 3D array structures have not been realized due to its special one-transistor-one-capacitor (1T1C) cell structure. SUMMARY

[0022] In various exemplary embodiments, three-dimensional (3D) cells, array structures, and associated processes are disclosed. Embodiments of the invention are applicable to a variety of technologies. For example, embodiments of the invention can be applied to dynamic random access memory (DRAM), floating body cell (FBC) memory, NOR-type flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), memristor transistors (memristor transistors), and split-gate NOR flash. Embodiments of the invention can also be used in applications such as in-memory computing (IMC) and artificial neural networks (ANNs), and any other suitable applications not listed.

[0023] In an exemplary embodiment, a three-dimensional (3D) array structure is provided that includes an array of NOR-type memory cells that includes one or more rows of memory cells, and each memory cell is configured to store data that controls a cell current of the memory cell. The structure further includes bit lines connected to the one or more rows of memory cells, and each bit line is connected to one memory cell in each of the one or more rows of memory cells. The structure further includes one or more source lines connected to the one or more rows of memory cells, respectively, and each source line is connected to all memory cells of a corresponding row of memory cells. The structure is configured such that an input signal applied to a bit line causes one or more cell currents to flow through one or more memory cells, respectively, and in each row of memory cells, selected cell currents combine to form a row cell current that flows on a source line connected to the row of memory cells.

[0024] In an exemplary embodiment, a three-dimensional (3D) array structure is provided that includes an array of NOR-type memory cells that includes one or more rows of memory cells, and each memory cell is configured to store data that controls a cell current of the memory cell. The structure further includes bit lines connected to the one or more rows of memory cells, and each bit line is connected to one memory cell in each of the one or more rows of memory cells. The structure further includes one or more source lines connected to the one or more rows of memory cells, respectively, and each source line is connected to all memory cells of a corresponding row of memory cells. The structure is configured such that an input signal applied to a bit line causes one or more cell currents to flow through one or more memory cells, respectively, and in each row of memory cells, selected cell currents combine to form a row cell current that flows on a source line connected to the row of memory cells.

[0025] In an example embodiment, a three-dimensional (3D) array structure is provided that includes a NOR-type array of memory cells that includes one or more rows of memory cells and each memory cell is configured to store data that controls a cell current of the memory cell. The structure further includes bit lines connected to the one or more rows of memory cells and each bit line is connected to one memory cell in each of the one or more rows of memory cells. The structure further includes one or more word lines connected to the one or more rows of memory cells, respectively, and each word line is connected to all memory cells of a corresponding row of memory cells. The structure is configured such that an input signal applied to a word line causes one or more cell currents to flow through one or more memory cells, respectively, and for each bit line, a selected combination of cell currents forms a bit line cell current that flows on the bit line.

[0026] In an embodiment, a memory cell array structure is provided that includes memory cells organized into a plurality of rows and a plurality of columns, a plurality of input lines, where each input line is connected to a memory cell in a selected row and the input lines form an input line group, and a plurality of output lines, where each output line is connected to a memory cell in a selected column and the output lines form an output line group. The array structure further includes a multiplexer having a multiplexer input and a multiplexer output, such that the multiplexer input is connected to the output line group, and a neuron circuit connected to the multiplexer output, the memory cell array emulating a neural network, where the plurality of input lines emulate input layer neurons of the neural network and the plurality of output lines emulate output layer neurons of the neural network.

[0027] In an embodiment, a 3D cell structure is provided that includes a plurality of blocks and a plurality of data buffers, where each block includes an input buffer, an array, and a neuron circuit, and where each neuron circuit outputs an output data group, the plurality of data buffers having a buffer input and a buffer output, where the plurality of buffer inputs are configured to receive the output data groups from the plurality of neuron circuits, respectively. The cell structure further includes a plurality of activation circuits having a circuit input and a circuit output, where the plurality of circuit inputs are connected to the plurality of buffer outputs, respectively, and the plurality of circuit outputs are configured to output an activation result, and the 3D cell structure emulates a neural network, where the plurality of input buffers emulate an input neuron group of the neural network, the plurality of data buffers emulate an output neuron group of the neural network, and the plurality of activation circuits emulate an activation function of the neural network.

[0028] Additional features and advantages of the example embodiments of the present application will be apparent from the detailed description, the drawings, and the claims set forth below. BRIEF DESCRIPTION OF DRAWINGS

[0029] The exemplary embodiments of this application will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1A An embodiment of a three-dimensional (3D) cell structure according to the present application is shown.

[0031] Figure 1B An embodiment of a cell structure is shown. Figure 1A The 3D cell structure shown, with the front gate and gate dielectric removed.

[0032] Figure 1C An embodiment of a cell structure similar to that shown. Figure 1A An embodiment of a cell structure similar to that shown.

[0033] Figure 1D An embodiment of a cell structure similar to that shown. Figure 1A An embodiment of a cell structure similar to that shown.

[0034] Figure 1E An embodiment of a cell structure is shown, where the floating body is thicker and more lightly doped than in previous embodiments.

[0035] Figure 1F An embodiment of a cell structure is shown, where the floating body is thinner and more heavily doped than in previous embodiments.

[0036] Figures 1G-1P An embodiment of a cell structure according to the present application is shown.

[0037] Figure 2A An embodiment of a memristor-transistor cell structure according to the present application is shown.

[0038] Figure 2B An embodiment of a cell structure according to the present application is shown.

[0039] Figures 2C-2E An example of the switching characteristics of a four-terminal memristor-transistor is shown.

[0040] Figure 2F A table illustrating some exemplary materials for embodiments of a memristor-transistor cell according to the present application is shown.

[0041] Figures 3A-7B An embodiment of a cell structure according to the present application is shown.

[0042] Figures 8A-8E An embodiment of a 3D array structure according to the present application is shown.

[0043] Figures 9A-9C An embodiment of a 3D array structure according to the present application is shown.

[0044] Figures 10A-10B An embodiment of an equivalent circuit of a 3D NOR-type array architecture according to the present application is shown.

[0045] Figures 11A-11B An embodiment of a 3D array structure according to the present application is shown.

[0046] Figure 12A An embodiment of a 3D array structure according to the present application Figure 3A An embodiment of a cell structure for a NOR-type flash memory is shown.

[0047] Figure 12B A symbolic representation of a NOR-type flash memory cell is shown.

[0048] Figures 12C-12E An embodiment of a preferred program and erase operation according to the present application is shown.

[0049] Figure 13A An exemplary architecture for a neural network is shown.

[0050] Figure 13B A layer of a neural network including input neurons and output neurons is shown.

[0051] Figures 13C-13D An embodiment of a neural network is shown demonstrating Figure 13C How a 3D cell array emulates Figure 13D An embodiment of a neural network is shown.

[0052] Figure 14A An embodiment of a neural network array formed using Figure 10A A 3D array structure is shown.

[0053] Figure 14B An embodiment of a neural network array using Figure 10B A 3D array structure is shown.

[0054] Figure 15A An embodiment of a neural network array providing "negative" weights for synapses of a neural network is shown.

[0055] Figure 15B An embodiment of a neural network array providing "negative" weights for synapses of a neural network is shown.

[0056] Figure 15C An embodiment of a neural network array providing "negative" weights for synapses of a neural network is shown.

[0057] Figures 16A-16D An embodiment of an output circuit for an in-memory compute or for forming an output neuron circuit of a neural network is shown.

[0058] Figures 17A-17B An embodiment of an output circuit performing a simulation matching function for a memory computing application is shown.

[0059] Figure 18A An embodiment of a 3D array for a memory computing or neural network application according to the invention is shown.

[0060] Figure 18B An element is shown in which the signal flow is indicated by arrows.

[0061] Figure 19A An embodiment of an array architecture according to the invention is shown.

[0062] Figure 19B An embodiment of an array architecture according to the invention is shown.

[0063] Figure 20A A signal flow of an embodiment of an array architecture according to the invention is shown.

[0064] Figure 20B An embodiment of an array architecture is shown in which the signal flow is reversed.

[0065] Figure 20C An embodiment of an array architecture according to the invention is shown.

[0066] Figure 20D An embodiment of an array architecture according to the invention is shown.

[0067] Figures 21A-12C An embodiment of an architecture of a neural network chip or a memory computing chip according to the invention is shown.

[0068] Figure 22 An embodiment of a 3D array element for a memory computing or neural network application according to the invention is shown.

[0069] Figure 23 An embodiment of a 3D array element for a memory computing or neural network according to the invention is shown.

[0070] Figures 24A-24C An embodiment of a structure of a neural network chip according to the invention is shown.

[0071] Figure 25A An embodiment of a 3D array structure element of the element shown is shown. Figure 18B An embodiment of a 3D array structure element of the element shown is shown.

[0072] Figure 25B An embodiment of a connection of bit lines, word line layers and source line layers of the 3D array structure element shown is shown. Figure 25A An embodiment of a connection of bit lines, word line layers and source line layers of the 3D array structure element shown is shown.

[0073] Figure 25CAn embodiment of a 3D array structure is shown. Figure 25A An embodiment of the connections of the bitline, wordline, and source line layers of the 3D array structure element is shown.

[0074] Figures 26A-26D An embodiment of a 3D array cell structure and equivalent circuit according to the present invention is shown.

[0075] Figure 27 An embodiment of a neural network array using the 3D cell structure is shown. Figures 26A-26D An embodiment of a neural network array using the 3D cell structure is shown.

[0076] Figure 28A An embodiment of a 3D array structure for in-memory computing or neural network applications according to the present invention is shown.

[0077] Figure 28B An embodiment of a 3D array structure is shown that illustrates how to divide the select gate lines into two groups.

[0078] Figures 28C-28D An embodiment of a 3D array implementing negative weights according to the present invention is shown.

[0079] Figure 29A An embodiment of a 3D array structure based on the circuit embodiment is shown. Figures 28A-28D An embodiment of a 3D array structure based on the circuit embodiment is shown.

[0080] Figure 29B Another embodiment of a 3D array structure according to the present invention is shown.

[0081] Figure 30A An embodiment of a 3D array structure according to the present invention is shown.

[0082] Figure 30B An embodiment of how to connect the wordline and source line layers to the circuitry located below the 3D array to reduce the die size is shown.

[0083] Figure 31 An embodiment of a 3D memory chip, 3D in-memory computing chip, or 3D artificial intelligence (AI) chip according to the present invention is shown.

[0084] Figure 32A An embodiment of an I-V (current-voltage) curve associated with a digital neural network is shown.

[0085] Figure 32B An embodiment of an I-V curve associated with an analog neural network is shown.

[0086] Figure 32C An embodiment of an I-V curve associated with an analog neural network is shown.

[0087] Figure 32DEmbodiments of an analog neural network using memory cells that store only two Vt levels are shown.

[0088] Figures 33A-33D Embodiments of an output neuron circuit are shown.

[0089] Figures 34A-34B Embodiments of an analog neural network using memory cells that have only two Vt levels are shown.

[0090] Figure 34C Embodiments according to the present invention are shown.

[0091] Figure 34D Another embodiment according to the present invention is shown.

[0092] Figure 35 Embodiments of a neural network architecture according to the present invention are shown.

[0093] Figure 36A Embodiments of a neural network architecture according to the present invention are shown. Figure 35 Detailed embodiments of a storage array, input neuron circuit, and output neuron circuit are shown.

[0094] Figure 36B Embodiments of a storage array implemented using exemplary memory cell technology are shown.

[0095] Figure 37A Detailed embodiments of a storage array, input neuron circuit, and output neuron circuit are shown. Figure 35 Detailed embodiments of a storage array, input neuron circuit, and output neuron circuit are shown.

[0096] Figure 37B Embodiments of a storage array implemented using exemplary memory cell technology are shown.

[0097] Figure 37C Embodiments of a storage array, input neuron circuit, and output neuron circuit are shown.

[0098] Figure 37D Embodiments of a storage array, input neuron circuit, and output neuron circuit are shown.

[0099] Figures 38A-38D Embodiments of a layout arrangement of a storage array and neuron circuit according to the present invention are shown.

[0100] Figure 39A Embodiments of a layout arrangement of a 3D storage array and neuron circuit of the architecture shown are shown. Figure 38B

[0101] Embodiments of a layout arrangement of a 3D storage array and neuron circuit of the architecture shown are shown. Figure 39B Figure 39A A layout arrangement of a neuron circuit is shown.

[0102] ​Figure 39C The connection between the neuronal circuit and the 3D storage array according to the present invention is shown.

[0103] Figures 40A-40D A storage array comprising multiple blocks is shown.

[0104] Figure 41 An embodiment of the present invention is shown, which is used to solve the above-mentioned mismatch problem.

[0105] Figure 42 An embodiment of the layout and neuron circuit connection according to the present invention is shown.

[0106] Figures 43A-43E An embodiment of the storage array and neuron circuit architecture according to the present invention is shown.

[0107] Figure 44A An embodiment of the circuit architecture according to the present invention is shown, which is configured to convert cell current into digital data.

[0108] Figure 44B An embodiment of the circuit implementation according to the present invention is shown for converting four sets of output data into eight-bit data.

[0109] Figure 44C The arrangement of shift register data is shown.

[0110] Figure 45A An embodiment according to the present invention is shown.

[0111] Figures 45B-45C An exemplary operation of the neural network according to the present invention is shown.

[0112] Figure 45D This demonstrates how to add data to a neural network to produce the final output.

[0113] Figure 46A An exemplary current distribution for the sum (cumulative) of multiple cells is shown.

[0114] Figure 46B The relationship between the change in unit current and the number of working units is shown.

[0115] Figure 47A An embodiment of the network according to the present invention is shown, which solves the cell summation fault.

[0116] Figure 47B It shows the result of Figure 47A The embodiment shown simulates an equivalent neural network architecture.

[0117] Figure 48A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown.

[0118] Figure 48B An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown.

[0119] Figure 49A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown.

[0120] Figure 49B An example of a timing diagram is shown, which illustrates... Figure 49A The operating waveform of the embodiment shown.

[0121] Figure 50A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown.

[0122] Figure 50B An embodiment of a timing diagram is shown, which illustrates... Figure 50A The operating waveforms of the architecture shown.

[0123] Figure 50C An embodiment of a timing diagram is shown, which illustrates... Figure 50A The operating waveforms of the architecture shown.

[0124] Figures 51A-51C An embodiment of the operating waveforms according to the architecture of the present invention is shown.

[0125] Figures 52A-52B An embodiment of a planar layout of a chip according to the present invention is shown.

[0126] Figure 53A An embodiment of a circuit architecture for converting unit current into digital data according to the present invention is shown.

[0127] Figure 53B An embodiment of a circuit architecture for converting unit current into digital data according to the present invention is shown.

[0128] Figures 54A-54B An exemplary neuron circuit according to the present invention is shown.

[0129] Figure 55 An example of an array representing blocks is shown.

[0130] Figure 56A An embodiment of the array architecture according to the present invention is shown.

[0131] Figure 56B It shows the result of Figure 56A The embodiments shown simulate the corresponding neural network layers.

[0132] Figure 57A An embodiment of the array architecture according to the present invention is shown.

[0133] Figure 57B It shows the result of Figure 57A The embodiments shown simulate the corresponding neural network layers.

[0134] Figure 58A An embodiment of the array architecture according to the present invention is shown.

[0135] Figure 58B An embodiment of the array architecture according to the present invention is shown.

[0136] Figure 59A A detailed embodiment of the block architecture according to the present invention is shown.

[0137] Figure 59B It shows Figure 59A An example of the operating waveforms of the array architecture shown.

[0138] Figure 60A A detailed embodiment of the block architecture according to the present invention is shown.

[0139] Figure 60B It shows Figure 59B An example of the operating waveforms of the array architecture shown.

[0140] Figure 61A An embodiment of an artificial intelligence (AI) chip or AI system architecture according to the present invention is shown.

[0141] Figure 61B An embodiment of an artificial intelligence (AI) chip or AI system architecture according to the present invention is shown.

[0142] Figure 62 Several blocks of a circuit simulating a summation function of multiple output neurons are shown. Detailed Implementation

[0143] Those skilled in the art will recognize that the following detailed description is merely illustrative and not intended to be limiting in any way. Other embodiments of the invention will readily emerge for those who benefit from this disclosure. Implementations of exemplary embodiments of the invention will now be described in detail with reference to the accompanying drawings. Throughout the drawings and the following detailed description, the same reference numerals or numbers will be used to refer to the same or similar parts.

[0144] In various exemplary embodiments, three-dimensional (3D) cells, array structures, and associated processes are disclosed. Embodiments of the invention are applicable to a variety of technologies. For example, embodiments of the invention can be applied to dynamic random access memory (DRAM), floating cell (FBC) memory, NOR flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), memristor transistors (memristor transistors), and split-gate NOR flash memory. Embodiments of the invention can also be used for applications such as in-memory computing (IMC) and artificial neural networks (ANN), as well as any other suitable applications not listed.

[0145] Figure 1A An embodiment of a three-dimensional (3D) cell structure according to the present invention is shown. In various embodiments, this cell structure is suitable for use as a storage cell or synaptic device (also referred to as a synaptic transistor) in neural network applications. The cell structure includes a bit line (BL) 101 comprising a semiconductor material, such as silicon or polysilicon. The cell structure also includes a float 102 comprising a semiconductor material, such as silicon, polysilicon, silicon germanium (SiGe), indium gallium zinc oxide (IGZO), or any other suitable semiconductor material. The cell structure also includes a source line (SL) (or layer) 103 comprising a semiconductor material (e.g., silicon or polysilicon). The cell structure forms a dual-gate transistor comprising a front gate (FG) 104a and a back gate (BG) 104b. The front gate 104a and the back gate 104b are formed of a conductive material (e.g., metal or polysilicon). In one application, the front gate 104a and the back gate 104b may be connected to a word line (WL) not shown.

[0146] The cell structure also includes gate dielectric layers (GDLs) 105a and 105b, which can be formed from a variety of suitable materials. In various embodiments, each of the gate dielectric layers 105a and 105b is formed as a single layer or a multilayer structure. In one embodiment, the gate dielectric layers 105a and 105b comprise a thin oxide (SiO2) layer or a high-k material, such as a hafnium oxide (HfO2) layer, to form a floating cell, also known as a capacitorless dynamic random access memory (DRAM) cell.

[0147] Figure 1B It shows Figure 1AThe 3D cell structure shown has the front gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell. In one embodiment, the float 102 is formed in a donut shape as shown. Although this embodiment shows the bit line 101 and float 102 as circular, the bit line 101 and float 102 can also be formed in other patterns or shapes, such as squares, rectangles, triangles, hexagons, etc. These variations are all within the scope of this invention.

[0148] In various embodiments, bit line 101, float 102, and source line 103 are formed from various materials to form different types of cells. For example, in one embodiment, bit line 101 and source line 103 are formed from N+ type semiconductor material, while float 102 is formed from P- type semiconductor material. This configuration forms an N-channel junction transistor. In another embodiment, bit line 101 and source line 103 are formed from P+ type semiconductor material, while float 102 is formed from N- type semiconductor material. This configuration forms a P-channel transistor.

[0149] In another embodiment, bit line 101 and source line 103 are formed of N+ type semiconductor material, while float 102 is formed of N+ or N- type semiconductor material. This configuration forms an N-channel junctionless transistor. In another embodiment, bit line 101 and source line 103 are formed of P+ type semiconductor material, while float 102 is formed of P+ or P- type semiconductor material. This configuration forms a P-channel junctionless transistor.

[0150] In another embodiment, bit line 101 is formed of N+ type semiconductor material, and source line 103 is formed of P+ type semiconductor material. Float 102 is formed of intrinsic or lightly doped P-type or N-type semiconductor material. This configuration forms a tunnel field-effect transistor (T-FET).

[0151] In another embodiment, bit line 101 and source line 103 are formed of metal, while float 102 is formed of P-type or N-type semiconductor material. This configuration forms a tunnel Schottky junction transistor.

[0152] According to the present invention, the float 102 can have any suitable thickness. Depending on the thickness of the float 102, the unit forms different types of channels, such as... Figures 1E-1F As shown.

[0153] Figure 1C It shows the relationship with Figure 1AThe cell structure shown is similar to the cell structure shown, except that the gate dielectric layers 105a and 105b are formed by charge trapping layers. In one embodiment, the charge trapping layer comprises an oxide-nitride-oxide (ONO) layer. Layer 150a is a tunnel oxide layer, which is thin enough to allow electrons to tunnel through when a high electric field is applied. Layer 150b is a nitride layer that traps electrons for data storage, while layer 150c is a barrier oxide, which is thick enough to prevent electrons from tunneling through to the gates 104a and 104b. Figure 1C The cell structure shown forms a non-volatile memory cell, such as a NOR flash memory cell.

[0154] In another embodiment, Figure 1C The tunnel oxide layer 150a shown is eliminated. Therefore, the charge trapping layers 105a and 105b will consist only of the nitride layer 150b and the barrier oxide layer 150c. This embodiment reduces the voltage required for the programming and erasing units.

[0155] Figure 1D It shows the relationship with Figure 1A The unit structure shown is similar to the unit structure except that the gate dielectric layers 105a and 105b are formed by at least one ferroelectric layer 151a and one dielectric layer 151b (or interface layer). The ferroelectric layer 151a includes materials such as lead zirconate titanate (PZT), fluorite structure oxides (such as hafnium oxide (HfO2) and zirconium oxide (ZrO2)), orthorhombic hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO2), while the dielectric layer 151b includes materials such as SiO2, HfO2, Al2O3, SiNX, SiON, AlON, ZrO2 and TiO2. Figure 1D The cell structure shown forms a ferroelectric random access memory (FRAM) cell.

[0156] In another embodiment, gate dielectric layers 105a and 105b include at least one adjustable resistance layer, such as hafnium oxide (HfOx), titanium oxide (TiOx), and tantalum oxide (TaOx), to form a resistive random access memory (RRAM) cell. In one embodiment, layer 151a is the aforementioned adjustable resistance layer, while layer 151b is an insulating layer, such as an oxide or a high-k material, such as a hafnium oxide (SiO2) layer.

[0157] In another embodiment, gate dielectric layers 105a and 105b include at least one phase change layer, such as germanium-antimony-tellurium alloy or chalcogenide glass, Ge2Sb2Te5 (GST), to form a phase change memory (PCM) cell. In one embodiment, layer 151a is the aforementioned phase change layer, and layer 151b is an insulating layer, such as an oxide or a high-K material, such as a hafnium oxide (SiO2) layer.

[0158] In another embodiment, gate dielectric layers 105a and 105b comprise at least one ferromagnetic material, such as a nickel-iron (NiFe) or cobalt-iron (CoFe) alloy, to form a magnetoresistive random access memory (MRAM) cell. In one embodiment, layer 151a is the aforementioned ferromagnetic layer, and layer 151b is an insulating layer, such as an oxide or a high-K material, such as a hafnium oxide (SiO2) layer.

[0159] It should be noted that the materials described above for forming the gate dielectric layers 105a and 105b are merely examples. Using any other suitable materials to form the gate dielectric layers 105a and 105b is within the scope of this invention.

[0160] Figure 1E An embodiment of the unit structure is shown, wherein the float 102 is compared to Figure 1F The illustrated cell embodiment is thicker and lightly doped. Using an N-channel cell as an example, when a positive voltage is applied to gates 104a and 104b, the applied voltage pushes away holes and attracts electrons to form N-type channels 152a and 152b on the surface of float 102, as shown. Channels 152a and 152b allow electrons to flow between bit line 101 and source line 103 for read and write operations. During storage, a negative voltage is applied to gates 104a and 104b. This attracts holes in channel regions 152a and 152b to increase data retention time.

[0161] Figure 1F An embodiment of the cell structure is shown, in which the float 102 is thinner than in previous embodiments. In this structure, the thin float 102 itself serves as a channel, forming a thin-film transistor. The thin body increases the controllability of the channel by the gates 104a and 104b. This enhances the cell performance and increases data retention time. The thin body also reduces short-channel effects and reduces gate-induced drain leakage (GIDL) current.

[0162] It is important to note that Figures 1E-1F The thickness of the illustrated unit structure depends on many factors, such as the gate voltage, doping concentration, and the materials forming the float, gate, and gate dielectric layer. In one application, the appropriate thickness of the float 102 can be determined using device simulation.

[0163] Figure 1G An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1AThe illustrated embodiment is similar, except that the channel of the unit transistor is formed using a thin semiconductor layer (SEMI) 109, which includes, for example, silicon, polycrystalline silicon, silicon germanium (SiGe), indium gallium zinc oxide (IGZO), or any other suitable semiconductor material. Depending on the material, the semiconductor layer 109 can be formed using epitaxial growth, thin film deposition, atomic layer deposition, or any other suitable process. The bit lines 101 are formed of a conductive material, such as a metal or heavily doped polycrystalline silicon. The unit structure also includes an insulator (INS) 110, which includes, for example, an oxide or nitride material, or an air gap, or a vacuum space.

[0164] Figure 1H An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1G The illustrated embodiment is similar, except that a portion of the semiconductor layer 109 on the sidewalls of the vertical bit line 101 is removed. Therefore, the semiconductor layer 109 forms a floating island for each cell. Before depositing the material of the bit line 101, a portion of the semiconductor layer 109 located on the sidewalls of the vertical bit line 101 is removed using an anisotropic etching process (e.g., dry etching).

[0165] Figure 1I An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1A The embodiments shown are similar, except that... Figure 1A The back gate 104b shown is replaced by an insulating layer (INSL) 123 comprising, for example, an oxide or nitride material. Thus, this cell structure forms a single-gate transistor cell.

[0166] Figure 1J An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1A The illustrated embodiment is similar, except that additional insulating layers 117a and 117b, comprising, for example, oxide or nitride materials, are formed on portions of bit line 101 to reduce parasitic capacitance of bit line 101 and capacitive coupling between bit line 101 and gates 104a and 104b. Figures 1I-1J The structure shown can be applied to Figures 1A-7B All other unit embodiments shown.

[0167] Figure 1K An embodiment of the cell structure according to the present invention is shown. For ease of description and clarity, the front gate 104a and the gate dielectric layer 105a have been removed to show the internal structure of the cell. This embodiment is similar to... Figures 1A-1B The illustrated embodiment is similar, except that a diode structure (DS) 162 is formed between the source line 103 and the float 102. This structure prevents voltage leakage from the bit line 101 to the source line 103 during programming operations.

[0168] As an example, suppose Figure 1K The cell structure in the diagram forms an N-channel cell to describe the programming operation. When a positive voltage is applied to the gate 104b, the selected bit line 101 is given a low voltage for programming, while the other unselected bit lines are given a high voltage to disable programming. The source line 103 is given a voltage equal to or higher than the voltage of the unselected bit lines to turn off the diode structure 162. This configuration prevents current leakage between the selected and unselected bit lines through the source line 103.

[0169] Refer again Figure 1K In one embodiment, a semiconductor layer 153 comprising, for example, silicon or polysilicon is formed between the source line 103 and the float 102. The semiconductor layer 153 is formed using diffusion, epitaxial growth, or polysilicon deposition processes. In one embodiment, the semiconductor layer 153 has a heavy doping of the opposite type to that of the float 102. For example, in one embodiment, if the float 102 has P-type doping, the semiconductor layer 153 has N+ type doping. This forms a diode structure 162 between the float 102 and the semiconductor layer 153. The source line 103 is formed of a conductive material, such as a metal or polysilicon material, having the same type of heavy doping as the semiconductor layer 153.

[0170] In another embodiment, the semiconductor layer 153 has the same type of heavy doping as the float 102, and the source line 103 is formed of a heavily doped semiconductor material of the opposite type (e.g., polysilicon). For example, in one embodiment, the semiconductor layer 153 is formed of P+ type silicon or polysilicon, and the source line 103 is formed of N+ type polysilicon. This configuration forms a diode structure 163 between the semiconductor layer 153 and the source line 103.

[0171] Figure 1L An embodiment of the unit structure according to the present invention is shown. In this embodiment, the diode structure 164 between the source line 103 and the float 102 is formed by two semiconductor layers 154 and 155, which comprise materials such as silicon or polycrystalline silicon.

[0172] In one embodiment, semiconductor layer 154 has the same type of heavy doping as buoy 102, and semiconductor layer 155 has the opposite type of heavy doping to buoy 102. For example, in one embodiment, buoy 102 has P-type doping, and semiconductor layers 154 and 155 have P+ and N+ type doping, respectively. This forms a doping layer between semiconductor layers 154 and 155. Figure 1L The diode structure 164 is shown. The source line 103 is formed of a conductive material, such as a metal or a heavily doped polycrystalline silicon material of the same type as the semiconductor layer 155.

[0173] Figure 1M An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1K The embodiments shown are similar, except that in this embodiment, the semiconductor layer 153 is formed with the shape shown, extending below SL103.

[0174] Figures 1N-1P An embodiment of the unit structure according to the present invention is shown. In these embodiments, a diode structure is formed between bit line 101 and float 102.

[0175] Figure 1N An embodiment of the unit cell structure is shown, comprising a semiconductor layer 156, such as silicon or polysilicon, formed between bit lines 101 and floats (FB) 102. The semiconductor layer 156 is formed using diffusion, epitaxial growth, or polysilicon deposition processes. In one embodiment, the semiconductor layer 156 has a heavy doping of the opposite type to that of the float 102. For example, in one embodiment, if the float 102 has P-type doping, the semiconductor layer 156 has N+ type doping. This forms a diode structure (DS) 165 between the float 102 and the semiconductor layer 156. The bit lines 101 are formed of a conductive material, such as metal or polysilicon, which has the same type of heavy doping as the semiconductor layer 156.

[0176] In another embodiment, semiconductor layer 156 has the same type of heavy doping as float 102, and bit line 101 is formed of a semiconductor material of the opposite type of heavy doping (e.g., polysilicon). For example, in one embodiment, semiconductor layer 156 is formed of P+ type silicon or polysilicon, and bit line 101 is formed of N+ type polysilicon. This configuration forms a diode structure 166 between semiconductor layer 153 and bit line 101.

[0177] Figure 1O An embodiment of the cell structure according to the present invention is shown. In this embodiment, the diode structure 167 between bit line 101 and float 102 is formed by two semiconductor layers 157 and 158, which comprise materials such as silicon or polycrystalline silicon. In one embodiment, semiconductor layer 157 has the same type of heavy doping as float 102, and semiconductor layer 158 has the opposite type of heavy doping to float 102. For example, in one embodiment, if float 102 has P-type doping, then semiconductor layers 157 and 158 have P+ and N+ type doping, respectively. This forms a diode between semiconductor layers 157 and 158. Bit line 101 is formed of a conductive material, such as metal or polycrystalline silicon, which has the same type of heavy doping as semiconductor layer 158.

[0178] Figure 1PAn embodiment of the unit structure according to the present invention is shown. In this embodiment, the semiconductor layer 156 is formed having Figure 1P The pattern or shape shown.

[0179] In another embodiment, Figure 1A and Figure 1I The cell structures shown are formed as four-terminal and three-terminal memristor-transistors, also known as "memristor transistors." In this embodiment, the cell's float 102 is formed of a "memristor" material. The resistance of the memristor is adjusted by the formation or breakage of conductive filaments within the memristor. These conductive filaments are formed by the migration of dopants, ions, or defects. Memristor materials are sometimes referred to as "synaptic" materials or "phase-change" materials.

[0180] Memristor materials are numerous, including MoS2, ReSe2, ZrO2, GaSe, WSe2, WO3-x, SrTiO3, TiO2, MoTe2, Ta2O5, VO2, VSiOx, Cu2S, In2Se3, C22H14 (pentaphenyl), indium gallium zinc oxide (IGZO), graphene, carbon nanotubes, van der Waals (vdW) materials (e.g., WSe2-NbSe2, Nb2O5-WSe2-NbSe2 layers), or combinations thereof. Gate dielectric layers 105a and 105b are formed from SiO2, HfO2, Al2O3, TiO2, Nb2O5, VSiOx, or any combination thereof. Gates 104a and 104b are formed from suitable metallic materials (e.g., W, Cr, Pt, Au, Pd, and many others).

[0181] It should be noted that the materials listed above for the memristor float 102, gate dielectric layers 105a and 105b, and gates 104a and 104b are exemplary. Listing all potentially suitable materials would be very difficult. However, the use of any other suitable memristor material is within the scope of this invention.

[0182] Figure 2A An embodiment of a memristor-transistor cell structure according to the present invention is shown. This embodiment includes a thin floating body 102, which serves as a connector with… Figure 1F The channel is similar to that of the cells described in the text. The gate dielectric layers 105a and 105b comprise multiple layers, such as layers 170a and 170b. In one embodiment, the thin float 102 is formed of WSe2, and the gate dielectric layers 170a and 170b are formed of SiO2 and Nb2O5, respectively.

[0183] In another embodiment, the thin floating body 102 is formed of MoS2, and the gate dielectric layers 170a and 170b are formed of Al2O3 and ZrO2-x, respectively. In another embodiment, the thin floating body 102 is formed of MoS2, and the gate dielectric layers 170a and 170b are formed of Al2O3 and Nb2O5, respectively. In another embodiment, the thin floating body 102 is formed of SrTiO3, and the gate dielectric layers 170a and 170b are formed of SiO2 and Si3N4, respectively.

[0184] Figure 2B An embodiment of the unit structure according to the present invention is shown. In this embodiment, the gate dielectric layers 105a and 105b comprise three layers 170a to 170c. The thin float 102 is formed of indium gallium zinc oxide (IGZO), and the gate dielectric layers (170a), (170b), and (170c) are formed of SiO2, TiO2, and Al2O3, respectively.

[0185] This unit structure combines the functions of a transistor and a memristor. The transistor can have, for example... Figure 1A The dual gate shown, or as Figure 1I The single-gate (single or dual) gate is shown. The formation and breakage of conductive filaments in the memristor material of the (single or dual) gate-controlled float 102. When a conductive filament forms, it reduces the resistance between bit line 101 and source line 103, thus making the cell an on-cell. When a conductive filament breaks, it increases the resistance between bit line 101 and source line 103, thus making the cell an off-cell.

[0186] Depending on the switching mechanism, memristors can be bipolar, unipolar, threshold, diffused, or complementary resistor switches.

[0187] Figures 2C-2E An example of the switching characteristics of a four-terminal memristor-transistor is shown, for example... Figure 1A The example shown. Figures 2C-2D The bipolar switching mechanism is shown. Figure 2E The unipolar switching mechanism is shown, where VFG, VBG, and Id represent the front gate voltage, back gate voltage, and drain current, respectively.

[0188] For some memristors, such as VO2 or SrTiO3 memristors, the resistance of the memristor is adjusted by modifying the Schottky barrier at the contacts. For example, in one embodiment, the float 102 is formed of VO2, and the bit line 101 and source line 103 are formed of TiN. When a low voltage is supplied to the gate 104a and a high voltage is applied to the bit line 101 and source line 103, the float 102 depletes V2+O, causing the contacts to exhibit Schottky characteristics. Therefore, the cell is in a high-resistance state. When a low voltage is supplied to the gate 104a and a high voltage is supplied to the bit line 101 and source line 103, the float 102 saturates at V2+O, causing the contacts to exhibit ohmic characteristics.

[0189] Figure 2F A table illustrating some exemplary materials for embodiments of the memristor-transistor cell according to the present invention is shown. This table shows... Figures 1A-1B The materials shown are those for gates 104a and 104b, float 102, gate dielectric layers (e.g., layers 105a and 105b), and source / drain electrodes (e.g., bit line 101 and source line 103). The source and drain electrodes are conductors used to form source line 103 and bit line 101, respectively. It should be noted that some materials are not specified in the table and are indicated by the symbol "-". These unspecified materials include any suitable material. For the gate and source / drain electrodes (e.g., BL101 and SL 103), suitable materials can be conductive materials, such as metals or heavily doped polysilicon. For the gate dielectric layers (e.g., GDL 105a / b), suitable materials can be insulating materials, such as oxides (SiO2) or high-k materials, such as hafnium silicon (HfO2). Figure 2F The materials described herein are exemplary and not limiting. Listing all possible materials is practically impossible. The use of any other memristor material is within the scope of this invention.

[0190] Figures 3A-7B An embodiment of the cell structure according to the present invention is shown. In these embodiments, the gate dielectric layers 105a and 105b may use a reference. Figures 1A-1D Any material described herein may be used to form it. However, for simplicity, an example using a charge trapping layer (e.g., an oxide-nitride-oxide (ONO) layer) will be used as an example in the following description. It should be noted that the use of materials including, but not limited to, [other materials]... Figure 1A Any other material described in Figure D is within the scope of this invention.

[0191] Figure 3A An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1AThe illustrated embodiments are similar, except that gate dielectric layers 105a and 105b are replaced by memory material layers (e.g., charge-trapping layers (CTLs) 160a and 160b). It should be noted that, for clarity and ease of description, the layers of charge-trapping layer 160b are not shown in detail, but in various embodiments, these layers are identical to those of charge-trapping layer 160a.

[0192] In one embodiment, charge trapping layers 160a and 160b comprise multiple layers 161a to 161c, such as oxide-nitride-oxide (ONO) layers. In one embodiment, oxide layer 161a is a tunnel oxide layer, thin enough to allow electrons to tunnel through when a high electric field is applied. In one embodiment, nitride layer 161b traps electrons for data storage. In one embodiment, oxide layer 161c is a barrier oxide, thick enough to prevent electrons from tunneling through to gates 104a and 104b. In another embodiment, oxide layer 161c is a tunnel oxide layer, and oxide layer 161a is a barrier oxide layer. In this embodiment, during programming, electrons are injected from a selected gate 104a or 104b into nitride layer 161b.

[0193] Although ONO layers 161a to 161c are used as example implementations of charge trapping layers 160a and 160b, in other embodiments, charge trapping layers 160a and 160b include any suitable number of oxide and nitride layers. For example, in another embodiment, charge trapping layers 160a and 160b include an oxide-nitride-oxide-nitride-oxide (ONONO) layer. In another embodiment, charge trapping layers 160a and 160b include only one oxide layer and one nitride layer (e.g., ON). These variations are all within the scope of the invention.

[0194] Figure 3B It shows Figure 3A The 3D cell structure shown has the front gate 104a and charge trapping layer 160a removed to show the internal structure of the cell.

[0195] Figure 4A An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1A The illustrated embodiment is similar, except that bit lines 101 are formed of metal to reduce bit line resistance. A semiconductor layer 107, comprising a material such as silicon or polysilicon, forms the drain region of the cell.

[0196] The semiconductor layer 107 forming the drain region is formed using an epitaxial growth process or a thin film deposition process. In one embodiment, the semiconductor layer 107 is heavily doped using an in-situ doping process, the opposite type to that of the float 102. The processes for forming and doping the semiconductor layer 107 described above are exemplary and not limiting. Forming and doping the semiconductor layer 107 using other processes is within the scope of this invention. The metal bit line 101 and semiconductor layer 107 structure shown in this embodiment can be implemented in all other embodiments of the cell structure disclosed herein according to the invention.

[0197] Figure 4B It shows Figure 4A The cell structure shown has the front gate 104a and charge trapping layer 160a removed to show the internal structure of the cell.

[0198] Figure 4C An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 4A The illustrated embodiment is similar, except that the semiconductor layer 107 is formed as a ring-shaped island as shown. In one embodiment, the semiconductor layer 107 is formed by implanting a heavy dopant of the opposite type to that used in the float 102 using a diffusion or plasma doping process. For example, assuming the float 102 has P-type or N-type doping, the semiconductor layer 107 is formed into N+ or P+ type regions by implanting an N-type dopant (e.g., phosphorus) or a P-type dopant (e.g., boron), respectively.

[0199] In another embodiment, the semiconductor layer 107 is formed by: forming a groove on the float 102 using an isotropic etching process (e.g., wet etching), and then filling the groove with a semiconductor material having a doping type opposite to that of the float 102 by using epitaxial growth or polysilicon deposition to form the semiconductor layer 107. The bit lines 101 are formed of metal to reduce bit line resistance. The previously described processes for forming and doping the semiconductor layer 107 are merely examples. Forming and doping the semiconductor layer 107 using other processes is within the scope of this invention. The metal bit lines 101 and semiconductor layer 107 structure shown in this embodiment can be applied to all other disclosed embodiments of the cell structure according to the invention.

[0200] Figure 4D It shows Figure 4C The cell structure shown has the front gate 104a and charge trapping layer 160a removed to show the internal structure of the cell.

[0201] Figure 5A An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 4AThe illustrated embodiment is similar, except that the source line 103 is formed of metal to reduce source line resistance. A semiconductor layer 108 comprising, for example, silicon or polysilicon is formed between the source line 103 and the float 102 to form a source region.

[0202] Prior to forming the source line 103, a semiconductor layer 108 is formed by injecting dopant into the float 102 through the space occupied by the source line 103 using a diffusion process or a lateral ion implantation process. In one embodiment, the semiconductor layer 108 is heavily doped using a diffusion process of the opposite type to that of the float 102. The processes for forming and doping the semiconductor layer 108 described above are exemplary and not limiting. Forming and doping the semiconductor layer 108 using other processes is within the scope of this invention.

[0203] Figure 5B It shows Figure 5A The cell structure shown has the front gate 104a and charge trapping layer 160a removed to show the internal structure of the cell.

[0204] Figure 6A An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 1A The embodiments shown are similar, except that... Figure 6A The cell shown is formed as a thin-film transistor rather than a junction transistor. A semiconductor layer 115 is formed, including, for example, silicon, polysilicon, silicon germanium (SiGe), indium gallium zinc oxide (IGZO), tungsten-doped indium oxide semiconductor, or any other suitable semiconductor material. An insulator 116, including, for example, an oxide or nitride material, is also shown. The semiconductor layer 115 forms the channel of the cell transistor.

[0205] Figure 6B It shows Figure 6A The cross-sectional view of the unit structure shown is taken along line A-A'.

[0206] Figure 7A An embodiment of the unit structure according to the present invention is shown. This embodiment is related to... Figure 6A The embodiments shown are similar, except that the semiconductor layer 115 is formed with different patterns or shapes.

[0207] Figure 7B It shows Figure 7A The cross-sectional view of the unit structure shown is taken along line A-A'.

[0208] Figures 8A-8E Embodiments of a 3D array structure according to the present invention are shown. In these embodiments, with... Figure 1A The unit structure shown is used to form an array structure as an example; however, Figures 8A-8E All embodiments of the 3D array structure shown are applicable and usable.Figures 1A-7B It can be formed from any unit structure shown.

[0209] Figure 8A It shows the use of Figure 1A An embodiment of a 3D array structure formed by the cell structure is shown. In this embodiment, five layers of cells 124a to 124e are shown as an example. The array structure also includes vertical bit lines 101a to 101c, floats 102a to 102e, and source lines 103a to 103e. Gates 104a to 104d form word lines (WL). A dielectric layer 105 is also shown. In this embodiment, the cells are formed as dual-gate transistors. Each cell (e.g., cell 124b) is coupled to two gates 104a and 104b. Each gate (e.g., gate 104a) is shared by two adjacent cells (e.g., cells 124a and 124b).

[0210] Figure 8B An embodiment of the 3D array structure according to the present invention is shown. This embodiment includes six layers of cells 124a to 124f as an example. This embodiment is related to... Figure 8A The illustrated embodiment is similar, except that the cells are formed as single-gate transistors. Each cell (e.g., cell 124b) is coupled to only a single gate (e.g., gate 104a). Insulating layers 123a and 123b, comprising, for example, an oxide material, to separate the cells, are also shown. In this embodiment, each gate (e.g., gate 104a) is shared by two adjacent cells (e.g., cells 124a and 124b).

[0211] Figure 8C An embodiment of the 3D array structure according to the present invention is shown. This embodiment includes two layers of units 124a and 124b as an example. Insulating layers 123a to 123c, comprising a material such as an oxide material, are provided to separate the units. This embodiment and... Figure 8A The illustrated embodiment is similar, except that gates 104a to 104d are not shared. Each cell (e.g., cell 124a) is coupled to two gates (e.g., gates 104a and 104b). In one embodiment, the two gates coupled to the cell are separated to form a dual-gate transistor. In another embodiment, the two gates coupled to the cell are connected to form a single-gate transistor.

[0212] Figure 8D An embodiment of a 3D array structure according to the present invention is shown. In this embodiment, two layers of cells 124a and 124b are shown as an example. Insulating layers 123a to 123c, comprising, for example, an oxide material, are provided to separate the cells. This embodiment and... Figure 8C The illustrated embodiment is similar, except that it is coupled to two gates of the cell (e.g. Figure 8C The cells 104a and 104b shown are connected to form a gate (e.g.,Figure 8D (Gates 104a' and 104b' are shown). This configuration forms a single-gate transistor.

[0213] Figure 8E An embodiment of the 3D array structure according to the present invention is shown. Three-layer units 124a to 124c are shown as an example. Insulating layers 123a to 123d, comprising, for example, an oxide material, are provided to separate the units. This embodiment is similar to... FIG. 8C The illustrated embodiment is similar, except that each cell (e.g., cell 124a) is coupled to only one gate (e.g., gate 104a). This configuration forms a single-gate transistor array.

[0214] FIGS. 9A-9C An embodiment of a 3D array structure according to the present invention is shown. As an example, FIG. 1A The unit structure shown is used to form an array structure, however, FIGS. 9A-9C All embodiments of the 3D array structure shown can be used FIGS. 1A-7B It can be formed from any unit structure shown.

[0215] FIG. 9A It shows the basis FIG. 1A The embodiment of the 3D array structure of the cell structure shown is an example. This array structure includes vertical bit lines 101a to 101e, word line layers 104a to 104d, and source lines 103a to 103e. A float body 102 and a gate dielectric layer 105 are also shown.

[0216] FIG. 9B It shows the use of FIG. 1A The embodiment of the 3D array structure formed by the unit structure shown is used as an example. This embodiment is similar to... FIG. 9A The illustrated embodiment is similar, except that the array is divided into multiple stacks by vertical slits (e.g., slits 125a and 125b). Character lines 104a to 104d in each stack can be connected to different character line decoder signals. In one embodiment, slits 125a and 125b are filled with an insulating material, such as an oxide material.

[0217] FIG. 9C It shows the use of FIG. 1A The embodiment of the 3D array structure formed by the unit structure shown is used as an example. This embodiment is similar to... FIG. 9BThe illustrated embodiment is similar, except that vertical slits 125a and 125b are filled with a conductive material (e.g., metal or polysilicon) to form vertical source line layers 126a and 126b. Vertical source line layers 126a and 126b are connected to source lines, such as source lines 103a to 103e. Vertical source line layers 126a and 126b can be connected to a common source line voltage, such as 0V. An insulating layer (e.g., insulating layer 127) is formed on the sidewalls of the word lines to prevent short circuits between the word lines and vertical source line layers 126a and 126b.

[0218] FIG. 10A An embodiment of an equivalent circuit of a 3D NOR array architecture according to the present invention is shown. This equivalent circuit includes memory cells 210a to 210m, which include… FIGS. 1A-7B Any embodiment of the memory cell shown. For illustration, this embodiment uses a NOR flash memory cell as an example. However, embodiments may use any other type of memory cell, such as FRAM, RRAM, MRAM, PCM, and memristor-transistor (memristor transistor) cells, all of which are within the scope of this invention.

[0219] FIG. 10A The circuit shown also includes vertical bit lines 101a-n and 111a-n, word lines 104a-m and 114a-m, and source lines 103a-m and 113a-m. As shown, vertical bit lines 101a-n and 111a-n are connected to horizontal bit line 130a-n. Horizontal bit line 130a-n can be located at the bottom or top of the array. In this embodiment, since bit lines 101a-n and 111a-n are connected to the same horizontal bit line 130a-n, word lines 104a-m and 114a-m cannot be connected. Instead, each word line 104a-m and 114a-m is connected to a word line decoder. Source lines 103a-m and 113a-m are connected to a separate source line decoder (not shown) or to a common source line voltage source.

[0220] FIG. 10B An embodiment of the equivalent circuit of the 3D NOR array architecture according to the present invention is shown. This embodiment is related to... FIG. 10AThe illustrated embodiment is similar, except for the addition of additional select gates 135a-n and 138a-n. Vertical bit lines 101a-n and 111a-n are connected to horizontal bit lines 130a-n via select gates 135a-n and 138a-n, respectively. Select gate signals 136a-k are connected to the gate terminals of select gates 135a-n and 138a-n, respectively. Select gate signals 136a-k select which set of vertical bit lines to couple to horizontal bit lines 130a-n. Horizontal bit lines 130a-n and select gates 135a-n and 138a-n are located at the top or bottom of the array. Adding select gates 135a-n and 138a-n allows multiple word lines in the same layer (e.g., word lines 104a and 114a and word lines 104m and 114m) to be connected. This significantly reduces the number of word line decoders required. Source lines 103a to 103m are connected to a separate source line decoder (not shown) or a common source line voltage source.

[0221] FIGS. 11A-11B An embodiment of the 3D array structure according to the present invention is shown.

[0222] FIG. 11A It shows the use of FIG. 4A The illustrated embodiment of a 3D array formed by a unit structure is provided as an example. In other embodiments, the following can be used: FIGS. 1A-7B Any other unit structure shown can be used to form a 3D array structure. This 3D array structure includes multiple word line layers 104a-h, multiple source line layers 103a-h, and multiple vertical bit lines, such as 101a-d. Each intersection of bit lines 101a-d and source lines 103a-h forms a unit, such as unit 112.

[0223] FIG. 11B An embodiment of the bit line connection of the 3D array structure according to the present invention is shown. In one embodiment, vertical bit lines 101a-d are connected to horizontal bit lines 130a-d via a select gate (e.g., select gate 135a) and a contact (e.g., contact 137a). Horizontal bit lines 130a-d are formed of a conductive material (e.g., metal or heavily doped polycrystalline silicon). The select gate (e.g., select gate 135a) is formed of a vertical channel transistor. In one embodiment, select gate lines 136a-d are connected to the control gate of the vertical channel select gate, such as gate 135a.

[0224] In one embodiment, the word line layer 104a-h and the source line layer 103a-h are connected to a word line decoder (not shown) and a source line voltage generator (not shown), respectively, by forming a stepped structure for word lines and source lines similar to that of conventional 3D NAND flash memory at the array edge.

[0225] FIG. 12A The present invention is shown FIG. 3A The illustration shows an embodiment of the cell structure of a NOR flash memory. Please refer to [the original text]. FIG. 3A Obtain a detailed description of the unit structure.

[0226] FIG. 12B The symbolic representation of a NOR flash memory cell is shown. This cell includes two gates, 104a and 104b, which can be connected to two different word lines (WL1 and WL2).

[0227] refer to FIG. 12A In one embodiment, charge trapping layers 160a and 160b include multiple layers 161a to 161c, such as oxide-nitride-oxide (ONO) layers. Data is stored in the form of electrons 120a and 120b trapped in the nitride layer 161b of charge trapping layers 160a and 160b by using programming operations. Due to the programming operations, electrons 120a and 120b can be independently controlled by gates 104a and 104b, respectively. The cell stores two data bits to increase storage capacity. In another embodiment, the cell is programmed to store electrons (120a or 120b) on only one side (160a or 160b) to perform single data storage.

[0228] For N-channel cells, the electrons trapped in charge trapping layers 160a and 160b increase the cell's threshold voltage (Vt). For P-channel cells, the electrons trapped in charge trapping layers 160a and 160b decrease the cell's threshold voltage (Vt). When the gates 104a and 104b are supplied with a read voltage, the cell current is determined by the cell's threshold voltage. Cells with higher threshold voltages will have higher impedance and conduct lower cell currents. Cells with lower threshold voltages will have lower impedance and conduct higher cell currents. The cell impedance represents the "weight" of the synapses in the artificial neural network array.

[0229] FIG. 12A The illustrated embodiments can be programmed and erased using conventional programming and erasing mechanisms, such as channel hot-electron (CHE) injection, Fowler-Nordheim (FN) tunneling, channel hot hole injection, band-to-band tunneling (BTBT), gate-induced-drain-leakage (GIDL) assisted injection, or any other suitable programming mechanism.

[0230] FIGS. 12C-12EAn embodiment of preferred programming and erasing operations according to the present invention is shown. However, other programming and erasing mechanisms may also be used with the cell structures disclosed herein within the scope of the invention.

[0231] FIG. 12C An embodiment of the cell structure is shown, illustrating programming operations using channel hotelectron (CHE) injection. Word line 104a and bit line 101 are supplied with positive voltages +VG and +VD, such as 10V and 5V, respectively. Source line 103 is supplied with a low voltage, such as 0V. This configuration causes current to flow through the channel, and electrons are injected into the charge trapping layer 160, as indicated by arrow 121, due to the high electric field applied to word line 104a. Electrons are trapped in the nitride layer 161b near the bit line 101 side to increase the cell's threshold voltage.

[0232] FIG. 12D An embodiment of the cell structure is shown, illustrating an erase operation using hot-hole injection (HHI). Word line 104a and bit line 101 are supplied with a negative voltage (-VG) (e.g., -5V) and a positive voltage (+VD) (e.g., +5V), respectively. Source line 103 is supplied with a low voltage, e.g., 0V. This configuration disconnects the channel and causes interband tunneling (BTBT) on the drain side, resulting in holes being injected into the charge-trapping layer 160, as indicated by arrow 122, due to the high electric field applied to word line 104a. The holes neutralize electrons trapped in the nitride layer 161b near bit line 101, thereby lowering the cell threshold voltage.

[0233] because FIGS. 12C-12D The programming and erasing operations shown both occur on the bit line 101 side, so the threshold voltage of the channel near the source line 103 side remains positive (Vt>0V), which is also known as "enhanced channel". The enhanced channel prevents the cell's Vt from being erased below 0V, thus preventing channel leakage current, the so-called "over-erasure" problem. Therefore, the "over-erasure" problem known in conventional NOR flash memory is eliminated by the enhanced channel.

[0234] FIG. 12EAn embodiment of the cell structure is shown, illustrating an erase operation using Fowler-Nordheim (FN) tunneling. In this embodiment, the word line (e.g., word line 104a) is supplied with 0V or a negative voltage -VG (e.g., -5V to -10V). Bit line 101 and source line 103 are supplied with the same positive high voltages +VD and +VS, e.g., +10V to +20V respectively. The high voltage applied to bit line 101 and source line 103a penetrates the channel and transmits the voltage to float 102a. This creates a high electric field, causing electrons stored in nitride layer 160b to tunnel through oxide layer 160a to float 102a, as indicated by arrow 122. This configuration lowers the cell's threshold voltage.

[0235] In another embodiment, a positive high voltage (e.g., +10V to +20V) is supplied only to one of the bit line 101 or the source line 103. The other line remains floating. The high voltage penetrates the channel to reach the floating line. Because the line is floating, no current flows through it after it is fully charged. The high voltage penetrating to the float 102 causes FN tunneling to occur, thereby erasing the cell described above.

[0236] In another embodiment, FIG. 12A The cell structure shown is used for dual-mode applications of volatile and non-volatile data storage. For volatile data storage, input data is stored in floats 102a and 102b. This improves programming speed. Next, the data is programmed to the charge trapping layer 160 for non-volatile data storage.

[0237] According to embodiments of the present invention, the 3D unit and array structure shown in the foregoing embodiments are used to implement a 3D neural network array for artificial intelligence (AI) applications.

[0238] FIG. 13A An exemplary architecture of a neural network is shown. The neural network includes multiple layers of neurons 260a-m forming an input layer. The neural network also includes neurons 264a-s forming an output layer. In one embodiment, multiple layers of neurons (e.g., neurons 261a-n, 262a-k, and 263a-p) are configured as hidden layers between the input and output layers. Each layer may have a different number of neurons.

[0239] FIG. 13BA layer of a neural network is shown, comprising input neurons 260a-m and output neurons 261a-n. Each of the output neurons 261a-n is connected to all the input neurons 260a-m via synapses 203a-m. Each synapse represents a value called a "weight" (e.g., weight 209a-d). The weights determine the influence of the signal from the input neuron to the output neuron. The values ​​of the weights can be positive (called "positive weights") or negative (called "negative weights"). The basic operations of the neural network include three functions. The first function is a "multiplication" of the input 260a-d with the weights 209a-d. The second function is a "summation" 222 of the multiplication result. The third function is an "activation function" 223 that transforms the linear input into a non-linear output, such as the sigmoid function or other suitable functions. In one embodiment, the summation and activation are performed internally within the output neurons 261a-n.

[0240] An artificial neural network array consists of multiple layers of neurons. The output of each layer is fed into the input of the next layer. By changing the weights of each synapse during training, the neural network can be trained to learn specific tasks.

[0241] FIGS. 13C-13D Proof is shown FIG. 13C How to simulate the 3DNOR type cell array shown FIG. 13D An example of a neural network is shown.

[0242] like FIG. 13C As explained, character lines 104a to 104f represent FIG. 13D The input neurons are shown as 260a to 260f. Vertical bit lines 101a to 101c represent output neurons 261a to 261c. Cells 210a to 210f represent synapses 203a to 203f. The data stored in cells 210a to 210f represents the "weights" of synapses 203a to 203f.

[0243] When the 3D array receives input data, character lines 104a to 104f are supplied with voltage according to the input data. For example, data 1 will supply a high voltage to turn on cells 210a to 210f, while data 0 will supply a low voltage to turn off cells 210a to 210f. The data stored in cells 210a to 210f will determine the cell current. For example, if the data is 1, the cell will conduct a high current. If the data is 0, the cell will conduct a low current.

[0244] The unit currents are added together in the vertical bit line 101a, such as FIG. 13C As illustrated by arrow 140a. This simulates the summation function of output neuron 261a, as... FIG. 13D As indicated by the arrow in the image.

[0245] Similarly, as illustrated by arrows 140b and 140c, the summing unit currents in vertical bit lines 101b and 101c simulate the summing function of output neurons 261b and 261c. As a result, FIG. 13D The function of the neural network shown is provided by FIG. 13C The 3D cell array simulation shown.

[0246] FIG. 14A It shows the use of FIG. 10A An embodiment of a neural network array formed by a 3D NOR array structure is shown. In one embodiment, horizontal bit lines 204a-m are connected to an input neuron circuit (not shown). The input neuron circuit applies various voltages to the horizontal bit lines 204a-m according to the input data. The horizontal bit lines 204a-m are connected to multiple vertical bit lines 205a-m. The vertical bit lines 205a-m are connected to the source line 207a through multiple cells 210a-m. Word lines 206a-n are supplied with a constant read voltage to turn on cells 210a-m. The source line 207a-n is connected to an output neuron circuit (not shown). Cells 210a-m represent synapses. The threshold voltage of cell 210a-m represents the weight of the synapse.

[0247] Assume input data is applied to bit lines 204a-m and word line 206a is selected. Current will flow from bit lines 204a-m through cells 210a-m to source line 207a. The current flowing through cells 210a-n depends on the cell's threshold voltage. When the threshold voltage of cells 210a-n is higher (or lower), the current flowing through cells 210a-n is lower (or higher), respectively.

[0248] Assume the currents flowing through cells 210a-m are "I1" to "Im" respectively. The current flowing to source line 207a is "Is". The source line current "Is" will be equal to the sum of "I1" and "Im". This configuration performs a summation function for in-memory computing and neural network applications. By using this function, the array can perform in-memory computing operations or form artificial neural networks, such as... FIG. 13B As shown. Horizontal bit line 204a-m represents... FIG. 13B The input neuron 260a-m is shown. Unit 210a-m represents... FIG. 13B The synapse 203a-n is shown. Source line 207a-n represents... FIG. 13B The output neuron shown is 261a-n.

[0249] In another embodiment, input is applied to word lines 206a-m instead of horizontal bit lines 204a-m. In this embodiment, source lines 207a-n are supplied with a constant voltage, such as VDD or 0V. Various voltages are supplied to word lines 206a-b according to the input data. Word line voltage conduction units 210a-a conduct unit currents "I1" to "In" respectively. Assuming the current flowing to or out of bit line 205a is "Ib", the bit line current "Ib" will be equal to the sum of unit currents "I1" to "In". This performs a summation function for in-memory computing and neural network applications. By using this function, the array can be used to perform in-memory computing operations or form artificial neural networks, such as... FIG. 13B As shown. In this embodiment, character lines 206a-n represent input neurons, and horizontal character lines 204a-b represent output neurons.

[0250] In another embodiment, input is applied to source lines 207a-n. In this embodiment, word lines 206a-n are supplied with a constant read voltage. Various voltages are supplied to source lines 207a-b according to the input data. The word line voltages respectively turn on cells 210a-a to conduct cell currents "I1" to "In". Assume the current flowing to or out of bit line 205a is "Ib". The bit line current "Ib" will be equal to the sum of cell currents "I1" to "In". This configuration performs a summation function for in-memory computing and neural network applications. By using this function, the array performs in-memory computing operations or forms artificial neural networks, such as... FIG. 13B As shown. In this embodiment, source lines 207a-n represent input neurons, and horizontal bit lines 204a-b represent output neurons.

[0251] FIG. 14B It shows the use of FIG. 10B An example of a neural network array with a 3D array structure is shown. This example is related to... FIG. 14A The illustrated embodiment is similar, except that horizontal bit lines 204a-m are connected to vertical bit lines 205a-m via select gates 220a-m. This embodiment allows word lines in the same layer to be connected as follows: FIG. 10B The described connection is made. This greatly reduces the number of character line decoders.

[0252] In another embodiment, the input is applied to the selection gate signal 136a-k, such as FIG. 10B As shown. Various voltages are supplied to the selection gate signals 136a-k according to the input data. Horizontal bit lines 130a-n are connected to a constant voltage, such as VDD or 0V. Word lines 104a-m are supplied with a constant read voltage. (Reference) FIG. 14BThe voltage of the selection line 221a controls the current flowing through the selection gates 220a-m. The current then flows through cells 210a-m to the source line 207a. The current flowing through cells 210a-n depends on the cell's threshold voltage (Vt). When the threshold voltage of cells 210a-n is higher (or lower), the current flowing through cells 210a-n is lower (or higher), respectively.

[0253] Assume the currents flowing through cells 210a-m are "I1" to "Im". The current flowing to source line 207a is "Is". The source line current "Is" will be equal to the sum of "I1" to "Im". This performs a summation function for in-memory computing and neural network applications. By using this function, the array can perform in-memory computing operations or form artificial neural networks, such as... FIG. 13B As shown. In this embodiment, the selection line (e.g., selection line 221a) represents the input neuron, while the source lines 207a-n represent the output neuron.

[0254] FIG. 15A An embodiment of a neural network array is shown, which provides "negative" weights to the synapses of the neural network. This embodiment uses... FIG. 14A The 3D NOR array structure shown is used as an example. Various aspects of this embodiment can also be applied to... FIG. 14B The array structure shown.

[0255] like FIG. 15A As shown, horizontal bit lines 204a-m are divided into multiple pairs 215a-k. Each pair of bit lines is connected to an input neuron circuit (not shown) to apply complementary input voltages BL0+ and BL0- to the bit line pairs (e.g., bit line pairs 204a and 204b, respectively) according to the input data. For example, assuming the input data is 1, the voltages applied to bit lines 204a and 204b are VDD and 0V, respectively. Assuming the input data is 0, the voltages applied to bit lines 204a and 204b are 0V and VDD, respectively.

[0256] Selected word lines (e.g., word line 206a) are supplied with a read voltage to turn on cells 210a and 210b, causing current to flow from bit line pairs 204a and 204b through cells 210a and 210b to source line 207a. Since bit lines 204a and 204b are supplied with complementary voltages BL0+ and BL0-, respectively, cells 210a and 210b represent the “positive weight” and “negative weight” of the synapse, respectively.

[0257] For example, suppose the currents flowing through cells 210a and 210b are "I1" and "I2", respectively. Also suppose bit lines 204a and 204b are supplied with VDD and 0V, respectively. When "I1" is high, the voltage of source line 207a becomes high. Therefore, cell 210a represents a positive weight. Conversely, when "I2" is high, the voltage of source line 207a becomes low. Therefore, cell 210b represents a negative weight.

[0258] like FIG. 14A As described, the current “Is” flowing to source line 207a is equal to the sum of the currents flowing through cells 210a-m. This configuration performs summation functions for in-memory computing and neural network applications. Source lines 207a-n can be connected to an output circuit (not shown) to perform in-memory computing or to provide outputs to an output neuron circuit (not shown) to perform neural network functions.

[0259] Please note that in another embodiment, the input and output directions are reversed. Source lines 207a-n are connected to the input neuron circuit to apply various voltages to the source lines 207a-n according to the input data. Bit lines 204a-m are connected to the output neuron circuit. Bit line pairs, such as 204a and 204b, are respectively connected to... FIG. 16B The diagram shows the positive and negative inputs of the neuron circuit. Thus, even-numbered units (e.g., units 210a and 210l) represent positive weights, and odd-numbered units (e.g., units 211b to 210m) represent negative weights.

[0260] FIG. 15B An embodiment of a neural network array is shown, which provides "negative" weights to the synapses of the neural network. This embodiment uses... FIG. 14A The 3D array structure shown is provided as an example. Various aspects of this embodiment are also applicable to... FIG. 14B The array structure shown.

[0261] In this embodiment, source lines 207a-n are divided into multiple pairs 217a-k. Each pair of source lines is connected to an input neuron circuit (not shown) to apply complementary input voltages SL0+ and SL0- to the source line pairs (e.g., source line pairs 207a and 207b) according to the input data. For example, assuming the input data is 1, the voltages applied to source lines 207a and 207b are VDD and 0V, respectively. Assuming the input data is 0, the voltages applied to source lines 207a and 207b are 0V and VDD, respectively.

[0262] Character lines 206a and 206b are supplied with read voltages to turn on cells 210a and 211a, causing current to flow from source lines 207a and 207b through cells 210a and 211a to character line 204a. Since source lines 207a and 207b are supplied with complementary voltages SL0+ and SL0-, respectively, cells 210a-m and 211a-m represent “positive weight” and “negative weight”, respectively.

[0263] For example, suppose the currents flowing through cells 210a and 211a are "I1" and "I2", respectively. Also suppose source lines 207a and 207b are supplied with VDD and 0V, respectively. When "I1" is high, the voltage of bit line 204a becomes high. Therefore, cell 210a represents a positive weight. Alternatively, when "I2" is high, the voltage of bit line 204a becomes low. Therefore, cell 211a represents a negative weight.

[0264] The current “Ib” flowing to bit line 204a is equal to the sum of the currents flowing through units 210a, 211a, ..., 212a to 213a. This configuration performs a summation function for in-memory computation and neural network applications. Bit line 204a-m can be connected to an output circuit (not shown) to perform in-memory computation, or to an output neuron circuit (not shown) to perform neural network functions.

[0265] In another embodiment, the input and output directions are opposite. Bit lines 204a-m are connected to the input neuron circuit to apply various voltages to bit lines 204a-m according to the input data. Source lines 207a-n are connected to the output neuron circuit. Source line pairs (e.g., source line pairs 207a and 207b) are respectively connected to... FIG. 16B The diagram shows the positive and negative inputs of the neuron circuit. Thus, cell 210a-m represents positive weights, while cell 211a-m represents negative weights.

[0266] FIG. 15C An embodiment of a neural network array is shown, which provides "negative" weights to the synapses of the neural network. This embodiment uses... FIG. 14A The 3D array structure shown is used as an example. Various aspects of this embodiment are also applicable to... FIG. 14B The array structure shown.

[0267] In this embodiment, character lines 206a-n are divided into multiple pairs 218a-k. Each pair of character lines is connected to an input neuron circuit (not shown) to provide complementary input voltages WL0+ and WL0- to the character line pairs (e.g., character line pairs 206a and 206b) according to the input data. For example, assuming the input data is 1, the voltages supplied to character lines 206a and 206b are VDD and 0V, respectively. Assuming the input data is 0, the voltages supplied to character lines 206a and 206b are 0V and VDD, respectively.

[0268] For example, suppose the currents flowing through cells 210a and 211b are "I1" and "I2", respectively. Word lines 206a and 206b are supplied with voltages WL0+ and WL0-, respectively, based on the input data. When the input data is high, the cell current "I1" becomes high, and the voltage on bit line 204a becomes high. Therefore, cell 210a represents a positive weight. Alternatively, when the input data is high, the cell current "I2" becomes low, and the voltage on bit line 204a becomes low. Therefore, cell 211a represents a negative weight.

[0269] The current “Ib” flowing to bit line 204a is equal to the sum of the currents flowing through cells 210a to 213a. This configuration performs a summation function for in-memory computation and neural network applications. Bit line 204a-m can be connected to an output circuit (not shown) to perform in-memory computation, or to an output neuron circuit (not shown) to perform neural network functions.

[0270] In another embodiment, the input and output directions are opposite. Bit lines 204a-m are connected to the input neuron circuit to apply various voltages to bit lines 204a-m according to the input data. Source lines 207a-n are connected to the output neuron circuit. In this configuration, cells 210a-m represent positive weights, and cells 211a-m represent negative weights.

[0271] FIGS. 16A-16D An example of an output circuit for in-memory computing or for forming output neuron circuits of a neural network is shown.

[0272] FIG. 16A An example of an output circuit using a single-input comparator 233 is shown. FIGS. 15A-15C The array embodiment shown describes cells 231a-m and 232a-m. The input data is divided into two groups: the original input data IN0+ to INm+ and their complementary data IN0- to INm-. Cells 231a-m are connected to the input data IN0+ to INm+, respectively, while cells 232a-m are connected to the complementary input data IN0- to INm-, respectively. When the input is higher, cell 231a-m results in a lower output, while cell 232a-m results in a higher output. Therefore, cells 231a-m represent negative weights, and cells 232a-m represent positive weights. The sum of the cell currents “Isum”, indicated by the arrows, is fed into the input of comparator 233 to produce the output. In neural network applications, the output can be used as the input to the next layer.

[0273] FIG. 16BAn embodiment of the output circuit using a dual-input comparator 234 is shown. In this embodiment, both sets of cells 231a-m and 232a-m are connected to the input data IN0 to INm. The output of cell 231a-m is connected to the negative input of comparator 234, and the output of cell 232a-m is connected to the positive input of comparator 234. When the input is high, cell 231a-m causes the output to be low, while cell 232a-m causes the output to be high. Therefore, cells 231a-m represent negative weights, and cells 232a-m represent positive weights. The sum of the cell currents “Isum+” and “Isum-” (as indicated by the arrows) is fed to the positive and negative inputs of comparator 234, respectively, to produce the output. In neural network applications, the output can be used as the input to the next layer.

[0274] FIG. 16C Another embodiment of the output circuit using a single-input comparator 233 is shown. This embodiment is similar to... FIG. 16A The illustrated embodiment is similar, except that complementary inputs IN0+ to INm+ and IN0- to INm- are applied to the gates of cells 231a-m and 232a-m, respectively. The sources of cells 231a-m and 232a-m are connected to a constant voltage, such as VDD. When the input is high, cell 231a-m causes the output to be low, while cell 232a-m causes the output to be high. Therefore, cells 231a-m represent positive weights, and cells 232a-m represent negative weights. The sum of the cell currents “Isum” (as indicated by the arrows) is fed to the input of comparator 233 to produce the output. In neural network applications, the output can be used as the input to the next layer.

[0275] FIG. 16D An embodiment using the output circuit of a dual-input comparator 234 is shown. This embodiment is related to... FIG. 16B The illustrated embodiment is similar, except that complementary inputs IN0+ to INm+ and IN0- to INm- are applied to the gates of cells 231a-m and 232a-m, respectively. The sources of cells 231a-m and 232a-m are connected to a constant voltage, such as VDD. The output of cell 231a-m is connected to the negative input of comparator 234, and the output of cell 232a-m is connected to the positive input of comparator 234. When the input is high, cell 231a-m causes the output to be low, while cell 232a-m causes the output to be high. Therefore, cells 231a-m represent negative weights, and cells 232a-m represent positive weights. The sum of the cell currents “Isum+” and “Isum-” (as indicated by the arrows) is fed to the positive and negative inputs of comparator 234, respectively, to produce the output. In neural network applications, the output can be used as the input to the next layer.

[0276] FIGS. 17A-17BAn embodiment of an output circuit for performing an analog matching function in a memory computing application, such as a content-addressable memory (CAM) application, is shown. This embodiment is related to... FIG. 16C The illustrated embodiment is similar, except that cells 231a-m are programmed with threshold voltages Vt0+ to Vtm+ to represent stored data, while cells 232a-m are programmed with threshold voltages Vt0- to Vtm- to represent complementary stored data. During operation, the gates of cells 231a-m are supplied with input data IN0+ to INm+, while the gates of cells 232a-m are supplied with complementary input data IN0- to INm- to match the data stored in the cells.

[0277] FIG. 17B The relationship between the threshold voltage and the input voltage is shown. In this relationship, Vt0 and Vt1 represent the threshold voltage distributions for data 0 and 1 stored in the cell, respectively. The voltages IN0 and IN1 applied to the gate of the cell for data 0 and 1, respectively, are also shown. Assuming... FIG. 17A Cells 231a and 232a, as shown, store data 0 and complementary data 1, respectively. The threshold voltages of cells 231a and 232a will be Vt0 and Vt1, respectively, as... FIG. 17B As shown.

[0278] If the input data is 0, the gates of cells 231a and 232a are supplied with IN0 and IN1, respectively. This configuration turns off cells 231a and 232a, so the output of comparator 233 becomes high. This indicates that the input data matches the data stored in the cell. Similarly, when the cell stores data 1 and the input data is 1, cells 231a and 232a will turn off to pull the output of comparator 233 high.

[0279] If the input data is 1, the gates of cells 231a and 231b are supplied with IN1 and IN0, respectively. This will turn on cell 231a because its gate is supplied with IN1 and its threshold voltage is Vt0. Therefore, the output of comparator 233 will become low. This indicates that the input data does not match the data stored in the cell. Similarly, when the cell stores data 1 and the input data is 0, cell 231b will be turned on to pull the output of comparator 233 low.

[0280] In one embodiment, the sum of the cell currents "Isum" indicated by the arrow is fed into the input of comparator 233 to produce an output. The output of comparator 233 becomes higher as more input data matches the data stored in the cell.

[0281] Although FIG. 17A The illustrated embodiment uses FIG. 16C The circuit shown implements the analog matching function, but it is clear that with minor modifications, it can be used... FIGS. 16A-16DOther circuits are shown. For simplicity, these examples will not be shown in separate diagrams. It should also be noted that, through the use of... FIGS. 16A-16D and FIGS. 17A-17B The illustrated embodiments can implement many other functions for in-memory computation, such as OR, NOR, AND, NAND, XOR, XNOR, addition, and subtraction. For simplicity, these modifications will not be shown or described in detail. However, these modifications and variations remain within the scope of the invention.

[0282] FIG. 18A An embodiment of a 3D array for in-memory computing or neural network applications according to the present invention is shown. The 3D array structure includes basic element 240. Element 240 and... FIG. 10B The 3D array shown is similar, except that it includes an output circuit 241 connected to source lines 114a-m via a common source line 243. The output circuit 241 includes a comparator, for example... FIGS. 16A-16D The comparator 233 or 234 shown. The output circuit 241 performs the function of memory calculation or the function of the output neuron of a neural network.

[0283] Vertical bit lines 101a-n and 111a-n are connected to horizontal bit lines 130a-n via select gates 135a-n and 138a-n, respectively. Select gate signals 136a-k are connected to the gates of select gates 135a-n and 138a-n, respectively. Select gate signals 136a-k select which set of vertical bit lines to couple to horizontal bit lines 130a-n. Horizontal bit lines 130a-n and select gates 135a-n and 138a-n are located at the top or bottom of the array. Adding select gates 135a-n and 138a-n allows multiple word lines (e.g., word lines 104a and 114a, and 104m and 114m) in the same layer to be connected. This significantly reduces the number of word line decoders. Source lines 103a-m are connected to output circuitry 241. In one embodiment, output circuitry 241 is located below the 3D array to reduce die size.

[0284] FIG. 18BComponent 240 is shown, with the signal flow during its operation indicated by arrows. In one embodiment, input data is applied to bit lines 130a-n. Assuming select gate line 136a is selected, current flows from bit lines 130a-n through select gates 135a-n to vertical bit lines 101a-n. Assuming word line 104a is selected, current flows through cells 210a-n to source line 103a. The current flowing through cells 210a-n depends on the threshold voltage of the cells. When the threshold voltage of cells 210a-n is higher (or lower), the current flowing through cells 210a-n is lower (or higher), respectively. The sum of the currents flowing through cells 210a-n is then applied to output circuit 241 via common source line 243. Output circuit 241 performs memory computation functions or outputs neuron functions, such as... FIGS. 16A-16D and FIGS. 17A-17B As shown.

[0285] FIG. 19A An embodiment of an array architecture 250 according to the present invention is shown. The array includes a plurality of elements 240a-p, such as... FIG. 18A As shown. The source lines 243a-p of components 240a-p are connected to the output circuit 241a-p, as follows. FIG. 18A As shown. Components 240a-p are connected to bit lines 130a-n. Bit lines 130a-n are connected to input circuits 242a-n. Word lines WL0–WLm (e.g. FIG. 18A The character lines 104a-m shown) and the select gate signals SG0–SGk (e.g.) FIG. 18A Each element 240a-p shown has select gates 136a-k connected to the character line and select gate decoder circuit 244.

[0286] FIG. 19B An embodiment of the array architecture 250 according to the present invention is shown. This embodiment is related to... FIG. 19A The illustrated embodiment is similar, except for the addition of a bit-line decoder 245 and a source-line decoder 246. The bit-line decoder 245 selects a portion of the bit lines 130a-n to connect to the input circuits 242a-i. The source-line decoder 246 selects a portion of the source lines 243a-p to connect to the output circuits 241a-j. This configuration reduces the number of input circuits 242a-j and output circuits 241a-j, thereby reducing the die size.

[0287] According to the present invention, the word line and select gate decoder 244, the bit line decoder 245, and the source line decoder 246 have multi-selection capabilities. They can select any number of elements, bit lines, and source lines at any location according to the required task.

[0288] During operation, the character line and select gate decoder 244 selects multiple elements. For each selected element, the character line and select gate decoder 244 selects one character line and one select gate. Input circuits 242a-i supply input to the selected bit lines 130a-n, which are then passed through the bit line decoder 245 to the selected elements 240a-p to produce outputs. The outputs are sent to output circuits 241a-j selected by the source line decoder 246. Using this configuration, in-memory computations or neural networks with any number of inputs and outputs can be performed.

[0289] FIG. 20A The signal flow of an embodiment of an array architecture including elements 240a-p according to the present invention is illustrated. For example, elements 240a-p represent... FIG. 18B An embodiment of element 240 is shown. As indicated by the arrows, signals flow from input circuits 242a-i through bit line decoder 245 to selected bit lines 130a-n, and then to selected elements 240a-p. Output signals flow from selected elements 240a-p through source lines 243a-p to source line decoder 246, and then to output circuits 241a-j.

[0290] FIG. 20B An embodiment of an array architecture with signal flow inversion is illustrated. In this embodiment, input circuits 242a-i are connected to source line decoder 246, while output circuits 241a-j are connected to bit line decoder 245. As indicated by the arrows, the signal flows from input circuits 242a-i through source line decoder 246 to selected source lines 243a-p, and then to selected elements 240a-p. The output signal flows from selected elements 240a-p through bit lines 130a-n, through bit line decoder 245, and to output circuits 241a-j.

[0291] It is important to note that for neural network applications, signals typically flow in two directions, referred to as "forward propagation" and "backward propagation." Forward propagation is used to produce the output based on the current weights of the synapses. During the training operation, backward propagation is used to calculate the output error of each neuron to adjust the synaptic weights. For this application, the input circuits 242a-i and the output circuits 241a-j are designed to allow bidirectional signal flow. Then, in the forward and backward propagation operations, respectively... FIG. 20A and FIG. 20B The signal flow shown.

[0292] FIG. 20C An embodiment of the array architecture 250 according to the present invention is shown. This embodiment is related to... FIG. 19BThe illustrated embodiment is similar, except that input circuits 242a to 242i are connected to character lines and a selection gate decoder 244. The character lines and selection gate decoder 244 select multiple character lines to connect to the input circuits 242a to 242i. Input neurons 242a to 242i supply input to the selected character lines to perform operations. FIG. 15C The operation is shown. The source line driver 235 applies current to the selected source lines 243a to 243p. The current flows through the selected cells to the bit lines 130a to 130n, and through the bit line decoder 245 to the output circuits 241a to 241j.

[0293] FIG. 20D An embodiment of the array architecture 251 according to the present invention is shown. This embodiment is related to... FIG. 20C The illustrated embodiment is similar, except that output circuits 241a to 241j are connected to source line decoder 246 instead of character lines and select gate decoder 244. Source line decoder 246 selects multiple source lines 243a to 243p to connect to output circuits 241a to 241j. Input neurons 242a to 242i apply input to the selected character lines to perform... FIG. 15C The operation is shown. The bit line driver 236 applies current to the selected bit lines 130a to 130n. The current flows through the selected cells to the source lines 243a to 243p, and through the source line decoder 246 to the output circuits 241a to 241j.

[0294] FIGS. 21A-21C An embodiment of the architecture of a neural network chip or memory computing chip according to the present invention is shown.

[0295] FIG. 21A An embodiment of an architecture for a memory computing chip is illustrated. In one embodiment, the chip includes logic element 251 and computing element 252. Logic element 251 includes input / output (I / O), data registers, control logic, decoders, voltage generators, central processing unit (CPU), arithmetic logic element (ALU), program memory, and any other elements that control the basic operation of the chip.

[0296] Computing element 252 includes multiple arrays 250a-n, for example FIG. 19A or FIG. 19B The array is shown. Logic element 251 feeds data to computing element 252 to perform memory computation operations, and then returns the output data to logic element 251. Multiple arrays 250a-n allow for parallel computation of large amounts of data to enhance chip performance.

[0297] FIG. 21B An embodiment of an architecture for a neural network chip is shown. The chip includes components such as... FIG. 21AThe diagram shows logic element 251 and computing element 252. Computing element 252 includes multiple arrays 250a-n, for example... FIG. 19A or FIG. 19B The array shown is an example. Multiple arrays 250a-n are connected to form a multi-layer neural network, such as 253a and 253b. This architecture allows for parallel processing of large amounts of data, thereby enhancing chip performance.

[0298] FIG. 21C An embodiment of an architecture for a neural network chip is shown. This embodiment is related to... FIG. 21B The illustrated embodiment is similar, except that multiple arrays 250a-n use bidirectional input / output connections, as indicated by the arrows. This architecture is implemented using conventional bidirectional input / output buffers between adjacent arrays 250a-n. The input / output direction of each array 250a-n is freely configurable by the control of logic element 251. This allows the arrays 250a-n to form multi-layer neural networks with arbitrary numbers of layers and arbitrary signal flow directions. This greatly increases the flexibility of neural network configuration.

[0299] FIG. 22 An embodiment of a 3D array element 240 for in-memory computing or neural network applications according to the present invention is shown. This array element 240 is related to... FIG. 18A The illustrated embodiment is similar, except that source lines 103a-m and 113a-m are formed in the vertical direction instead of the horizontal direction. This array structure with parallel bit lines 101a-m and source lines 103a-m is also called an "AND" array.

[0300] The arrows indicate the signal flow during operation in this embodiment. In one embodiment, input data is applied to bit lines 130a-n. Assuming select gate line 136a is selected, current flows from bit lines 130a-n through select gates 135a-n to vertical bit lines 101a-n. Assuming word line 104a is selected, current flows through cells 210a-n to source lines 103a-m. A select source line select gate signal 247 turns on source line select gates 139a-n to transfer current from source lines 103a-m to common source line 243. Common source line 243 is connected to output circuitry 241 to perform memory computation functions or output neuron functions, such as... FIGS. 16A-16D and FIGS. 17A-17B As shown.

[0301] The current flowing through cells 210a to 210n depends on the threshold voltage of the cells. When the threshold voltage of cells 210a-n is high (or low), the current flowing through cells 210a-n is low (or high), respectively. The sum of the currents flowing through cells 210a-n is then applied to the output circuit 241 through the common source line 243. The output circuit 241 performs memory computation functions or outputs neuron functions, such as...FIGS. 16A-16D and FIGS. 17A-17B As shown.

[0302] FIG. 23 An embodiment of a 3D array element 240 for in-memory computing or neural networks according to the present invention is shown. In this embodiment, a 3D array element 240 for in-memory computing or neural networks is used. FIG. 10A The array structure is shown. Character lines at the same level are not connected. For example, character lines 104a-m and 114a-m are connected to character lines of different decoders.

[0303] The arrows indicate the signal flow during operation in this embodiment. In one embodiment, input data is applied to bit lines 130a-n. Assuming word line 104a is selected, current flows from bit lines 130a-m through the perpendicular bit lines 101a-n and cells 210a-n to source line 103a. Source line 103a is connected to output circuit 241 via common source line 243a and source line selection gate 248a to perform memory computation functions or output neuron functions, such as... FIGS. 16A-16D and FIGS. 17A-17B As shown.

[0304] FIGS. 24A-24C An embodiment of the structure of a neural network chip according to the present invention is shown. FIG. 24A In the illustrated embodiment, computing element 252 is located on top of logic element 251. This configuration reduces die size, thereby lowering manufacturing costs and chip footprint. The computing element 252 and logic element 251 are formed on the same wafer, also referred to as a "monolithic integrated circuit (IC)".

[0305] FIG. 24A The structure shown can be formed using any suitable 3D integration technique. For example, in one embodiment, the structure is formed by forming logic elements 251 on top of a substrate on a wafer, and then forming computing elements 252 on top of the logic elements 251. FIG. 24B In another embodiment shown, logic element 251 is located on top of computing element 252. For this embodiment, computing element 252 is first formed on top of the substrate of the wafer, and then logic element 251 is formed on top of computing element 252.

[0306] exist FIG. 24CIn another embodiment shown, the neural network chip structure is formed using wafer-to-wafer bonding. Two wafers, each including a computing element 252 and a logic element 251, are placed on top of a substrate wafer. The two wafers are then bonded face-to-face to connect the computing element 252 and the logic element 251 using any suitable 3D wafer integration technology, such as through-silicon vias (TSVs) or microbumps, as indicated by indicators 254a to 254n.

[0307] FIG. 25A Implementation shown FIG. 18B An embodiment of the 3D array structure element 240 is shown. The 3D array structure includes horizontal bit lines 130a to 130n and elements for selecting, such as... FIG. 18B The gate lines 135a to 135k and the select gate lines 136a to 136k are shown. Horizontal word line layers 104a to 104m and horizontal source line layers 103a to 103m are also shown. As shown, stepped structures 255a for word line layers 104a to 104m and stepped structures 255b for source line layers 103a to 103m are formed at the edges of the array.

[0308] The stepped structures 255a and 255b can be formed using the conventional pull-back etch process used in the production of 3D NAND flash memory, or by using the process disclosed in U.S. Patent Application No. 18 / 492,625 (titled “3D Array Structures and Processes,” filed October 23, 2023 by the same inventor of this invention). The stepped structures 255a and 255b allow word line layers 104a to 104m and source line layers 103a to 103m to be connected to word line circuitry 256 and source line circuitry 258, respectively.

[0309] In one embodiment, the character line circuit 256, bit line circuit 257, and source line circuit 258 are located below the 3D array, as shown, to reduce die size. In another embodiment, the character line circuit 256, bit line circuit 257, and source line circuit 258 are located at the edge of the array. Depending on the array architecture, the character line circuit 256 includes character lines, a select gate decoder 244, and input circuits 242a to 242i, as shown. FIGS. 19A-20D As shown. FIGS. 19A-20D As shown, the bitline circuit 257 includes a bitline decoder 245, output circuits 241a to 241j, and a bitline driver circuit 236. The source line circuit 258 includes a source line decoder 246 and output circuits 241a to 241j, as shown... FIGS. 19A-20D As shown.

[0310] FIG. 25BIt shows FIG. 25A The embodiment shown illustrates the connection of bit lines 130a to 130n, word line layers 104a to 104m, and source line layers 103a to 103m in a 3D array structure element. In this embodiment, bit lines 130a to 130n are connected to bit line circuit 257 using contacts 265a to 265n. Contacts 265a to 265n are formed by etching contact holes through a thick insulating layer (e.g., an oxide layer) using a high aspect ratio deep trench process, and then filling the contact holes with metal (e.g., tungsten (W), titanium (Ti), and titanium nitride (TiN)).

[0311] Character line layers 104a to 104m are connected to character line circuit 256 via contacts (e.g., contacts 266a to 266m and contacts 267a to 267m) and metal lines 268a to 268m. Source line layers 103a to 103m are connected to source line circuit 258 via contacts (e.g., contacts 269a to 269m, contacts 270a to 270m) and metal lines 271a to 271m. In one embodiment, contacts 266a to 266m, 267a to 267m, 269a to 269m, and 270a to 270m are formed using the same processes and materials used to form the previously described contacts 265a to 265n.

[0312] FIG. 25C It shows FIG. 25A Another embodiment of the connection of bit lines 130a to 130n, word line layers 104a to 104m, and source line layers 103a to 103m of the 3D array structure element shown. This embodiment is related to... FIG. 24B The illustrated embodiment is similar, except that the character line circuit 256, bit line circuit 257, and source line circuit 258 are located on top of the 3D array.

[0313] FIG. 26A An embodiment of the 3D array cell structure according to the present invention is shown. This embodiment is related to... FIGS. 1A-1B The embodiments shown are similar, except that a resistive storage layer or a phase-change storage layer 150 is added on the bit line 101 side of the cell to form a 3D resistive random access memory (RRAM) cell or a 3D phase-change memory (PCM) cell, respectively.

[0314] FIG. 26A The internal cell structure is shown, in which the front gate 104a and gate dielectric layer 105a have been removed. The resistance of the resistive storage layer or phase change storage layer 150 can be changed by applying appropriate bias conditions to the front gate 104a, back gate 104b, bit line 101 and source line 103 of the cell.

[0315] FIG. 26B It shows FIG. 26AAn embodiment of the equivalent circuit of the unit structure shown is illustrated. Transistor 100 is a transistor formed by a gate 104b, a gate dielectric layer 105b, and a float 102. A resistive storage layer or phase change layer 150 is also shown in the figure.

[0316] FIG. 26C An embodiment of a 3D RRAM or PCM cell according to the present invention is shown. This embodiment is related to... FIG. 26A The illustrated embodiment is similar, except that a resistive storage layer or phase-change storage layer 150 is added to the source line 103 side of the cell.

[0317] FIG. 26D It shows FIG. 26C An embodiment of the equivalent circuit of the unit structure shown is illustrated. Transistor 100 is a transistor formed by a gate 104b, a gate dielectric layer 105b, and a float 102. A resistive storage layer or phase change layer 150 is also shown in the figure.

[0318] In one embodiment, the storage layer 150 is implemented using a resistive storage material, such as a special metal oxide layer, like HfOx, TiOx, TaOx, AlOx, NiOx, WOx, ZrOx, NbOx, CuOx, CrOx, MnOx, MoOx, SiOx, etc. The metal oxide layer is formed between two metal electrodes. The metal electrodes are formed of specific metals, such as titanium (Ti), tantalum (Ta), platinum (Pt), tungsten (W), copper (Cu), chromium (Cr), ruthenium (Ru), aluminum (Al), nickel (Ni), praseodymium (Pr), silver (Ag), etc.

[0319] When a suitable bias condition is applied to the metal electrode, conductive filaments form within the metal oxide layer to allow current to flow. Thus, the metal oxide is set to a low-resistance state. By applying another bias condition, the filaments are disrupted, resetting the metal oxide layer to a high-resistance state.

[0320] In another embodiment, the storage layer 150 is implemented using a phase change memory (PCM) material, such as chalcogenides, Ge2Sb2Te5 (GST), GeTe–Sb2Te3, Al50Sb50, etc. By applying appropriate bias conditions to the cells, the phase change material changes between an amorphous phase and a polycrystalline phase to represent a high-resistance state and a low-resistance state, respectively.

[0321] FIG. 27 It shows the use of FIGS. 26A-26D An example of a neural network array with a 3D unit structure is shown. This example is related to... FIG. 14B The embodiments shown are similar, except for the different unit structures. FIG. 27The array shown includes multiple horizontal bit lines 204a-m, which are connected to input neuron circuitry (not shown). The horizontal bit lines 204a-m are located at the top or bottom of the array. The horizontal bit lines 204a-m are connected to multiple vertical bit lines 205a-m via bit line selection gates 213a-m. The gates of the bit line selection gates 213a-m are connected to selection gate line 214a.

[0322] Each vertical bit line (e.g., 205a) is connected to multiple source lines 207a-n via a cell (e.g., cell 212a). Each cell (e.g., cell 212a) includes a cell transistor 208a and a resistive memory element 209a. The cell transistor 208a is connected to word lines, such as word lines 206a-n. The resistive memory element (e.g., element 209a) represents the "weight" of cell 212a.

[0323] FIG. 28A An embodiment of a 3D array structure 240 for in-memory computing or neural network applications according to the present invention is shown. Structure 240 represents a basic unit of a 3D array structure. This embodiment is related to... FIG. 18A The illustrated embodiment is similar, except that the input IN (0-k) is applied to select gate lines 136a-k instead of bit lines 130a-n. Common source line 243 is connected to a voltage source, such as VDD or VSS 0V.

[0324] Assume the common source line 243 is connected to VDD. During operation, one of the word lines 104a-m can be selected. If word line 104a is selected, a voltage will be supplied to it to turn on cells 210a-n and 211a-n, thereby allowing current to flow from the common source line 243 through cells 210a-n and 211a-n to the vertical bit lines 101a-n and 111a-n, respectively. The current flowing through cells 210a-n and 211a-n is determined by the cell's threshold voltage.

[0325] Based on the input data IN0 to INk applied to select gate lines 136a-k, select gates 135a-n and 138a-n are turned on or off to transfer current from vertical bit lines 101a-n and 111a-n to horizontal bit line 130a-n. The sum of the currents is then applied to the output circuit (not shown) connected to horizontal bit line 130a-n. The arrows indicate the direction of current flow.

[0326] FIG. 28A The illustrated embodiment achieves "positive weights", while FIGS. 28B-28D The example shown implements "negative weights".

[0327] FIG. 28BAn embodiment is shown illustrating how select gate lines are divided into two groups. For illustration, only two select gate lines 136a-b are shown in this example. Input data (e.g., input data IN0) is provided to the first group of select gate lines (e.g., select gate line 136a). Complementary input data INB0 is provided to the second group of select gate lines (e.g., select gate line 136b). A common source line 243 is connected to a voltage source, such as VDD or VSS.

[0328] If the input data IN0 is 1, selector gates 135a-n are turned on, allowing current to flow from the common source line 243a through cells 210a-n to the vertical bit lines 101a-n, and then through selector gate 135a-n to the horizontal bit lines 130a-n. Assuming the common source line 243 is connected to VDD, this will pull the voltage of the horizontal bit lines 130a-n high. Therefore, cells 210a-n represent "positive weights".

[0329] If input data IN0 is 0, then complementary input data INB0 will be 1. This configuration will turn on selector gates 138a-n to allow current to flow from common source line 243 through cell 211a-n to vertical bit line 111a-n, and then through selector gate 138a-n to horizontal bit line 130a-n. Therefore, cell 211a-n represents "negative weight".

[0330] FIG. 28C An embodiment of a 3D array implementing negative weights according to the present invention is shown. This embodiment is related to... FIG. 28B The illustrated embodiment is similar, except that the same input data (e.g., input data IN0) is applied to two sets of select gate lines (e.g., 136a and 136b). Therefore, when input data IN0 is 1, it will turn on both sets of select transistors (e.g., 135a-n and 138a-n).

[0331] The common source line is also divided into two groups, such as group 243a and group 243b, which are connected to voltage sources (e.g., VDD and VSS 0V), respectively. The current flowing from the common source line 243a through cells 210a-n to the horizontal bit line 130a-n pulls the voltage of the horizontal bit line 130a-n high. Therefore, cells 210a-n represent "positive weight". The current flowing from the common source line 243b through cells 211a-n to the horizontal bit line 130a-n pulls the voltage of the horizontal bit line 130a-n low. Therefore, cells 211a-n represent "negative weight".

[0332] FIG. 28D An embodiment of a 3D array implementing negative weights according to the present invention is shown. This embodiment is related to... FIG. 28AThe illustrated embodiment is similar, except that two word lines (e.g., word lines 104a and 104b) are selected together. For illustration, only two word lines 104a and 104b are shown in the figure as examples. Even-numbered source lines (e.g., source line 103a) and odd-numbered source lines (e.g., source line 103b) are connected to common source lines 243a and 243b, respectively. Common source lines 243a and 243b are connected to voltage sources (e.g., VDD and VSS (0V)).

[0333] Input data IN0 to INk are applied to select gate lines 136a-k. Assuming input data IN0 is 1, one or more select gates 135a-n may be activated. When two word lines (e.g., 104a and 104b) are selected, voltage is supplied to both word lines 104a and 104b to activate cells 210a-n and 211a-n. Since cells 210a-n are connected to the common source line 243a, the current flowing from the common source line 243a through cells 210a-n pulls the voltage of horizontal bit lines 130a-n high. Therefore, cells 210a-n represent "positive weight". Conversely, the current flowing from the common source line 243b through cells 211a-n to horizontal bit lines 130a-n pulls the voltage of horizontal bit lines 130a-n low. Therefore, cells 211a-n represent "negative weight".

[0334] Although FIG. 21A The embodiment shown in Figure 21D uses NOR flash memory cells, but it is clear that all embodiments can be applied to other memory cell structures, such as floating cell (FBC), ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), memristor transistors (memristor transistors), and split-gate NOR flash memory. Depending on the type of memory cell, the array structure and operation may be slightly modified, but these applications and modifications should still fall within the scope of this invention.

[0335] FIG. 29A It shows the use of FIGS. 28A-28D This is an embodiment of the 3D array structure 251 shown in the circuit example. Selection gate lines 136a-k are connected to input circuits 242a-k. Bit lines 130a-n are connected to output circuits 241a-1. Word lines 104a-m are connected to a word line decoder (not shown). Input circuits 242a-k, output circuits 241a-n, and the word line decoder (not shown) are located below the 3D array to reduce die size.

[0336] FIG. 29BAnother embodiment of the 3D array structure 251 is shown. In this embodiment, word lines 104a-m are connected to input circuits 242a-k. Bit lines 130a-n are connected to output circuits 241a-1. Select gate lines 136a-k are connected to a select gate decoder (not shown). In one embodiment, input circuits 242a-k, output circuits 241a-n, and a select gate decoder (not shown) are located below the 3D array to reduce die size.

[0337] FIG. 30A An embodiment of the 3D array structure 252 according to the present invention is shown. For example... FIGS. 29A-29B As shown, the 3D array 252 includes multiple 3D array structures 251a-c. FIG. 30A The number of 3D arrays 251a-c shown is merely an example and is not limiting. 3D array structure 252 includes any suitable number of 3D arrays 251, such as those shown in 3D arrays 251a-c.

[0338] like FIG. 30A The array 252 shown includes horizontal bit lines 130a-r, word line layers 104a-g, and select gate lines 136a-l connected to select gates 135a-n to 138a-n, as shown. FIG. 28A As shown. Step structures 253a and 253b are formed on character line layers 104a-g and source line layers 103a-g, respectively. Character line layers 104a-g and source line layers 103a-g are connected to a circuit (not shown) located below the 3D array via contacts connected to step structures 205a and 205b, respectively.

[0339] FIG. 30B The diagram illustrates how character line layers 104a-g and source line layers 103a-g are connected to circuitry 254 located below the 3D array to reduce die size. Circuitry 254 and the 3D array are separated by an insulating layer made of a material such as oxide. Character line layers 104a-g in ladder structure 253a are connected to character line control circuitry, such as character line drivers or character line decoders, in 254 via contacts 256a-g and metal wires. Source line layers 103a-g in ladder structure 253b are connected to source line control circuitry, such as source line drivers or source line decoders, in circuitry 254 via contacts 257a-g and metal wires. Horizontal bit lines 130a-r are connected to bit line control circuitry, such as sense amplifiers and data read / write buffers, in circuitry 254 via contacts 258a-r. Contacts 256a-g, 257a-g, and 258a-r are formed by creating holes in the insulating layer using a deep trench process, and then filling the holes with a conductive material (such as metal).

[0340] FIG. 31An embodiment of a 3D memory chip, 3D memory computing chip, or 3D artificial intelligence (AI) chip according to the present invention is shown. The chip includes one or more arrays 259. Array 259 includes multiple... FIG. 30B The 3D array structures 252a-p are shown. The control unit 260 includes control logic, a central processing unit (CPU) or state machine, a data buffer, an input / output (I / O) buffer, a timing control unit, a voltage control unit, an error correction code (ECC) circuit, an address mapping unit, a read / write algorithm unit, and / or any other circuitry. The control unit 260 communicates with external systems via an I / O bus and transmits data to and from the data buffer 261. The data buffer 261 is connected to the data read / write circuitry of each of the 3D array structures 252a-p via an internal data bus.

[0341] Various 3D neural network arrays constructed according to the present invention are implemented as either "digital" neural networks or "analog" neural networks. (Reference) FIG. 28A The illustrated embodiment, using a digital neural network as an example, stores data in storage units (such as units 210a-n) that are digital data with values ​​such as 1 and 0. For analog neural networks, the data stored in storage units (such as units 210a-n) includes analog values.

[0342] FIG. 32A An example of an IV (current-voltage) curve associated with a digital neural network is shown. Cells of the network can be written using two threshold voltage levels, Vt0 and Vt1, as shown in Figures 270a and 270b. During a read operation, a read voltage VR between Vt0 and Vt1 is applied to the selected cell. If the cell's Vt is Vt0, the cell is turned on to conduct a cell current I0 to represent the data "0". If the cell's Vt is Vt1, the cell is turned off, and zero current is conducted to represent the data "1".

[0343] FIG. 32B An example of an IV curve associated with a simulated neural network is shown. The network cells can be programmed with different threshold voltages Vt0 to Vt7, as shown in Figures 270a-g. For demonstration purposes, FIG. 32BEight Vt levels are used as an example. Obviously, any other suitable number of Vt levels can be used. During a read operation, an appropriate voltage, such as VR, is applied to the word line. This turns on the cell and causes it to conduct different currents I0 to I7 depending on the cell's Vt level. Therefore, the cell's output current represents an analog value. This embodiment can be implemented using non-volatile memory such as flash memory, ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), memristor transistors (memristor transistors), and other types of memory.

[0344] FIG. 32C An example of an IV curve associated with a simulated neural network is shown. (e.g.) FIG. 32C As shown, analog input voltages VR0 through VR7 are supplied to the character lines. This will turn on the cell to generate analog output current. For example, for a cell with a threshold voltage of Vt0 270a, applying analog input voltages VR0 through VR7 will cause the cell to generate output currents I0 through I7.

[0345] FIG. 32D Another embodiment of implementing an analog neural network is shown, as illustrated in Figures 271a and 271b, using a memory cell that stores only two Vt levels, Vt0 and Vt1. This embodiment can be implemented using the floating body cell (FBC) mentioned above or a non-volatile memory cell. Reference FIG. 21A The 3D neural network array shown in this embodiment can have its character line layers 104a-m divided into multiple groups. Each group can consist of three character line layers, such as 104a to 104b with three data bits. For demonstration purposes, three data bits are used as an example. Obviously, any other suitable number of bits can also be used. Referring to Figure 25D, during a read operation, different voltages VR0 to VR2 can be applied to the three character line layers 104a to 104b of the selected group. This will cause the cells with Vt0271a to conduct currents I0 to I1 respectively. The voltages VR0 to VR2 are appropriately selected so that I2 is twice I1, and I1 is twice I0. Therefore, currents I0, I1, and I2 will represent the currents of bits 20, 21, and 22, respectively. If the selected cell is Vt1271b, the cell current will be zero. In this way, the three selected cells on the character line layers 104a to 104b will generate analog currents based on the three bits of data stored in the cell.

[0346] FIGS. 33A-33D An embodiment of the output neuron circuit is shown, for example. FIGS. 19A-20D The circuit 241a-p shown is shown.

[0347] FIG. 33AAn embodiment of the output neuron circuit is shown, which receives an analog input current I0 and generates an analog output voltage OUT. Devices 275, 276, 273, 274, and 278 form a comparator. Devices 273 and 274 are the input devices of the comparator.

[0348] Bit line 130 is connected to the gate of input device 273 of the comparator. The input voltage of input device 273 is determined by the ratio of the cell current I0 of bit line 130 to the load current of device 272. The gate of load device 272 is connected to a constant voltage VLOAD to generate a constant load current. The gate of another input device 274 is connected to a reference voltage VREF or a reference bit line REFBL. The comparator compares the input voltages of input devices 273 and 274 to generate an analog output voltage OUT.

[0349] FIG. 33B An embodiment of the output neuron circuit is shown, for example. FIGS. 19A-20D The circuit 241a-p shown is illustrated. This embodiment is similar to... FIG. 33A The illustrated embodiment is similar, except that bit line 130 is connected to the input devices 273a-c of the three comparators 280a-c. The gates of the other input devices 274a-c of the three comparators 280a-c are connected to either the three reference voltages VREF (0-2) or the three reference bit lines REFBL (0-2), respectively. The three comparators 280a-c form an ADC (analog-to-digital converter) for converting the analog input current from bit line 130 into three-bit output voltage data OUT (0-2).

[0350] FIG. 33C An embodiment of the output neuron circuit is shown, for example. FIGS. 19A-20D The circuit 241a-p shown is illustrated. This embodiment is similar to... FIG. 33A The illustrated embodiment is similar, except that bit lines 130a to 130c are connected to a digital-to-analog converter (DAC). In this embodiment, the memory cell stores digital data, such as... FIG. 32A As shown. The gates of the input devices 273a-c of the comparator are connected to three bit lines 130a-c. The three bit lines 130a-c are connected to three load devices 272a-c. The input voltage is determined by the ratio of the cell currents I0 to I2 of the bit lines 130a-c to the load currents of the load devices 272a-c.

[0351] The width ratios of input devices 273a, 273b, and 273c are 1:2:4, respectively. This configuration amplifies the currents from I0 to I2 by a factor of 1, 2, and 4, respectively. Therefore, the data stored in bit lines 130a, 130b, and 130c represents 20, 21, and 22 bits of data, respectively. The comparator compares the input with a reference voltage VREF or a reference bit line REFBL applied to the gate of another input device 274 to produce an analog output OUT.

[0352] FIGS. 33A-33C The circuits shown are examples used to demonstrate the operation and function of output neuron circuits. It will be apparent to those skilled in the art that these circuits can be modified or implemented using other circuit designs. Such variations and modifications should still fall within the scope of this invention.

[0353] FIG. 33D An embodiment of an implementation of an analog neural network using digital input data and weights is shown. This embodiment uses three digital bits D0, D1, D2 to represent eight levels of analog data and weights as an example. It is assumed that the three bits of the digital weights W0, W1, W2 are stored in cells 610a-610c and 611a-611c, respectively. The figure also shows input neuron circuits 657a-n or input drivers, and output neuron circuits 658a-c. In one embodiment, the output neuron circuits 658a-c are implemented using comparators, such as… FIGS. 16A-16B Comparator 233 or 234 is shown.

[0354] During operation, three digital inputs D0 through D2 are sequentially fed into the input neuron circuits 657a-n to generate three input signals for the input lines 655a-n. The input signals can be voltage levels, for example... FIG. 32A The data shown is VR for data 1 and 0V for data 0. The input signals turn units 610a-c on or off according to the weights stored in the units.

[0355] When bit D0 is fed to the input neuron circuits 657a-n, the corresponding output neuron circuit 658a is activated to sense the current on output line 656a. This configuration allows output neuron circuit 658a to sense the current flowing through cells 610a and 611a storing W0, generating output S0. Next, when bit D1 is fed to the input neuron circuits 657a-n, the corresponding output neuron circuit 658b is activated to sense the current on output line 656b. This configuration allows output neuron circuit 658b to sense the current flowing through cells 610a and 611a storing W1, generating output S1. Next, when bit D2 is fed to the input neuron circuits 657a-n, the corresponding output neuron circuit 658c is activated to sense the current on output line 656c. This configuration allows output neuron circuit 658c to sense the current flowing through cells 610a and 611a storing W2, generating output S2. The data converter 659 converts S0 to S2 into three digital output bits D0' to D2'. By using this process, a simulated neural network can be implemented using digital data and digital weights.

[0356] FIGS. 34A-34B An embodiment of the present invention is shown, which implements an analog neural network using a memory cell (e.g., DRAM or floating cell) with only two Vt levels. For illustration, an example is used where three data bits represent eight analog levels.

[0357] FIG. 34A An embodiment is shown, in which word lines 206a-c are connected to the input neuron circuit, and bit lines 204a-c are connected to the output neuron circuit. It is assumed that three storage units 210a-c are used to store bits D0 to D1, each storing a digital bit 1 or 0.

[0358] FIG. 34B A graph showing the relationship between cell current and gate voltage is presented. For example, FIG. 34B Figures 271a and 271b show the cell currents of data 1 and data 0 relative to the gate voltage, respectively.

[0359] Refer again FIG. 34A The three storage cells 210a-c are located in the three word lines 206a-c. Three inputs IN0 to IN2 are supplied to the three word lines, representing three bits of data from the input signal. If the input data bit is 1, then the word lines are supplied with... FIG. 34B The voltage VR3 is shown. If the input data bit is 0, 0V is supplied to the word line to disconnect the cell.

[0360] Three currents I0, I1 and I2 are supplied to the three power supply lines 207a-c respectively. FIG. 34BThe current levels I0, I1, and I2 are shown, where I1 is twice I0 and I2 is twice I1. Therefore, I0, I1, and I2 represent the three current levels of the three-digit data D0, D1, and D2.

[0361] Assume VR0, VR1, and VR2 are the gate voltages that enable cell currents I0, I1, and I2, respectively. The voltage VR3 applied to word lines 206a to 206c must be higher than VR2. This allows word line voltage VR3 to turn on cells 210a to 210c, thereby enabling the conduction of currents I0 to I2.

[0362] If the data stored in cells 210a-c is 1, these cells will be turned on to transfer the currents I0-I2 from source lines 207a-c to bit line 205a. If the data stored in cells 210a-c is 0, these cells will be turned off. The currents flowing through cells 210a-c will merge in bit line 205a to form a current "Ib". Current Ib is sent to the output neuron circuit.

[0363] Similarly, currents I0 to I2 flow through units 211a-c according to the data stored in units 211a-c and are combined in bit line 205b. Likewise, depending on the data stored in units 212a-c, currents I0 to I2 flow through units 212a-c and are combined in bit line 205c. Bit lines 204a-c are connected to the output neuron circuitry.

[0364] In another embodiment, the current direction is reversed to flow from bit lines 204a-c to source lines 207a-c. In this embodiment, three currents I0, I1, and I2 are applied to the three bit lines 204a-c, respectively. The current flows through the cell and merges in the source lines 207a-c.

[0365] FIG. 34C An embodiment according to the present invention is shown. This embodiment is related to... FIG. 34A The illustrated embodiment is similar, except that the input neuron circuitry is connected to source lines 207a-c instead of word lines 206a-c. The three source lines 207a-c are supplied with N0-IN2 respectively to represent the three bits of data of the input signal. The source lines 207a-c are supplied with three current levels I0, I1, and I2 respectively. FIG. 34B The diagram shows the current levels I0, I1, and I2. If the input data bit is 0, no current is supplied to the source lines 207a-c.

[0366] Supply voltage VR3 to the three character lines 206a-c, such as FIG. 34BAs shown, this voltage is higher than VR2. Therefore, if the data stored in cells 210a-c is 1, the word line voltage VR3 will turn on cells 210a-c to transfer currents I0 to I2 from source lines 207a-c to bit line 205a. If the data stored in cells 210a-c is 0, the cell will be turned off. The current flowing through cells 210a-c will combine in bit line 205a to form current "Ib". Current "Ib" will be sent to the output neuron circuit.

[0367] Similarly, depending on the data stored in units 211a-c, currents I0 to I2 flow through units 211a-c and are combined in bit line 205b. Similarly, depending on the data stored in units 212a-c, currents I0 to I2 flow through units 212a-c and are combined in bit line 205c. Bit lines 204a-c are connected to the output neuron circuitry.

[0368] In another embodiment, the current direction is reversed to flow from bit lines 204a-c to source lines 207a-c. In this embodiment, three currents I0, I1, and I2 are applied to the three bit lines 204a-c, respectively. The current flows through the cell and merges in the source lines 207a-c.

[0369] FIG. 34D Another embodiment according to the present invention is shown. This embodiment is related to... FIG. 34A The illustrated embodiment is similar, except that three different voltages VR0, VR1, and VR2 are supplied to the character lines 206a-c to represent three input data bits. For example... FIG. 34B As shown, this configuration will turn on data cell 1 to conduct three current levels I0, I1, and I2. If the input data bit is 0, 0V will be supplied to word lines 206a-c to turn off the cell.

[0370] A current "Is" higher than I2 is supplied to the source lines 207a-c. Therefore, if the data stored in cells 210a-c is 1, word line voltages VR0 to VR2 will turn on cells 210a-c, conducting currents I0 to I2 from the source lines 207a-c to the bit line 205a. If the data stored in cells 210a-c is 0, the cell will be turned off. The current flowing through cells 210a-c will combine in the bit line 205a to form a current "Ib". Current "Ib" will be sent to the output neuron circuit.

[0371] Similarly, depending on the data stored in units 211a-c, currents I0 to I2 may flow through units 211a-c and merge in bit line 205b. Similarly, depending on the data stored in units 212a-c, currents I0-I2 may flow through units 212a-c and merge in bit line 205c. Bit lines 204a-c are connected to the output neuron circuitry.

[0372] In another embodiment, the current direction is reversed to flow from bit lines 204a-c to source lines 207a-c. In this embodiment, current "Is" is supplied to all three bit lines 204a-c. The current flows through the cell and merges in the source lines 207a-c.

[0373] FIG. 35 An embodiment of a neural network architecture according to the present invention is illustrated. The neural network architecture includes multiple storage arrays 603a-c for simulating multilayer synapses of a neural network. The storage arrays 603a-c are connected via neuron circuits 630a-d. Each storage array (e.g., array 603b) receives input from a previous neuron circuit 630b (referred to as an input neuron circuit) and generates an output to the next neuron circuit 630c (referred to as an output neuron circuit).

[0374] FIG. 36A It shows FIG. 35 Detailed embodiments of the storage array 603b, input neuron circuit 630b, and output neuron circuit 630c are shown. The input neuron circuit 630b includes multiple input neuron circuits 601a-m. The output neuron circuit 630c includes multiple output neuron circuits 602a-n.

[0375] Storage array 603b includes a plurality of storage cells 610a to 613m. Storage cells 610a to 613m store data to represent the “weights” of synapses in a neural network. Storage cells 610a to 613m are connected to input lines 626a-m and output lines 620a-n. In one embodiment, input lines 626a-m are respectively… FIG. 10B The source lines 103a-m and output lines 620a-n shown are respectively FIG. 10B The bit lines 130a-n are shown. In another embodiment, the input lines 626a-m are respectively... FIG. 18A The bit lines 130a-n and output lines 620a-n shown are respectively FIG. 18A The source line 103a-m is shown.

[0376] Input lines 626a-m are connected to input neuron circuit 601a-m. Output lines 620a-n are connected to output neuron circuit 602a-n. Storage cells 610a-m and 611a-m are connected to bit lines 620a and 620b, respectively. Bit lines 620a and 620b are connected to the positive and negative inputs of comparator 604a, respectively. When the data value stored in cell 610a-m increases, the output 621a of comparator 604a also increases. When the data value stored in cell 611a-m is high, the output 621a of comparator 604a becomes low. Therefore, storage cell 610a-m represents "positive weight," and storage cell 611a-m represents "negative weight."

[0377] Each output neuron circuit (e.g., circuit 602a) includes an output comparator 604a, a feedback comparator 605a, and a control circuit 606a. The output comparator 604a is used for forward propagation, and the feedback comparator 605a is used for backward propagation. During forward propagation, the input neuron circuits 601a-m apply input to input lines 626a-m. The input causes current to flow from input lines 626a-m through storage cells 610a to 613m to output lines 620a-n. The current depends on the input and the data weights stored in storage cells 610a to 613m. The current flowing through cells 610a-m is summed in output line 620a. The current flowing through cells 611a-m is summed in output line 620b.

[0378] Output comparator 604a receives input from bit lines 620a and 620b to produce output 621a. Output comparator 604a executes some activation function of the neurons in the neural network, such as sigmoid, ReLU, Binary, Tanh, or any other activation function. Control circuitry 606a passes the output 621a of output comparator 604a to output 622a. Output 622a can be used as input to the next memory array.

[0379] After the above process, the forward propagation can be performed in the next memory array to produce the output of the next memory array. This forward propagation can be repeated until the output of the last memory array is produced.

[0380] Backpropagation is used to "train" a neural network. During training, forward propagation is used to apply training data to the neural network to produce an output. This output is compared to a "target" output to determine the "error." Then, the backpropagation process is performed, updating the data (weights) stored in the memory cells based on the error. Forward and backpropagation can be performed alternately, and multiple iterations can be executed. The goal is to minimize the error through this training process.

[0381] During the reverse propagation process, control circuit 606a feeds the target from output 622a and compares the target with the output 621a of output comparator 604a to generate an error. Control circuit 606a then feeds the error to feedback comparator 605a to generate complementary outputs 623a and 624a. Complementary outputs 623a and 624a are applied to output lines 620a and 620b to modify the data in memory cells 610a-m and 611a-m. Appropriate write operation bias conditions are applied to memory cells 610a-m to modify the data in those cells.

[0382] For example, if the output is lower than the target, the control circuit 606a will generate a positive error in the feedback comparator 605a. The feedback comparator 605a will then generate complementary outputs 623a and 624b to increase the data weight of memory cells 610a-m and decrease the data weight of memory cells 611a-m. This process will increase the output 621a of the output comparator 604a to reduce the error between the output and the target.

[0383] Next, control circuit 606a applies a target to feedback comparator 605a to produce new outputs 623a and 624a. This causes current to flow from bit lines 620a-n through storage cells 610a to 613m and sum in input lines 626a-m. The current depends on the new outputs 623a and 624a and the data weights stored in storage cells 610a to 613m. Control circuit 606b-m converts the current in input lines 626a-m into voltages. These voltages become the target for input neuron circuits 601a-m.

[0384] Control circuit 606b-m compares the target with the outputs 621b and 621m of output comparator 604b-m to generate an error. Control circuit 606b-m then feeds the error to feedback comparator 605b-m to generate complementary outputs 623b-m and 624b-m. Complementary outputs 623b-m and 624b-m are sent to the output line 625a-m of the previous memory array to update the data in the memory cells of the previous memory array. This backpropagation process is repeated until all data stored in the memory cells of each memory array has been updated.

[0385] FIG. 36B This illustrates the use of exemplary storage cell technologies (e.g.) FIGS. 1A-7BAn embodiment of the memory array 603b, implemented using a floating body unit, flash memory unit, ferroelectric random access memory unit, memristor unit, or 3D floating body unit, is shown. In one embodiment, output lines 620a-n are connected to bit lines, and input lines 626a-m are connected to the source lines of memory cells 610a-m. In another embodiment, output lines 620a-n are connected to source lines, and input lines 626a-m are connected to the bit lines of memory cells 610a-m. The gate of memory cell 610a-m is connected to word line 627a-m. Word line 627a-m is connected to control circuitry 606b-m or another decoder circuit.

[0386] FIG. 37A It shows FIG. 35 A detailed embodiment of the storage array 603b, input neuron circuit 630b, and output neuron circuit 630c is shown. This embodiment is related to... FIG. 36A The illustrated embodiment is similar, except that storage cells 610a to 613m are arranged differently. In this embodiment, control circuitry 606b-m provides input data to input lines 626a-m and complementary input data to input lines 628a-m. Therefore, the data stored in storage cells 610a to 612a and 610m to 612m represents positive weights, and the data stored in storage cells 611a to 613a and 611m to 613m represents negative weights.

[0387] During forward propagation, comparator 604b of input neuron 601a receives input 625a from the previous storage array to produce complementary outputs 621b and 631b. Control circuit 606b passes complementary outputs 621b and 631b to input lines 626a and 628a, respectively. Storage cells 610a to 613m generate currents based on the input data and the data weights stored in storage cells 610a to 613m. The currents flow through storage cells 610a-m and are summed in output lines 620a-n. In output neuron circuit 602a, output comparator 604a converts the current from bit line 620a into complementary data 621a and 631a. Output comparator 604a executes a selected activation function for the neurons in the neural network, such as sigmoid, ReLU, Binary, Tanh, and others. The control circuit 606a passes complementary outputs 621a and 631a to the input lines 622a and 622b of the next memory array.

[0388] During backpropagation, control circuit 606a receives the target from input lines 622a and 622b of the next memory array and compares the target with outputs 621a and 631a to generate an error. Control circuit 606a feeds the error to feedback comparator 605a to generate output 623a, and applies output 623a to output line 620a to change the data weights stored in memory cells 610a-m and 611a-m. Appropriate write operation bias conditions are applied to memory cells 610a-m and 611a-m to change the data in the cells.

[0389] Current applied to bit lines 620a-n flows through storage cells 610a to 613m and is summed in input lines 626a-m and 628a-m. Control circuit 606b-m converts these currents into voltages. These voltages are used as targets for the input neuron circuit 601a-m. Control circuit 606b-m compares the target with the output 621b-m of output comparator 604b-m to generate an error. Control circuit 606b-m then feeds the error to feedback comparator 605b-m to generate output 623b-m. Output 623b-m is applied to the output line 625a-m of the previous storage array to update the data in the storage cells of the previous storage array. This backpropagation process is repeated until all the data stored in the storage cells of each storage array has been updated.

[0390] FIG. 37B This illustrates the use of exemplary storage cell technologies (e.g.) FIGS. 1A-3B An embodiment of the memory array 603b implemented using a floating body unit, flash memory unit, ferroelectric random access memory unit, memristor unit, or 3D floating body unit is shown. In one embodiment, output lines 620a-n are connected to the bit lines of memory cells 610a to 613m, and input lines 626a-m and 628a-m are connected to the source lines of memory cells 610a to 613m. In another embodiment, output lines 620a-n are connected to the source lines of memory cells 610a to 613m, and input lines 626a-m and 628a-m are connected to the bit lines of memory cells 610a to 613m. The gates of memory cells 610a to 613m are connected to word lines 627a-m. Word lines 627a-m are connected to control circuitry 606b-m or another decoder circuit.

[0391] FIG. 37C An embodiment of a storage array 603b, an input neuron circuit 630b, and an output neuron circuit 630c is illustrated. The storage array 603b uses exemplary storage cell technologies (e.g., FIGS. 1A-3B This is implemented using the shown floating body unit, flash memory unit, ferroelectric random access memory unit, memristor unit, or 3D floating body unit. This embodiment is similar to... FIG. 36BThe illustrated embodiment is similar, except that word lines 627a-n are connected to decoder circuit 654. Decoder circuit 654 selects a subset of word lines 627a-n, such as 1, 2, 4, 8, 16, or any suitable number of word lines. This process allows current to flow only through the cells of the selected word lines. For example, assuming only word line 627a is selected, current will flow only from input lines 626a-m and 629a to 628m to output line 620a to produce the output of output neuron circuit 602a. Decoder circuit 654 sequentially selects a subset of word lines to produce the output of output neuron circuit 602a-n until all required word lines have been selected. By using this process, the peak current experienced during operation is significantly reduced.

[0392] FIG. 37D An embodiment of the storage array 603b, the input neuron circuit 630b, and the output neuron circuit 630c is shown. This embodiment is similar to... FIG. 37C The illustrated embodiment is similar, except that word lines 627a-n are connected to the source or drain of cells 610a to 613m. Input lines 206a-m and 208a-m are connected to the gates of cells 610a to 613m. During operation, decoder circuit 654 selects a subset of word lines 627a-n to supply current only to the selected cells. The decoder circuit sequentially selects a subset of word lines to generate the output of output neuron circuit 602a-n until all required word lines have been selected. By using this process, the peak current experienced during operation is significantly reduced. It should be noted that the architecture of the embodiments shown in Figures 30C to 30D is also applicable to other array architectures, such as... FIG. 36B The architecture shown or any other suitable architecture.

[0393] FIGS. 38A-38D Embodiments of the layout arrangement of the storage arrays and neuron circuits according to the present invention are shown. These embodiments include multiple storage arrays 603a-i and neuron circuits 630a-l, such as FIGS. 36A-37D As shown. Reference FIG. 36A Since the input lines 626a-m and the output lines 620a-n are arranged in a vertical direction, the input neuron circuit 630b and the output neuron circuit 630c are located on two adjacent sides of the storage array 603b.

[0394] FIG. 38A An embodiment of the layout arrangement of multiple storage arrays 603a-d and neuron circuits 630a-e is shown. Input data is fed to the first neuron circuit 630a and then propagates through the storage arrays 603a-d and the neuron circuits 630b-e. Although this embodiment uses four storage arrays as an example, it is clear that this arrangement is applicable to any number of storage arrays.

[0395] FIG. 38B An embodiment of the layout arrangement of the storage arrays and neuron circuits according to the present invention is shown. In this embodiment, input data is fed to a first neuron circuit 630a and then propagates through multiple storage arrays 603a to 603d and neuron circuits 630b-d. The output data of the last storage array 603d is fed back to the first neuron circuit 630a. This forms a “closed-loop” neural network architecture. This architecture allows data to propagate continuously through storage arrays 603a-d for multiple rounds. In each round, different storage units in storage arrays 603a-d are selected. Propagation is repeated as needed for multiple rounds. This architecture provides the flexibility to simulate (e.g., provide the same functionality) neural networks of any number of layers. For example, if the architecture includes M storage arrays and propagation is repeated N rounds, then the architecture simulates a neural network of M multiplied by N layers. Although the illustrated embodiment uses four storage arrays as an example, it will be apparent to those skilled in the art that a closed-loop architecture can include any number of storage arrays.

[0396] FIG. 38C An embodiment of the layout arrangement of the storage array and neuron circuits according to the present invention is shown. In this embodiment, the neuron circuits 630a and 630b are bidirectional, rather than unidirectional. Referring now... FIG. 36A Using output neuron circuit 602a as an example, in the first direction, comparator 604a is used as an output comparator, and comparator 605a is used as a feedback comparator. In this configuration, 620a and 620b are inputs, and 622a is the output. In the second direction, comparator 605a is used as an output comparator, and comparator 604a is used as a feedback comparator. In this configuration, 622a is an input, and 620a and 620b are outputs. The direction can be changed by control circuit 606a.

[0397] Refer again FIG. 38C In the first propagation direction, input data is fed to input neuron circuit 630a and then propagates through storage array 603a to output neuron circuit 630b. Then, in the second propagation direction, the orientations of neuron circuits 630a and 630b are changed so that the output of neuron circuit 630b is fed back to storage array 603a and then to neuron circuit 630a.

[0398] During the operation in the second propagation direction, different storage cells in storage array 603a are selected. Then, in the third propagation direction, the directions of neuron circuits 630a and 630b are changed again, and the output of neuron circuit 630a is fed back to storage array 603a, and then to neuron circuit 630b. This procedure is repeated as needed to simulate neural networks of any number of layers using only one storage array 603a.

[0399] FIG. 38D An embodiment of the layout arrangement of the storage array and neuron circuit according to the present invention is shown. In this embodiment, multiple storage arrays 603a to 603i are connected via neuron circuits 630a-l, as shown. FIG. 38C As described in the illustrated embodiment, the neuron circuits 630a-l are bidirectional. The direction of each neuron circuit 630a-l can be freely configured. For example, for neuron circuit 630a, the output direction can be set from neuron circuit 630a to storage array 603a or 603d. Furthermore, each neuron circuit 630a-l can be independently disabled, thus preventing data from flowing through it. In one embodiment, this functionality is achieved using a tri-state buffer. For example, in one embodiment, neuron circuit 630c is disabled so that data can propagate from neuron circuit 630b to storage array 603b, and then to neuron circuit 630d. By using this process, the storage array and neuron circuits can be freely configured to form any type of neural network.

[0400] FIG. 39A It shows FIG. 38B An embodiment of the layout arrangement of the 3D storage array and neuron circuits in the illustrated architecture is shown. As an example, a block 640 comprising four 3D storage arrays 603a-d is shown. The four neuron circuits 630a-d are respectively located below the 3D storage arrays 603a to 603d.

[0401] FIG. 39B It shows FIG. 39A The layout of the neuron circuits 630a-d is shown. Additional circuitry 641a-d is also shown, including circuitry such as control logic, decoders, data buffers, and data buses.

[0402] FIG. 39C The connection between the neuronal circuit and the 3D storage array according to the present invention is shown. (Example) FIG. 39A As shown, the 3D storage arrays 603a-d (not shown) are located above the neuron circuits 630a-d. For the 3D storage array 603a (not shown), input lines 641a-m are connected to the input neuron circuit 630a, and output lines 642a-n are connected to the output neuron circuit 630b. The contact points 653a-h connecting the input and output lines to the neuron circuits are also shown in the figure.

[0403] As described above, the output neuron circuit 630b also serves as the input neuron circuit for the next 3D storage array 603b (not shown). The input neuron circuit 630b is connected to input lines 641a-m, and output lines 644a-m are connected to the output neuron circuit 630c. The output neuron circuit 630c also serves as the input neuron circuit for the next 3D storage array 603c (not shown). The input neuron circuit 630c is connected to input lines 645a-m, and output lines 646a-n are connected to the output neuron circuit 630d. The output neuron circuit 630d also serves as the input neuron circuit for the next 3D storage array 603d (not shown). The input neuron circuit 630d is connected to input lines 647a-n, and output lines 648a-m are connected to the output neuron circuit 630a, which also serves as the input neuron circuit for the next 3D storage array 603a (not shown).

[0404] FIGS. 40A-40D A storage array comprising multiple blocks is shown.

[0405] FIG. 40A An embodiment of a storage array is shown, comprising four blocks 640a-d (separated by thick lines). The neuronal circuits in each block 640a-d (e.g., neuronal circuits 630e-h in block 640b) are arranged with the same orientation as the neuronal circuits 630a-d in block 640a.

[0406] FIG. 40B An embodiment is shown in which the orientation of the neuronal circuits 630e-h in block 640b is different from (a mirror image) of the neuronal circuits 630a-d in block 640a. Similarly, the orientation of the neuronal circuits in blocks 640c and 640d is a mirror image of the orientation of the neuronal circuits in blocks 640a and 640b. This layout arrangement provides a better... FIG. 40A The illustrated embodiment features a simpler data bus layout.

[0407] FIG. 40C An embodiment of a storage array comprising 16 blocks 640a-p (separated by thick lines) is shown.

[0408] FIG. 40D An embodiment of a memory array comprising 64 blocks 640a-n (separated by thick lines) is shown. It is important to note that when the array is divided into more blocks, the lengths of the input and output lines become shorter. Shorter lines reduce the resistance-capacitance (RC) delay of the input and output lines, thereby improving the speed performance of the memory array. It should also be noted that when comparing… FIG. 40A and FIG. 40C When the neuron circuit 630a is in the middle, FIG. 40CThe layout width of the 630a neuron circuit is FIG. 40A The layout width of the 630a neuron circuit is half that of the 630a circuit, but FIG. 40C The layout area of ​​the 630a neuron circuit is FIG. 40A The layout area of ​​the 630a neuron circuit is 1 / 4 of the total area. This means... FIG. 40A The number of input lines in the circuit is reduced by half, while the number of neuron circuit units is reduced to one-quarter. Therefore, special designs are needed to address this mismatch.

[0409] FIG. 41 An embodiment according to the present invention is shown for resolving the aforementioned mismatch problem. This embodiment is related to... FIG. 36A The illustrated embodiment is similar, except that a multiplexer circuit 650 is added between the input neuron circuit 601a and the input lines 620a-m, and a multiplexer circuit 653 is added between the output neuron circuit 602a and the output lines 620a-n. It should also be noted that the array can have multiple input neuron circuits (such as 601a-m) and multiple output neuron circuits (such as 602a-n), as... FIG. 36A As shown. FIG. 41 As an example, a circuit with only one input neuron 601a and an output neuron 602a is shown.

[0410] Multiplexer circuit 650 selects one input line from multiple input lines 626a-m to connect to input neuron circuit 601a. ​​Multiplexer circuit 651 selects one output line from multiple output lines 620a-n to connect to output neuron circuit 602a. This configuration solves the aforementioned mismatch problem.

[0411] FIG. 42 Another embodiment of the layout and connection of the neuronal circuit according to the present invention is shown. This embodiment is related to... FIG. 40C The illustrated embodiment is similar, except that additional channel gates, such as channel gates 652a-n, are added between the memory arrays to connect the input and output lines, as shown. When channel gate 652a is enabled, input lines 641a-m and 642a-m are connected. This configuration extends the output lines from the original 645a-n to 645a-n and 649a-n. Therefore, the number of output lines is doubled. When channel gates 652a, 652b, and 652c are enabled, input lines 641a-m, 642a-m, 643a-m, and 644a-m are connected. This configuration quadruples the number of output lines.

[0412] A similar method can be used to expand the number of input lines. When channel gate 652d is enabled, output lines 645a-n and 646a-n are connected. This configuration doubles the number of input lines. When channel gates 652d, 652e, and 652f are enabled, output lines 645a-n, 646a-n, 647a-n, and 648a-n are connected. This configuration quadruples the number of input lines. By selectively enabling channel gates 652a-n, the number of input and output lines of the neural network can be flexibly configured.

[0413] FIG. 43A An embodiment of the storage array and neuron circuit architecture according to the present invention is illustrated. This embodiment simulates a neural network where the amount of input data is greater than the number of input neuron circuits, just like... FIG. 43B The neural network shown.

[0414] FIG. 43B A neural network with a large amount of input data is shown. Assume the amount of input data is greater than... FIG. 43A The number of input neuron circuits 630a shown. For example... FIG. 43B As shown, the input data is divided into input data groups 1 to N. The amount of data in each group is equal to or less than the number of input neuron circuits 630a.

[0415] Refer again FIG. 43A Input data groups 1 to N are sequentially loaded into the input neuron circuit 630a and stored in input data buffers (also called data registers 663a-n), respectively. In one embodiment, input data buffers 663a-n are implemented using static random access memory (SRAM). Then, the input neuron circuit 630a feeds the data stored in the input data buffers 663a to a storage array to generate output data in the output neuron circuit 630b, and stores the data in the output data buffer 664a. This operation simulates a neural network between neuron groups 660a and 661a, such as... FIG. 43A As shown in the image. FIG. 43A The input neuron circuits 630a and 630b in the model respectively simulate... FIG. 43B Neuron groups 660a and 661a.

[0416] Next, the input neuron circuit 630a repeats the above operation to feed the next set of input data stored in the input data buffers 663a-n to the storage array 603a to produce output data. This operation is repeated until all the sets of input data stored in the input data buffers 663a-n have been processed and the output data has been stored in the output data buffers 664a-n. For each set of input data, a different storage cell in the storage array 603a is selected to represent it. FIG. 43BThe synapses between neuron groups 660a-n and neuron group 661a are shown. The output neuron circuit 630b combines the data stored in data buffers 664a-n to generate... FIG. 43B The final output data of neuron group 661a-n is shown.

[0417] The above description demonstrates the operation used to simulate the neural network between the first layer of neurons 660a-n and neuron groups 661a-n. This operation is repeated to simulate the next layer of the neural network until the entire neural network is simulated and the final output data of the last layer of neurons is produced.

[0418] The next step depends on the architecture of the memory array and the neuron circuitry. If using... FIGS. 38A-38B and FIG. 38D The architecture shown repeats the above operations using the data stored in data buffers 664a-n to process the output data based on the cell data weights stored in the storage array 603b, and stores the output data in output data buffers 665a-n.

[0419] If using FIG. 38C In the architecture shown, the next operation will reverse the direction of input and output by using the data stored in data buffers 664a-n to generate output data based on the cell data weights stored on the storage array 603a, and store the output data in data buffers 663a-n.

[0420] FIG. 43C An embodiment of a storage array and neuron circuit architecture is illustrated. This embodiment is related to... FIG. 43A The illustrated embodiment is similar, except that the input data buffers 663a-n are omitted. FIG. 43B The input data sets 1 to N shown are sequentially loaded from the system into the neuron circuit 630a to generate outputs, and the outputs are stored in the output data buffers 664a-n respectively.

[0421] FIG. 43D An embodiment of a storage array and neuron circuit architecture is illustrated. This embodiment is related to... FIG. 43A The illustrated embodiment is similar, except that the input data sets are stored in storage units. For example, input data sets 1 to N are sequentially loaded into neuron circuit 630a and then written to pages 666a-n in storage array 603a, respectively.

[0422] Next, neural circuit 630a sequentially loads data from pages 666a-n to process the output data via output neuron circuit 630b based on the weights of the unit data stored in storage array 603a. Output neuron circuit 630b writes the output data for each data group into pages 667a-n in storage array 603b. This operation simulates... FIG. 43B The first layer of the neural network shown is between neuron group 660a-n and neuron group 661a-n.

[0423] Next, the neuron circuit 630b reads data from pages 667a-n and repeats the above operation to simulate the next layer of the neural network. This embodiment eliminates the need for a data buffer (e.g., ...). FIG. 43A The data buffers 663a-n, 664a-n and 665a-n shown in the figure reduce layout size and die cost.

[0424] FIG. 43E An embodiment of a storage array and neuron circuit architecture is illustrated. This embodiment is related to... FIG. 43D The illustrated embodiment is similar, except that the output data set is stored in pages 667a-n of the same storage array 603a as the input data set. This embodiment is applicable to... FIG. 38C The single storage array architecture is shown. In one embodiment, if a 3D storage array is used, the input data pages 666a to 666n and the output data pages 667a to n are located in different layers of the storage array.

[0425] While 3D cell structures and 3D array structures are illustrated according to some embodiments of the present invention, the application of the present invention is not limited to 3D cell and array structures. All disclosed embodiments, including but not limited to array architectures, neural circuit architectures, layout arrangements, operations, bias conditions, and circuit designs, are applicable to any suitable storage technology, including two-dimensional (2D) and three-dimensional (3D) cell structures and array structures, and are particularly suitable for… FIGS. 16A-17B , FIGS. 19A-20D , FIGS. 32A-32D , FIG. 36A To Figure 36D, FIG. 41 and FIGS. 43A-43E The example shown.

[0426] FIG. 44A An embodiment of a circuit architecture according to the present invention is shown, which is configured to convert cell currents into digital data. For illustration, it is assumed that each input contains four bits of data D0-3 (e.g., 668a-n), and each synapse contains four bits of weight W0-2 stored in four cells (e.g., 610a-d and 611a-d).

[0427] The operation of this embodiment is similar to FIG. 33DThe illustrated embodiment is similar. First, bit D0 of the input data 668a-n is applied to the input neuron circuits 657a-n to generate the input signals for the input lines 655a-n. The input signals include voltage levels, such as... FIG. 32A The data shown is VR for data 1 and 0V for data 0. The input signals turn units 610a to 611a on or off according to the weights stored in the units. This operation simulates... FIG. 13B The multiplication function described in [the document] is used. The currents from units 610a to 611a are added together in output line 656a, simulating [the multiplication function]. FIG. 13B The summation function 222 is described in the text.

[0428] When bit D0 is fed to the input neuron circuits 657a to 657n, the corresponding output neuron circuit 670a is activated to sense the current on the output line 656a. Each output neuron circuit 670a-d includes an analog-to-digital (A / D) converter circuit. For illustration, assume 16 input data points 668a-n are applied. This will generate 16 levels of current on the output line 656a. Therefore, the A / D converter in the output neuron circuit 670a converts the current on the output line 656a into 4-bit data DA0-3.

[0429] Next, the D1, D2, and D3 bits of the input data 668a-n are sequentially applied to the input neuron circuits 657a-n. The above operation is repeated by activating the corresponding output neuron circuits 670b-d respectively, thereby generating three other sets of output data DB0-3, DC0-3, and DD0-3 respectively.

[0430] FIG. 44B An embodiment of the circuit implementation according to the present invention is shown for converting four sets of output data DA0-3, DB0-3, DC0-3, and DD0-3 into eight-bit data. The circuit includes two eight-bit shift registers, 672a and 672b. The operation comprises three cycles. In cycle 1, the first set of data DA0-3 and the second set of data DB0-3 are located in shift registers 672a and 672b, respectively.

[0431] FIG. 44C The arrangement of data in shift registers 672a and 672b is shown. Data positions 671a and 671b show the bit positions of DA0-3 and DB0-3 in shift registers 672a and 672b, respectively. Because DA0-3 represents the result of multiplying the D0 bit of the input data by the W0 bit of the weight, DA0-3 is shifted into bit D0-3 of shift register 672a. Because DB0-3 represents the result of multiplying the D1 bit of the input data by the W1 bit of the weight, DB0-3 is shifted into bits D1-4 of shift register 672b. Then, refer to... FIG. 44BThe adder circuit 673 adds DA0-3 in shift register 672a and DB0-3 in shift register 672b to generate output data DE0-7 stored in the third shift register 672c.

[0432] In cycle 2, the output data DE0-7 and the next set of data DC0-3 are loaded into shift registers 672a and 672b, respectively. FIG. 44C The diagram 671c shows the position of bit DC0-3 in the shift register. Since DC0-3 represents the result of multiplying the input data (bit D2) by the weight (bit W2), DC0-3 is shifted into bits D2-5 of the shift register. Then, refer to... FIG. 44B The adder circuit 673 adds DE0-7 and DC0-3 in shift registers 672a and 672b to generate output data DF0-7 stored in the third shift register 672c.

[0433] In cycle 3, the output data DF0-7 and the next set of data DD0-3 are loaded into shift registers 672a and 672b, respectively. FIG. 44C Table 671d shows the position of bit DD0-3 in the shift register. Since DD0-3 represents the result of multiplying the input data's D3 bit by the weight's W3 bit, DD0-3 is shifted into bits D3-6 of the shift register. Then, refer to... FIG. 44B The adder circuit 673 adds DF0-7 and DD0-3 in shift registers 672a and 672b to produce output data DG0-7 stored in the third shift register 672c. Therefore, data DG0-7 represents the result of multiplying and adding the 16 input data 668a-n with the weights stored in cells 610a-d. Next, the output data DG0-7 is sent to an activation function generator (not shown) to produce the final output data. In the previous embodiment, the number of input data, the number of input data bits, the number of weight data bits, and the number of shift register data bits are merely examples. In other embodiments, the invention can be applied to any variation of the above parameters.

[0434] FIG. 45A An embodiment according to the present invention is illustrated. In this embodiment, it is assumed that the simulated neural network contains a large amount of input data 668a-n. To reduce peak current consumption and error rate caused by variations in cell current, the input data 668a-n and the corresponding cells are divided into multiple groups, such as groups 675a-k. Each group has any suitable number of inputs. For illustration, it is assumed that the total number of input data 668a-n is 256. The 256 input data 668a-n are divided into 16 groups. Each group has 16 input data, such as input data 668a-i. It is also assumed that each input data includes 4 data bits D0-3, such as...FIGS. 44A-44C The illustrated embodiment. Therefore, FIGS. 44A-44C The description of the illustrated embodiment can be used to explain the operation of each set of input data in this embodiment.

[0435] FIGS. 45B-45C An exemplary operation of the neural network according to the present invention is shown. First, the D0 bits of 16 sets of input data are loaded sequentially to generate 16 sets of data DA0-3674a-n, as follows. FIG. 45B As shown. FIG. 45C As shown, 16 sets of data DA0-3 are sequentially loaded into shift registers 672a-b to add the 16 sets of data DA0-3 together, producing the following result: FIG. 45B The output shown is DA'0-7678a.

[0436] FIG. 45C The operation shown is the same as FIG. 44C The operation is similar. First, the data DA0-3 from groups 0 and 1 are loaded into shift registers 672a and 672b, and then added together by adder circuit 673 to produce output DOUT stored in register 672c. Then, DOUT is loaded into shift register 672a and added to DA0-3 from the next group 2. This operation is repeated until DA0-3 from all 16 groups has been added. Then, the above operation is repeated for bits D1-3 of the input data to produce... FIG. 45B DB'0-7 678b, DC'0-7 678c, and DD'0-7 678d are shown.

[0437] FIG. 45D This demonstrates how to add the data DA'0-7, DB'0-7, DC'0-7, and DD'0-7 together to produce the final output DG'0-11. FIG. 45D The operation shown is the same as FIG. 44C The operation is similar, except that each shift register 672a-c includes 12 bits. First, DA'0-7 and DB'0-7 are loaded into shift registers 672a and 672b and added by adder circuit 673 to produce output DE'0-11 stored in register 672c. Next, DE'0-11 is loaded into shift register 672a and added with DC'0-7 to produce output DF'0-11. Next, data DF'0-11 is loaded into shift register 672a and added with data DD'0-7 to produce the final output DG'0-11. Therefore, FIGS. 45A-45D The operation shown performs multiplication and summation of 256 input data points 668a-n and weights stored in groups 675a-k to produce the final data DG'0-11. DG'0-11 is then sent to an activation function generator (not shown in the figure) to produce the final output data.

[0438] FIG. 46A An exemplary current distribution for the sum (cumulative) of multiple cells is shown. It is assumed that the current in each cell varies, as indicated by the gray shading. When the total current of more cells is accumulated, the variation becomes larger, leading to a failure, as shown in cells 8 through 11.

[0439] FIG. 46B The relationship between the change in unit current and the number of working units is shown. The greater the change in unit current, the fewer the total number of working units.

[0440] FIG. 47A An embodiment of a storage cell network according to the present invention is shown, which is configured to resolve cell summation failures. FIG. 47A It includes multiple storage cells, such as storage cells 682a-n. In one embodiment, each storage cell stores one bit of digital data. In another embodiment, the storage cells (e.g., storage cells 682a-n) store multiple levels of analog data. The storage cells can be any suitable type of storage cell, such as flash memory cells, floating-body cells, ferroelectric random access memory (FRAM) cells, resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, or phase-change memory (PCM) cells. It should be noted that the embodiments disclosed herein are not limited to these cell structures and can be applied to any type of storage cell structure, such as planar cell structures and intersection-type cell structures.

[0441] refer to FIG. 47A As shown, the input lines 680a-f to the network are divided into multiple (0 to M) groups 681a-m. Each group includes multiple input lines; for example, group (0) 681a includes input lines 680a-b. The number of input lines in each group must not exceed [number missing]. FIG. 46A The number of cells shown. During operation, groups 681a-m are sequentially selected via selector (S1) (e.g., selecting appropriate input lines) to limit the number of cells selected in each output line within the selected output line group, for example, from group '0 (683a-b) to group 'N (683a-n). Output lines 683a-n are also organized into multiple groups (groups '0 to N).

[0442] Multiplexer 684 sequentially selects output line groups (e.g., group '0 including output lines 683a to 683b) and passes the sum of the cell currents to neuron circuit 685. Neuron circuit 685 includes an analog-to-digital converter, operational amplifier, or comparator for converting the sum of cell currents into digital data. In one embodiment, the converter, amplifier, or comparator circuit also executes an "activation function" (e.g., a sigmoid function).

[0443] FIG. 47B It shows the result of FIG. 47A The storage cell network embodiment shown simulates an equivalent neural network architecture. FIG. 47A The input lines 680a-b are simulated. FIG. 47B Neurons 690a-b are shown. For example, FIG. 47A Input line 680e-f (group M) simulation FIG. 47B The neuron shown is 690e-f (group M). FIG. 47A The output lines 683a-b (group '0) are simulated. FIG. 47B Neurons 693a-b (group '0) are shown in the diagram. FIG. 47A The output line 683m-n (group 'N) is simulated. FIG. 47B The neuron shown is 693m-n (group 'N').

[0444] FIG. 48A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown. The chip includes multiple planes 701a-n. Each plane includes one or more memory cell arrays, such as array 702a. A data buffer 703a applies input data to the input lines of array 702a. The input data includes multiple groups, for example, 16 groups of 16 inputs (16×16) as an example. FIGS. 47A-47B As shown.

[0445] The multiplication and summation functions of a neural network are performed by storage units to produce, for example, FIGS. 13A-13D The sum of the unit currents is shown. This sum of unit currents will be sent to the neuron circuit 704. The neuron circuit 704 converts the current into digital data. In one operating mode, the digital data will be sent to the data buffer 703a, and then to the input / output (I / O) buffer 705 for data output. This embodiment uses 16 groups of 16 inputs and outputs (16×16) as an example; however, any suitable number of inputs and outputs can be applied.

[0446] In another operating mode, the output data sent from the neuron circuit 704a to the data buffer 703a is sent back to the array 702a as input data for the next layer of the simulated neural network. After the input data is processed in the array 702a and the neuron circuit 704a, the next output data is sent to the data buffer 703a, and then sent back to the array 702a again as input data for the next layer of the simulated neural network. This process is repeated multiple times as needed to simulate a multi-layer neural network, such as... FIG. 13A As shown.

[0447] FIG. 48B An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown. This embodiment is related to...FIG. 48A The illustrated embodiment is similar, except for the addition of an additional data buffer 703b. Output data is sent from the neuron circuit 704 to the data buffer 703b, and then to the I / O buffer 705 for data output. This embodiment allows the chip to simultaneously input data to the data buffer 703a and output data from the data buffer 703b.

[0448] FIG. 49A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown. This embodiment is related to... FIG. 48A The illustrated embodiment is similar, except for the addition of an additional array 702b. This dual-array structure allows the two arrays 702a and 702b to alternately output data to the neuron circuit 704. While array 702a or 702b outputs data to the neuron circuit, the other array 702b or 702a simultaneously receives data from data buffers 703b or 703a. This process reduces latency while waiting for data input.

[0449] FIG. 49B This shows an example of a timing diagram that illustrates... FIG. 49A The operating waveforms of the illustrated embodiment are shown. Processing intervals 706a and 706b respectively show the intervals between data processing in arrays 1702a and 2702b and the output of data to neuron circuit 704. Intervals 707a and 707b respectively show the intervals between data output from neuron circuit 704 to data buffers 703a and 703b.

[0450] In another operating mode, the data output from the neuron circuit 704 to data buffers 703a and 703b is sent back to arrays 702a and 702b as input data for the next layer of the simulated neural network, thus simulating a multi-layer neural network, such as... FIG. 48A As shown.

[0451] FIG. 50A An embodiment of a circuit block diagram of an AI memory chip architecture according to the present invention is shown. This embodiment is related to... FIG. 49A The illustrated embodiment is similar, except that each array is divided into two or more subarrays, such as subarrays 702a, 702b, 702c, and 702d. Data buffers 703a-d apply input data to subarrays 702a-d respectively. Neuron circuit 704 independently outputs data to data buffers 703a-d. This embodiment allows the chip to input, output, and process data in parallel.

[0452] FIG. 50B An embodiment of a timing diagram is shown, which illustrates... FIG. 50AThe operating waveforms of the illustrated architecture are shown. Interval 708a shows the time interval during which arrays 1a and 702a process data and output it to neuron circuit 704. During interval 709a, arrays 1a and 702a process input data from data buffer 703a. When the data is ready, interval 709a shows when the data is output to neuron circuit 704 and then sent to data buffer 703b. Simultaneously, during interval 708b, array 2a and 702c process input data from data buffer 703c. When the data is ready (as shown during interval 709b), the data is output to neuron circuit 704 and then sent to data buffer 703d. Meanwhile, arrays 1a and 702a process the next input data from data buffer 703a in parallel, as shown during interval 708c.

[0453] The above operations can be repeated to input data from data buffers 703a-c, process the data in arrays 1a, 702a, and 2a, 702c, and output the data to neuron circuit 704, and then to data buffers 703b and 703d respectively. This embodiment allows the above operations to be performed continuously without a waiting period, thereby improving data processing throughput.

[0454] FIG. 50C An embodiment of a timing diagram is shown, which illustrates... FIG. 50A The operating waveforms of the architecture are shown. In another operating mode, the output data sent from the neuron circuit 704 to the data buffers 703b and 703d are sent back to the arrays 702b and 702d, respectively, as input data for the next layer of the simulated neural network, thus simulating a multi-layer neural network, such as... FIG. 48A As shown. In this operating mode, data is processed alternately by arrays 1a, 2a, 1b, and 2b, as shown respectively. FIG. 50C As shown at positions 708a, 708b, 708c, and 708d.

[0455] FIGS. 51A-51C An embodiment of the operating waveforms according to the architecture of the present invention is shown.

[0456] FIG. 51A The waveform illustrating the "random mode" of operation is shown. During interval 710, data is input to the chip. During interval 711, data is used... FIGS. 48A-50B The operations shown and described previously process data internally within the chip. During interval 712, the chip outputs data. This operation can be repeated with the next input data, as shown in intervals 713 and 714.

[0457] FIG. 51BThe waveform illustrating the "sequential mode" of operation is shown. During interval 710, data is input to the chip. During interval 711, a reference is used. FIGS. 48A-50B The operations shown and described previously process the data internally. Next, the output data is sent back to the array as input data for the next layer of the simulated neural network, as shown in the reference. FIGS. 48A-50B As previously described. Therefore, the output cycle is canceled. This operation can be repeated to simulate multi-layer neural networks, such as... FIG. 51B As shown in 715 and 716 in the figure. When simulating the required neural network, the output data can be emitted from a chip not shown in the figure.

[0458] FIG. 51C The diagram illustrates waveforms for "multi-chip" operation. This operation applies to memory products containing multiple chips, such as high bandwidth memory (HBM). Assume the product comprises eight chips as an example. During interval 717a, the system loads input data into the first chip. Once the data is input, the first chip can begin processing the data internally, as shown during interval 718a. This frees up the system data bus. Therefore, the system can continue loading input data into the next chip in parallel until all chips have been loaded, as shown during interval 717h. Once the data is loaded, each chip begins processing the data.

[0459] Once the data processing interval 718a of the first chip is complete, the system reads output data from the first chip or loads the next input data into the first chip, as shown during interval 717i. Once the next input data is loaded, the first chip begins processing the data, as shown during interval 718i. Then, the operations shown during intervals 717a-h are repeated to load the next input data into all chips and process the data internally, as shown during intervals 718a-h. This operation reduces latency and significantly improves data processing throughput.

[0460] FIGS. 52A-52B An embodiment of the chip layout plane according to the present invention is shown.

[0461] FIG. 52A The illustration shows a chip comprising multiple memory banks, such as banks 719a to 719m. Each memory bank processes one bit of input data. For example, assuming the input data has M bits, such as D0 to Dm, the chip can have M memory banks to process the data D0 to Dm. The chip includes multiple planes, such as planes 701a to 701n. Each plane includes multiple blocks (such as block 721a) for parallel data processing. This configuration significantly improves data processing throughput.

[0462] FIG. 52B It shows FIG. 52A An embodiment of the layout plane of block 721 is shown. Block 721 includes multiple arrays (e.g., arrays 702a and 702b), multiple neuron circuits (e.g., neurons 704a-d), and multiple data buffers (e.g., buffers 703a and 703b). This architecture allows multiple arrays to execute in parallel. FIGS. 48A-50B The operations shown greatly improve data processing throughput.

[0463] FIG. 53A An embodiment of a circuit architecture for converting unit current into digital data according to the present invention is shown. This embodiment is related to... FIG. 52A The illustrated embodiment is similar, except that the data bits of the input data (e.g., bits D0 to Dm) are processed in different memory banks, for example... FIG. 52A The storage bank 719 is shown. For example, assuming the input data contains 8 bits (D0–7) and the array comprises 8 storage banks, then each storage bank will process one bit of data.

[0464] FIG. 53A Blocks are shown (e.g.) FIG. 52A The array in block 721 shown (e.g.) FIG. 52B An embodiment of array 702a) is shown. As an example, assume the input contains 16 input data groups 730a-n. Each input group contains 16 bits of input data, such as bits 731a-i and bits 731j-n. Also assume the output contains 16 output line groups 732a-k. Each output group contains 16 output lines, such as output lines 656a-i and output lines 656j-m. It should be noted that the number of input groups, input data, output groups, and output lines described above are merely examples for illustrative purposes, and any other suitable number can be used.

[0465] Assuming the array resides in the memory bank containing data bits D0, each input data 731a-n is the D0 bit of the input data. Storage cells (e.g., cells 610a-d) store the W0 bits of the weights. The W0 bits of the weights correspond to the D0 bits of the input data. During operation, the input data groups 730a-n are sequentially applied to the input neuron circuit or input driver (e.g., circuits 657a-i) to generate data for the input lines (e.g., input lines 655a-i). This operation limits the number of inputs processed to prevent reference... FIGS. 46A-46B The resolution loss problem described.

[0466] Based on the weights stored in the cells, the input lines (e.g., input lines 655a-i) connect cells 610a-b and 611a-b. This process simulates the multiplication function of a neural network. The cell currents are summed in the output lines 656a-m. This process simulates the summation function of a neural network. The total current is sent to the neuron circuit 670a-m.

[0467] In one embodiment, the neuron circuit 670a-m executes an activation function (e.g., a sigmoid function or any other suitable function) to generate an output based on the total current. In this embodiment, the neuron circuit 670a-m includes operational amplifier circuitry for generating a non-linear output of the activation function.

[0468] In another embodiment, the neuron circuit 670a-m converts the total current into digital output data without using an activation function. The output data is then sent to other chips, such as a graphics processing unit (GPU), where the GPU executes the activation function. In this embodiment, the neuron circuit 670a-m includes an analog-to-digital (A / D) converter circuit.

[0469] FIG. 53B Another embodiment of the array architecture according to the present invention is shown. This embodiment is related to... FIG. 53A The illustrated embodiment is similar, except for the addition of a multiplexer 743. The multiplexer 743 selects one output line group (e.g., group 656a-i or group 656j-m) to connect to the neuron circuit 670a-i. This embodiment reduces the circuit size of the neuron circuit.

[0470] FIGS. 54A-54B An exemplary neuron circuit according to the present invention is shown. In one embodiment, the neuron circuit 670a-m includes a unit A / D converter, such as... FIG. 54A The converter shown. FIG. 54A The circuit shown includes a comparator or amplifier circuit 733 and a pull-down or pull-up device 734. The gate of the pull-down device is connected to a reference voltage VREF to allow the pull-down device to conduct a constant current. The current of the pull-down device 734 is proportional to the sum of the cell currents of the output line 656a, thereby generating an input voltage for the comparator 733. The input voltage is compared with a reference voltage VREF0 in another input 735 to generate the output data OUT. FIG. 53A The neuron circuit (e.g., circuit 670a) converts the total current of the input group (e.g., input data group 730a and units 610a to 611a) into unit data.

[0471] In another embodiment, the neuron circuit 670a-m includes a multi-bit A / D converter, such as... FIG. 54B The circuit shown is a multi-bit A / D converter. FIG. 54AThe circuit shown is similar, except that the input voltage of output line 656a is applied to multiple comparators or amplifiers 733a-k and then compared with multiple reference voltages (VREF0 to VREFk) to produce multi-bit outputs OUT0 to OUTk.

[0472] Note that the number of comparators 733a-k used can be any suitable number. For example, suppose each input data set (such as input data set 730a) contains M input data points, and the neuronal circuit (such as circuit 270a) contains K comparators. When 2K = M, the comparator outputs will have the full resolution of the input set. When 2K < M, the comparator outputs will reduce the resolution of the input set. In one embodiment, the number of comparators is determined based on a trade-off between the desired resolution and the number of comparators.

[0473] In another embodiment, the neuron circuit 670a-m includes logic circuitry (e.g. FIG. 45C The circuit shown is used to combine multiple output data from input data group 730a-n into one data. FIGS. 45A-45C The detailed description describes this operation.

[0474] FIG. 55 The representative block is shown (e.g.) FIG. 52A An array of blocks 721 shown (e.g.) FIG. 52B The embodiment shown is of array 702a) shown in the block. This embodiment is related to... FIG. 53A The illustrated embodiment is similar, except that each comparator 733a-m in the neuron circuit is connected to two output lines, such as lines 656a-b. Comparator 733a compares the voltages of output lines 656a and 656b to produce output OUT0. Output lines 656a and 656b are connected to the positive and negative inputs of comparator 733a, respectively. Therefore, the weights stored in cells 610a to 613a represent positive weights, and the weights stored in cells 610b to 613b represent negative weights.

[0475] FIG. 56A An embodiment of the array architecture according to the present invention is illustrated. The array is divided into multiple blocks, such as blocks 721a-m. Each block contains an input data buffer (e.g., buffer 703a-m), an array (e.g., array 702a-m), and a neuron circuit (e.g., circuit 704a-m). Each block 721a-m is further divided into multiple smaller arrays to reduce signal delay, similar to... FIG. 52B The example shown.

[0476] Blocks 721a-m are formed using any suitable array architecture shown in previous embodiments according to the invention. For example, using FIG. 53A or FIG. 53BThe array architecture shown is for example. (Reference) FIG. 56A The input data buffer 703a-m will hold different inputs (e.g., FIG. 53A The input data set 730a) shown is applied to each array 702a-m to produce FIG. 53A The output data set shown is 740a. FIG. 53A A detailed description is provided in the description.

[0477] Neuron circuits 704a-m generate output data sets 740a-n. These output sets are sent to output data buffers 741a-n, and then to activation circuits 742a-n to generate an output. Activation circuits 742a-n contain comparators, operational amplifiers, or A / D converters to generate the desired activation function.

[0478] FIG. 56B It shows the result of FIG. 56A The embodiment shown simulates the corresponding neural network layer. FIG. 56A The input data buffer 703a-m shown represents FIG. 56B The input neuron group 750a-m is shown in the figure. FIG. 56A The output data buffer 741a-n shown represents FIG. 56B The output neuron group 751a-n is shown in the figure. FIG. 56A The activation circuit 742a-n shown represents FIG. 56B The activation function group 752a-n is shown.

[0479] In another embodiment, the output data groups 740a-n sent to the output data buffers 741a-n are used FIGS. 45B-45D The illustrated embodiment combines multiple output data into a single output data group. Furthermore, by using... FIGS. 44B-44C The illustrated embodiment allows for the use of different memory banks (e.g.) FIG. 52A The output data in Bank 719a-m is merged into a single data D0-m.

[0480] FIG. 57A Another embodiment of the array architecture according to the present invention is shown. This embodiment is related to... FIG. 56A The illustrated embodiment is similar, except that the activation circuitry 742a-n is omitted. In this embodiment, the output data buffers 741a-n output data to external chips (such as graphics processing unit (GPU) chips or central processing unit (CPU) chips) to execute activation functions in these chips.

[0481] FIG. 57B It shows the result of Figure 57A The example shown simulates the corresponding neural network layer. Figure 57A The input data buffer 703a-m shown representsFigure 57B The input neuron group 750a-m is shown in the figure. Figure 57A The output data buffer 741a-m shown represents Figure 57B The output neuron group 751a-m is shown in the figure.

[0482] Figure 58A An embodiment of the array architecture according to the present invention is shown. This embodiment is related to... Figure 56A The illustrated embodiment is similar, except that it has only one output data buffer 741a and one activation circuit 742a. ​​In this embodiment, output data sets 740a-n are sequentially loaded into the output data buffer 741a from neuron circuits 704a-m. The output data buffer 741a outputs the previous data set to the activation circuit 742a and loads the next data set 704a-n in parallel. This configuration reduces the circuit size of the output data buffer and the activation circuit.

[0483] Figure 58B An embodiment of the array architecture according to the present invention is shown. This embodiment is related to... Figure 58A The illustrated embodiment is similar, except that the activation circuit 742a is omitted. The output data buffer 741a outputs data to an external chip (such as a graphics processing unit (GPU) chip or a central processing unit (CPU) chip) to execute the activation function in these chips.

[0484] Figure 59A A block according to the invention (e.g.) is shown. Figure 58A An embodiment of the detailed architecture of block 721a) shown in the diagram. This embodiment uses... Figure 57B The array architecture shown is an example. Note that this embodiment can be applied to other array architecture embodiments with slight modifications, based on this array architecture.

[0485] This block includes a memory array divided into multiple subarrays 702a-d to reduce signal delay. An input data buffer 703a applies multiple input data sets (e.g., input data group 730a) to selected input lines. Input drivers 744a-c are provided for the subarrays 702b-d. The input drivers 744a-d receive data from the input data buffer 703a and apply the same data from input data group 730a to input data groups 730b-d.

[0486] Each subarray (e.g., subarray 702a) includes multiple output line groups (e.g., output line groups 732a and 732e). Each output line group includes multiple output lines. Cells at the intersection of each input data group and output line group are selected, e.g., cells 745a-d. The selected cells 745a-d are then referenced. Figure 57AThe multiplication function generates output current for output lines 732a to 763d. Multiplexer circuits 743a-d select and connect output lines 732a to 752d to neuron circuits 704a-d. Neuron circuits 704a-d convert the current from output lines 732a-d into output data groups 740a-d.

[0487] Next, output data groups 740a-d will be sent together as output data group 740a to... Figure 57A and Figure 58A The output data buffer 741a is shown. Then, multiplexers 743a-d select the next output line group (e.g., output line group 732e-h) to connect to the neuron circuit 704a-d to produce the next output data group. This process is repeated until all the required output data groups are produced.

[0488] Figure 59B It shows Figure 59A An embodiment of the operating waveforms of the array architecture shown. At time T0, input data sets 730a-d are applied to the selected cells. After a delay time T1, the selected cells generate current based on the input data and the stored data. Starting from time T2, Figure 59A The multiplexers 743a-d shown sequentially select the first output line group 732a-d and the second output line group 732e-h, and so on, connecting them to the neuron circuit 704a-d to generate output data. After all the desired output groups have been selected, at time T3, the next input data is applied to begin the next cycle.

[0489] Figure 60A A block according to the invention (e.g.) is shown. Figure 58A An embodiment of the detailed architecture of block 721a) shown in the diagram. This embodiment is related to... Figure 59A The illustrated embodiment is similar, except that neural circuit 704a-b is located between the two sets of subarrays 702a-d and subarrays 702a' and 702d', and is shared by both sets of subarrays. This embodiment allows the two sets of subarrays to alternately output data to the neuronal circuit 704a-d, thus enabling continuous data output without idle time.

[0490] Figure 60B It shows Figure 59B An embodiment of the operating waveforms of the array architecture shown. At time T0, the first set of input data 730a-d is applied to selected cells in the first set of subarrays 702a-d. After a delay time T1, the selected cells generate current based on the input data and the stored data. Starting at time T2, multiplexers 743a-d sequentially connect output line groups 732a-d and the next group to the neuron circuits 704a-d to generate output data.

[0491] Simultaneously, the second input data groups 730a' to 730d' are applied to selected cells in the second set of subarrays 702a' to 702d' to generate the output current of the second set of output lines 732a' to 732d'. Therefore, at time T3, after all the outputs of the first set of subarrays 702a-d have been generated, the second set of multiplexers 743a' to 743d' sequentially connects the second set of output lines 732a' to 732d' and the next set to the neuron circuit 704a-d to generate output data. Simultaneously, the next input data group is applied to the first set of subarrays to repeat the process. By using this process, the neuron circuit 704a-d continues to generate output data from both sets of subarrays without any idle time.

[0492] Figure 61A An embodiment of an artificial intelligence (AI) chip or AI system architecture according to the present invention is illustrated. The AI ​​chip or AI system includes at least one data processing chip 760, such as a graphics processing unit (GPU) chip, a central processing unit (CPU) chip, a microprocessor chip, or an application-specific integrated circuit (ASIC) chip. The AI ​​chip or system also includes at least one memory chip 761, which includes at least one memory cell array 762 that stores data or so-called weights or models of synapses. As shown in FIG763a, the data processing chip 760 sends input data to the memory chip 761 via a data bus.

[0493] As shown in Figures 764a-m, memory chip 761 performs a multiplication function on the input data and the weights stored in memory 762. Next, memory chip 761 executes a summation function (as shown in functions 765a-n) and an activation function (as shown in activation functions 766a-n) to produce output data. After this, the output data is sent from memory chip 761 to data processing chip 760 via the data bus shown in Figure 763b. The above process can be repeated as needed to simulate large-scale multilayer neural networks.

[0494] Figure 61B An embodiment of an artificial intelligence (AI) chip or AI system architecture according to the present invention is shown. This embodiment is related to... Figure 61A The illustrated embodiment is similar, except that activation functions 766a-n are executed in data processing chip 760. After memory chip 761 executes summation functions 765a-n to generate output data, the output data is sent to data processing chip 760 via a data bus as shown in 763b. Data processing chip 760 executes activation functions 766a-n on the data from memory chip 760 to generate output data. The above process can be repeated as needed to simulate large-scale multilayer neural networks.

[0495] In one embodiment, the input data is stored in an input data buffer or data cache or SRAM 770. Multiplier circuits 771a-m are used to multiply the data with weights stored in the memory array 762. This configuration simulates... Figure 61B The multiplication function 764a-m in the shown memory chip 761. The output data of the multiplier circuit 771a-m is summed by the adder circuit 772a-n. This simulates... Figure 61B The summation function 765a of an output neuron in the memory chip 761 shown. Figure 61B The memory chip 761 in the middle includes Figure 62 The circuit shown comprises multiple blocks used to simulate the summation function 765a-n of multiple output neurons. The output is then transmitted to the data processing chip 760 to execute an activation function, such as... Figure 61B The function 766a-n is shown.

[0496] It should be noted that in this embodiment, the multiplier circuits 771a-m and the adder circuits 772a-n use any commonly used multiplier and adder logic circuits. Furthermore, since the memory array 762 does not perform multiplication and summation functions, it can use any type of memory, such as DRAM, SRAM, flash memory, RRAM, FRAM, MRAM, and / or PCM.

[0497] To illustrate in more detail, assume the input consists of 16 data points. Each data point is 2 bytes (2B) in size. Multiplier circuits 771a-m multiply the 16×2 bytes of input data with 16×2 bytes of weights to obtain 16×16×2 bytes of output data. Then, adder circuits 772a-n add these 16×16×2 bytes of data to obtain 8-bit wide × 2-byte data. This data is then transmitted to... Figure 61B The data processing chip 760 shown is used to execute the activation function. This configuration significantly reduces the amount of data transmitted compared to transferring 16×2B weights to the data processing chip 760 in a conventional system.

[0498] Although exemplary embodiments of the invention have been shown and described, it will be apparent to those skilled in the art, based on the teachings herein, that changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. Therefore, the appended claims are intended to cover all such changes and modifications within the true spirit and scope of the exemplary embodiments of the invention.

Claims

1. A memory cell array structure, comprising: Multiple storage units are organized into multiple rows and columns; Multiple input lines, wherein each input line is connected to a storage cell in a selected row, and wherein the multiple input lines form multiple input line groups; Multiple output lines, wherein each output line is connected to a storage cell in a selected column, and wherein the multiple output lines form multiple output line groups; A multiplexer having a multiplexer input and a multiplexer output, wherein the multiplexer input is connected to the output line group; A neuron circuit connected to the output of the multiplexer; and The storage cell array simulates a neural network, wherein the plurality of input lines simulate the input layer neurons of the neural network, and the plurality of output lines simulate the output layer neurons of the neural network.

2. The storage cell array structure according to claim 1, wherein, The plurality of storage units include one of the following: a floating body unit, a flash memory unit, a resistive random access memory unit, a ferroelectric random access memory unit, a magnetoresistive random access memory unit, a phase-change memory unit, and a memristor transistor unit.

3. The storage cell array structure according to claim 1, wherein, The neuron circuit includes at least one of an analog-to-digital converter, an operational amplifier, or a comparator for converting the sum of the unit currents into digital data.

4. The storage cell array structure according to claim 3, wherein, The analog-to-digital converter, operational amplifier, or comparator circuit also executes an activation function.

5. The storage cell array structure according to claim 1 further includes a selector that sequentially selects input data groups to limit the number of selected cells in each output line of the selected output line group.

6. The storage cell array structure according to claim 1, wherein, The multiplexer sequentially selects the output line groups and transmits the sum of the unit currents to the neuron circuit.

7. A 3D unit structure, comprising: Multiple blocks, each block including an input buffer, an array and a neuron circuit, wherein each neuron circuit outputs a set of output data; Multiple data buffers having buffer inputs and buffer outputs, wherein the multiple buffer inputs are configured to receive the output data groups from the multiple neuron circuits, respectively; Multiple activation circuits have circuit inputs and circuit outputs, wherein the multiple circuit inputs are respectively connected to the multiple buffer outputs, and wherein the multiple circuit outputs are configured to output activation results; and The 3D unit structure simulates a neural network, wherein the plurality of input buffers simulate the input neuron group of the neural network, the plurality of data buffers simulate the output neuron group of the neural network, and the plurality of activation circuits simulate the activation function of the neural network.

Images