Managing connection structures in semiconductor devices

Abstract

The present disclosure relates to methods, devices, systems, and techniques for managing connection structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. The semiconductor device further includes a partition wall between the first stack and the second stack along a second direction perpendicular to the first direction. The isolation wall includes first isolation structures extending in a first direction and spaced apart in a third direction perpendicular to the first direction and the second direction. The semiconductor device further includes a contact structure extending through at least a portion of the second stack in a first direction and a connection structure extending through the isolation wall in a second direction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers in a similar footprint of space. A 3D memory device typically includes a memory array of memory cells and a peripheral circuit to facilitate operation of the memory array. SUMMARY

[0003] The present disclosure describes methods, devices, systems, and techniques for managing connection structures in semiconductor devices.

[0004] One aspect of the present disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. The semiconductor device also includes an isolation wall between the first stack and the second stack along a second direction perpendicular to the first direction. The isolation wall includes first isolation structures extending along the first direction and spaced apart along a third direction perpendicular to the first direction and the second direction. The semiconductor device further includes contact structures extending along the first direction through at least a portion of the second stack and connection structures extending along the second direction through the isolation wall. Connection structures of the connection structures connect contact structures of the contact structures to conductive layers of the conductive layers of the first stack, and isolation structures of the first isolation structures extend along the first direction through the connection structures.

[0005] In some embodiments, the semiconductor device further includes gate line structures extending along the third direction. The first stack is between the gate line structures and the isolation wall along the second direction.

[0006] In some embodiments, the semiconductor device further includes second isolation structures extending along the first direction through the first stack. At least one of the second isolation structures is adjacent to the connection structures along the second direction.

[0007] In some embodiments, the isolation wall further includes inner structures extending along the first direction and spaced apart along the third direction. The inner structures and the first isolation structures alternate with each other along the third direction. The isolation wall further includes outer layers extending along the third direction and spaced apart along the first direction. The inner structures and the first isolation structures extend through the outer layers along the first direction.

[0008] In some embodiments, the inner structures include a dielectric material, and the outer layers include a semiconductor material.

[0009] In some embodiments, the inner structures and the outer layers include a same dielectric material.

[0010] In some embodiments, along the third direction, a first size of the connection structure at a first location is less than a second size of the connection structure at a second location, the first location being closer to a center of the isolation structure along the second direction than the second location.

[0011] In some embodiments, the semiconductor device includes an array region and a connection region adjacent to the array region in the second direction, the second stack is in the connection region, and the semiconductor device includes an array of channel structures in the array region.

[0012] In some embodiments, the semiconductor device includes a first semiconductor structure and a second semiconductor structure bonded together. The first semiconductor structure includes the first stack, the second stack, the isolation wall, the contact structure, and the connection structure, and the second semiconductor structure includes a peripheral circuit coupled to the first semiconductor structure and configured to control the semiconductor device.

[0013] Another aspect of the present disclosure features a semiconductor device. The semiconductor device includes a first stack of conductive layers and isolation layers alternating with each other along a first direction and a second stack of dielectric layers and isolation layers alternating with each other along the first direction. The semiconductor device further includes an isolation wall between the first stack and the second stack along a second direction perpendicular to the first direction, a contact structure extending through at least a portion of the second stack along the first direction, and a connection structure extending through the isolation wall along the second direction. Along a third direction perpendicular to the first direction and the second direction, a first size of the connection structure at a first location is less than a second size of the connection structure at a second location. The first location is closer to a center of the isolation wall along the second direction than the second location.

[0014] In some implementations, the connection structures connect a contact structure of the contact structures to a conductive layer of the conductive layers of the first stack along the first direction.

[0015] In some implementations, the isolation wall includes isolation structures that extend along the first direction and are spaced apart along a third direction that is perpendicular to the first direction and the second direction. A isolation structure of the isolation structures extends through the connection structures along the first direction.

[0016] In some implementations, the isolation wall further includes inner structures that extend along the first direction and are spaced apart along the third direction. The inner structures and the isolation structures alternate with each other along the third direction. The isolation wall further includes outer layers that extend along the third direction and are spaced apart along the first direction. The inner structures and the isolation structures extend through the outer layers along the first direction.

[0017] Another aspect of the present disclosure features a method of forming a semiconductor device. The method includes forming a first stack of conductive layers and isolation layers that alternate with each other along a first direction and a second stack of dielectric layers and isolation layers that alternate with each other along the first direction. The method further includes forming an isolation wall between the first stack and the second stack along a second direction that is perpendicular to the first direction. The isolation wall includes first isolation structures that extend along the first direction and are spaced apart along a third direction that is perpendicular to the first direction and the second direction. The method further includes forming contact structures that extend through at least a portion of the second stack along the first direction and forming connection structures that extend through the isolation wall along the second direction. Forming the connection structures includes forming a connection structure of the connection structures that connects a contact structure of the contact structures to a conductive layer of the conductive layers of the first stack. A isolation structure of the first isolation structures extends through the connection structures along the first direction.

[0018] In some embodiments, the method further includes forming a stack of dielectric layers and isolation layers alternating with each other along the first direction, and forming, by the same etching process, the array of via holes, the isolation holes, the first dummy via holes, the second dummy via holes, and the gate line holes extending through the stack of dielectric layers and isolation layers along the first direction. The array of via holes is in an array region of the semiconductor devices, the isolation holes, the first dummy via holes, and the second dummy via holes are in a connection region of the semiconductor devices, and the gate line holes include gate line holes in the array region and gate line holes in the connection region. The isolation holes and the first dummy via holes are arranged along lines extending in the third direction. One of the first dummy via holes is between two adjacent ones of the isolation holes along the third direction. The second dummy via holes are arranged along lines extending in the third direction. The gate line holes are arranged along lines extending in the third direction. The second dummy via holes are between the gate line holes and the first dummy via holes along the second direction. The method further includes forming the array of channel structures in the array of via holes, first isolation structures in the first dummy via holes, and second isolation structures in the second dummy via holes.

[0019] In some embodiments, the method further includes forming internal holes by expanding and connecting the isolation holes. The internal holes and the first isolation structures alternate with each other along the third direction. The method further includes forming channels between the isolation layers of the stack by removing portions of the dielectric layers of the stack exposed by the internal holes. The channels extend along the third direction, and the internal holes and the first isolation structures extend through the channels along the first direction.

[0020] In some embodiments, forming the isolation walls includes forming outer layers of the isolation walls by depositing semiconductor material in the channels, and forming inner structures of the isolation walls by depositing dielectric material into the internal holes. The method further includes forming gate line spaces by expanding the gate line holes. The gate line spaces include expanded gate line holes connected to each other along the third direction.

[0021] In some embodiments, the first stack forming a conductive layer and an isolation layer, and the second stack forming a dielectric layer and an isolation layer, include replacing the dielectric layer of the stack in the array region and the dielectric layer of the stack in the connection region between the gate line space and the isolation wall with a conductive layer. The first stack includes the conductive layer and the isolation layer in the array region and the conductive layer and the isolation layer in the connection region between the gate line space and the isolation wall. The second stack includes the remaining portion of the dielectric layer of the stack in the connection region and the isolation layer of the stack. Furthermore, the conductive layer in the conductive layer of the first stack is surrounded by a padding layer.

[0022] In some embodiments, the method further includes: forming a gate line structure by filling the gate line space with the semiconductor material, and forming a contact hole in the connection region. The contact hole extends along the first direction into the second stack and reaches a dielectric layer in the dielectric layer of the second stack, the contact hole is aligned with the isolation structure along the second direction, and an outer layer of the outer layer of the isolation wall contacts the dielectric layer and the conductive layer along the second direction. The method further includes: forming a first space in the dielectric layer by removing a portion of the dielectric layer that contacts the contact hole to expose the outer layer, forming a second space by removing a portion of the outer layer to expose a pad layer that contacts the conductive layer along the second direction, and expanding the second space by removing a portion of the pad layer to expose the conductive layer.

[0023] In some embodiments, forming the connection structure includes: forming the connection structure in the first space and the second space by depositing a conductive material through the contact hole into the first space and the second space. Forming the contact structure includes: forming a first layer of the contact structure by depositing the conductive material on the inner surface of the contact hole, and forming a second layer of the contact structure by filling the contact hole with a dielectric material. Attached Figure Description

[0024] FIGS. 1A-1D An example semiconductor device is shown.

[0025] FIGS. 2A-2B Another example semiconductor device is shown.

[0026] FIGS. 3A(1)-3T(2) An example process for manufacturing a semiconductor device is shown.

[0027] FIG. 4 A flowchart of an example process for manufacturing a semiconductor device is shown.

[0028] FIG. 5 A block diagram of the example system is shown.

[0029] Similar reference numerals and designations in the various figures denote similar elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0030] Due to the demand for relatively inexpensive memory devices with high density, memory devices (e.g., 3D NAND flash memory) can be formed with a large number of layers and a high aspect ratio. For example, a memory device can have multiple layers, and each layer can have multiple layers. The filling and connection of conductive layers between contact structures and conductive layers are critical steps in the manufacturing process of memory devices. The large number of layers and high aspect ratio of such memory devices can pose challenges to the manufacturing process. For example, to improve the quality and reliability of the conductive layers, conductive layer filling can be performed in separate processes (e.g., gate line loops in the array region and connection region can be performed separately), and these processes can involve multiple sacrificial layer filling and removal steps, thereby increasing manufacturing complexity and reducing the process window. In another example, the connection between the conductive layer and the contact structure may lead to the loss of high-k dielectric material in the padding layer between the conductive layer and the adjacent isolation layer. That is, it affects the uniformity of the conductive layer structure, thereby reducing the breakdown voltage between the conductive layer and the adjacent conductive layer. Therefore, contact structures and manufacturing methods that can solve the above problems are desired.

[0031] In one or more embodiments of this disclosure, an example semiconductor device is provided. The semiconductor device includes a first stack of alternating conductive and insulating layers and a second stack of alternating dielectric and insulating layers. The semiconductor device also includes an isolation wall between the first and second stacks. The isolation wall includes isolation structures extending in a vertical direction and spaced apart in a first horizontal direction. The semiconductor device also includes contact structures extending in a vertical direction through at least a portion of the second stack and connection structures extending in a second horizontal direction through the isolation wall.

[0032] Embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. First, in the exemplary semiconductor device described above, the sacrificial layer removal step can be stopped at the isolation wall, and the subsequent polysilicon removal step can be stopped on the high-k dielectric material of the pad layer. By applying etchants with different selectivity ratios in the sacrificial layer removal step, the polysilicon removal step, and the high-k removal step, the high-k loss problem can be solved, and a reliable interconnect structure can be formed. Second, a process for removing the isolation wall and filling the dielectric material can be added to create an isolation structure between the conductive layers. Third, the described techniques can reduce the number of manufacturing cycles for forming conductive layers and contact structures and avoid multiple sacrificial layer filling and removal steps, thereby improving product yield and reducing manufacturing costs.

[0033] These technologies can be applied to any semiconductor structure or device configured to avoid, for example, leakage or breakdown between conductive layers or components. The technologies can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices), or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (such as phase-change random access memory (PCRAM)), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), etc.). The technologies can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. The technologies can be applied to three-dimensional (3D) memory devices. The technologies can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0034] It should be noted that, FIGS. 1A-1DThe X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device may include two lateral surfaces extending laterally in the XY plane: a top surface on the front side of the substrate on which components of the semiconductor device may be formed; and a bottom surface on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, whether a component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (a vertical direction perpendicular to the XY plane, such as the thickness direction of the substrate) when the substrate is positioned in the Z direction in the lowest plane of the semiconductor device. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0035] FIG. 1A A top view of an example semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections to the one or more array regions. In some embodiments, such as FIG. 1A As shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). It should be understood that... FIG. 1A The examples in the examples are for illustrative purposes and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of various regions in the semiconductor device 100 can be applied. In some cases, the semiconductor device 100 may have two connecting regions 104 and an array region 102 arranged along the X direction between the two connecting regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connecting region 104 along the X direction between the two array regions 102.

[0036] Semiconductor device 100 includes alternating conductive layers and insulating layers (e.g., such as...). FIG. 1B The stack 106 (shown as conductive layer 106A and isolation layer 106B) is a composite structure. In some embodiments, a portion of the stack 106 may be in the array region 102, and another portion of the stack 106 may be in the connection region 104. The semiconductor device 100 also includes alternating dielectric and isolation layers (e.g., as shown in the diagram). FIG. 1B The stack 108 consists of a dielectric layer 106D and an isolation layer 106B. In some embodiments, the stack 108 may be located in a connection region 104. The stack 106 is connected to the stack 108.

[0037] Semiconductor device 100 may include one or more gate line structures 118. Each gate line structure 118 may extend in the X direction. The gate line structure 118 may extend into both the array region 102 and the connection region 104. In some embodiments, the gate line structure 118 may divide the array region into multiple memory blocks. In some embodiments, the gate line structure 118 may serve as a common source contact for the channel structure 110 in the array region 102.

[0038] Semiconductor device 100 may include isolation walls 120. Isolation walls 120 may be located in connection regions 104. Each isolation wall 120 may separate a stack 106 (e.g., a portion of the stack 106 in the connection region 104) from a stack 108 along a second horizontal direction (e.g., the Y direction) perpendicular to a first horizontal direction (e.g., the X direction). The portion of the stack 106 in the connection region 104 may be located along the Y direction between an adjacent gate line structure 118 and an adjacent isolation wall 120. Isolation walls 120 may include inner structures 136 and outer layers 138. The inner structures 136 may extend along a vertical direction (e.g., the Z direction) perpendicular to the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). The outer layers 138 may extend in a plane perpendicular to the Z direction (e.g., the XY plane). The inner structures 136 may be spaced apart along the X direction.

[0039] Semiconductor device 100 may include contact structure 116 and connection structure 114 in connection region 104. Connection structure 114 may extend along the Y direction through isolation wall 120. In some embodiments, one of the conductive layers 106A of stack 106 is coupled to control circuitry via corresponding connection structure 114 and corresponding contact structure 116. For example, each contact structure 116 may extend along the Z direction through at least a portion of stack 108 and connect to a corresponding connection structure in connection structure 114. Corresponding connection structure 114 is further connected to a corresponding conductive layer 106A of stack 106 in connection region 104. FIG. 1A As shown, each connection structure 114 may include a portion 114a and a portion 114b. Portion 114a is located along the Y direction between stacks 106 and 108 in the connection region 104, and extends along the Y direction through the isolation wall 120. Portion 114a is connected along the Y direction to the conductive layer 106A. Portion 114b is connected along the Z direction to the contact structure 116 (e.g., ...). FIG. 1B (As shown). The following will refer to... FIG. 1C Details of part 114a of the connection structure 114.

[0040] Semiconductor device 100 may include an array of channel structures 110 extending through a stack 106 in array region 102. Each channel structure 110 may be used to form a string of memory cells coupled in series along a vertical direction (e.g., the Z direction). In some embodiments, semiconductor device 100 may include isolation structures 112 for process variation control during manufacturing and / or for additional mechanical support. In some cases, the isolation structure may also be referred to as a dummy channel structure or a dummy memory string. Isolation structure 112 may include isolation structure 112a extending along the Z direction in isolation wall 120 and isolation structure 112b extending along the Z direction through the stack 106 in connection region 104. In some embodiments, the isolation structure or dummy channel structure 112 may be in one or more dummy regions or peripheral regions ( FIG. 1A (Not shown in the image). The isolation structures 112a in the isolation wall 120 can be spaced apart along the X direction. For example... FIG. 1A As shown, the internal structure 136 and the isolation structure 112a in the same isolation wall 120 can alternate with each other along the X direction. In some embodiments, the isolation structure 112a can extend through the corresponding connecting structure 114 along the Z direction. In some embodiments, at least one of the isolation structures 112b is adjacent to the corresponding connecting structure 114 along the Y direction.

[0041] Each channel structure 110 may be cylindrical or pillar-shaped and may include a high-k layer, a barrier layer surrounded by the high-k layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core-filling layer surrounded by the channel layer. These extend through the conductive layer 106A and the isolation layer 106B of the stack 106 in the array region 102, and a channel contact formed above the core-filling layer and in contact with the channel layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer (collectively referred to as the storage film) may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0042] In some embodiments, the isolation structure 112 and the channel structure 110 may have similar or identical structures and may be formed in the same manufacturing process. In other embodiments, the isolation structure 112 and the channel structure 110 may have different structures. For example, the isolation structure 112 may be a solid dielectric structure. In other words, the isolation structure 112 may be a continuous structure made of a dielectric material (e.g., silicon oxide).

[0043] FIG. 1B It shows along FIG. 1A The image shows a cross-sectional view of the semiconductor device 100 with cut line AA'. The semiconductor device 100 includes a substrate 101, a stack 106 of alternating conductive layers 106A and isolation layers 106B, and a stack 108 of alternating dielectric layers (also called sacrificial layers) 106D and isolation layers 106B. Each isolation layer 106B may have a portion between two adjacent conductive layers 106A in the stack 106 and another portion between two adjacent dielectric layers 106D in the stack 108. The stacks 106 and 108 are disposed on the substrate 101. The substrate 101 can be any suitable semiconductor substrate having any suitable semiconductor material, such as a single crystal, polycrystalline, or single-crystal semiconductor. For example, the substrate 101 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 101 may be removed from the semiconductor device 100 in a later process of manufacturing the semiconductor device 100. The semiconductor device 100 may include a top layer 107 made of an insulating material (e.g., oxide).

[0044] The stack 106 can extend in a second horizontal direction (e.g., Y direction) parallel to the top surface of the substrate 101 and perpendicular to the first horizontal direction (e.g., X direction). The conductive layer 106A and the insulating layer 106B can alternate in a vertical direction (e.g., Z direction) perpendicular to the second horizontal direction (e.g., Y direction). The thickness of the conductive layer 106A can be the same or different from each other, for example, in the range of 10-500 nm, e.g., about 35 nm. The insulating layers 106B can also be the same or different from each other in thickness, for example, in the range of 10-500 nm, e.g., about 25 nm. It should be noted that in... FIG. 1B The number of conductive layers 106A and insulating layers 106B shown is for illustrative purposes only, and any suitable number of conductive layers 106A and insulating layers 106B may be included in the stack 106. Conductive layer 106A may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicides, or any combination thereof. Insulating layer 106B may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 106B may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0045] In some implementations, such as FIG. 1BAs shown, the stack 106 includes a padding layer 106C. The padding layer 106C may cover part or all sides of the corresponding conductive layer 106A and is located between the conductive layer 106A and two isolation layers 106B adjacent to the corresponding conductive layer 106A. The padding layer 106C may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 106A includes a metallic material (e.g., W) and an adhesive material (e.g., TiN), and the adhesive material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 106A includes a metallic material (e.g., W), and the padding layer 106C includes an adhesive material (e.g., TiN) and a high-k dielectric material.

[0046] Stack 108 includes dielectric layers 106D and isolation layers 106B that alternate with each other along a vertical direction (e.g., the Z direction). Stack 108 can be connected to stack 106. Isolation layer 106B can extend into both stack 106 and stack 108 in a connection region 104 along a second horizontal direction (e.g., the Y direction). Dielectric layer 106D in stack 108 can extend to and contact a corresponding conductive layer 106A (or a pad layer 106C surrounding the corresponding conductive layer 106A) in stack 106. To fabricate stack 106 and stack 108, a series of alternating dielectric layers 106D and isolation layers 106B can be formed first. Then, dielectric layers 106D in regions of stack 106 can be etched away, for example, through openings formed in the location of gate line structure 118, while dielectric layers 106D in stack 108 remain unchanged. Then, a pad layer 106C and a conductive layer 106A can be formed to replace the dielectric layer 106D in the region of the stack 106 to form the stack 106.

[0047] The gate line structure 118 may extend through the stack 106 in a vertical direction (e.g., the Z direction). In some embodiments, such as FIG. 1B As shown, the gate line structure 118 can extend along the Z-direction from the top layer 107 into the substrate 101. The isolation structures 112 (e.g., 112a and 112b) can also extend along a vertical direction (e.g., the Z-direction) through the stack 106. In some embodiments, as... FIG. 1B As shown, the isolation structure 112 may extend along the Z-direction into the substrate 101. The contact structure 116 may extend along the Z-direction through at least a portion of the stack 108 (e.g., a set of dielectric layers 106D and isolation layers 106B of the stack 108). FIG. 1BAs shown, the contact structure 116 may include a first layer 124 and a second layer 125. The first layer 124 and the second layer 125 may extend along the Z-direction. The second layer 125 may surround and contact the first layer 124. The first layer 124 may include a dielectric material (e.g., silicon oxide). The second layer 125 may include a conductive material. In some embodiments, the contact structure 116 may be surrounded by a contact spacer 126, and the contact spacer 126 may include a dielectric material (e.g., silicon oxide).

[0048] The second layer 125 of the contact structure 116 can be coupled to a corresponding conductive layer in the conductive layer 106A of the stack 106 via a corresponding connection structure of the connection structure 114. For example, as FIG. 1B As shown, the second layer 125 of the contact structure 116 can be connected to the corresponding connection structure 114 along the Z direction. The corresponding connection structure 114 can be connected to the corresponding conductive layer 106A along the Y direction. A portion 114a of the connection structure 114 is connected to the conductive layer 106A along the Y direction. A portion 114b is connected to the contact structure 116 along the Z direction. The portion 114b is located along the Z direction between two adjacent isolation layers 106B of the stack 108. The connection structure 114 may include a conductive material. In some embodiments, both the second layer 125 of the contact structure 116 and the connection structure 114 may include the same conductive material (e.g., W or TiN). In some other embodiments, the second layer 125 of the contact structure 116 and the connection structure 114 may include different conductive materials. For example, the second layer 125 of the contact structure 116 may include W, and the connection structure 114 may include TiN.

[0049] like FIG. 1B As shown, the outer layers 138 of the isolation wall 120 can be spaced apart along the Z direction. Adjacent outer layers 138 can be separated along the Z direction by isolation layers 106B in stack 106 and 106B in stack 108. The inner structure 136 of the isolation wall 120 can extend along the Z direction through the outer layers 138. Isolation structure 112a ( FIG. 1B (Not shown) It may also extend along the Z direction through the outer layer 138. In some embodiments, the inner structure 136 and the outer layer 138 of the isolation wall 120 may include the same dielectric material (e.g., silicon oxide).

[0050] In some embodiments, the semiconductor device 100 includes a first semiconductor structure and a second semiconductor structure. FIGS. 1A-1BA first semiconductor structure may be stacked on top of a second semiconductor structure (e.g., along the Z-direction). The first and second semiconductor structures may be bonded at a bonding structure or bonding layer (not shown) therebetween. In some embodiments, a bonding structure is disposed between the first and second semiconductor structures due to hybrid bonding (also known as “metal / dielectric hybrid bonding”), which is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive), and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. The first semiconductor structure may include stack 106, stack 108, isolation wall 120, contact structure 116, connection structure 114, channel structure 110, and isolation structure 112. The second semiconductor structure may include peripheral circuitry coupled to the first semiconductor structure. The peripheral circuitry may be configured to control components of the first semiconductor structure (e.g., conductive layer 106A and channel structure 110 as described above). In some embodiments, the peripheral circuitry includes multiple transistors (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., the well, source, and drain of a transistor) can also be formed on or in the substrate. In some examples, complementary metal-oxide-semiconductor (CMOS) technology is used to form the peripheral circuitry, and a second semiconductor structure can be formed on a semiconductor die called a control die or CMOS die.

[0051] FIG. 1C An enlarged top view of the connection structure 114 is shown. The connection structure 114 may include portions 114a and 114b connected along the Y direction. Portion 114a may have at least four sides 140a, 140b, 140c, and 140d. Side 140a is adjacent to the stack 106 in the connection region 104. Side 140c contacts portion 114b. Sides 140b and 140d may be two inwardly curved concave surfaces. Sides 140b and 140d may contact two adjacent internal structures 136 of the partition wall 120 along the X direction. In other words, sides 140b and 140d may form two back-to-back curved surfaces (e.g., semicircles in the XY plane) arranged along the X direction. In some embodiments, along the X direction, a first dimension of portion 114a at position 142 is smaller than a second dimension of portion 114a at position 144. Position 142 is closer to the central axis 146 of the isolation structure 112a along the Y direction than position 144. The isolation structure 112a extends through the connecting structure 114 along the Z direction. In some embodiments, the central axis 146 of the isolation structure 112a may overlap with the central axis of the isolation wall 120 (e.g., extending along the X direction).

[0052] FIG. 1DIt shows FIGS. 1A-1B Enlarged view of the gate line structure 118 and internal structure 136. (See also...) FIG. 1D As shown, the gate line structure 118 may have at least two non-planar surfaces 148a and 148b opposite to each other (e.g., along the Y direction). Each of the two surfaces 148a and 148b includes a series of curved portions connected together. For example, surface 148a includes curved portions 150 connected to each other along the X direction. In other words, surfaces 148a and 148b are wavy or caterpillar-shaped. In some embodiments, the cross-section of the gate line structure 118 has a partially circular shape arranged and connected together in lines. The cross-section of the gate line structure 118 is in the XY plane (e.g., perpendicular to the vertical direction). Similarly, the inner structure 136 may also have a series of curved surfaces connected together. For example, the cross-section of the inner structure 136 (e.g., in the XY plane) has a partially circular shape arranged and connected together in lines. In other words, the surface of the inner structure 136 is also wavy or caterpillar-shaped.

[0053] FIG. 2A A top view of another example semiconductor device 200 is shown. FIG. 2B The semiconductor device 200 is shown along FIG. 1A A cross-sectional view of the cutting line at the same location as the cutting line AA'. The semiconductor device 200 can be similar to... FIGS. 1A-1D The semiconductor device 100 may also include a stack 106, a stack 108, a channel structure 110, an isolation structure 112, a gate line structure 118, an isolation wall 120, and a connection structure 114, etc. In some embodiments, such as FIGS. 2A-2B As shown, the outer layer 138 and inner structure 136 of each isolation wall 120 may include different materials. For example, the inner structure 136 of the isolation wall 120 may include a dielectric material (e.g., silicon oxide), and the outer layer 138 of the isolation wall 120 may include a semiconductor material (e.g., polycrystalline silicon).

[0054] FIGS. 3A(1)-3T(2) This illustrates the manufacture of semiconductor devices (such as...) FIGS. 1A-1D The semiconductor device 100 shown or FIGS. 2A-2B The example process of the semiconductor device 200 shown is illustrated. Figures 3A(1), 3B(1), ... and 3T(1) show top views of example semiconductor structures at various stages of the manufacturing process. Figures 3A(2), 3B(2), ... and 3T(2) show cross-sectional views of example semiconductor structures at various stages of the manufacturing process (e.g., along the... FIG. 1A (The cutting line at the same position as the cutting line AA').

[0055] like FIGS. 3A(1)-3A(2)As shown, a semiconductor structure 300a is formed. Figure 3A(1) shows that the semiconductor structure 300a may have an array region 302 and a connection region 304 adjacent to the array region 302 (e.g., along the X direction). The array region 302 may be FIG. 1A Examples of array regions 102 of semiconductor device 100, and examples of connection regions 304 of semiconductor device 100. Semiconductor structure 300a includes a substrate 301 and a stack 305 of a sacrificial layer 306D (also referred to as a dielectric layer) and an isolation layer 306B disposed on the substrate 301. The stack 305 may extend across array region 302 and connection region 304. The sacrificial layer 306D and isolation layer 306B may alternate with each other along a vertical direction (e.g., the Z direction). Each of the sacrificial layer 306D and isolation layer 306B, as well as the substrate 301, may extend in an XY plane. Semiconductor structure 300a also includes a semiconductor layer 303 along the Z direction between the stack 305 and the substrate 301. Semiconductor layer 303 may be made of a suitable semiconductor material (e.g., polysilicon). The semiconductor structure 300a can be formed, for example, by depositing a stack 305 of a sacrificial layer 306D and an isolation layer 306B over the semiconductor layer 303. The isolation layer 306B may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 306D may include a dielectric material different from the dielectric material of the isolation layer 306B. For example, the isolation layer 306B may include silicon oxide, and the sacrificial layer 306D may include silicon nitride.

[0056] Semiconductor structure 300a includes one or more sets of gate line vias 317. Each set of gate line vias 317 includes gate line vias in array region 302 and gate line vias in connection region 304. Each set of gate line vias 317 is arranged in a line extending along the X direction and spaced apart from each other along the line. Semiconductor structure 300a includes an array of channel vias 309 in array region 302. Semiconductor structure 300a includes one or more sets of isolation vias 333, one or more sets of first dummy channel vias 311a, and one or more sets of second dummy channel vias 311b in connection region 304. Each set of second dummy channel vias 311b is arranged in a line extending along the X direction. A set of isolation vias 333 and a set of first dummy channel vias 311a are arranged in a line extending along the X direction. The set of isolation vias 333 can be separated by a set of first dummy channel vias 311a along the X direction. For example, as shown in FIG3A(1), one of the first dummy channel vias 311a is located along the X direction between two adjacent isolation vias 333. Each set of second dummy channel vias 311b may be arranged along the Y direction between a set of gate line vias 317 and a set of first dummy channel vias 311a. An array of one or more sets of gate line vias 317, channel vias 309, one or more sets of isolation vias 333, one or more sets of first dummy channel vias 311a, and one or more sets of second dummy channel vias 311b may extend along the Z direction through a stack 305 of sacrificial layer 306D and isolation layer 306B. In some embodiments, an array of one or more sets of gate line vias 317, channel vias 309, one or more sets of isolation vias 333, one or more sets of first dummy channel vias 311a, and one or more sets of second dummy channel vias 311b are formed by the same etching process.

[0057] The semiconductor structure 300a can be formed by filling one or more sets of gate line vias 317, an array of channel vias 309, one or more sets of isolation vias 333, one or more sets of first dummy channel vias 311a, and one or more sets of second dummy channel vias 311b with a filler material (also known as a sacrificial material, such as polysilicon or carbon). A dielectric layer 307 (e.g., silicon oxide) can be deposited on top of the semiconductor structure 300a to cover the one or more sets of gate line vias 317, an array of channel vias 309, one or more sets of isolation vias 333, one or more sets of first dummy channel vias 311a, and one or more sets of second dummy channel vias 311b. A planarization process such as chemical mechanical polishing (CMP) can be performed to remove excess dielectric material on top of the semiconductor structure 300a.

[0058] like FIGS. 3B(1)-3B(2)As shown, a semiconductor structure 300b is formed by forming an array of channel structures 310 in an array of channel vias 309, forming a first isolation structure 312a in a first dummy channel via 311a, and forming a second isolation structure 312b in a second dummy channel via 311b. Openings can be formed to expose the filler material in the array of channel vias 309. The filler material in the array of channel vias 309 can be removed. The array of channel structures 310 can be formed by depositing a high-k layer, a storage film, a channel layer, and a core-filling layer into each of the array of channel vias 309. The storage film may include a barrier layer, a charge-trapping layer, and a tunneling layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge-trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the first isolation structure 312a and the second isolation structure 312b may have a structure similar to that of the channel structure 310. The first isolation structure 312a and the second isolation structure 312b may be referred to as dummy channel structures. In some embodiments, the array of channel structures 310, the first isolation structure 312a, and the second isolation structure 312b can be formed using the same deposition process.

[0059] like FIGS. 3C(1)-3C(2) As shown, a semiconductor structure 300c is formed by forming an opening in the dielectric layer 307 to expose the filling material in the isolation via 333 and removing the filling material in the isolation via 333. A new isolation via 333 may be formed, which includes the isolation via 333 (e.g., in the semiconductor structure 300b) and an opening on the top of the isolation via 333.

[0060] FIGS. 3D(1)-3D(2) A semiconductor structure 300d including an internal hole 335 is shown. The isolation hole 333 can be extended, for example, by an etching process. Each internal hole 335 can be formed by connecting or merging adjacent isolation holes of the extended isolation hole 333. As shown in FIG3D(1), the internal holes 335 and the first isolation structure 312a can alternate with each other along the X direction.

[0061] FIGS. 3E(1)-3E(2)A semiconductor structure 300e is shown, comprising a channel 337 between isolation layers 306B of a stack 305. The channel 337 can be formed by an etching process that removes portions of the sacrificial layer 306D of the stack 305 exposed by an internal via 335. The channel 337 may extend along the X direction. The internal via 335 and a first isolation structure 312a may extend through the channel 337 along the Z direction. In some embodiments, a protective structure 339a (e.g., polysilicon oxide) may be formed on the bottom of the internal via 335 (which may contact the substrate 301) to protect the substrate 301.

[0062] like FIGS. 3F(1)-3F(2) As shown, a semiconductor structure 300f including an outer layer 338 is formed. The outer layer 338 can be formed by depositing a semiconductor material (e.g., polysilicon) in the channel 337.

[0063] FIGS. 3G(1)-3G(2) A semiconductor structure 300g including one or more spacer layers 341 is shown. Each spacer layer 341 can be formed by depositing a dielectric material on the inner surface of the outer layer 338. Alternatively, in some embodiments, the internal vias 335 can be filled with a dielectric material, and the dielectric material in the internal vias 335 is formed with... FIGS. 2A-2B The internal structure 136 is similar to or the same as the internal structure. In some cases, the dielectric material in the internal hole 335 and the outer layer 338 can form... FIGS. 2A-2B The isolation wall is 120.

[0064] like FIGS. 3H(1)-3H(2) As shown, a semiconductor structure 300h is formed by filling an internal hole 335 with a sacrificial material (e.g., carbon). A new dielectric layer 307 can be formed by depositing a dielectric material (e.g., silicon oxide) on top of the semiconductor structure 300h to cover the internal hole 335 and performing a planarization process (e.g., CMP) to remove excess dielectric material on top of the semiconductor structure 300h.

[0065] like FIGS. 3I(1)-3I(2) As shown, a semiconductor structure 300i is formed by forming openings in the dielectric layer 307 to expose the filling material in one or more sets of gate line vias 317 and removing the filling material in one or more sets of gate line vias 317.

[0066] FIGS. 3J(1)-3J(2)A semiconductor structure 300j including one or more gate line spaces 319 is shown. Each gate line space 319 can be formed by extending a set of gate line vias 317 (e.g., by an etching process) and connecting or merging the set of extended gate line vias 317. In some embodiments, a protective structure 339b (e.g., polysilicon oxide) can be formed on the bottom of one or more gate line spaces 319 (which may be in contact with the substrate 301) to protect the substrate 301.

[0067] FIGS. 3K(1)-3K(2) A semiconductor structure 300k including spaces 321 formed by an etching process is shown. For example, the etching process may include filling the gate line spaces 319 with an etching solution. The spaces 321 are formed by removing portions of the sacrificial layers 306D of the stack 305 in the array region 302 and the sacrificial layers 306D of the stack 305 in the connection region 304 between each gate line space 319 and the adjacent outer layer 338. The spaces 321 expose the ends of the outer layers 338.

[0068] FIGS. 3L(1)-3L(2) A semiconductor structure 300l is shown, comprising a conductive layer 306A and a pad layer 306C. Each conductive layer 306A includes a portion between isolation layers 306B in array region 302. The conductive layer 306A also includes another portion in space 321 in connection region 304 (e.g., a portion in connection region 304 along the Y direction between gate line space 319 and adjacent outer layer 338). In some embodiments, each conductive layer 306A may be surrounded by a corresponding pad layer 306C. The conductive layer 306A may include a conductive material (e.g., W). The pad layer 306C may include a high-k dielectric material (e.g., Al2O3). The pad layer 306C and the conductive layer 306A may be formed, for example, by depositing the high-k dielectric material and the conductive material (e.g., through gate line space 319) into space 321. In some embodiments, as shown in FIG3L(2), the conductive layer 306A may be connected by excess conductive material deposited on the inner surface of gate line space 319.

[0069] FIGS. 3M(1)-3M(2)A semiconductor structure 300m is shown, comprising one or more gate line structures 318, a stack 306 of alternating conductive layers 306A and isolation layers 306B, and a stack 308 of alternating dielectric layers 306D and isolation layers 306B. The semiconductor structure 300m is formed by isolating the conductive layers 306A from each other by removing excess conductive material deposited on the inner surface of the gate line space 319. Each gate line structure 318 may include a fill structure 318a and a dielectric layer 318b surrounding the fill structure. The fill structure 318a may include a fill material (e.g., polysilicon), and the dielectric layer 318b may include a dielectric material (e.g., silicon oxide). The gate line structure 318 can be formed by depositing the dielectric material and the fill material into the gate line space 319.

[0070] Stack 306 includes a conductive layer 306A and a padding layer 306C in array region 302 and connection region 304. Stack 306 also includes portions of an isolation layer 306B along the Z-direction between the conductive layers 306A in array region 302 and connection region 304. Stack 308 includes the remainder of a sacrificial layer or dielectric layer 306D in connection region 304 and portions of an isolation layer 306B along the Z-direction between the sacrificial layers 306D in connection region 304. Stack 306 may be... FIGS. 1A-1B An example of a stack 106 of a semiconductor device 100. Stack 308 may be... FIGS. 1A-1B An example of a stack 108 of a semiconductor device 100.

[0071] FIGS. 3N(1)-3N(2)A semiconductor structure 300n is shown, including contact holes 315 in a connection region 304. Contact holes 315 can be formed by one or more etching processes. Each contact hole 315 can extend from the top of the semiconductor structure 300n (e.g., a surface away from the substrate 301) through a dielectric layer 307 and into one of the sacrificial layers 306D of a stack 308. Each contact hole 315 can extend along the Z-direction through at least a portion of the stack 308. For example, as shown in FIG3N(2), contact holes 315 extend along the Z-direction into the stack 308 and reach the sacrificial layer 306D-1 of the stack 308. In some embodiments, contact spacers 327 can be deposited on the inner surface of the contact holes 315. Contact spacers 327 can protect the sacrificial layer 306D exposed by the contact holes 315 from the etching process. In some embodiments, each contact hole 315 is aligned along the Y-direction with one of the first isolation structures 312a. As shown in Figure 3N(2), the outer layer 338-1 of the outer layer 338 is in contact with the sacrificial layer 306D-1 and the corresponding conductive layer 306A-1 of the conductive layer 306A along the Y direction. In some embodiments, the outer layer 338-1 is connected to the conductive layer 306A-1 by a padding layer 306C-1 surrounding the conductive layer 306A-1.

[0072] FIGS. 3O(1)-3O(2) A semiconductor structure 300o including a first space 342 is shown. The first space 342 can be formed in the sacrificial layer 306D-1 by removing (e.g., by an etching process) a portion of the sacrificial layer 306D-1 that contacts the contact hole 315 (e.g., along the Z direction) to expose the outer layer 338-1.

[0073] FIGS. 3P(1)-3P(2) A semiconductor structure 300p including a second space 344 is shown. The second space 344 is connected to the first space 342 along the Y direction. The second space 344 can be formed by removing (e.g., by an etching process) a portion of the outer layer 338-1 to expose the pad layer 306C-1. A first isolation structure 312a can extend through the second space 344 along the Z direction. Although in FIGS. 3P(1)-3P(2) The second space 344 is not shown, but it can be further extended by removing a portion of the padding layer 306C-1 to expose the conductive layer 306A-1.

[0074] FIGS. 3Q(1)-3Q(2) A semiconductor structure 300q including a connection structure 314 is shown. The connection structure 314 may include a portion 314a in a first space 342 and a portion 314b in a second space 344. The connection structure 314 can be formed by depositing conductive material through a contact hole 315 into the first space 342 and the second space 344. The portion 314a of the connection structure 314 can be connected to... FIG. 1CPart of 114a is similar to or the same.

[0075] The semiconductor structure 300q also includes contact structures 316. As shown in FIG3Q(2), one of the contact structures 316 is connected along the Z direction to a portion 314b of the connection structure 314. Each contact structure 316 may include a first layer 324 and a second layer 325 surrounding and contacting the first layer 324. The first layer 324 and the second layer 325 may extend along the Z direction. The first layer 324 may include a dielectric material (e.g., silicon oxide). The second layer 325 may include a conductive material. The second layer 325 of the contact structure 316 may be formed by depositing a conductive material on the inner surface of the contact hole 315. The first layer 324 of the contact structure 316 may be formed by filling the contact hole 315 with a dielectric material.

[0076] The semiconductor structure 300q also includes one or more isolation walls 320. Each isolation wall 320 may include an outer layer 338 spaced apart along the Z direction and a first isolation structure 312a extending through the outer layer 338 along the Z direction. The isolation wall 320 also includes an inner structure 336 extending through the outer layer 338 along the Z direction. FIGS. 3Q(1)-3Q(2) As shown, each internal structure 336 may include a spacer layer 341 and a filler material or sacrificial material surrounded by the spacer layer 341.

[0077] In some implementations, the partition wall 320 may have the same characteristics as... FIGS. 3Q(1)-3Q(2) The structures shown are different. FIGS. 3R(1)-3T(2) An example semiconductor structure with isolation walls featuring some alternative structures is shown.

[0078] like FIGS. 3R(1)-3R(2) As shown, the semiconductor structure 300r is formed by depositing a dielectric layer on top of the dielectric layer 207 to cover and isolate the contact structure 316. Forming the semiconductor structure 300r also includes removing the sacrificial material surrounded by the spacer layer 341 of the internal structure 336. In some embodiments ( FIGS. 3R(1)-3R(2) In (not shown), dielectric material can be filled into the space within the spacer layer 341 to form a dielectric material that is compatible with the dielectric material. FIGS. 2A-2B The semiconductor device 200 has a similar or identical semiconductor structure.

[0079] like FIGS. 3S(1)-3S(2) As shown, a semiconductor structure 300s is formed. The semiconductor structure 300s includes an internal hole 335 and a channel 337 formed by removing the spacer layer 341 and the outer layer 338.

[0080] FIGS. 3T(1)-3T(2)A semiconductor structure 300t with an isolation wall 320 is shown. The isolation wall 320 is formed by filling the internal holes 335 and channels 337 with a dielectric material. As shown in FIG3T(2), the internal structure 336 and the outer layer 338 of the isolation wall 320 are filled with a dielectric material. Semiconductor structure 300t and FIGS. 1A-1D The semiconductor device 100 is similar to or the same as that of the semiconductor device. In some embodiments, it is similar to the isolation wall 120 having an outer layer 138 made of semiconductor material (e.g., as shown in the figure). FIGS. 2A-2B Compared to (as shown), it has the following characteristics: FIGS. 3T(1)-3T(2) The solid dielectric structure shown in the diagram provides better insulation for the isolation wall 320.

[0081] FIG. 4 A flowchart of an example process 400 is shown. Process 400 can be performed to form a semiconductor device (e.g., FIGS. 1A-1D The semiconductor device 100 shown or FIGS. 2A-2B The semiconductor device 200 shown is applicable. FIGS. 3A(1)-3T(2) To describe process 400. Process 400 may include forming FIGS. 3A(1)-3T(2) This refers to one or more steps in the manufacturing process of a semiconductor structure. It should be understood that the operations shown in process 400 are not exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... FIG. 4 The different execution orders shown are illustrated.

[0082] At operation 402, a first stack of conductive layers (e.g., conductive layer 306A) and insulating layers (e.g., insulating layer 306B) alternating with each other along a first direction (e.g., the Z direction) is formed. FIGS. 3M(1)-3M(2) The stack 306) and the second stack (e.g., the stack body 306) consisting of dielectric layers (e.g., sacrificial or dielectric layer 306D) and isolation layers (e.g., isolation layer 306B) alternating with each other along a first direction (e.g., the Z direction). FIGS. 3M(1)-3M(2) Stacked body 308).

[0083] At operation 404, an isolation wall is formed (e.g., FIGS. 3Q(1)-3Q(2) 320 or FIGS. 3T(1)-3T(2) The isolation wall 320 is located between the first stack and the second stack along a second direction perpendicular to the first direction (e.g., the Y direction). The isolation wall includes a first isolation structure (e.g., first isolation structure 312a) extending along the first direction and spaced apart along a third direction perpendicular to the first and second directions (e.g., the X direction).

[0084] At operation 406, a contact structure is formed that extends along a first direction through at least a portion of the second stack (e.g., stack 308).FIGS. 3Q(1)-3T(2) (Contact structure 316).

[0085] At operation 408, a connection structure is formed extending along the second direction through the isolation wall (e.g., isolation wall 320). FIGS. 3Q(1)-3T(2) The connection structure 314). Forming the connection structure includes forming one of a plurality of connection structures that connects one of a plurality of contact structures (e.g., contact structure 316) to one of a plurality of conductive layers (e.g., conductive layer 306A-1) of the first stack. An isolation structure (e.g., first isolation structure 312a) in the first isolation structure extends through the connection structure along a first direction.

[0086] In some embodiments, process 400 further includes: forming a stack of dielectric layers (e.g., dielectric layer 306D) and isolation layers (e.g., isolation layer 306B) alternating with each other along a first direction. FIGS. 3A(1)-3A(2) The stack 305). Process 400 further includes forming, by means of the same etching process, an array of channel vias (e.g., an array of channel vias 309), isolation vias (e.g., isolation vias 333), a first dummy channel via (e.g., a first dummy channel via 311a), a second dummy channel via (e.g., a second dummy channel via 311b), and a gate line via (e.g., a gate line via 317).

[0087] The array of vias is located in an array region of the semiconductor device (e.g., array region 302), and the isolation vias, the first dummy channel via, and the second dummy channel via are located in a connection region of the semiconductor device (e.g., connection region 304). Gate line vias include gate line vias in the array region and gate line vias in the connection region. The isolation vias and the first dummy channel via are arranged along lines extending upward in a third direction (e.g., as shown in the image). FIGS. 3A(1)-3A(2) (As shown). One of the first dummy channel holes is located between two adjacent isolation holes in the third direction. The second dummy channel hole is arranged along a line extending upward in the third direction (e.g., as shown). FIGS. 3A(1)-3A(2) (As shown). The gate line vias are arranged along a line extending upwards on a third side (e.g., as shown). FIGS. 3A(1)-3A(2) (As shown in the diagram). The second dummy channel via is located along the second direction between the gate line via and the first dummy channel via.

[0088] In some embodiments, process 400 further includes: a channel structure (e.g., formed in an array of channel holes (e.g., channel holes 309)). FIGS. 3B(1)-3B(2)The array of channel structures 310, the first isolation structure (e.g., first isolation structure 312a) in the first dummy channel hole (e.g., first dummy channel hole 311a), and the second isolation structure (e.g., second isolation structure 312b) in the second dummy channel hole (e.g., second dummy channel hole 311b).

[0089] In some embodiments, process 400 further includes: expanding and connecting isolation holes (e.g., FIGS. 3C(1)-3C(2) The isolation hole 333) is used to form the internal hole (e.g., FIGS. 3D(1)-3D(2) The internal aperture 335). The internal aperture (e.g., internal aperture 335) and the first isolation structure (e.g., first isolation structure 312a) alternate with each other along a third direction. In some embodiments, process 400 further includes forming channels (e.g., isolation layer 306B) between isolation layers (e.g., isolation layer 306B) of the stack (e.g., stack 305) by removing portions of the dielectric layer (e.g., dielectric layer 306D) of the stack (e.g., stack 305) exposed by the internal aperture. FIGS. 3E(1)-3E(2) The channel 337 extends along a third direction (e.g., as shown in FIG3E(1)), and the internal hole and the first isolation structure extend through the channel along a first direction (e.g., as shown in FIG3E(2)).

[0090] In some implementations, forming the isolation wall includes: forming an outer layer of the isolation wall (e.g., by depositing a semiconductor material (e.g., polysilicon) in the channel). FIGS. 3G(1)-3G(2) The outer layer 338), and the internal structure of the insulating wall is formed by depositing a dielectric material (e.g., silicon oxide) into the internal pores (e.g., internal pores 335). FIGS. 3R(1)-3R(2) The internal structure 336). In some embodiments, process 400 further includes: expanding the gate line via (e.g., FIGS. 3I(1)-3I(2) Gate line via 317) to form gate line space (e.g., gate line via 317) to form gate line space. FIGS. 3J(1)-3J(2) The gate line space 319). The gate line space includes extended gate line vias that are connected to each other along a third direction.

[0091] In some embodiments, the first stack forming a conductive layer and an insulating layer, and the second stack forming a dielectric layer and an insulating layer, include: using a conductive layer (e.g., FIGS. 3M(1)-3M(2) The conductive layer 306A is replaced (e.g., as referenced). FIGS. 3K(1)-3M(2)(Description) The dielectric layer of the stack in the array region and the dielectric layer of the stack in the connection region between the gate line space and the isolation wall. The first stack (e.g., stack 306) includes a conductive layer (e.g., conductive layer 306A) and an isolation layer (e.g., isolation layer 306B) in the array region (e.g., array region 302) and a conductive layer (e.g., conductive layer 306A) and an isolation layer (e.g., isolation layer 306B) between the gate line space (e.g., gate line space 319) and the isolation wall (e.g., isolation wall 320) in the connection region (e.g., connection region 304). The second stack (e.g., stack 308) includes the remainder of the dielectric layer (e.g., dielectric layer 306D) of the stack (e.g., stack 205) and the isolation layer (e.g., isolation layer 306B) of the stack in the connection region. The conductive layer in the conductive layer of the first stack (e.g., conductive layer 306A-1 in FIG. 3N(2)) is surrounded by a padding layer (e.g., padding layer 306C-1 in FIG. 3N(2)).

[0092] In some embodiments, process 400 further includes forming a gate line structure by filling the gate line space (e.g., gate line space 319) with a semiconductor material (e.g., polysilicon). FIGS. 3M(1)-3M(2) (Gate line structure 318).

[0093] In some embodiments, process 400 further includes: forming a contact hole in the connection area (e.g., FIGS. 3N(1)-3N(2) The contact hole 315 extends along a first direction into a second stack (e.g., stack 308) and reaches a dielectric layer (e.g., dielectric layer 306D-1) within the dielectric layer of the second stack. The contact hole is aligned along a second direction with an isolation structure (e.g., first isolation structure 312a), and an outer layer (e.g., outer layer 338-1) within the outer layer of the isolation wall contacts the dielectric layer (e.g., dielectric layer 306D-1) and a conductive layer (e.g., conductive layer 306A-1) along the second direction.

[0094] In some embodiments, process 400 further includes forming a first space (e.g., ...) in the dielectric layer by removing a portion of the dielectric layer that contacts the contact hole (e.g., along the Z direction) to expose the outer layer (e.g., outer layer 338-1). FIGS. 3O(1)-3O(2) First space 342).

[0095] In some embodiments, process 400 further includes forming a second space (e.g., by removing a portion of the outer layer (e.g., outer layer 338-1) to expose a padding layer (e.g., padding layer 306C-1) that contacts the conductive layer (e.g., conductive layer 306A-1) along a second direction. FIGS. 3P(1)-3P(2) The second space 344).

[0096] In some embodiments, process 400 further includes expanding the second space by removing portions of the liner layer (e.g., liner layer 306C-1) to expose the conductive layer (e.g., conductive layer 306A-1).

[0097] In some implementations, a connection structure is formed (e.g., FIGS. 3Q(1)-3Q(2) The connection structure 314 includes forming a connection structure in the first space and the second space by depositing conductive material through a contact hole (e.g., contact hole 315) into the first space (e.g., first space 342) and the second space (e.g., second space 344). Forming a contact structure (e.g., contact structure 316) includes forming a first layer (e.g., first layer 324) of the contact structure by depositing conductive material on the inner surface of the contact hole, and forming a second layer (e.g., second layer 325) of the contact structure by filling the contact hole with a dielectric material.

[0098] FIG. 5 A block diagram of an example system 500 is shown. According to one or more embodiments of this disclosure, system 500 may have one or more semiconductor devices (e.g., storage devices). System 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage. FIG. 5 As shown, system 500 may include a host device 508 and a storage system 502 having one or more storage devices 504 and a memory controller 506. The host device 508 may include a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). The host device 508 may be configured to send data to or receive data from one or more storage devices 504.

[0099] Storage device 504 can be any storage device disclosed herein, such as FIGS. 1A-1D The storage device shown (e.g., NAND flash memory) or such FIGS. 2A-2BThe storage device is shown in the diagram. A memory controller 506 (also referred to as controller circuitry) is coupled to the storage device 504 and the host device 508. Consistent with embodiments of this disclosure, the storage device 504 may include a plurality of conductive interconnects through a cover layer contacting conductive pads in a conductive pad layer, and the memory controller 506 may be coupled to the storage device 504 through at least one of the plurality of conductive interconnects. The memory controller 506 is configured to control the storage device 504. For example, the memory controller 506 may be configured to operate a plurality of channel structures via word lines. The memory controller 506 may manage data stored in the storage device 504 and communicate with the host device 508.

[0100] In some implementations, the memory controller 506 is designed / configured to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 506 is designed / configured to operate in high-duty-cycle environments in Solid State Drives (SSDs) or embedded Multi-Media Cards (eMMCs), used for data storage in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 506 can be configured to control the operation of the storage device 504, such as read, erase, and program (or write) operations. The memory controller 506 can also be configured to manage various functions regarding data stored or to be stored in the storage device 504, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 506 is also configured to process error correction codes (ECC) regarding data read from or written to the storage device 504. The memory controller 506 may also perform any other suitable function, such as formatting the storage device 504.

[0101] The memory controller 506 can communicate with external devices (e.g., host device 508) according to a specific communication protocol. For example, the memory controller 506 can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0102] The memory controller 506 and one or more storage devices 504 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the storage system 502 can be implemented and packaged into different types of end electronic products. FIG. 5 In one example shown, the memory controller 506 and a single storage device 504 can be integrated into a memory card 502. The memory card 502 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0103] The embodiments of the subject matter and actions described in this disclosure may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or in combinations thereof. Embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs encoded on a computer program carrier, such as one or more modules of computer program instructions, for execution by or control of the operation of a data processing device. The carrier may be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagation signal, such as a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, or a combination or part thereof. The computer storage medium is not a propagation signal.

[0104] Note that references to "an embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment does not necessarily include those specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, its combination with other embodiments affects the scope of knowledge of those skilled in the art regarding such features, structures, or characteristics (whether explicitly described or not).

[0105] Generally, terms can be understood at least partly from their use in context. For example, the term "one or more," as used herein, can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but can also, at least partly depending on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0106] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” something with an intermediate feature or layer. Furthermore, “above” or “on top of” means not only “above” or “on top of” something but also includes “above” or “on top of” something without an intermediate feature or layer (i.e., directly on).

[0107] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to describe the relationship of an element or feature to other elements or features (single or multiple) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the apparatus in use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0108] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom surface of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0109] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire undercoat or overcoat structure, or may have a range smaller than that of the undercoat or overcoat structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a conical surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect pathways (VIAs) are formed) and one or more dielectric layers.

[0110] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter of a component or process step, which is set during the design phase of the product or process along with a range of values ​​that are higher and / or lower than the expected value. As used herein, the range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given amount that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given amount that varies within, for example, 10%–30% of the value (e.g., ±0.10%, ±0.20%, or ±0.30% of the value).

[0111] In this disclosure, the terms “horizontal / horizontally / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to the lateral surface of the substrate.

[0112] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate.

[0113] This disclosure provides numerous different implementations or examples for carrying out various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features can be in direct contact, and may also include implementations in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, in various examples, reference numerals and / or letters may be repeated in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0114] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance given herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0115] While this disclosure contains numerous details of specific implementations, these should not be construed as limiting the scope of the claims (as defined by the claims themselves), but rather as descriptions of features specific to particular embodiments of a particular invention. Certain features described in this disclosure in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, in some cases, one or more features from the claimed combination may be removed from the combination, and the claims may be for sub-combinations or variations thereof.

[0116] Similarly, although operations are shown in the accompanying drawings and described in the claims in a specific order, this should not be construed as requiring such operations to be performed in the specific order or sequence shown, or to perform all of the shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0117] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0118] The scope and extent of this disclosure should not be limited to any of the embodiments described in the foregoing exemplary embodiments, but should be defined solely by the appended claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first stack of conductive and insulating layers alternating with each other along a first direction; A second stack of dielectric and insulating layers alternating with each other along the first direction; An isolation wall between the first stack and the second stack along a second direction perpendicular to the first direction, wherein the isolation wall includes a first isolation structure extending along the first direction and spaced apart along a third direction perpendicular to the first direction and the second direction; A contact structure extending at least a portion of the second stack along the first direction; and A connection structure extending through the isolation wall along the second direction, wherein the connection structure in the connection structure connects the contact structure in the contact structure to the conductive layer in the conductive layer of the first stack, and the isolation structure in the first isolation structure extends through the connection structure along the first direction.

2. The semiconductor device according to claim 1, further comprising: A gate line structure extending along the third direction, wherein the first stack body is located between the gate line structure and the isolation wall along the second direction.

3. The semiconductor device according to claim 1 or claim 2, further comprising: A second isolation structure extending through the first stack along the first direction, wherein at least one of the second isolation structures is adjacent to the connection structure along the second direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The isolation wall also includes: An internal structure extending along the first direction and spaced apart along the third direction, wherein the internal structure and the first isolation structure alternate with each other along the third direction; and An outer layer extending along the third direction and spaced apart along the first direction, wherein the inner structure and the first isolation structure extend through the outer layer along the first direction.

5. The semiconductor device according to claim 4, wherein, The internal structure includes a dielectric material, and the outer layer includes a semiconductor material.

6. The semiconductor device according to claim 4, wherein, The internal structure and the outer layer comprise the same dielectric material.

7. The semiconductor device according to any one of claims 1 to 6, wherein, Along the third direction, the first dimension of the connection structure at the first position is smaller than the second dimension of the connection structure at the second position, and the first position is closer to the center of the isolation structure along the second direction than the second position.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The semiconductor device includes an array region and a connection region adjacent to the array region in the second direction, the second stack being in the connection region, and the semiconductor device including an array of channel structures in the array region.

9. The semiconductor device according to any one of claims 1 to 8, comprising a first semiconductor structure and a second semiconductor structure bonded together, wherein, The first semiconductor structure includes a first stack, a second stack, the isolation wall, the contact structure, and the connection structure, wherein the second semiconductor structure includes peripheral circuitry coupled to the first semiconductor structure and configured to control the semiconductor device.

10. A semiconductor device, comprising: A first stack of conductive and insulating layers alternating with each other along a first direction; A second stack of dielectric and insulating layers alternating with each other along the first direction; An isolation wall between the first stack and the second stack along a second direction perpendicular to the first direction; A contact structure extending along the first direction through at least a portion of the second stack; as well as A connecting structure extending through the isolation wall along the second direction, wherein, along a third direction perpendicular to the first and second directions, the first dimension of the connecting structure at a first position is smaller than the second dimension of the connecting structure at a second position, and wherein, the first position is closer to the center of the isolation wall along the second direction than the second position.

11. The semiconductor device according to claim 10, wherein, The connection structure connects the contact structure in the contact structure to the conductive layer in the conductive layer of the first stack.

12. The semiconductor device according to claim 10 or claim 11, wherein, The isolation wall includes isolation structures extending along the first direction and spaced apart along a third direction perpendicular to the first and second directions, and the isolation structures in the isolation structures extend through the connecting structure along the first direction.

13. The semiconductor device according to claim 12, wherein, The isolation wall also includes: An internal structure extending along the first direction and spaced apart along the third direction, wherein the internal structure and the isolation structure alternate with each other along the third direction; and An outer layer extending along the third direction and spaced apart along the first direction, wherein the inner structure and the isolation structure extend through the outer layer along the first direction.

14. A method of forming a semiconductor device, comprising: A first stack of conductive and insulating layers alternating with each other along a first direction and a second stack of dielectric and insulating layers alternating with each other along the first direction are formed. An isolation wall is formed between the first stack and the second stack along a second direction perpendicular to the first direction, wherein the isolation wall includes a first isolation structure extending along the first direction and spaced apart along a third direction perpendicular to the first direction and the second direction; Forming a contact structure extending along the first direction through at least a portion of the second stack; and A connection structure is formed extending through the isolation wall along the second direction, wherein forming the connection structure includes: The connection structure forms a connection structure that connects the contact structure in the contact structure to the conductive layer in the conductive layer of the first stack, and the isolation structure in the first isolation structure extends through the connection structure along the first direction.

15. The method of claim 14, further comprising: A stack of dielectric and insulating layers alternating with each other along the first direction is formed; An array of channel vias, isolation vias, a first dummy channel via, a second dummy channel via, and gate line vias extending along the first direction through the dielectric layer and the isolation layer are formed using the same etching process, wherein: The array of vias is located in the array region of the semiconductor device, the isolation via, the first dummy via, and the second dummy via are located in the connection region of the semiconductor device, and the gate line vias include gate line vias in the array region and gate line vias in the connection region. The isolation hole and the first dummy channel hole are arranged along a line extending upward from the third party, wherein one of the first dummy channel holes is arranged along the third party between two adjacent isolation holes in the isolation hole; The second dummy channel hole is arranged along a line extending upward from the third party; The gate line via is arranged along a line extending upward from the third party; and The second dummy channel via is located between the gate line via and the first dummy channel via along the second direction; and an array of channel structures formed in the array of channel vias, a first isolation structure in the first dummy channel via, and a second isolation structure in the second dummy channel via.

16. The method of claim 15, further comprising: An internal hole is formed by expanding and connecting the isolation holes, wherein the internal holes and the first isolation structure alternate with each other along the third direction; and A channel is formed between the isolation layers of the stack by removing the portion of the dielectric layer of the stack exposed by the internal aperture, wherein the channel extends along the third direction, and the internal aperture and the first isolation structure extend through the channel along the first direction.

17. The method according to any one of claims 14 to 16, wherein, The formation of the isolation wall includes: The outer layer of the isolation wall is formed by depositing semiconductor material in the channel; and The internal structure of the isolation wall is formed by depositing a dielectric material into the internal pores. The method also includes: A gate line space is formed by expanding the gate line vias, wherein the gate line space includes expanded gate line vias connected to each other along the third direction.

18. The method according to claim 17, wherein, The first stack forming the conductive layer and the insulating layer, and the second stack forming the dielectric layer and the insulating layer, comprise: The dielectric layer of the stack in the array region and the dielectric layer of the stack in the connection region between the gate line space and the isolation wall are replaced with conductive layers, wherein the first stack includes the conductive layer and the isolation layer in the array region and the conductive layer and the isolation layer between the gate line space and the isolation wall in the connection region, the second stack includes the remaining portion of the dielectric layer of the stack in the connection region and the isolation layer of the stack, and the conductive layer in the conductive layer of the first stack is surrounded by a pad layer.

19. The method according to any one of claims 14 to 18, further comprising: A gate line structure is formed by filling the gate line space with the semiconductor material. A contact hole is formed in the connection area, wherein the contact hole extends along the first direction into the second stack and reaches the dielectric layer in the dielectric layer of the second stack, the contact hole is aligned with the isolation structure along the second direction, and the outer layer of the outer layer of the isolation wall contacts the dielectric layer and the conductive layer along the second direction; A first space is formed in the dielectric layer by removing the portion of the dielectric layer that contacts the contact hole to expose the outer layer; A second space is formed by removing a portion of the outer layer to expose the padding layer that contacts the conductive layer along the second direction; and The second space is expanded by removing a portion of the liner layer to expose the conductive layer.

20. The method according to claim 19, wherein, Forming the connection structure includes: forming the connection structure in the first space and the second space by depositing conductive material through the contact hole into the first space and the second space, wherein forming the contact structure includes: The first layer of the contact structure is formed by depositing the conductive material on the inner surface of the contact hole; and The second layer of the contact structure is formed by filling the contact holes with a dielectric material.

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