Semi-insulating SiC substrate for semiconductor device
By introducing interstitial atoms and diffusing them on a semi-insulating SiC substrate, the problem of high material cost for high-voltage semiconductor devices has been solved, enabling the fabrication of low-resistivity high-voltage semiconductor devices, reducing material and device costs, and making it suitable for devices such as PiN devices and IGBTs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-28
- Publication Date
- 2026-03-27
AI Technical Summary
In the prior art, the thick and lightly doped epitaxial layer materials required for manufacturing high-voltage semiconductor devices are expensive and have high resistivity, making it difficult to obtain sufficiently low resistivity while reducing costs.
A semi-insulating SiC substrate is used. By introducing interstitial atoms into the Si and/or C surfaces and diffusing them to form a doped SiC substrate, the background doping concentration is reduced and the semiconductor deep level concentration is increased. Interstitial atoms are introduced using ion beam technology, thermal annealing or plasma immersion ion implantation, and the annealing temperature and time are adjusted to reduce resistivity.
This technology enables the production of low-resistivity semiconductor devices suitable for high-voltage applications while reducing costs. It also reduces material losses and lowers costs, making it suitable for various semiconductor devices such as PiN devices and IGBTs.
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Figure CN121753529A_ABST
Abstract
Description
[0001] This disclosure relates to a method for fabricating a semiconductor device for high voltage (HV) applications using a doped semi-insulating (SI) SiC substrate, and to a semiconductor device comprising a doped semi-insulating SiC substrate.
[0002] To fabricate high-voltage devices, thick, lightly doped layers are typically required. Devices with blocking voltages above 10 kV require epitaxial layers much thicker than 100 µm and with doping concentrations below 1E14 cm⁻³, to achieve approximately 1E5 Ohm. The resistivity is in the range of 1 E7 Ohm. Unfortunately, these layers are extremely expensive. SiC semi-insulating (SI) substrates, on the other hand, are inexpensive. However, the problem is that the resistivity of SI SiC substrates is higher than 1 E7 Ohm. cm. A low-cost layer with sufficiently low resistivity is needed for high-voltage devices.
[0003] The goal is to manufacture low-cost semiconductor devices while still obtaining semiconductor devices with sufficiently low resistivity for high-voltage applications.
[0004] This objective is achieved through the features of the independent claim. Advantageous embodiments are indicated in the dependent claims.
[0005] The embodiments of this disclosure (e.g., embodiments of this disclosure as claimed in the independent claims) address, in whole or in part, the aforementioned disadvantages in the art. Further embodiments of semiconductor devices and methods for manufacturing semiconductor devices are the subject of the additional claims.
[0006] A method for manufacturing a semiconductor device is provided, the method comprising the steps of: providing a semi-insulating SiC substrate having a predefined first thickness, introducing interstitial atoms into the Si and / or C surfaces of the semi-insulating SiC substrate, and forming a doped SiC substrate of a first conductivity type or a second conductivity type by diffusing the interstitial atoms.
[0007] The main advantage of semi-insulating SiC substrates lies in cost. Unlike conductive SiC, SI-SiC does not require the 4° off-axis dicing used for epitaxial growth. This reduction in material loss makes SI-SiC substrates cheaper than conductive SiC substrates. Cheaper materials will allow for the manufacture of cheaper high-voltage devices.
[0008] A semi-insulating SiC substrate with a predefined thickness is provided. This thickness depends on the preferred application and preferred parameters, such as blocking voltage.
[0009] Semi-insulating SiC substrates are those with resistivity ranging from 1E5 to 1E9 Ohms at room temperature (RT). Substrates between cm⁻³. To obtain SI-SiC, the background doping concentration (N₀d) must be reduced, and the concentration of deep semiconductor levels (N₀t) capable of trapping charge carriers must be increased. This second step is necessary because reducing the background doping concentration (N₀d) below 1E¹⁰ cm⁻³ is difficult. When the semiconductor deep level concentration (N₀t) is greater than the background doping concentration (N₀d), semi-insulating SiC is obtained. In this case, charge carriers are trapped in the deep levels, and the Fermi level is pinned close to these deep levels. When N₀t is less than N₀d, the Fermi level is close to the conduction band, so almost no charge carrier trapping occurs, and semi-insulating SiC cannot be obtained.
[0010] Subsequently, interstitial atoms are introduced into the Si surface, the C surface, or both surfaces, so that a doped SiC substrate is formed by the diffusion of interstitial atoms.
[0011] The doped SiC substrate exhibits a first conductivity type, which can be n-type, meaning it can be n-type doped. Alternatively, the doped SiC substrate exhibits a second conductivity type, the opposite of the first conductivity type. The second conductivity type can be p-type, meaning the SiC substrate can be p-type doped.
[0012] Si-SiC substrates are inherently unsuitable for high-voltage device fabrication due to their poor conductivity. Therefore, the resistivity must be reduced to approximately 1E9 Ohm. The resistivity of a SiC substrate with a thickness of cm was measured. The resistivity was reduced by introducing interstitial atoms.
[0013] To introduce interstitial atoms, standard ion beam techniques are used with energies below 10 keV and doses ranging from 1E10 to 1E16 ions / cm². The lower the energy used to introduce interstitial atoms, the greater the reduction in the manufacturing cost of the SiC substrate, and consequently, the greater the reduction in the cost of the semiconductor device.
[0014] Alternatively, in order to introduce interstitial atoms, thermal annealing is used in an environment rich in the interstitial atoms at a first temperature in the range of 1200°C to 1600°C.
[0015] Alternatively, to introduce interstitial atoms, plasma immersion ion implantation (PIII) is used with energies from 1 keV to 15 keV and doses ranging from 1E10 to 1E16 ions / cm2.
[0016] The diffusion of interstitial atoms is promoted by annealing the semi-insulating SiC substrate at a second temperature for a second duration, so that the concentration of interstitial atoms is uniform along the depth of the doped SiC substrate. For this annealing step, for example, a resistance furnace is used.
[0017] The second temperature range is between 1200°C and 1800°C, and the second time period ranges between 20 minutes and 48 hours.
[0018] Furthermore, the second temperature range is preferably between 1500°C and 1700°C, and the second time period range is preferably between 30 minutes and 24 hours.
[0019] To introduce interstitial atoms, Group II elements are provided. The material used to introduce interstitial atoms can be any chemical element from Group II. For example, beryllium is provided to introduce interstitial atoms. In this case, an n-type doped SiC substrate is produced. For the Fermi level value of interest in semi-insulating SiC, beryllium interstitial atoms act as dual donors. Beryllium interstitial atoms are also a fast-diffusing material, diffusing through an interstitial mechanism with a low activation barrier (3.1 eV). For these reasons, beryllium is used to reduce the resistivity of SiC substrates (e.g., Si-4H-SiC substrates). The diffusion rate of beryllium interstitial atoms is approximately 6E-9 cm² / s at 1700°C. This means that, for example, during a 1-h annealing at 1700°C, beryllium interstitial atoms diffuse over 50 µm. The diffusion time and temperature can be adjusted to make the concentration of beryllium interstitial atoms uniform along the entire substrate depth.
[0020] Alternatively, group VII elements are provided to introduce interstitial atoms. The material used to introduce interstitial atoms can be any chemical element from group VII. For example, fluorine is provided to introduce interstitial atoms. In this case, a p-type doped SiC substrate is produced.
[0021] Using SI-SiC substrates for high-voltage (HV) devices also allows for thinner devices. For example, devices with blocking voltages above 10 kV typically require a 100 µm thick epitaxial layer. This 100 µm thick epitaxial layer is grown on a 350 µm thick substrate, such as a conductive SiC substrate. This results in a 450 µm thick device. However, if a 350 µm thick SI substrate is used, it can be thinned to 110 µm. 100 µm is used as a drift layer, and 10 µm is used as a cathode.
[0022] Therefore, depending on the preferred application or parameters (e.g., according to the blocking voltage), the semi-insulating SiC substrate is thinned to a first thickness before introducing interstitial atoms.
[0023] By further processing the doped SiC substrate, it can be used in a variety of applications.
[0024] According to an embodiment, the method further includes: implanting a group III element on a first side of a doped SiC substrate to form an anode; and implanting a group V element on a second side of the doped SiC substrate arranged opposite to the first side to form a cathode.
[0025] According to a further embodiment, the method includes: masking a doped SiC substrate with a mask; and implanting a substrate region, a collector electrode, and a contact region in the doped SiC substrate using the mask. The method further includes: annealing the doped SiC substrate at a third temperature for a third duration to form a gate oxide on top of the doped SiC substrate; and metallizing the doped SiC substrate to form a gate electrode, a first main electrode, and a second main electrode.
[0026] The third annealing temperature ranges from 1500°C to 1800°C, and the third time ranges from 10 minutes to 3 hours. Preferably, the third temperature ranges from 1600°C to 1700°C, and the third time ranges from 30 minutes to 1 hour.
[0027] A semiconductor device is also provided, comprising a semi-insulating SiC substrate doped with interstitial atoms of a first conductivity type or a second conductivity type. The resistivity of the semi-insulating SiC substrate at room temperature ranges from 1E5 Ohm. cm to 1E9 Ohm Between cm, the background doping concentration (Nd) is greater than 1E10 cm-3, and it has a semiconductor deep level concentration (Nt), wherein the semiconductor deep level concentration (Nt) is greater than the background doping concentration (Nd).
[0028] The substrate used is a semi-insulating 4H-SiC substrate. The 4H-SiC crystal structure is commonly used in power devices due to its high carrier mobility and high critical electric field strength. Alternatively, the semi-insulating substrate is a SiC polytype with a 6H-SiC structure. Additionally or alternatively, the substrate is semi-insulating 4H-SiC or 6H-SiC, and / or made of conductive 4H-SiC or 6H-SiC.
[0029] Semi-insulating SiC substrates can be used in a variety of semiconductor devices. According to an embodiment, the semiconductor device includes: an anode located on a first side of the SiC substrate, the anode comprising a group III element, and a cathode located on a second side of the SiC substrate, the cathode comprising a group V element, the second side being arranged opposite to the first side.
[0030] This corresponds to a simple PiN device. The SiC substrate is not limited to PiN devices. It can be further used for power bipolar devices, and includes, for example, PiN diodes, PN junctions, and / or IGBTs.
[0031] The accompanying drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be indicated by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative and not necessarily drawn to scale.
[0032] Figures 1 to 4 Different locations in an exemplary embodiment of a method for manufacturing a semiconductor device are shown. Figure 5 An exemplary embodiment of a semiconductor device is shown.
[0033] Figure 1 The location is shown in an exemplary embodiment of a method for manufacturing a semiconductor device 1. A semi-insulating SiC substrate 100' with a predefined first thickness d1 is provided. The semi-insulating SiC substrate 100' is thinned to the first thickness d1 before introducing interstitial atoms i. The first thickness d1 is selected according to a preferred application or parameter (e.g., according to blocking voltage). The semi-insulating SiC substrate 100' has a resistivity in the range of 1E5-1E9 Ohms at room temperature. Substrates between cm⁻³. To obtain SI-SiC, the background doping concentration (N₀d) must be reduced, and the concentration of deep semiconductor levels (N₀t) capable of trapping charge carriers must be increased. This second step is necessary because reducing the background doping concentration (N₀d) below 1E¹⁰ cm⁻³ is difficult. When the semiconductor deep level concentration (N₀t) is greater than the background doping concentration (N₀d), a semi-insulating SiC 100' is obtained. In this case, charge carriers are trapped at the deep levels, and the Fermi level is pinned to a position close to these deep levels. For example, vanadium doping can be used to obtain the semi-insulating SiC substrate 100'.
[0034] Figure 2The following locations are shown, where interstitial atoms i are introduced on the Si facet 110 and C facet 120 of the semi-insulating SiC substrate 100'. Interstitial atoms i can also be introduced only on the Si facet 110 or only on the C facet 120. Interstitial atoms i can be introduced in several ways. For example, standard ion beam techniques with energies below 10 keV and doses ranging from 1E10 to 1E16 ions / cm² can be used to introduce interstitial atoms i. Alternatively or additionally, interstitial atoms i can be introduced by thermal annealing in an environment rich in interstitial atoms i chemical elements. The first temperature T1 used for thermal annealing ranges from 1200°C to 1600°C. Alternatively or additionally, interstitial atoms i can be introduced by plasma immersion ion implantation (PIII). The energies used for PIII range from 1 keV to 15 keV, and the doses range from 1E10 to 1E16 ions / cm². The introduced interstitial atoms i are provided by Group II or Group VII elements. The material used to introduce interstitial atoms i can be any chemical element from Group II or Group VII elements. For example, beryllium or fluorine can be used. When beryllium is used as interstitial atom i, an n-type doped SiC substrate 100 is produced. When fluorine is used as interstitial atom i, a p-type doped SiC substrate 100 is produced.
[0035] Figure 3 The diagram shows a later location where the doped SiC substrate 100 is annealed at a second temperature T2 for a second duration Z2 to diffuse interstitial atoms i, such that the concentration of these interstitial atoms i is uniform along a first depth d1 of the doped SiC substrate 100. The second temperature T2 ranges from 1200°C to 1800°C, and the second duration Z2 ranges from 20 minutes to 48 hours. Furthermore, the second temperature T2 is preferably between 1500°C and 1700°C, and the second duration Z2 is preferably between 30 minutes and 24 hours. For this annealing step, a resistance furnace is used, for example.
[0036] The diffusion rate of beryllium interstitial atoms is approximately 6E-9 cm² / s at 1700°C. This means that, for example, during annealing at 1700°C for 1 h, beryllium interstitial atoms diffuse over 50 µm. The diffusion time and temperature can be adjusted to make the concentration of beryllium interstitial atoms uniform along the entire substrate depth. Therefore, the diffusion time and temperature can be adjusted for different materials (e.g., fluorine).
[0037] exist Figure 4At the location specified, an anode 113 comprising group III elements is implanted on the first side 111 of the SiC substrate 100. On the second side 112 opposite to the first side 111, a cathode 114 comprising group V elements is implanted. The first side 111 can be either a Si surface 110 or a C surface 120. Correspondingly, the second side 112 is either a C surface 120 or a Si surface 110. Meanwhile, Figure 4 The final semiconductor device 1 is shown. Figure 4 The semiconductor device 1 is a PiN device.
[0038] Figure 5 Another exemplary embodiment of the semiconductor device 1 is shown. Through... Figure 3 Following the steps shown, the doped SiC substrate 100 is further processed to fabricate the IGBT. To manufacture... Figure 5 The semiconductor device 1 uses a mask to mask a doped SiC substrate 100. Using the mask, a base region 11, a collector 12, a buffer layer 19, and a contact region having an n+ region 13 and a p+ region 14 are formed in the doped SiC substrate 100 by implantation.
[0039] The doped SiC substrate 100 is annealed at a third temperature T3 for a third time period Z3. After annealing, a gate oxide 15 is formed on top of the doped SiC substrate 100, and the doped SiC substrate 100 is metallized to form a gate electrode 16, a first main electrode 17, and a second main electrode 18. The doped SiC substrate 100 and the buffer layer 19 have the same conductivity type. Both are of the first conductivity type, which can be n-type, i.e., both can be n-type doped. Alternatively, the doped SiC substrate 100 has a second conductivity type opposite to the first conductivity type. The second conductivity type can be p-type, i.e., the SiC substrate 100 and the buffer layer 19 can be p-type doped. The substrate region 11 and the collector 12 have the opposite conductivity type to the SiC substrate 100. They are, for example, of the second conductivity type, which can be p-type, i.e., both can be p-type doped. Alternatively, the substrate region 11 and the collector 12 have the first conductivity type, which can be n-type, i.e., both can be n-type doped. The third annealing temperature T3 ranges from 1500°C to 1800°C, and the third time period Z3 ranges from 10 minutes to 3 hours. Preferably, the third temperature T3 ranges from 1600°C to 1700°C, and the third time period Z3 ranges preferably from 30 minutes to 1 hour. Meanwhile, Figure 5 The final semiconductor device 1 is shown. Figure 5 The semiconductor device 1 is an IGBT.
[0040] As stated Figures 1 to 5The embodiments shown represent exemplary embodiments of semiconductor devices and methods for manufacturing semiconductor devices; therefore, these exemplary embodiments do not constitute a complete list of all embodiments according to semiconductor devices and methods. Actual semiconductor devices and methods may differ from the illustrated embodiments, for example, in terms of arrangement, elements, and regions.
[0041] Figure Labels 1 Semiconductor Devices 11 base 12 collectors 13n+ region 14p+ area 15 Gate Oxide 16 gate electrodes 17 First main electrode 18 Second main electrode 19 buffer layers 100' semi-insulating SiC substrate 100-doped SiC substrate 110Si surface 111 First side 112 Second side 113 anode 114 cathode 120C side i Interstitial atom d1 First thickness T1 First Temperature T2 Second Temperature Z2 Second Time Quantity T3 Third Temperature Z3 is the third time quantity.
Claims
1. A method for manufacturing a semiconductor device (1), the method comprising the following steps - Provide a semi-insulating SiC substrate (100') with a predefined first thickness (d1). - Interstitial atoms (i) are introduced into the Si surface (110) and / or C surface (120) of the semi-insulating SiC substrate (100'), and - A doped SiC substrate (100) of a first conductivity type or a second conductivity type is formed by diffusing the interstitial atoms (i).
2. The method according to claim 1, wherein, To introduce the interstitial atoms (i), standard ion beam techniques are used with energies below 10 keV and doses ranging from 1E10 to 1E16 ions / cm².
3. The method according to claim 1, wherein, In order to introduce the interstitial atom (i), thermal annealing is performed at a first temperature (T1) in an environment rich in the interstitial atom (i) at a range of 1200°C to 1600°C.
4. The method according to claim 1, wherein, To introduce the interstitial atoms (i), plasma immersion ion implantation (PIII) was used with energies from 1 keV to 15 keV and doses ranging from 1E10 to 1E16 ions / cm2.
5. The method according to any one of the preceding claims, wherein, The diffusion of the interstitial atoms (i) is promoted by annealing the semi-insulating SiC substrate (100') at a second temperature (T2) for a continuous second time period (Z2), so that the concentration of the interstitial atoms (i) is uniform along the depth of the doped SiC substrate (100).
6. The method according to claim 5, wherein, The second temperature (T2) ranges from 1200°C to 1800°C, and the second time period (Z2) ranges from 20 minutes to 48 hours.
7. The method according to any one of the preceding claims, wherein, To introduce the interstitial atom (i), a group II element is provided.
8. The method according to claim 7, wherein, Beryllium is provided to introduce the interstitial atom (i).
9. The method according to any one of claims 1 to 6, wherein, To introduce the interstitial atom (i), a group VII element is provided.
10. The method according to claim 9, wherein, Fluorine is provided in order to introduce the interstitial atom (i).
11. The method according to any one of the preceding claims, comprising thinning the semi-insulating SiC substrate (100') to the first thickness (d1) according to a preferred blocking voltage.
12. The method according to any one of the preceding claims, comprising: - Group III elements are implanted into the first side (111) of the doped SiC substrate (100) to form an anode (113), and - A group V element is implanted on the second side (112) of the doped SiC substrate (100), which is arranged opposite to the first side (111) to form a cathode (114).
13. The method according to any one of claims 1 to 11, comprising: - The doped SiC substrate (100) is masked using a mask. - By using the mask for implantation, a base region (11), a collector (12), and a contact region (13) are formed in the doped SiC substrate (100). - The doped SiC substrate (100) is annealed at a third temperature (T3) for a third time period (Z3). - A gate oxide (15) is formed on top of the doped SiC substrate (100), and - The doped SiC substrate (100) is metallized to form a gate electrode (16), a first main electrode (17), and a second main electrode (18).
14. The method according to any one of the preceding claims, wherein, The third annealing temperature (T3) ranges from 1500°C to 1800°C, and the third time (Z3) ranges from 10 minutes to 3 hours.
15. A semiconductor device (1), comprising: - A doped SiC substrate (100) of a first conductivity type or a second conductivity type, wherein the doped SiC substrate is a semi-insulating SiC substrate (100') doped with interstitial atoms (i), wherein... - The semiconductor deep energy level concentration (Nt) is greater than the background doping concentration (Nd) of the semi-insulating SiC substrate (100').
16. The semiconductor device (1) according to claim 15, wherein, The semi-insulating SiC substrate (100') is semi-insulating 4H-SiC or 6H-SiC, and / or is made of conductive 4H-SiC or 6H-SiC.
17. The semiconductor device (1) according to claim 15 or 16, comprising: - An anode (113) located on the first side (111) of the doped SiC substrate (100), the anode comprising a group III element, and - A cathode (114) located on the second side (112) of the doped SiC substrate (100), the cathode comprising group V elements, the second side being arranged opposite to the first side (111).
18. The semiconductor device (1) according to any one of claims 15 to 17, wherein, The semiconductor device (1) is a power bipolar device.
19. The semiconductor device (1) according to any one of claims 15 to 18, wherein, The semiconductor device (1) includes a PN junction.
20. The semiconductor device (1) according to any one of claims 15 to 18, wherein, The semiconductor device (1) includes a PiN diode or an IGBT.