Method for etching silicon and oxygen-containing features at low temperatures

Abstract

An example semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. The substrate may be accommodated in the processing region. The silicon-containing material layer may be disposed on the substrate. The method may include forming a plasma effluent of a fluorine-containing precursor and a hydrogen-containing precursor. The method may include contacting a substrate with a plasma effluent of a fluorine-containing precursor and a hydrogen-containing precursor. The contact may etch features in the silicon-containing material layer. During a semiconductor processing method, a substrate support pedestal temperature may be maintained at less than or about-20 DEG C.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 236,042, filed August 21, 2023, entitled “METHODS OF ETCHING SILICON-AND-OXYGEN-CONTAINING FEATURES AT LOW TEMPERATURES”, which is incorporated herein by reference in its entirety.

[0002] This technology relates to semiconductor processes and equipment. More specifically, this technology relates to etching operations on silicon- and oxygen-containing materials. Background Technology

[0003] Integrated circuits can be fabricated by producing intricately patterned layers of material on a substrate surface. Creating the patterned material on the substrate requires controlled methods for removing the exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist into underlying layers, thinning layers, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have etching processes that etch one material faster than another to facilitate, for example, pattern transfer processes. Such etching processes are called selective for the first material. Due to the diversity of materials, circuits, and processes, selective etching processes for multiple materials have been developed.

[0004] Depending on the materials used in the process, etching processes can be described as wet or dry. Wet HF etching preferentially removes silicon oxide compared to other dielectrics and materials. However, wet processes may struggle to penetrate certain confined trenches and can sometimes deform the remaining material. Dry etching, generated in localized plasma within the substrate processing area, can penetrate more confined trenches and exhibit less deformation of the fine remaining structure. However, localized plasma can damage the substrate by generating arcs during discharge.

[0005] Therefore, there is a need for improved systems and methods for producing high-quality devices and structures. This technology can meet these and other needs. Summary of the Invention

[0006] An exemplary semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A silicon-containing material layer may be disposed on the substrate. The method may include forming a plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor. The method may include contacting the substrate with the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor. This contact may etch features in the silicon-containing material layer. During the semiconductor processing method, the substrate support stage temperature may be maintained at below or about -20 °C.

[0007] In some embodiments, the fluorinated precursor may be or may include nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), or fluoromethane (CH3F). The hydrogen-containing precursor may be or may include diatomic hydrogen (H2). The silicon-containing material may be or may include silicon oxide. The plasma effluent of the fluorinated and hydrogen-containing precursors can form a hydrogen fluoride (HF) plasma. The plasma effluent of the fluorinated and hydrogen-containing precursors can be formed at a plasma power greater than or about 750 W. The method may include applying a bias power while contacting the substrate with the plasma effluent of the fluorinated and hydrogen-containing precursors. The bias power may be greater than or about 1,500 W. Features in the oxygen-containing material layer may be characterized as a critical dimension less than or about 30 nm. Features in the oxygen-containing material layer may be characterized as an aspect ratio greater than or about 5:1. The substrate support stage temperature may be less than or about -60 °C. The contact can etch features in the oxygen-containing material layer at an etching rate greater than or about 100 nm / min.

[0008] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A silicon- and oxygen-containing material layer may be disposed on the substrate. The methods may include: forming a plasma effluent of the fluorine- and hydrogen-containing precursors. The methods may include: contacting the substrate with the plasma effluent of the fluorine- and hydrogen-containing precursors. The contact may etch features in the silicon- and oxygen-containing material layer. The features in the silicon- and oxygen-containing material layer may be characterized by a critical size less than or about 30 nm.

[0009] In some embodiments, the plasma effluent from the fluorine-containing precursor and the hydrogen-containing precursor can form a hydrogen fluoride (HF) plasma. The silicon and oxygen-containing material layer can be a layer in the DRAM structure. The substrate support stage temperature can be between about -100 °C and about -20 °C. The semiconductor processing chamber operating pressure can be less than or about 2 Torr.

[0010] Some embodiments of this technology may cover semiconductor processing methods. The methods may include: providing an etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. A silicon-containing material layer may be disposed on the substrate. The methods may include: forming a plasma effluent of the etchant precursor. The plasma effluent may be or may include hydrogen fluoride (HF) plasma. The methods may include: contacting the substrate with the hydrogen fluoride (HF) plasma. The contact may etch features in the silicon-containing material layer. During the semiconductor processing method, the substrate support stage temperature may be maintained below or about -40 °C.

[0011] In some embodiments, the etchant precursor may be or may include one or more of the following: nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), and fluoromethane (CH3F). The method may include applying a bias power while contacting the substrate with a plasma effluent of the etchant precursor. The bias power may be greater than or about 1,250 W.

[0012] Such techniques offer numerous advantages over conventional systems and techniques. For example, these processes can increase the desired properties of the contours of one or more features etched into an oxygen-containing material. Furthermore, these processes prevent slowed etching rates, bowing of etched features, bending of etched features, twisting of etched features, and / or blockage of etched features. These and other embodiments, along with their many advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0013] The nature and advantages of the technology disclosed herein can be further understood by referring to the rest of the specification and the drawings.

[0014] Figure 1 This shows a top plan view of an exemplary processing system according to some embodiments of the present technology.

[0015] Figure 2 A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0016] Figure 3 This shows an operation selected from the etching methods according to some embodiments of the present technology.

[0017] Figures 4A to 4C A cross-sectional view of a substrate material on which an operation is being performed according to some embodiments of the present technology.

[0018] Several diagrams are included in this work in an illustrative manner. It should be understood that these diagrams are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, as schematic diagrams, these diagrams are intended to aid understanding and may not include all aspects or information compared to a realistic representation, and may include exaggerated material for illustrative purposes.

[0019] In the accompanying drawings, similar parts and / or features may have the same component symbol. Furthermore, parts of the same class may be distinguished by adding a letter after the component symbol (the letter distinguishing similar parts). If only a first component symbol is used in the specification, the description applies to any similar parts having the same first component symbol, regardless of the letter. Detailed Implementation

[0020] As structures evolve, the aspect ratios of features and other structures also increase, sometimes even dramatically. For example, during DRAM processing, features can be etched through one or more materials, such as oxygen-containing materials. When forming features, holes can extend through the entire thickness of the oxygen-containing material before approaching the substrate. As the aspect ratios of features and other structures increase, the resulting feature or hole dimensions may become critically reduced. Ideally, these critical dimensions should be uniform throughout the feature or hole.

[0021] Conventional techniques typically etch features into oxygen-containing materials at room temperature. However, as aspect ratios increase, the etching operation may fail to provide sufficient contour control for the resulting features. For example, with increasing aspect ratios, critical dimensions may not be maintained throughout the etching process. Furthermore, uneven etching can lead to bowing and / or tapering of features. In some extreme cases, etching may fail to penetrate the entire desired thickness of the oxygen-containing material, resulting in bridging defects. In these cases, as the etchant species become less directional, they may begin to etch outwards. Outward etching can lead to bowing, bending, twisting, or other etch inhomogeneities.

[0022] This technology overcomes these problems by using a combination of precursors (such as fluorine-containing and carbon-containing precursors) to perform the etching process at a lower temperature, thereby increasing the uniformity of the etched features. For example, hydrogen-rich chemicals can be used to reduce the taper of the features. The lower temperature allows for an increased amount of fluorine-containing material reaching the etch front and continued etching through the oxygen-containing material.

[0023] While the remainder of the disclosure will specify the specific etching processes utilizing the disclosed techniques in a conventional manner, it will be readily understood that the systems and methods described are equally applicable to deposition and cleaning processes that may occur within the chambers. Therefore, the techniques should not be construed as being limited to use with these etching processes or chambers. Furthermore, although exemplary chambers are described to provide a basis for this technique, it should be understood that the technique is applicable in practice to any semiconductor processing chamber that allows for the described single-chamber operation. Similarly, although specific etching operations will be described, it should be understood that the processes are equally applicable to other processes in which etching can be performed. Therefore, the examples presented should not be considered as limiting the scope of the techniques described herein.

[0024] Figure 1 Showing a top plan view of an embodiment of a processing system 10 for deposition, etching, baking, and / or hardening chambers according to an embodiment. Figure 1The depicted tool or processing system 10 may include multiple processing chambers 24a to 24d, a transfer chamber 20, a service chamber 26, an integrated metering chamber 28, and a pair of loading gate chambers 16a to 16b. The processing chambers may include any number of structures or components, as well as any number of processing chambers or combinations of processing chambers.

[0025] To transfer substrates between chambers, transfer chamber 20 may include a robotic transfer mechanism 22. Transfer mechanism 22 may have a pair of substrate transfer blades 22a, each attached to the distal end of an extendable arm 22b. Blades 22a can be used to bring individual substrates into and out of processing chambers. In operation, one of the substrate transfer blades of transfer mechanism 22 (such as blade 22a) can retrieve a substrate W from one of the loading gate chambers (such as chambers 16a to 16b) and bring the substrate W to a first stage of processing, for example, the processing in chambers 24a to 24d described below. Chambers may be included to perform individual or combined operations of the described techniques. For example, while one or more chambers may be configured for deposition or etching operations, one or more other chambers may be configured for pre-processing operations and / or one or more post-processing operations as described herein. This technology covers any number of configurations that can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0026] If a chamber is occupied, the robot can wait until processing is complete, then use a blade 22a to remove the processed substrate from the chamber, and a second blade can be inserted to insert a new substrate. Once the substrate has been processed, it can be moved to the second stage of processing. For each move, the transfer mechanism 22 typically has one blade carrying the substrate and an empty blade to perform the substrate exchange. The transfer mechanism 22 can wait at each chamber until the exchange can be completed.

[0027] Once processing within the processing chamber is complete, the transfer mechanism 22 can move the substrate W from the final processing chamber and transfer it to the wafer cassette within the loading gate chambers 16a to 16b. The substrate can be moved from the loading gate chambers 16a to 16b into the fab interface 12. The fab interface 12 is typically operable to transfer substrates between the wafer cassette loaders 14a to 14d in an atmospheric pressure clean environment and the loading gate chambers 16a to 16b. A clean environment in the fab interface 12 is typically provided through an air filtration process (e.g., HEPA filtration). The fab interface 12 may also include a substrate orienter / aligner for properly aligning the substrate prior to processing. At least one substrate robot (e.g., robots 18a to 18b) may be positioned within the fab interface 12 to transfer substrates between multiple locations within the fab interface 12 and to other locations communicating with the fab interface 12. Robots 18a to 18b can be configured to travel from one end of the factory interface 12 to the second end along a track system within the factory interface 12.

[0028] The processing system 10 may further include an integrated metering chamber 28 to provide control signals, which can provide adaptive control over any process performed in the processing chamber. The integrated metering chamber 28 may include any of a variety of metering devices to measure various film properties, such as thickness, roughness, and composition, and the metering devices may further have the ability to characterize grating parameters (such as critical dimensions, sidewall angles, and feature heights) automatically under vacuum.

[0029] Each processing chamber 24a to 24d can be configured to perform one or more process steps in the fabrication of a semiconductor structure, and any number of processing chambers and combinations thereof can be used in the multi-chamber processing system 10. For example, any processing chamber can be configured to perform several substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that can be performed in any chamber or any combination of chambers may include metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Those skilled in the art will readily understand that any other processes, including any processes described below, can be similarly performed in specific chambers incorporated within the multi-chamber processing system 10.

[0030] Figure 2A schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 within the processing chamber 100 is shown. The exemplary processing chamber 100 is suitable for patterning processes, but it should be understood that aspects of the technology can be performed in any number of chambers, and substrate supports according to the technology can be included in etching chambers, deposition chambers, processing chambers, or any other processing chambers. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which the substrate can be processed. The chamber body 105 may have sidewalls 112 and a bottom 118 coupled to a ground 126. The sidewalls 112 may have linings 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and are generally proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, such as display or solar cell substrates.

[0031] The chamber body 105 supports the chamber cover assembly 110 to enclose the chamber volume 101. The chamber body 105 may be made of aluminum or other suitable material. A substrate pick-up port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 302 into and out of the plasma processing chamber 100. The pick-up port 113 may be coupled to a transfer chamber and / or other chambers of the substrate processing system as described above. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to vent and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0032] Gas control panel 160 can be coupled to chamber body 105 via gas line 167 to supply process gases to chamber volume 101. Gas control panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert gases, non-reactive gases, and reactive gases, which can be used for any number of processes. Examples of process gases that can be supplied by gas control panel 160 include, but are not limited to: hydrocarbon gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. In addition, process gases may include nitrogen-containing gases, chlorine-containing gases, fluorine-containing gases, oxygen-containing gases, and hydrogen-containing gases, such as H2, NH3, H2O, H2O2, O2, O3, NF3, HF, F2, CH4, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, COS, and SO2, as well as any number of additional precursors.

[0033] Valve 166 can control the flow of process gas from sources 161, 162, 163, and 164 from gas control panel 160 and can be managed by controller 165. The gas flow supplied from gas control panel 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be one or more ports for introducing process gas from sources 161, 162, 164, and 163 of gas control panel 160 into chamber volume 101. After the process gas is introduced into plasma processing chamber 100, the gas can be excited to form plasma. Antenna 148, such as one or more induction coils, may be provided adjacent to plasma processing chamber 100. Antenna power supply 142 may power antenna 148 via matching circuit 141, which has inductively coupled energy, such as RF energy, to the process gas to maintain plasma formed by the process gas in chamber volume 101 of plasma processing chamber 100. Alternatively, or in addition to the antenna power supply 142, process electrodes below and / or above the substrate 302 can be used to capacitively couple RF power to the process gas to maintain the plasma within the chamber volume 101. The operation of the power supply 142 can be controlled by a controller (such as controller 165), which can also control the operation of other components in the plasma processing chamber 100.

[0034] A substrate support stage 135 can be disposed within the chamber volume 101 to support the substrate 302 during processing. The substrate support stage 135 may include an electrostatic chuck (“ESC”) 122 for holding the substrate 302 during processing. The electrostatic chuck 122 uses electrostatic attraction to hold the substrate 302 to the substrate support stage 135. The ESC 122 may be powered by an RF power supply 125 integrated with matching circuitry 124. The ESC 122 may include electrodes 121 embedded within a dielectric body. The electrodes 121 may be coupled to the RF power supply 125 and can provide a bias voltage that attracts plasma ions formed by process gases in the chamber volume 101 to the ESC 122 and the substrate 302 located on the stage. The RF power supply 125 may be cyclically turned on and off, or pulsed, during processing of the substrate 302. ESC 122 may have an isolator 128, the purpose of which is to reduce the attraction of the sidewalls of ESC 122 to the plasma, thereby extending the maintenance life of ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gas and extend the maintenance interval of the plasma processing chamber 100.

[0035] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide an adsorption voltage of approximately 500 volts to approximately 15,000 volts to electrode 121. Power supply 150 may also include a system controller for controlling the operation of electrode 121 to adsorb and desorb substrate 302 by directing DC current to electrode 121. For example, similar to RF power supply 125, power supply 150 may provide a bias voltage that attracts plasma ions formed by process gases in chamber volume 101 to ESC 122 and substrate 302 located on the stage. Power supply 150 may be cycled on and off, or pulsed, during processing of substrate 302. In embodiments, power supply 150 may be provided with RF power, DC current, or voltage, or a combination thereof, applicable to adsorption and / or bias. In additional embodiments, various power supplies may be configured to supply RF power and DC current or voltage for adsorption and / or bias. ESC 122 may include a heater disposed within a pedestal and connected to a power source for heating the substrate, while a cooling base 129 supporting ESC 122 may include conduits for circulating heat transfer fluid to maintain the temperature of ESC 122 and the substrate 302 disposed thereon. ESC 122 may be configured to operate within the temperature range required by the thermal budget of the apparatus manufactured on substrate 302. For example, depending on the process performed, ESC 122 may be configured to maintain substrate 302 at a temperature of about -150 °C or below about 500 °C or higher.

[0036] A cooling base 129 may be provided to assist in controlling the temperature of the substrate 302. To reduce process drift and time, the temperature of the substrate 302 can be maintained substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. Although any temperature can be used, in some embodiments, the temperature of the substrate 302 can be maintained at a temperature between about -150 °C and about 500 °C throughout the subsequent cleaning process. A cover ring 130 may be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gases to a desired portion of the exposed top surface of the substrate 302 while shielding the top surface of the substrate support pedestal 135 from the plasma environment within the plasma processing chamber 100. Lifting pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism as described above.

[0037] The process sequence can be controlled using controller 165, which regulates the airflow from gas control panel 160 into plasma processing chamber 100 and other processing parameters. When executed by the CPU, the software routine transforms the CPU into a specific-purpose computer, such as a controller, which controls plasma processing chamber 100 to perform the processes described herein. The software routine can also be stored and / or executed by a second controller, which may be associated with plasma processing chamber 100.

[0038] The chambers discussed above can be used for exemplary methods, including etching methods. See also... Figure 3This illustrates exemplary operation of method 300 according to an embodiment of the present technology. Prior to the first operation of the method, the substrate may be treated in one or more ways before being placed into the processing area of ​​the chamber in which method 300 is performed. For example, an oxygen-containing material (such as silicon oxide) may be formed on the substrate, and then one or more patterns may be formed by a shielding material covering the oxygen-containing material. The shielding material may include, but is not limited to, any number of shielding materials. In embodiments, the shielding material may include multiple materials to form a shielding stack. For example, the multiple materials forming the shielding stack may include one or more silicon-containing materials, carbon-containing materials, and / or any other material that can be used as a shielding material. For example, the shielding material may include silicon- and nitrogen-containing materials that can be formed on the oxygen-containing material. Furthermore, the shielding material may include a carbon-containing material (such as amorphous carbon) that can be formed on the oxygen-containing material. One or more patterns may be formed through the layers of the shielding material. Some or all of these operations may be performed in the chamber or system described above, or some or all of these operations may be performed in different chambers on the same system tool, which may include the chamber in which the operation of method 300 is performed.

[0039] Method 300 may include several operations, which may or may not be specifically related to some embodiments of the method according to the present technology. For example, many operations are described to provide a broader scope of structure formation, but these operations are not critical to the technology, or may be performed by alternative methods, which will be described further below. Method 300 may describe Figures 4A to 4C The operations illustrated in the diagram will be described in the operation description of method 300. Figures 4A to 4C The diagram is shown. It should be understood that... Figures 4A to 4C This is only a partial schematic diagram, and the substrate may contain any number of structural blocks having the aspects shown in the diagram, as well as alternative structural aspects that may still benefit from the operation of this technology.

[0040] Method 300 may or may not involve optional operations such as developing a semiconductor structure prior to a particular manufacturing operation. It should be understood that Method 300 can be performed on any number of semiconductor structures, and Figure 4A illustrates an example memory structure in which contact cleaning or etching processes can be performed. As illustrated in Figure 4A, the processed semiconductor structure 400 may include a substrate 405, which may have an oxygen-containing material 410 covering the substrate 405, such as a silicon- and oxygen-containing material (e.g., silicon oxide). In embodiments, the oxygen-containing material 410, such as a silicon- and oxygen-containing material layer, may be a layer in a DRAM structure. A shielding material 415 may cover the oxygen-containing material 410 and may be patterned to form one or more holes 420 extending through the shielding material 415. As previously discussed, the shielding material 415 may be multiple layers, such as various different materials (e.g., silicon- and nitrogen-containing materials and carbon-containing materials, such as amorphous carbon). Sidewalls formed by the shielding material 415 may define one or more holes 420. It should be understood that the structures mentioned are not intended to be limiting and can similarly encompass any of a variety of other semiconductor structures. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, in which oxygen-containing material is to be removed relative to one or more other materials. Furthermore, while high aspect ratio structures may benefit from this technique, it is equally applicable to lower aspect ratio and any other structures.

[0041] As shown, multiple materials can be present and exposed to the etchant material. Method 300 can be performed to etch or remove a portion of the oxygen-containing material 410 exposed within the hole 420, while minimizing the etching of other materials such as the overlying shielding material 415. By utilizing the processing conditions (e.g., temperature) and precursors according to embodiments of the present technology, the etching rate of the oxygen-containing material 410 relative to the shielding material 415 can be increased. Furthermore, compared to conventional techniques, the contour control of features etched into the oxygen-containing material 410 can be more uniform.

[0042] Method 300 may include, in operation 305, providing a precursor (such as an etchant precursor) to a processing region. The processing region may house a substrate 405, such as a processed semiconductor structure 400, for example, the semiconductor structure 400 may have layers of one or more materials disposed on the substrate 405, such as an oxygen-containing material 410 and a shielding material 415. The oxygen-containing material 410 may be exposed in openings or holes 420 in the shielding material 415. The etchant precursor may include fluorine-containing precursors and hydrogen-containing precursors. In embodiments, one or more inert gases or carrier gases may also be provided along with the etchant precursor. For example, the precursor may include any number of carrier gases, which may include argon (Ar), helium (He), nitrogen, or other rare, inert, or useful precursors. The carrier gas may be used to dilute the precursor, which may further reduce the etch rate to allow sufficient diffusion through the holes. In operation 310, plasma effluent may be formed, for example, within the processing region of a semiconductor processing chamber. The plasma effluent may include the plasma effluent of any precursor discussed above. Operations 305 and 310 may occur in various sequences and, in some embodiments, may be performed substantially simultaneously. Furthermore, in different embodiments, plasma may be formed from the precursor or from one or more inert gases before the addition of the etchant precursor.

[0043] Method 300 may include applying a bias power in an optional operation 315. The bias power may increase the directionality of the plasma effluent formed at operation 310. As shown in Figure 4B, in operation 320, the semiconductor structure 400 and substrate 405 may contact the plasma effluent 425 of the etchant precursor, which may etch or remove the oxygen-containing material 410 to form feature 430 in the oxygen-containing material 410. The plasma effluent 425 may contact the semiconductor structure 400 and all exposed surfaces, including the surfaces to be etched (such as the oxygen-containing material 410) and the surfaces to be retained (such as the shielding material 415). Due to the precursors and processing conditions associated with etching feature 430, conventional techniques typically face issues such as decreased etching rates with increasing aspect ratio, bowing, and other contour problems (e.g., bending and / or twisting) caused by sidewall attacks, etch termination, or blockage at the bottom of feature 430, and / or etch imbalance between the oxygen material and the shielding material. However, by providing a precursor and operating under the processing conditions described in this embodiment, problems common in the prior art can be reduced and / or avoided.

[0044] Precursors used in etching processes may include fluorinated and hydrogen-containing precursors, as well as one or more inert gases or carrier gases. Example fluorinated precursors may be or may include nitrogen trifluoride (NF3) or carbon tetrafluoride (CF4), which can be supplied to the processing area. Other fluorine sources may be used in combination with or as alternatives to NF3 or CF4. For example, fluorinated precursors may be or may include NF3, CF4, diatomic fluorine (F2), hydrogen fluoride (HF), hexafluorobutadiene (C4F6), trifluoromethane (CHF3), fluoromethane (CH3F), difluoromethane (CH2F2), methyl fluoride (CH3F), or additional fluorinated materials. Example hydrogen-containing precursors may be diatomic hydrogen (H2), which can be supplied to the processing area. Other hydrogen sources may be used in combination with or as alternatives to H2. For example, hydrogen-containing precursors may include one or more materials, including HF, CHF3, CH2F2, CH3F, water or water vapor (H2O), hydrogen peroxide (H2O2), or additional hydrogen-containing materials.

[0045] In embodiments, plasma effluents from fluorine-containing and hydrogen-containing precursors can form HF-containing plasma. Therefore, contacting the substrate 405 with the plasma effluent can include contacting the substrate 405 with the HF-containing plasma. The plasma effluent formed from the precursors can be locally formed in the processing area or formed in a remote plasma system. For example, the plasma effluent can be generated with or without one or more carrier gases (such as Ar, He, diatomic nitrogen (N2), H2, or mixtures thereof) via a remote plasma source (RPS), capacitively coupled plasma (CCP), or inductively coupled plasma (ICP). The plasma effluent can be a low-level plasma to limit the amount of bombardment and resulting sputtering, the possibility of clogging the orifice 420, and / or the bending / bowing of feature 430. In embodiments, the plasma power may be greater than or about 750 W, and may be greater than or about 800 W, greater than or about 850 W, greater than or about 900 W, greater than or about 950 W, greater than or about 1,000 W, or greater, and the plasma power may also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges. In embodiments, the plasma power may be less than or about 1,250 W, and may be less than or about 1,200 W, less than or about 1,150 W, less than or about 1,100 W, less than or about 1,050 W, less than or about 1,000 W, or less, and the plasma power may also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges. By utilizing low-level plasma power, plasma effluent can be better controlled for delivery through the aperture 420 of the shielding material 415, while limiting sputtering of the shielding material 415 and other exposed surfaces.

[0046] Furthermore, a bias power can be applied to the substrate 405. The bias power can provide directional flow of the plasma effluent 425 to the substrate 405. Thus, the plasma effluent 425 can be directed into the via 420, which facilitates the plasma effluent's travel through the etched oxygen-containing material 410 and to the substrate 405. In embodiments, the bias power can be greater than or about 1,250 W, and can be greater than or about 1,500 W, greater than or about 1,750 W, greater than or about 1,800 W, greater than or about 1,900 W, greater than or about 2,000 W, or greater, and the bias power can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges. The bias power can be less than or about 3,000 W, and can be less than or about 2,750 W, less than or about 2,500 W, less than or about 2,250 W, less than or about 2,000 W or less, and the bias power can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges. By applying bias power, a narrow ion angle distribution can be achieved, providing better profile control (e.g., no bending and / or twisting) and etch perpendicularity. A narrow ion angle distribution can reduce sidewall attack, increase etch rate, and make the etch lead edge more square. However, at higher bias powers (e.g., greater than 3,000 W), selectivity may be reduced due to bombardment of the shielding material 415 and the resulting increase in sputtering. In addition, higher bias power may cause bending / bow bending of feature 430.

[0047] As shown in Figure 4C, the resulting feature 430 may extend through the layers of the oxygen-containing material 410. Although the aspect ratio and depth of the etched feature 430 may depend on the thickness of the oxygen-containing material 410, the feature 430 may be characterized by an aspect ratio greater than or about 2:1, or a height-to-width ratio measured from the upper surface of the substrate 405 to the upper surface of the oxygen-containing material 410. In embodiments, the feature 430 may be characterized by the following aspect ratios: greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 40:1, greater than or about 50:1, or greater, and the aspect ratio may also be included in the range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. Furthermore, the depth of feature 430 measured from the upper surface of substrate 405 to the upper surface of oxygen-containing material 410 may be greater than or about 20 nm, and may be greater than or about 30 nm, greater than or about 40 nm, greater than or about 50 nm, greater than or about 75 nm, greater than or about 100 nm, greater than or about 200 nm, greater than or about 300 nm, greater than or about 400 nm, greater than or about 500 nm, greater than or about 750 nm, greater than or about 1,000 nm or greater, and the depth may also be included in the range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. The critical size or width of feature 430 may be less than or about 50 nm, and may be less than or about 45 nm, less than or about 40 nm, less than or about 35 nm, less than or about 30 nm, less than or about 28 nm, less than or about 26 nm, less than or about 24 nm, less than or about 22 nm, less than or about 20 nm, less than or about 19 nm, less than or about 18 nm, less than or about 17 nm, less than or about 16 nm, less than or about 15 nm, less than or about 14 nm, less than or about 13 nm, less than or about 12 nm, less than or about 11 nm, less than or about 10 nm or smaller, and the critical size or width may also be included in a range between any two of these stated figures, or in any smaller range covered by any of the stated ranges.

[0048] As previously discussed, the increased hydrogen content can enhance the etching rate of the oxygen-containing material 410. At lower temperatures, H2O (a byproduct of removing the oxygen-containing material 410) can condense on the substrate 405 and catalyze and accelerate the etching of the oxygen-containing material 410. For example, this contact can etch features in the layer of oxygen-containing material 410 at etching rates greater than or about 400 Å / min, and features can be etched at etching rates greater than or about 450 Å / min, greater than or about 500 Å / min, greater than or about 550 Å / min, greater than or about 600 Å / min, greater than or about 650 Å / min, greater than or about 700 Å / min, greater than or about 750 Å / min, greater than or about 800 Å / min, greater than or about 900 Å / min, greater than or about 1,000 Å / min or greater, and the etching rate can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges.

[0049] Increasing the etching rate of the oxygen-containing material 410 can also lead to an increase in etching selectivity between the oxygen-containing material 410 and the shielding material 415. In embodiments, the contact can selectively etch the oxygen-containing material 410 relative to the shielding material 415 with a selectivity greater than or about 5:1, and the etching selectivity can be greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1 or greater, and the etching selectivity can also be included in the range between any two of these described figures, or in any smaller range covered by any of the described ranges.

[0050] Process conditions may also affect the operations performed in method 300. In embodiments, each operation of method 300 may be performed during a isothermal period, while in some embodiments, the temperature may be adjusted during different operations. For example, during method 300, the semiconductor processing chamber operating temperature (which may include the substrate, substrate support platform, or chamber temperature) may be maintained at a temperature less than or about 0 °C, and in some embodiments, the temperature may be maintained at less than or about -20 °C, less than or about -40 °C, less than or about -50 °C, less than or about -60 °C, less than or about -70 °C, less than or about -80 °C, less than or about -90 °C, less than or about -100 °C, less than or about -110 °C, less than or about -120 °C, or lower, and the temperature may also be included in a range between any two of these stated figures, or in any smaller range covered by any of the stated ranges. For example, the semiconductor processing chamber operating temperature may be between about -100 °C and about -20 °C, or between any other value previously described. However, at very low temperatures, feature 430 may begin to bow. Therefore, in some embodiments, the semiconductor processing chamber operating temperature can be maintained between about -100°C and about -20°C.

[0051] The pressure within the processing chamber can be controlled during method 300. For example, while forming plasma effluent and performing etching operations, the operating pressure of the semiconductor processing chamber can be maintained at less than or about 2 Torr, and can be less than or about 1 Torr, less than or about 750 millitors, less than or about 500 millitors, less than or about 250 millitors, less than or about 125 millitors, less than or about 100 millitors, less than or about 75 millitors, less than or about 50 millitors, less than or about 45 millitors, less than or about 40 millitors, less than or about 35 millitors, less than or about 30 millitors, less than or about 125 millitors, less than or about 100 millitors, less than or about 75 millitors, less than or about 50 millitors, less than or about 30 millitors, less than or about 125 millitors, less than or about 10 ...100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about 100 millitors, less than or about Approximately 25 mTorr, less than or about 20 mTorr, less than or about 18 mTorr, less than or about 16 mTorr, less than or about 14 mTorr, less than or about 12 mTorr, less than or about 10 mTorr, less than or about 9 mTorr, less than or about 8 mTorr, less than or about 7 mTorr, less than or about 6 mTorr, less than or about 5 mTorr, less than or about 4 mTorr, less than or about 3 mTorr or less, and the pressure may also be included in any range between these stated figures, or in any smaller range covered by any of the stated ranges. The pressure within the processing chamber can affect the ability to flow into the orifice 420. For example, as the pressure increases, it may become more difficult for plasma effluent to penetrate the orifice 420 and reach the etch lead of feature 430.

[0052] In the foregoing description, numerous details have been set forth for illustrative purposes to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art to which this application pertains that certain embodiments may be practiced without some of these details or with additional details.

[0053] Having disclosed several embodiments, those skilled in the art to which this application pertains will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the art, several well-known processes and components have not been described. Therefore, the foregoing description should not be construed as limiting the scope of the art. Additionally, methods or processes may be described as performed sequentially or in steps; however, it should be understood that operations may be performed simultaneously or in a different order than those listed.

[0054] Where a range of values ​​is provided, unless otherwise expressly specified herein, it should be understood that each intermediate value between the upper and lower limits of this range is also specifically disclosed, with precision to the smallest quantile of the lower limit unit. Any narrower range between any stated value or unstated intermediate value within the stated range and any other stated value or intermediate value within this stated range is also included. The upper and lower limits of these narrower ranges may be independently included in or excluded from the stated range, and each range in which any one, no, or both limits are included is also covered by this technique, each range being governed by any specifically excluded limit within the stated range. Where the stated range includes one or both of the included limits, ranges excluding one or both of those included limits are also included.

[0055] As used herein and in the appended claims, unless expressly specified otherwise, the singular forms “a”, “an”, and “the” include multiple references. Thus, for example, reference to “a precursor” includes multiple such precursors, and reference to “the layer” includes reference to one or more layers and equivalents known to a person skilled in the art to which this application pertains, etc.

[0056] Furthermore, when the terms “comprise,” “comprising,” “contain,” “include,” and “including” are used in this specification and in the claims below, they are intended to specify the presence of a stated feature, integer, component, or operation, but such terms do not exclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising the following steps: Fluorine-containing precursors and containing hydrogen A precursor is provided to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, and wherein a silicon-containing material layer is disposed on the substrate; The plasma effluents forming the fluorine-containing precursor and the hydrogen-containing precursor; and The substrate is brought into contact with the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor, wherein the contact etching etches features in the silicon-containing material layer, and wherein the substrate support stage temperature is maintained at below or about -20 °C during the semiconductor processing method.

2. The semiconductor processing method according to claim 1, wherein the fluorine-containing precursor comprises nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), or fluoromethane (CH3F).

3. The semiconductor processing method according to claim 1, wherein the hydrogen-containing precursor comprises diatomic hydrogen (H2).

4. The semiconductor processing method according to claim 1, wherein the silicon-containing material comprises silicon oxide.

5. The semiconductor processing method according to claim 1, wherein the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor forms a hydrogen fluoride (HF) plasma.

6. The semiconductor processing method according to claim 1, wherein the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor is formed at a plasma power greater than or about 750 W.

7. The semiconductor processing method according to claim 1, further comprising the following steps: A bias power is applied while the substrate is brought into contact with the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor.

8. The semiconductor processing method according to claim 7, wherein the bias power is greater than or about 1,500 W.

9. The semiconductor processing method according to claim 1, wherein the features in the oxygen-containing material layer are characterized by a critical size of less than or about 30 nm.

10. The semiconductor processing method according to claim 1, wherein the features in the oxygen-containing material layer are characterized by an aspect ratio greater than or about 5:

1.

11. The semiconductor processing method according to claim 1, wherein the temperature of the substrate support platform is below or about -60 °C.

12. The semiconductor processing method of claim 1, wherein the contact etches the features in the oxygen-containing material layer at an etching rate greater than or about 100 nm / min.

13. A semiconductor processing method, comprising the following steps: A fluorine-containing precursor and a hydrogen-containing precursor are provided to a processing area of ​​a semiconductor processing chamber, wherein a substrate is housed in the processing area, and wherein a silicon- and oxygen-containing material layer is disposed on the substrate. The plasma effluents forming the fluorine-containing precursor and the hydrogen-containing precursor; and The substrate is brought into contact with the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor, wherein the contact etching features in the silicon- and oxygen-containing material layer, and wherein the features in the silicon- and oxygen-containing material layer are characterized by a critical size of less than or about 30 nm.

14. The semiconductor processing method according to claim 13, wherein the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor forms a hydrogen fluoride (HF) plasma.

15. The semiconductor processing method according to claim 13, wherein the silicon and oxygen-containing material layer is a layer in a DRAM structure.

16. The semiconductor processing method according to claim 13, wherein the temperature of the substrate support platform is between about -100 °C and about -20 °C.

17. The semiconductor processing method according to claim 13, wherein the operating pressure of the semiconductor processing chamber is less than or about 2 Torr.

18. A semiconductor processing method, comprising the following steps: An etchant precursor is provided to a processing region of a semiconductor processing chamber, wherein a substrate is housed in the processing region, and wherein a silicon-containing material layer is disposed on the substrate; The plasma effluent forming the etchant precursor, wherein the plasma effluent comprises hydrogen fluoride (HF) plasma; and The substrate is brought into contact with the hydrogen fluoride (HF) plasma, wherein the contact etching etches features in the silicon-containing material layer, and wherein the substrate support stage temperature is maintained at below or about -40 °C during the semiconductor processing method.

19. The semiconductor processing method according to claim 18, wherein the etchant precursor comprises one or more of the following: nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), hexafluorobutadiene (C4F6), and fluoromethane (CH3F).

20. The semiconductor processing method according to claim 18, further comprising the following steps: While bringing the substrate into contact with the plasma effluent of the etchant precursor, a bias power is applied, wherein the bias power is greater than or about 1,250 W.

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