Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device capable of accurately maintaining a gap between a housing and a multilayer substrate. A case of a semiconductor device is provided with: an exterior member (11a) which faces the upper surface of a wiring substrate (20) and is disposed with a second gap from the upper surface of the wiring substrate (20); an external connection terminal (12a) fixed to the exterior member (11a), the lower end of the external connection terminal (12a) being inserted into the wiring hole (22a) of the wiring substrate (20) and electrically connected to the wiring hole (22a); a first isolation member (14a) that protrudes from the lower surface of the exterior member (11a) and is inserted through the guide hole (23a) of the wiring board (20), the lower end of the first isolation member (14a) being in contact with the upper surface of the circuit board (30) to maintain a first gap (L1) between the lower surface of the exterior member (11a) and the upper surface of the circuit board (30); and a second isolation member (15a) protruding from the lower surface of the exterior member (11a), the lower end of the second isolation member (15a) being in contact with the upper surface of the wiring substrate (20) to maintain a second gap (L2) between the lower surface of the exterior member (11a) and the upper surface of the wiring substrate (20).

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] A semiconductor device is proposed, comprising a semiconductor mounting substrate on which semiconductor elements are mounted, and an implantation substrate disposed on the upper surface side of the substrate, wherein the end of an implantation pin pressed into a via provided in the implantation substrate is electrically connected to the semiconductor device (for example, see reference 1).

[0003] In addition, an automotive semiconductor device is proposed, which includes a lower substrate, a positioning plate disposed on the upper side of the lower substrate, an upper substrate disposed on the upper side of the positioning plate, and a vertical terminal inserted through a terminal through-hole formed in both the lower substrate and the upper substrate (for example, see reference 2).

[0004] In addition, a semiconductor device is proposed having a substrate on which semiconductor elements and a first terminal and a second terminal are mounted, and a housing having a terminal holding member surrounding the first terminal and the second terminal (for example, see reference 3).

[0005] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2013-125803 Patent Document 2: Japanese Patent Application Publication No. 2010-278093 Patent Document 3: Japanese Patent Application Publication No. 2005-223141 Summary of the Invention

[0006] Technical issues The purpose of this invention is to provide a semiconductor device capable of accurately maintaining the spacing between the housing and the multilayer substrate, as well as a method for manufacturing the semiconductor device.

[0007] Technical solution According to one aspect of the invention, a semiconductor device is provided, comprising: a circuit substrate; a wiring substrate facing the upper surface of the circuit substrate, disposed with a first gap spaced relative to the upper surface of the circuit substrate, and having a wiring hole and a guide hole therethrough; a housing including an outer mounting member, an external connection terminal, a first isolation member, and a second isolation member, wherein the outer mounting member faces the upper surface of the wiring substrate and is disposed with a second gap spaced relative to the upper surface of the wiring substrate, and the external connection terminal is fixed to the outer mounting member, and its lower end is inserted into the wiring hole of the wiring substrate and... The wiring hole is electrically connected, the first isolation member protrudes from the lower surface of the outer component and inserts into the guide hole of the wiring substrate, and its lower end abuts against the upper surface of the circuit board to maintain a first gap between the lower surface of the outer component and the upper surface of the circuit board; the second isolation member protrudes from the lower surface of the outer component and its lower end abuts against the upper surface of the wiring substrate to maintain a second gap between the lower surface of the outer component and the upper surface of the wiring substrate; and a sealing member fills the first gap and the second gap to seal the wiring substrate.

[0008] Additionally, according to one aspect of the invention, a method for manufacturing a semiconductor device is provided, comprising: a preparation step, preparing a circuit board, a wiring board having through-holes and guide holes, and a housing, the housing comprising: an outer mounting member for fixing external connection terminals, one end of the external connection terminals protruding from a main surface of one side of the outer mounting member; a first isolation member protruding from the main surface of the outer mounting member on the same side; and a second isolation member protruding from the main surface of the outer mounting member on the same side and having a length from the main surface of the same side shorter than the length of the first isolation member from the main surface of the same side; and a first assembly step, wherein the wiring board protrudes from the main surface of the outer mounting member on the same side within the housing. In the first assembly step, the circuit board is positioned opposite the outer component to the wiring hole, and the first isolation member inserted through the guide hole is electrically connected to the wiring hole and the external connection terminal, so that the end of the second isolation member abuts against the wiring substrate; in the second assembly step, the circuit board is positioned opposite the outer component relative to the wiring substrate, so that the first isolation member inserted through the guide hole of the wiring substrate abuts against the circuit board; and in the sealing step, a sealing member is filled into the first gap between the circuit board and the wiring substrate and the second gap between the wiring substrate and the outer component to seal the wiring substrate.

[0009] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention.

[0010] Technical effect According to the disclosed technology, the spacing between the housing and the multilayer substrate can be accurately maintained.

[0011] The above and other objects, features and advantages of the present invention will become apparent from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the invention. Attached Figure Description

[0012] Figure 1 It is a top view showing the appearance of a semiconductor device.

[0013] Figure 2 This is a side view showing the appearance of a semiconductor device.

[0014] Figure 3 This is a top view of the semiconductor device with the sealing and cover components removed.

[0015] Figure 4 This is a side view of a semiconductor device with the sealing components removed.

[0016] Figure 5 This is a top view of the wiring board.

[0017] Figure 6 This is a top view of the circuit board and external connection terminals.

[0018] Figure 7 This is a diagram showing an example of the circuit configuration of a three-level inverter.

[0019] Figure 8 This is a diagram showing the location of the isolation components.

[0020] Figure 9 It is an enlarged cross-sectional view of the installation area of ​​the isolation component.

[0021] Figure 10 This is a flowchart illustrating the manufacturing process of a semiconductor device.

[0022] Figure 11 This diagram illustrates the mounting process of the wiring board relative to the external components.

[0023] Figure 12 This is a diagram showing the location of the gate opening.

[0024] Figure 13 This is a top view showing a modified example of the isolation component.

[0025] Figure 14 It is a top view and cross-sectional view of the installation area of ​​the isolation component.

[0026] Explanation of reference numerals in the attached figures 1. Semiconductor device 10. Shell 10a Storage components 10b, 10c Terminal holding components 10d cover component 11a External components 11a1, 11a2 Edges 11b Sidewall 11c, 11d openings External connection terminals 12a~12j, 13a~13d 12a1, 12b1 ends 13a1, 13b1, 13c1, 13d1 Flat plate section Connection parts 13a2, 13b2, 13c2, 13d2 14a~14d, 17a~17d First isolation member 15a~15d, 18a~18d Second isolation components 16a, 16b Gating nozzle 20 Wiring substrate 20a First Edge Section 20b Second Edge 21a, 21b wiring pins Wiring holes 22a~22j 23a~23d, 23a1 guide holes Circuit patterns 24a~24c 30 Circuit board Semiconductor chips 31a1~31a4, 31b1~31b4, 31c1~31c4, 31d1~31d4, 31e 32 Insulation Board 33a~33g circuit patterns 34a and 34b solders 40 Sealing components Areas A1 and A2 G1~G4 gate terminals L1 First Interval L2 Second Interval Transistors Q1 to Q4 S1~S4 Auxiliary Source Extremes Detailed Implementation

[0027] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, the X and Y axes are defined on a horizontal plane, the Z axis is defined in a direction perpendicular to the horizontal plane, the +Z direction is defined as the upper side, and the -Z direction is defined as the lower side. Furthermore, the terms "upper surface," "upper," "front," "lower surface," "lower," "back," and "side" are merely expressions to facilitate the determination of relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0028] First, use Figure 1 and Figure 2 The appearance of the semiconductor device according to the embodiment will be described. Figure 1 It is a top view showing the appearance of a semiconductor device. Figure 2 This is a side view showing the appearance of the semiconductor device. It should be noted that... Figure 2 Observing from the +X direction Figure 1 A side view of the semiconductor device 1.

[0029] Semiconductor device 1 is a modular assembly consisting of a circuit board housing a semiconductor chip, external connection terminals, etc. Semiconductor device 1 is mounted on the front side (+Z direction side) of a cooling module (not shown). It should be noted that the cooling module may be, for example, a heat sink with heat dissipation fins or a cooling device in which a cooling medium circulates internally.

[0030] Semiconductor device 1 has the ability to... Figure 4 The housing 10 houses the wiring board 20 and circuit board 30, as described later. The housing 10 includes a housing member 10a, terminal holding members 10b and 10c, and a cover member 10d. The terminal holding member 10b is integrally connected to the -Y direction side of the housing member 10a, and the terminal holding member 10c is integrally connected to the +Y direction side of the housing member 10a. The cover member 10d is disposed at the opening 11c, which is also disposed on the outer member 11a. In this case, the cover member 10d can be integrally formed with the outer member 11a to close the opening 11c.

[0031] The storage member 10a is, for example, box-shaped and includes an outer member 11a forming an upper surface parallel to the horizontal plane (XY plane), a side wall parallel to the YZ plane, and a side wall parallel to the XY plane. The side wall parallel to the YZ plane is formed on the underside (-Z direction side) of the respective end edges in the +X and -X directions of the outer member 11a. Figure 2The figure shows the sidewall 11b on the -X direction side, but the reference numerals for the sidewall on the +X direction side are omitted. Sidewalls (reference numerals omitted) parallel to the XY plane are formed on the underside of the respective end edges on the +Y and -Y directions of the outer member 11a.

[0032] It should be noted that the sidewalls of the external component 11a and the +X and -X directions can be flat and integrally connected. In addition, the sidewall of the +Y direction can be integral with the end face of the terminal holding component 10c on the -Y direction, and the sidewall of the -Y direction can be integral with the end face of the terminal holding component 10b on the +Y direction.

[0033] In addition, the storage component 10a is not limited to a box shape, and may include an outer component 11a, and a side wall formed on the lower side of the respective end edge of the +Y direction side and the -Y direction side of the outer component 11a, which is parallel to the XY plane.

[0034] The outer component 11a has a rectangular shape when viewed from above. Furthermore, when viewed from above, a rectangular opening 11c is formed in the center of the outer component 11a. The opening 11c can be closed by a cover component 10d integrally formed with the outer component 11a.

[0035] The housing member 10a includes a region (housing section) surrounded by the lower surface of the outer member 11a, the sidewalls on the +X and -X directions, and the sidewalls on the +Y and -Y directions. The wiring substrate 20 and circuit board 30 are housed in this housing section. The outer member 11a forms an outer casing on the upper side of the wiring substrate 20 and circuit board 30 housed in the housing section.

[0036] On the other hand, openings for injecting the sealing member 40 are provided on the +X and -X direction sides of the storage section. In this embodiment, as an example, sidewalls are also provided on the +X and -X direction sides of the storage section, and openings are provided in a portion of each sidewall. For example, in... Figure 2 The diagram shows a sidewall 11b provided at the end edge of the outer component 11a on the -X direction side. An opening 11d is formed in the sidewall 11b, opening downwards (on the -Z direction side). The opening 11d is formed between the sidewall (terminal holding member 10c) on the +Y direction side of the receiving component 10a and the sidewall (terminal holding member 10b) on the -Y direction side. The interior of the receiving component is sealed by a sealing member 40, and the opening 11d is closed from the inside by the sealing member 40. Similarly, the opening 11c of the outer component 11a is also closed from the inside by the sealing member 40. As described above, the sealing member 40 that closes the opening 11c is further closed by the cover member 10d.

[0037] The outer component 11a includes edges 11a1 (first region) and 11a2 (second region) extending along the Y-axis direction on the -X and +X directions of the opening 11c, respectively. External connection terminals 12a-12d, 12i, and 12j are provided on the edge 11a1 of the outer component 11a. External connection terminals 12e-12h are provided on the edge 11a2 on the +X direction side of the outer component 11a. The external connection terminals 12a-12j are cylindrical, extending approximately vertically. The cylindrical shape can refer to a prism or a cylinder; here, a cylindrical press-fit pin is shown as an example.

[0038] External connection terminals 12a-12d, 12i, and 12j are fixed to edge 11a1 with their upper and lower (±Z directions) portions passing through edge 11a1. External connection terminals 12e-12h are fixed to edge 11a2 with their upper and lower (±Z directions) portions passing through edge 11a2. Furthermore, the upper ends of external connection terminals 12a-12j, which protrude from the upper surface of outer member 11a, become connection terminal portions for connection with external circuitry. On the other hand, as described later, the lower ends of external connection terminals 12a-12j, which protrude from the lower surface of outer member 11a, are inserted into wiring holes provided on wiring substrate 20 and electrically connected to wiring layers formed on wiring substrate 20.

[0039] External connection terminals 13a to 13c are provided on the terminal holding member 10b. Flat plate portions 13a1 to 13c1 are formed at the ends (outer ends) of the external connection terminals 13a to 13c in the -Y direction direction, respectively (see reference). Figure 6 External connection terminals 13a to 13c are held in the terminal holding member 10b with the upper surfaces of the flat portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b, respectively. Furthermore, the flat portions 13a1 to 13c1 exposed on the upper surface of the terminal holding member 10b become connection terminal portions for connection to external circuitry. On the other hand, as described later, the +Y direction end (inner end) of the external connection terminals 13a to 13c is connected to the circuit pattern on the upper surface of the circuit board 30 inside the receiving member 10a.

[0040] An external connection terminal 13d is provided on the terminal holding member 10c. A flat plate portion 13d1 is formed at the +Y direction side end (outer end) of the external connection terminal 13d (see reference). Figure 6The external connection terminal 13d is held in the terminal holding member 10c with the upper surface of the flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c. Furthermore, the flat plate portion 13d1 exposed on the upper surface of the terminal holding member 10c becomes a connection terminal portion for connection to an external circuit. On the other hand, as described later, the end (inner end) of the external connection terminal 13d in the -Y direction is connected to the circuit pattern on the upper surface of the circuit board 30 inside the receiving member 10a.

[0041] In this embodiment, a three-level inverter circuit is constituted by a wiring board 20, a circuit board 30 housed inside the housing 10, and a semiconductor chip described later. External connection terminals 13a to 13d correspond to the N-terminal, P-terminal, neutral terminal, and output terminal of the three-level inverter circuit, respectively. External connection terminals 12a to 12h correspond to control terminals used to control the switching operations of the transistors included in the three-level inverter circuit. External connection terminals 12i and 12j correspond to output terminals that output sensing signals from the semiconductor chip performing various sensing operations.

[0042] It should be noted that the housing 10, including the receiving member 10a and the terminal retaining members 10b and 10c, includes a portion of the external connection terminals 12a-12j and 13a-13d, and is integrally molded using thermoplastic resin by injection molding. The cover member 10d can be formed separately using thermoplastic resin by injection molding. Alternatively, the cover member 10d can also be integrally molded using thermoplastic resin by injection molding, in addition to the receiving member 10a and the terminal retaining members 10b and 10c. Thermoplastic resins include, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, acrylonitrile butadiene styrene resin, or liquid crystal polymers. Furthermore, the external connection terminals 12a-12j and 13a-13d are formed of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or alloys with at least one of these as a main component.

[0043] Figure 3 This is a top view of the semiconductor device with the sealing and cover components removed. Figure 4 This is a side view of a semiconductor device with the sealing components removed.

[0044] A wiring substrate 20 and a circuit board 30 are housed on the lower surface of the outer component 11a. Both the wiring substrate 20 and the circuit board 30 are rectangular in shape when viewed from above. The wiring substrate 20 is positioned with its upper surface facing the lower surface of the outer component 11a, separated by a second gap. Furthermore, the wiring substrate 20 has multiple wiring holes (described later), and the wiring substrate 20 is fixed relative to the outer component 11a by pressing the lower ends of the external connection terminals 12a-12j into the corresponding wiring holes. The external connection terminals 12a-12j are electrically connected to the wiring layers included in the wiring substrate 20. The circuit board 30 is positioned with its upper surface facing the lower surface of the wiring substrate 20, separated by a first gap from the lower surface of the outer component 11a.

[0045] Multiple semiconductor chips are mounted on the upper surface of the circuit board 30. Figure 4 The diagram illustrates semiconductor chips 31b1, 31b2, 31d1, 31d2, and 31e. On the other hand, a plurality of cylindrical wiring pins extending vertically are inserted into the wiring substrate 20. The upper end of each wiring pin is electrically connected to the wiring layer included in the wiring substrate 20, and the lower end of each wiring pin is electrically connected to the output electrode and control electrode on the upper surface of the corresponding semiconductor chip via solder. For example, in... Figure 4 In this circuit, wiring pins 21a and 21b are provided on the wiring substrate 20. The lower ends of the wiring pins 21a and 21b are electrically connected to the upper surfaces of the semiconductor chips 31b1 and 31e respectively through solder. Therefore, the external connection terminals 12a to 12j are electrically connected to the output electrode and control electrode of the semiconductor chip via the wiring substrate 20 and each wiring pin.

[0046] Furthermore, with the wiring substrate 20 and circuit board 30 arranged relative to the outer mounting member 11a as described above, a sealing member 40 is filled at least in the area between the lower surface of the outer mounting member 11a and the upper surface of the circuit board 30, thereby sealing the wiring substrate 20 and the semiconductor chip. In this embodiment, the sidewalls around the circuit board 30 and the lower part of the outer mounting member 11a do not contact the terminal holding members 10b and 10c when viewed from above. Therefore, the sealing member 40 fills the area by covering the side of the circuit board 30, and the back surface of the circuit board 30 is exposed from the back surface (the surface on the -Z direction side) of the housing member 10a (housing 10). In addition, the back surface of the circuit board 30 may be on the same plane as the back surfaces of the housing member 10a and the terminal holding members 10b and 10c of the housing 10.

[0047] A thermosetting resin is used as the sealing material for the sealing member 40. For example, epoxy resin is used. By using such a resin to transfer mold the housing 10, which houses the wiring substrate 20, the circuit board 30, and the semiconductor chip, a semiconductor device 1 with high rigidity is manufactured. In particular, high rigidity of the semiconductor device 1 relative to the vertical direction (Z-axis direction) can be obtained, and even when a force is applied from the outside along the vertical direction, predetermined intervals can be maintained between the outer component 11a and the wiring substrate 20, and between the wiring substrate 20 and the circuit board 30.

[0048] Figure 5 This is a top view of the wiring substrate. The wiring substrate 20 is, for example, a multilayer printed circuit board (PCB). In the wiring substrate 20, for example, a wiring layer may be formed on at least one of the upper and lower surfaces of the insulating layer, and more than one wiring layer may also be formed inside the insulating layer.

[0049] The insulating layer is formed, for example, of an insulating resin. Examples of insulating resins include paper-phenolic resin substrates, paper-epoxy resin substrates, glass composite substrates, and glass-epoxy resin substrates. The wiring layer is formed of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy with at least one of these as a main component.

[0050] A plurality of wiring holes (through holes) are provided through the wiring substrate 20, and wiring leads are inserted into each wiring hole. The wiring leads are formed of a metal with excellent conductivity. Each wiring hole is connected to a circuit pattern of any wiring layer formed on the wiring substrate 20, and the wiring leads are electrically connected to the circuit patterns connected to the inserted wiring holes. These wiring leads protrude at least on the lower surface side of the corresponding wiring hole. Alternatively, the wiring leads may protrude on the upper surface side of the corresponding wiring hole to a degree that does not contact the lower surface of the outer component 11a. It should be noted that in Figure 5 In the diagram, wiring pins 21a and 21b are illustrated as such wiring pins. Figure 4 As shown, the lower ends of wiring pins 21a and 21b are electrically connected to the output electrodes and control electrodes on the upper surfaces of semiconductor chips 31b1 and 31e mounted on the circuit board 30 via solder.

[0051] Furthermore, wiring holes (through holes) 22a to 22j are provided through the wiring substrate 20. Wiring holes 22a to 22d, 22i, and 22j are arranged along the first edge 20a on the -X direction side of the wiring substrate 20. When the wiring substrate 20 is mounted on the outer component 11a, the area of ​​this first edge 20a becomes the area opposite to the lower surface of the edge 11a1 of the outer component 11a. External connection terminals 12a to 12d, 12i, and 12j are inserted into the wiring holes 22a to 22d, 22i, and 22j, respectively. Additionally, wiring holes 22e to 22h are arranged along the second edge 20b on the +X direction side of the wiring substrate 20. When the wiring substrate 20 is mounted on the outer component 11a, the area of ​​this second edge 20b becomes the area opposite to the lower surface of the edge 11a2 of the outer component 11a. Furthermore, the lower ends of external connection terminals 12e to 12h are inserted into wiring holes 22e to 22h respectively.

[0052] Wiring holes 22a to 22j are also connected to the circuit pattern of any wiring layer formed on the wiring substrate 20. Furthermore, by inserting the lower ends of external connection terminals 12a to 12j into wiring holes 22a to 22j, external connection terminals 12a to 12j are electrically connected to the circuit patterns connected to the inserted wiring holes 22a to 22j.

[0053] In addition, the wiring substrate 20 may also have through holes for electrically connecting the wiring layers.

[0054] Furthermore, guide holes 23a to 23d are provided through the wiring substrate 20. When the wiring substrate 20 is mounted on the outer component 11a, the guide holes 23a and 23b are arranged along the edge 11a1 of the outer component 11a in a top view. Additionally, when the wiring substrate 20 is mounted on the outer component 11a, the guide holes 23c and 23d are arranged along the edge 11a2 of the outer component 11a in a top view. Details regarding the guide holes 23a to 23d will be explained later.

[0055] Figure 6 This is a top view of the circuit board and external connection terminals.

[0056] The circuit board 30 includes an insulating plate 32 forming the bottom surface, circuit patterns 33a to 33g formed on the upper surface (+Z direction side) of the insulating plate 32, and a metal plate (not shown) formed on the lower surface (-Z direction side) of the insulating plate 32. Furthermore, semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, and 31e are mounted on the circuit board 30.

[0057] The insulating board 32 is made of resin, for example. The resin can be a material with low thermal resistance and high insulation, and can be a thermosetting resin or a thermoplastic resin. Examples of thermosetting resins include at least one selected from epoxy resin, cyanate ester resin, polyimide resin, benzoxazine resin, unsaturated polyester resin, phenolic resin, melamine resin, silicone resin, and maleimide resin. Examples of thermoplastic resins include at least one selected from acrylic resin and polyamide resin. Furthermore, these resins may contain fillers. The fillers are made of at least one selected from oxides and nitrides. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Hexagonal boron nitride may also be used as a filler.

[0058] The insulating plate 32 can be a ceramic substrate instead of resin. The ceramic substrate is made of ceramic with good thermal conductivity. The ceramic is, for example, made of a material mainly composed of alumina, aluminum nitride, and silicon nitride. The insulating circuit board 30, including the insulating plate 32 having such a structure, can, for example, use a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate.

[0059] It should be noted that in this embodiment, the insulating plate 32 is made of resin, and the difference between the coefficient of linear expansion of the insulating plate 32 and the coefficient of linear expansion of the metal plate and the circuit patterns 33a to 33g is small.

[0060] The circuit patterns 33a-33f and the metal plate are formed of a metal with excellent electrical conductivity. Such a metal is, for example, copper, aluminum, or an alloy with at least one of them as the main component.

[0061] Semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, and 31d1-31d4 can be power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) primarily composed of silicon carbide. In a power MOSFET, the body diode can function as a freewheeling diode (FWD). Such semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, and 31d1-31d4, for example, have an input electrode (drain electrode) as the main electrode on the back side, and an output electrode (source electrode) and a control electrode (gate electrode) as the main electrode on the front side.

[0062] Alternatively, semiconductor chips 31a1–31a4, 31b1–31b4, 31c1–31c4, and 31d1–31d4 may include switching elements primarily composed of silicon. These switching elements may be, for example, RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). An RC-IGBT is a semiconductor element formed by connecting an IGBT and a FWD in reverse parallel within a single chip. Such semiconductor chips 31a1–31a4, 31b1–31b4, 31c1–31c4, and 31d1–31d4, for example, have an input electrode (collector electrode) as the main electrode on the back side, and an output electrode (emitter electrode) and a control electrode (gate electrode) as the main electrode on the front side.

[0063] Furthermore, semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, and 31d1-31d4 can each be a semiconductor chip comprising a group of switching elements and diode elements mainly composed of silicon. The switching elements are, for example, power MOSFETs or IGBTs. The semiconductor chip including the switching elements has, for example, an input electrode (drain electrode in a power MOSFET, collector electrode in an IGBT) as the main electrode on the back side, and a gate electrode as the control electrode and an output electrode (source electrode in a power MOSFET, emitter electrode in an IGBT) as the main electrode on the front side. Additionally, the diode elements are, for example, SBD (Schottky Barrier Diode) or PiN (P-intrinsic-N) diodes as the FWD. The semiconductor chip including the diode elements has, for example, an output electrode (cathode) as the main electrode on the back side and an input electrode (anode) as the main electrode on the front side.

[0064] It should be noted that in this embodiment, the semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, and 31d1 to 31d4 are shown as power MOSFETs mainly composed of silicon carbide.

[0065] Semiconductor chips 31c1 to 31c4 are mounted on the upper surface of circuit pattern 33c. Although not shown in the figure, the input electrodes of the lower surfaces of semiconductor chips 31c1 to 31c4 are electrically connected to the upper surface of circuit pattern 33c via solder. Semiconductor chips 31d1 to 31d4 are mounted on the upper surface of circuit pattern 33d. Although not shown in the figure, the input electrodes of the lower surfaces of semiconductor chips 31d1 to 31d4 are electrically connected to the upper surface of circuit pattern 33d via solder. Semiconductor chips 31a1 to 31a4 and 31b1 to 31b4 are mounted on the upper surface of circuit pattern 33e. Although not shown in the figure, the input electrodes of the lower surfaces of semiconductor chips 31a1 to 31a4 and 31b1 to 31b4 are electrically connected to the upper surface of circuit pattern 33e via solder.

[0066] A semiconductor chip 31e is mounted on the upper surface of the circuit pattern 33g. The semiconductor chip 31e includes semiconductor elements that perform various sensing operations. For example, the semiconductor chip 31e includes a diode element for detecting temperature. Although not shown in the figure, electrodes disposed on the lower surface of the semiconductor chip 31e are electrically connected to the upper surface of the circuit pattern 33g via solder.

[0067] The circuit pattern 33a is electrically connected to the external connection terminal 13a. Specifically, a flat plate portion 13a1 is formed at the end of the external connection terminal 13a on the -Y direction side. Furthermore, at the end of the flat plate portion 13a1 on the +Y direction side of the external connection terminal 13a, a flat plate-shaped connecting portion 13a2 is formed in the horizontal direction via a middle portion (not shown) extending downward (in the -Z direction). The lower surface of the connecting portion 13a2 is engaged with the upper surface of the circuit pattern 33a.

[0068] Circuit pattern 33b is electrically connected to external connection terminal 13c. Specifically, a flat plate portion 13c1 is formed at the end of the external connection terminal 13c on the -Y direction side. Furthermore, at the end of the flat plate portion 13c1 on the +Y direction side of the external connection terminal 13c, a flat plate-shaped connecting portion 13c2 is formed in the horizontal direction via a middle portion (not shown) extending downward (in the -Z direction). The lower surface of the connecting portion 13c2 is engaged with the upper surface of circuit pattern 33b.

[0069] The circuit pattern 33d is electrically connected to the external connection terminal 13b. Specifically, a flat plate portion 13b1 is formed at the end of the external connection terminal 13b in the -Y direction. Furthermore, at the end of the flat plate portion 13b1 in the external connection terminal 13b in the +Y direction, a flat plate-shaped connecting portion 13b2 is formed in the horizontal direction via a middle portion (not shown) extending downward (in the -Z direction). The lower surface of the connecting portion 13b2 is engaged with the upper surface of the circuit pattern 33d.

[0070] The circuit pattern 33f is electrically connected to the external connection terminal 13d. Specifically, a flat plate portion 13d1 is formed at the end of the external connection terminal 13d on the +Y direction side. Furthermore, at the end of the flat plate portion 13d1 on the -Y direction side of the external connection terminal 13d, a flat plate-shaped connecting portion 13d2 is formed in the horizontal direction via a middle portion (not shown) extending downward (in the -Z direction). The lower surface of the connecting portion 13d2 is engaged with the upper surface of the circuit pattern 33f.

[0071] Figure 7 This is a diagram illustrating an example of the circuit configuration of a three-level inverter. Semiconductor device 1, for example, includes... Figure 7 The diagram shows a three-level inverter. This three-level inverter is a T-type NPC (Neutral Point Clamped) inverter circuit, comprising four transistors Q1 to Q4. Transistor Q1 corresponds to semiconductor chips 31d1 to 31d4, and transistor Q2 corresponds to semiconductor chips 31c1 to 31c4. Additionally, transistor Q3 corresponds to semiconductor chips 31b1 to 31b4, and transistor Q4 corresponds to semiconductor chips 31a1 to 31a4.

[0072] The drain electrode of transistor Q1 is connected to the P terminal, which is the positive input terminal, via the circuit board 30. The P terminal corresponds to the external connection terminal 13b. The source electrode of transistor Q2 is connected to the N terminal, which is the negative input terminal, via the wiring board 20 and the circuit board 30. The N terminal corresponds to the external connection terminal 13a.

[0073] The drain electrode of transistor Q3 is connected to the drain electrode of transistor Q4 via circuit board 30, and the source electrode of transistor Q3 is connected to the M terminal (neutral terminal), which is an input terminal at an intermediate potential, via wiring board 20 and circuit board 30. The M terminal corresponds to the external connection terminal 13c.

[0074] The source electrode of transistor Q1, the drain electrode of transistor Q2, and the source electrode of transistor Q4 are connected via circuit board 30 and wiring board 20, and their connection point is connected to the U terminal, which serves as an output terminal, via wiring board 20 and circuit board 30. The U terminal corresponds to the external connection terminal 13d.

[0075] The gate electrodes of transistors Q1 to Q4 are connected to gate terminals (control terminals) G1 to G4 via wiring substrate 20, respectively. These gate terminals (control terminals) G1 to G4 are input terminals for the control signals of the switching operation. Gate terminals G1 to G4 correspond to external connection terminals 12c, 12g, 12b, and 12f, respectively. It should be noted that the source electrodes of transistors Q1 to Q4 are connected to auxiliary source terminals S1 to S4, which serve as output terminals, via wiring substrate 20, respectively. Auxiliary source terminals S1 to S4 correspond to external connection terminals 12d, 12h, 12a, and 12e, respectively.

[0076] In this three-level inverter, when the control signals to gate terminals G1 and G2 are turned on and the control signals to gate terminals G3 and G4 are turned off, the output voltage from terminal U becomes E / 2. When the control signals to gate terminals G2 and G3 are turned on and the control signals to gate terminals G1 and G4 are turned off, the output voltage from terminal U becomes 0. When the control signals to gate terminals G3 and G4 are turned on and the control signals to gate terminals G1 and G2 are turned off, the output voltage from terminal U becomes -E / 2.

[0077] It should be noted that the semiconductor device 1 in this embodiment is equipped with four sets of transistors Q1 to Q4. Therefore, the semiconductor device 1 includes four sets of three-level inverters, each including transistors Q1 to Q4. These three-level inverters are connected in parallel. Although not shown in the figure, three semiconductor devices 1 with such parallel three-level inverters are used in combination. One semiconductor device 1 generates a U-phase output voltage, another semiconductor device 1 generates a V-phase output voltage, and a third semiconductor device 1 generates a W-phase output voltage.

[0078] Next, use Figure 8 and Figure 9 The isolation member used to determine the position of the wiring board 20 and the circuit board 30 relative to the outer casing member 11a of the housing 10 will be described.

[0079] Figure 8 This is a diagram showing the positions of the isolation members. First isolation members 14a-14d and second isolation members 15a-15d are provided on the lower surface of the outer casing member 11a of the housing 10. The first isolation members 14a, 14b and the second isolation members 15a, 15b extend from the edge 11a1 of the outer casing member 11a (see...). Figure 1 The lower surface of the outer component 11a protrudes. The first isolation members 14c, 14d and the second isolation members 15c, 15d protrude from the edge 11a2 of the outer component 11a (see...). Figure 1 The lower surface of the ) protrudes.

[0080] The first isolation members 14a-14d and the second isolation members 15a-15d are columnar in shape. In this embodiment, as an example, the first isolation members 14a-14d and the second isolation members 15a-15d are cylindrical, but they may also be prismatic, for example. The vertical lengths (L1) of the first isolation members 14a-14d are the same. The vertical lengths (L2) of the second isolation members 15a-15d are all the same, and are shorter than those of the first isolation members 14a-14d.

[0081] With the wiring substrate 20 mounted relative to the outer component 11a, the lower ends of the second isolation members 15a to 15d abut against the upper surface of the wiring substrate 20. Therefore, the distance between the lower surface of the outer component 11a and the upper surface of the wiring substrate 20 is maintained at a predetermined second distance L2. Furthermore, in this state, the first isolation members 14a to 14d are respectively inserted into the guide holes 23a to 23d provided in the wiring substrate 20 (see reference). Figure 5 The lower ends of the first isolation members 14a to 14d abut against the upper surface of the circuit board 30. As a result, the distance between the lower surface of the outer member 11a and the upper surface of the circuit board 30 is maintained at a predetermined first distance L1, and consequently, the distance between the lower surface of the wiring board 20 and the upper surface of the circuit board 30 is also maintained at a predetermined distance. Simultaneously, by inserting the first isolation members 14a to 14d through the guide holes 23a to 23d respectively, the horizontal relative position of the wiring board 20 with respect to the outer member 11a is positioned.

[0082] Figure 9 This is an enlarged cross-sectional view of the installation area of ​​the isolation component. Figure 9 It involves cutting using the I1-I1 line. Figure 8 An enlarged cross-sectional view of region A1. Inside the housing 10, it is configured as follows: Figure 3 and Figure 4 The wiring board 20 and the circuit board 30 are mounted as shown.

[0083] In region A1, external connection terminals 12a and 12b are fixed to the edge 11a1 of the outer component 11a in a vertically penetrating state. Furthermore, the lower ends of the external connection terminals 12a and 12b are respectively inserted into wiring holes 22a and 22b provided in the wiring substrate 20. For example, circuit patterns 24a and 24b are formed on the upper surface of the wiring substrate 20 at positions surrounding the wiring holes 22a and 22b. By inserting the lower ends of the external connection terminals 12a and 12b into the wiring holes 22a and 22b, the external connection terminals 12a and 12b are electrically connected to the circuit patterns 24a and 24b. Additionally, by pressing the lower ends of the external connection terminals 12a and 12b into the wiring holes 22a and 22b, the wiring substrate 20 is fixed relative to the edge 11a1 of the outer component 11a.

[0084] Furthermore, in region A1, the first isolation member 14a and the second isolation member 15a protrude from the lower surface of the edge 11a1 of the outer component 11a. The lower end of the second isolation member 15a abuts against the upper surface of the wiring substrate 20. Thus, the distance between the lower surface of the edge 11a1 and the upper surface of the wiring substrate 20 is maintained at a length in the vertical direction of the second isolation member 15a, i.e., a second gap L2.

[0085] Here, the second gap L2 is preset to allow the lower ends of the external connection terminals 12a and 12b to reach or exceed the lower ends of the wiring holes 22a and 22b by a predetermined position. Therefore, when the external connection terminals 12a and 12b, mounted on the outer component 11a, are pressed into the wiring holes 22a and 22b of the wiring substrate 20, the predetermined second gap L2 between the lower surface of the edge 11a1 of the outer component 11a and the upper surface of the wiring substrate 20 can be set simply by pressing the front end of the second isolation member 15a until it abuts against the upper surface of the wiring substrate 20. Thus, high positioning accuracy relative to the vertical direction can be obtained through a simplified manufacturing process, improving the assembly workability of the semiconductor device 1.

[0086] Furthermore, the first isolation member 14a is inserted through the guide hole 23a provided in the wiring substrate 20, and its lower end abuts against the upper surface of the circuit board 30. Thus, the distance between the lower surface of the edge 11a1 and the upper surface of the circuit board 30 is maintained at the length in the vertical direction of the first isolation member 14a, i.e., the first gap L1. As a result, the gap between the lower surface of the wiring substrate 20 and the upper surface of the circuit board 30 can be maintained at a desired distance.

[0087] Here, as Figure 9As shown, wiring pins 21a are inserted into the wiring substrate 20, and the wiring pins 21a are electrically connected, for example, to a circuit pattern 24c formed on the upper surface of the wiring substrate 20. On the other hand, a circuit pattern 33e is formed on the upper surface of the insulating plate 32 of the circuit substrate 30, and a semiconductor chip 31b1 is mounted on the upper surface of the circuit pattern 33e via solder 34a. Furthermore, the lower end of the wiring pin 21a is bonded to the upper surface of the semiconductor chip 31b1 via solder 34b.

[0088] Therefore, a gap is needed between the lower surface of the wiring substrate 20 and the upper surface of the circuit substrate 30 for bonding the wiring pins to the semiconductor chip via solder. As described above, the lower ends of the first isolation member 14a and the second isolation member 15a abut against the upper surfaces of the wiring substrate 20 and the circuit substrate 30, respectively, thereby easily maintaining the desired gap between the lower surface of the wiring substrate 20 and the upper surface of the circuit substrate 30.

[0089] Furthermore, by inserting the first isolation member 14a through the guide hole 23a, the horizontal relative position of the wiring substrate 20 with respect to the external mounting member 11a can be accurately positioned with simple operation. Specifically, as described above, when mounting the wiring substrate 20, the external connection terminals 12a and 12b are inserted into the wiring holes 22a and 22b of the wiring substrate 20. At this time, by first inserting the first isolation member 14a into the guide hole 23a of the wiring substrate 20, the positions of the ends of the external connection terminals 12a and 12b can be easily aligned with the positions of the wiring holes 22a and 22b.

[0090] It should be explained that, for example Figure 9 As shown, the lower end portion of the first isolation member 14a (the front end portion that abuts against the wiring substrate 20) has a tapered shape whose cross-sectional area decreases towards the lower end. This facilitates the insertion of the first isolation member 14a into the guide hole 23a. For example, even if the center of the diameter of the first isolation member 14a does not precisely align with the center of the diameter of the guide hole 23a when viewed from above, the first isolation member 14a can still be inserted into the guide hole 23a. Therefore, the workability of mounting the wiring substrate 20 to the outer component 11a is improved. The lower ends of the other first isolation members 14b to 14d also have the same shape as the first isolation member 14a.

[0091] Furthermore, regarding the pairs (pairs of isolation members) of adjacent first isolation members 14a-14d and second isolation members 15a-15d, the following can be derived. In order to stably maintain a constant spacing between the lower surface of the outer casing member 11a and the upper surface of the wiring substrate 20 across their opposing surfaces, it is preferable, for example, to arrange two or more pairs of isolation members on one edge (e.g., edge 11a1) of the outer casing member 11a, and one or more pairs of isolation members on the opposite edge. In this case, it is preferable that on one edge, isolation member pairs are arranged near both ends in the Y-axis direction, and on the other edge, isolation member pairs are arranged near the center in the Y-axis direction.

[0092] In addition, when four or more sets of isolation member pairs are configured, it is preferable to configure isolation member pairs at one end and the other end of the edge on one side, respectively, near the Y-axis direction, and at one end and the other end of the edge on the other side, respectively (i.e., near the four corners of the outer member 11a, which is rectangular in shape when viewed from above).

[0093] Next, use Figures 10-12 The manufacturing process of semiconductor device 1 will be described.

[0094] Figure 10 This is a flowchart illustrating the manufacturing process of a semiconductor device.

[0095] [Process P1] Fabrication of housing 10, wiring board 20, and circuit board 30. When fabricating housing 10, for example, resin is filled into a predetermined mold in which external connection terminals 12a-12j and 13a-13d are assembled. Thereafter, the mold is removed to fabricate housing 10, which includes external connection terminals 12a-12j and 13a-13d, and is integrally formed from housing member 10a, terminal holding members 10b and 10c, and cover member 10d. Additionally, at this time, first isolation members 14a-14d and second isolation members 15a-15d are provided on the outer component 11a of housing 10.

[0096] A circuit pattern is formed on the wiring substrate 20, and wiring holes 22a-22j and guide holes 23a-23d are provided, with wiring pins mounted thereon. A circuit pattern is formed on the circuit substrate 30, and semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, 31d1-31d4, and 31e are bonded to it via solder. It should be noted that, in this case, a metal sintering material may be used instead of solder.

[0097] [Step P2] The wiring substrate 20 is assembled to the housing 10. In this step, the wiring substrate 20 is mounted on the back side (the side in the direction of the first and second isolation members protruding) of the outer member 11a of the housing 10 with the housing 10 and the wiring substrate 20 flipped upside down. First, the wiring substrate 20 is brought close to the back side of the outer member 11a, and the first isolation members 14a to 14d are inserted into the guide holes 23a to 23d of the wiring substrate 20. Then, the first isolation members 14a to 14d pass through the guide holes 23a to 23d, and the ends of the external connection terminals 12a to 12j are inserted into the wiring holes 22a to 22j of the wiring substrate 20. By pressing the wiring substrate 20 against the outer member 11a, the external connection terminals 12a to 12j are pressed into the wiring holes 22a to 22j. This pressing is performed until the ends of the second isolation members 15a to 15d abut against the wiring substrate 20.

[0098] [Step P3] The circuit board 30 is assembled onto the housing 10 on which the wiring board 20 is mounted. In this step, the vertical orientation of the housing 10 is changed so that the main surface of the housing 10 (the surface where the external connection terminals 13a to 13d are exposed) faces upward. In addition, in the circuit board 30, solder for bonding with the corresponding wiring pins is applied to the electrodes on the upper surfaces of the semiconductor chips 31a1 to 31a4, 31b1 to 31b4, 31c1 to 31c4, 31d1 to 31d4, and 31e. Furthermore, the circuit board 30 is positioned so that it approaches from the lower surface of the outer mounting member 11a and abuts against the upper surface of the circuit board 30 at the ends of the first isolation members 14a to 14d.

[0099] Here, in step P2, with the ends of the second isolation members 15a-15d abutting against the wiring substrate 20, and in step P3, with the ends of the first isolation members 14a-14d abutting against the circuit board 30, the lower surface of the outer mounting member 11a and the upper surface of the wiring substrate 20, as well as the lower surface of the wiring substrate 20 and the upper surface of the circuit board 30, are respectively separated by desired intervals. Thus, by utilizing the vertical lengths of the first isolation members 14a-14d and the second isolation members 15a-15d to maintain these intervals, the workability of mounting the wiring substrate 20 and the circuit board 30 relative to the housing 10 can be improved.

[0100] [Step P4] Reflow soldering is performed. In step P3, the housing 10, which is equipped with the wiring substrate 20 and the circuit substrate 30, is heated and the solder is melted. After the solder melts, it is cooled to solidify, and the electrodes on the upper surface of the semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, 31d1-31d4, and 31e are joined to the corresponding wiring pins by the solder.

[0101] [Step P5] The housing 10 is assembled in the cavity of a predetermined molding apparatus. In the molding apparatus, molten sealing material in the material cavity is pressurized by a plunger and fed from the material cavity into the runner, and injected into the sealing member at the gate (described later) of the opening (including opening 11d) on the side of the receiving member 10a in the X-axis direction. The sealing material injected into the interior of the housing 10 solidifies, and the wiring substrate 20, circuit board 30, semiconductor chips 31a1-31a4, 31b1-31b4, 31c1-31c4, 31d1-31d4, and 31e are sealed by the sealing member 40. Through such transfer molding of the housing 10, a... Figure 1 and Figure 2 Semiconductor device 1 is shown.

[0102] Figure 11 This diagram illustrates the mounting process of the wiring board relative to the external components. Figure 11 about Figure 10 Process P2 involves cutting using the I1-I1 line. Figure 8 An enlarged cross-sectional view of region A1.

[0103] As previously described, in step P2, the housing 10 and the wiring substrate 20 are flipped upside down. In this state, the outer surface of the wiring substrate 20 near the back of the outer member 11a of the housing 10 (the side in which the first isolation member 14a and the second isolation member 15a protrude) is visible. Here, the protrusion of the first isolation member 14a from the back of the outer member 11a is greater than the protrusion of the external connection terminals 12a and 12b. Therefore, before inserting the ends of the external connection terminals 12a and 12b into the wiring holes 22a and 22b of the wiring substrate 20, the end of the first isolation member 14a is inserted into the guide hole 23a of the wiring substrate 20 (step P2-1).

[0104] As previously described, the front end portion of the first isolation member 14a (the front end portion that abuts against the wiring substrate 20) has a tapered shape whose cross-sectional area decreases towards the end. Therefore, in step P2-1, it is easy to insert the first isolation member 14a into the guide hole 23a. For example, even if the center of the diameter of the first isolation member 14a does not precisely coincide with the center of the diameter of the guide hole 23a when viewed from above, the first isolation member 14a can still be inserted into the guide hole 23a. Therefore, the workability of aligning the position of the first isolation member 14a relative to the guide hole 23a can be improved.

[0105] If the wiring substrate 20 moves further closer to the outer component 11a, the ends 12a1 and 12b1 of the external connection terminals 12a and 12b are then inserted into the wiring holes 22a and 22b of the wiring substrate 20 (step P2-2). At this time, the first isolation member 14a is inserted into the guide hole 23a, thereby aligning the wiring substrate 20 with respect to the outer component 11a in the horizontal direction. Therefore, the ends 12a1 and 12b1 of the external connection terminals 12a and 12b can be smoothly inserted into the wiring holes 22a and 22b.

[0106] Specifically, since the external connection terminals 12a and 12b are pressed into the wiring holes 22a and 22b, the alignment of the ends 12a1 and 12b1 of the external connection terminals 12a and 12b relative to the wiring holes 22a and 22b requires high precision. As described above, by inserting the first isolation member 14a into the guide hole 23a, the accuracy of such alignment can be improved, and the workability of pressing can be improved. In addition, the possibility of component breakage due to pressing in a state where the external connection terminals 12a and 12b are already misaligned relative to the wiring holes 22a and 22b can be reduced.

[0107] Figure 12 This diagram shows the location of the gate. It should be noted that... Figure 12 The image shows a top view and a side view of the semiconductor device 1 with the sealing member 40 and the cover member 10d removed.

[0108] As previously described, an opening is formed on the side wall of the housing member 10a in the X-axis direction. For example, an opening 11d is formed on the side wall 11b in the -X direction. Figure 10 In process P5, sealing member 40 is injected through these openings to seal the interior of housing 10.

[0109] like Figure 12 As shown, in this embodiment, as an example, only a portion of the opening 11d expands upward (in the +Z direction), and the expanded area constitutes the gate openings 16a and 16b, which are used for injection. Figure 10 The sealing material for sealing component 40 in process P5. Figure 12 In the example, sealing material is injected into the sealing member 40 in the +X direction relative to the gate openings 16a and 16b.

[0110] Here, the first isolation members 14a, 14b and the second isolation members 15a, 15b formed on the edge 11a1 of the outer component 11a are preferably formed at positions offset from the gate openings 16a, 16b relative to the direction along the edge 11a1 (Y-axis direction). This prevents the isolation members from obstructing the flow of sealing material from the gate openings 16a, 16b into the sealing member 40. By offsetting the positions of the first isolation members 14a, 14b from the gate openings 16a, 16b, the sealing member 40 is appropriately filled into the interior of the housing 10, thereby suppressing the reduction of insulation and preventing a decrease in the reliability of the semiconductor device 1.

[0111] Next, a variation example of deforming the shapes of the first and second isolation members will be described. In the above embodiment, the first and second isolation members are each configured as separate columnar members. Alternatively, the first and second isolation members can also be configured as an integral member.

[0112] Figure 13 This is a top view showing a modified example of the isolation member. Figure 13 A top view of a modified example of a housing 10 with an isolation member is shown.

[0113] exist Figure 13 In the example, on the lower surface of the outer component 11a of the housing 10, the first isolation members 17a-17d and the second isolation members 18a-18d are disposed near the four corners of the outer component 11a when viewed from above. That is, the first isolation members 17a, 17b and the second isolation members 18a, 18b are disposed at the edge 11a1 of the outer component 11a (refer to...). Figure 1 On the lower surface of the outer component 11a, the first isolation members 17c, 17d and the second isolation members 18c, 18d are disposed on the edge 11a2 of the outer component 11a (refer to...). Figure 1 The lower surface of ).

[0114] Furthermore, the first isolation member 17a and the second isolation member 18a are formed as an integral component. The second isolation member 18a is a columnar component protruding from the lower surface (the surface on the -Z direction side) of the outer component 11a. The length of the second isolation member 18a in the vertical direction is L2 (refer to...). Figure 9 The first isolation member 17a is a columnar member with the same central axis as the second isolation member 18a, but with a smaller cross-sectional area than the second isolation member 18a, and is configured to protrude from the lower end of the second isolation member 18a. The length from the lower surface of the outer member 11a to the lower end of the first isolation member 17a is L1 (refer to...). Figure 9 ).

[0115] Similarly, the first isolation member 17b and the second isolation member 18b are formed as an integral component. The second isolation member 18b is a columnar component protruding from the lower surface of the outer component 11a, and its length in the vertical direction is L2. The first isolation member 17b is a columnar component with the same central axis as the second isolation member 18b, but with a smaller cross-sectional area than the second isolation member 18b, and is configured to protrude from the lower end of the second isolation member 18b. The length from the lower surface of the outer component 11a to the lower end of the first isolation member 17b is L1.

[0116] Furthermore, the first isolation member 17c and the second isolation member 18c are formed as a single unit. The second isolation member 18c is a columnar member protruding from the lower surface of the outer member 11a, and its length in the vertical direction is L2. The first isolation member 17c is a columnar member with the same central axis as the second isolation member 18c, but with a smaller cross-sectional area than the second isolation member 18c, and is configured to protrude from the lower end of the second isolation member 18c. The length from the lower surface of the outer member 11a to the lower end of the first isolation member 17c is L1.

[0117] Furthermore, the first isolation member 17d and the second isolation member 18d are formed as a single unit. The second isolation member 18d is a columnar member protruding from the lower surface of the outer member 11a, and its length in the vertical direction is L2. The first isolation member 17d is a columnar member with the same central axis as the second isolation member 18d, but with a smaller cross-sectional area than the second isolation member 18d, and is configured to protrude from the lower end of the second isolation member 18d. The length from the lower surface of the outer member 11a to the lower end of the first isolation member 17d is L1.

[0118] The wiring substrate 20 has guide holes corresponding to the first isolation members 17a to 17d respectively. Figure 7 (Corresponding to guide holes 23a to 23d). When the wiring substrate 20 is mounted on the lower surface of the outer component 11a, the ends of the first isolation members 17a to 17d are inserted into the guide holes corresponding to the wiring substrate 20. For example, when the first isolation members 17a to 17d are cylindrical, the diameter of the guide hole is the same as the diameter of the first isolation members 17a to 17d.

[0119] It should be noted that, in Figure 13 and the following Figure 14 In this configuration, the first isolation member 17a-17d and the second isolation member 18a-18d are cylindrical in shape, but they can also be, for example, prismatic in shape.

[0120] Figure 14It is a top view and cross-sectional view of the installation area of ​​the isolation component. Figure 14 The top view is Figure 13 The diagram shows an enlarged view of region A2. Figure 14 The cross-sectional view shows that it will utilize Figure 13 The line I2-I2 is cut Figure 14 A cross-sectional view of the area in the top view. Wherein... Figure 14 In the cross-sectional view, let it be as follows Figure 3 and Figure 4 As shown, a wiring board 20 and a circuit board 30 are mounted relative to the housing 10.

[0121] As previously described, the first isolation member 17a is a columnar member with the same central axis as the second isolation member 18a, but with a smaller cross-sectional area than the second isolation member 18a, and is configured to protrude from the lower end of the second isolation member 18a. When the wiring substrate 20 is mounted on the lower surface of the outer component 11a of the housing 10, the first isolation member 17a is inserted into the guide hole 23a1 of the wiring substrate 20. The first isolation member 17a passes through the guide hole 23a1, and then the lower end of the second isolation member 18a abuts against the upper surface of the wiring substrate 20.

[0122] Thus, by abutting the lower end of the second isolation member 18a against the upper surface of the wiring substrate 20, a predetermined second gap L2 can be maintained between the lower surface of the outer component 11a and the upper surface of the wiring substrate 20. Furthermore, by inserting the first isolation member 17a through the guide hole 23a1, the horizontal relative position of the wiring substrate 20 with respect to the outer component 11a can be precisely positioned through simple operation.

[0123] Furthermore, the circuit board 30 is mounted on the housing 10 with the lower end of the first isolation member 17a abutting against the upper surface of the circuit board 30. As a result, a predetermined first distance L1 can be maintained between the lower surface of the outer member 11a and the upper surface of the circuit board 30, and consequently, the distance between the lower surface of the wiring board 20 and the upper surface of the circuit board 30 can be maintained at a desired distance.

[0124] The foregoing has only illustrated the principles of the invention. Furthermore, those skilled in the art can make various modifications and alterations. The invention is not limited to the precise configuration and application examples shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the invention based on the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, have: Circuit board; A wiring substrate is disposed opposite to the upper surface of the circuit substrate, spaced apart from the upper surface of the circuit substrate by a first gap, and has wiring holes and guide holes through it. A housing includes an outer component, an external connection terminal, a first isolation component, and a second isolation component. The outer component is opposite to the upper surface of the wiring substrate and is disposed with a second gap between it and the upper surface of the wiring substrate. The external connection terminal is fixed to the outer component and its lower end is inserted into the wiring hole of the wiring substrate and electrically connected to the wiring hole. The first isolation component protrudes from the lower surface of the outer component and passes through the guide hole of the wiring substrate, and its lower end abuts against the upper surface of the circuit board, maintaining a first gap between the lower surface of the outer component and the upper surface of the circuit board. The second isolation component protrudes from the lower surface of the outer component and its lower end abuts against the upper surface of the wiring substrate, maintaining a second gap between the lower surface of the outer component and the upper surface of the wiring substrate. as well as A sealing member that fills the first gap and the second gap to seal the wiring substrate.

2. The semiconductor device according to claim 1, characterized in that, The external connection terminal is pressed into the wiring hole of the wiring substrate.

3. The semiconductor device according to claim 1, characterized in that, The external component is formed at least in the region where, when viewed from above, the opposing first and second edges are on the upper side relative to the wiring substrate. For the first isolation member and the second isolation member, two or more sets are formed along the first edge in the region of the lower surface of the outer component opposite to the first edge, and one or more sets are formed along the second edge in the region of the lower surface of the outer component corresponding to the second edge.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a semiconductor chip disposed on the upper surface of the circuit substrate. The wiring substrate also has wiring pins protruding from the lower surface of the wiring substrate. The upper surface of the semiconductor chip and the lower end of the wiring pin are joined by solder in the first gap.

5. The semiconductor device according to claim 1, characterized in that, The external component is formed at least in the region that is above the first edge of the wiring substrate when viewed from above. The housing also includes a sprue for injection of the sealing member on the side of the outer component. The first isolation member and the second isolation member are formed on the lower surface of the outer component at a position offset from the gate opening.

6. The semiconductor device according to claim 1, characterized in that, The cross-sectional area of ​​the front end portion of the first isolation member that abuts against the upper surface of the circuit board decreases to a cone shape as it approaches the upper surface of the circuit board.

7. The semiconductor device according to claim 1, characterized in that, The second isolation member is columnar. The first isolation member protrudes from the lower end of the second isolation member and is columnar with a cross-sectional area smaller than that of the second isolation member.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a semiconductor chip disposed on the upper surface of the circuit substrate for performing switching operations. The upper end of the external connection terminal protrudes from the upper surface of the outer component. The upper end of the external connection terminal becomes a control terminal, and the control terminal inputs a control signal to control the switching action of the semiconductor chip.

9. The semiconductor device according to claim 1, characterized in that, The external component includes a first region and a second region respectively disposed on the upper side relative to the first edge and the second edge of the wiring substrate when viewed from above. An opening is formed in the housing between the first region and the second region of the outer component. The housing also includes a cover member that seals the opening.

10. A method for manufacturing a semiconductor device, characterized in that, have: The preparation process includes preparing a circuit board, a wiring board with through-holes and guide holes, and a housing. The housing includes: an outer component that fixes an external connection terminal, one end of which protrudes from a main surface of one side of the outer component; a first isolation component that protrudes from the main surface of the outer component on the same side; and a second isolation component that protrudes from the main surface of the outer component on the same side and is shorter than the length of the first isolation component from the main surface of the same side. In the first assembly process, the wiring board is brought close to the outer component from the main surface side of one side of the outer component in the housing, and the first isolation member is inserted through the guide hole. One end of the external connection terminal is inserted into the wiring hole so that the wiring hole is electrically connected to the external connection terminal, and the end of the second isolation member abuts against the wiring board. In the second assembly step, the circuit board is arranged opposite to the outer mounting member relative to the wiring board, such that the first isolation member, which passes through the guide hole of the wiring board, abuts against the circuit board; and In the sealing process, a sealing member is filled into the first gap between the circuit board and the wiring board, and the second gap between the wiring board and the outer component, to seal the wiring board.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, In the first assembly process Relative to the housing with the main surface of one side of the outer component facing upward, the first isolation member is inserted through the guide hole, one end of the external connection terminal is inserted into the wiring hole, and the end of the second isolation member abuts against the wiring substrate, thereby supporting the wiring substrate on the second isolation member.

12. The method for manufacturing a semiconductor device according to claim 10, characterized in that, In the first assembly process Press one end of the external connection terminal into the wiring hole.

13. The method for manufacturing a semiconductor device according to claim 10, characterized in that, Between the second assembly step and the sealing step, there is a bonding step in which a surface of the semiconductor chip on the wiring substrate side is bonded to the end of the wiring pin on the circuit substrate side through solder in the first gap. The semiconductor chip is disposed on the main surface of the wiring substrate side of the circuit substrate, and the wiring pin is disposed in the wiring substrate protruding toward the circuit substrate side.

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