Burr detector
By sharing the computing module functionality within the hardware accelerator to provide latency for the glitch detector, the problem of wasted resources in the glitch detector is solved, achieving resource optimization and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-25
- Publication Date
- 2026-03-31
AI Technical Summary
In existing integrated circuits, glitch detectors consume a large amount of resources, and most of these resources are idle during unsafe operations, resulting in resource waste and increased costs.
The delay function of the glitch detector is provided by sharing the functionality of the computing module in the hardware accelerator, thereby reducing the hardware footprint of the glitch detector and utilizing the unused functions of the hardware accelerator during safe operation as the delay function of the glitch detector.
This reduces the hardware footprint of the glitch detector in the integrated circuit, optimizes resource utilization, lowers security costs, and maintains the ability to detect fault injection attacks.
Smart Images
Figure CN121763047A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to glitch detection in integrated circuits for detecting fault injection attacks. Background Technology
[0002] Fault injection (FI) attacks can be used to bypass the security mechanisms of secure devices (such as microcontrollers used in smart cards) to attempt to extract confidential information, such as passwords and decryption keys. Such attacks can be detected using a glitch detector by detecting short-scale changes in the voltage supply that can indicate an FI attack.
[0003] Faults can be injected through various methods, the most common being clock or voltage glitch generation, electromagnetic fault injection, and laser fault injection. A subset of these methods introduces faults into the chip by introducing critical path violations. These specific faults can be detected by a glitch detector. If a fault is detected, safe operation can be restarted or a specific function of the chip can be enabled, such as the chip entering a special safe mode or being able to reboot. Glitch detectors are also known as fault detectors or fault sensors.
[0004] An integrated circuit on a single chip can include multiple glitch detectors. Each glitch detector uses some of the chip's resources, including power, transistors, and wiring (i.e., physical space). Physical space is always required, while power may only be needed when the glitch detector is enabled or active. Typically, a single chip will have many glitch detectors, which can consume a significant amount of system resources. Summary of the Invention
[0005] According to a first aspect, an integrated circuit is provided, the integrated circuit comprising: a hardware accelerator including a computing module configured to perform computing functions; and a glitch detector including a delay function and a comparator arranged to compare an output from the delay function with an expected result to provide an output for detecting glitch, wherein the delay function of the glitch detector is provided at least in part by the computing functions of the computing module in the hardware accelerator.
[0006] The output from the delay function can be either a delay or a calculation result.
[0007] The computational function can be one of the following: Fourier transform, inverse Fourier transform, cryptographic operations, digital signal processing operations, and floating-point operations.
[0008] The spur detector may include configuration modules that are at least partially provided by a hardware accelerator.
[0009] The glitch detector can be configured to provide multiple different inputs to the delay function.
[0010] The glitch detector may include an additional delay function, which is configured to provide input to the additional delay function in serial sequence with the computation module to provide the output from the delay function to the comparator.
[0011] The additional delay function may include a series arrangement of multiple alternating logic NOT gates and registers.
[0012] The computation module can be one of multiple computation modules, and the glitch detector can be one of multiple glitch detectors, with the latency function of each glitch detector being provided at least in part by a corresponding computation module in the computation module of the hardware accelerator.
[0013] According to a second aspect, a method for performing glitch detection in an integrated circuit is provided, the integrated circuit comprising: a hardware accelerator including a computing module configured to perform computational functions; and a glitch detector including a delay function and a comparator arranged to compare an output from the delay function with an expected result to provide an output for detecting glitch, the method comprising: operating the glitch detector while the integrated circuit is performing a security operation, wherein the delay function of the glitch detector is at least partially provided by the computing module of the hardware accelerator.
[0014] If the output from the delay function does not match the expected result, the comparator's output can indicate that a supply voltage or clock frequency glitch has been detected.
[0015] The output from the delay function can be either a delay or a calculation result.
[0016] A security operation can be one or more of the following: a secure boot phase, an encryption operation, an authentication operation, an operation to verify access permissions, an operation to access secure storage, and a signature verification operation.
[0017] The method may include disabling the glitch detector when the integrated circuit is not performing a safety operation.
[0018] The method may be included in the integrated circuit (411) (4161, 4162).
[0019] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description
[0020] The embodiments will be described by way of example only, in which:
[0021] Figure 1 This is a schematic representation of a general-purpose glitch detector;
[0022] Figure 2This is a schematic representation of a general-purpose hardware accelerator;
[0023] Figure 3 This is a schematic representation of four spur detectors with different functions that replace the delay function;
[0024] Figure 4a It is a schematic representation of the current arrangement of hardware accelerators and separate spur detectors; and
[0025] Figure 4b This is a schematic representation of the arrangement of a hardware accelerator and two glitch detectors according to the present disclosure, wherein some functions are shared between the hardware accelerator and the glitch detectors.
[0026] Figure 5 This is a schematic representation of a glitch detector with computational delay functionality, which extends with short delays to achieve longer critical paths;
[0027] Figure 6 yes Figure 5 A schematic representation of a short-delay NOT gate implementation; and
[0028] Figure 7 This is a schematic flowchart illustrating an example method of operating an IC with a glitch detector.
[0029] It should be noted that the drawings are illustrative and not to scale. For clarity and convenience in the drawings, the relative dimensions and proportions of the parts have been shown in enlarged or reduced form. The same reference numerals are used generally to refer to corresponding or similar features in modified and different embodiments. Detailed Implementation
[0030] Figure 1 The standard method used in current glitch detectors is illustrated schematically. A delay function 101 is used, which is well-known and has been characterized or tuned. When delay function 101 is operating in normal mode (i.e., no glitch and no FI attack), the time delay and output of delay function 101 are known and therefore predictable. Therefore, when comparator 102 compares the result with the expected result 103, there should be no mismatch indicated by the output 104 from comparator 102.
[0031] When an attacker injects a glitch, a critical path violation occurs, causing a mismatch between the expected result 103 and the actual result from the delay function 101. The output 104 from comparator 102 should then indicate that an anomaly has occurred. This anomaly typically addresses situations where the device is under FI attack, which could result in the erasure of secret keys or the device being set to a special security mode. The expected result 103 can be a value calculated by the delay function, or it can be, for example, the time taken by delay function 101 to calculate the result. This process typically executes indefinitely in a loop while the device is operational, implemented using a dedicated piece of hardware on the chip. Multiple such glitch detectors can be placed within a single SoC (System-on-a-Chip) to increase overall protection and protect specific parts of the chip from local FI attacks.
[0032] In many cases, glitch detectors are not always necessary because their primary purpose is, for example, to protect security-related functionalities or portions of the device during secure boot, encryption, authentication, access permission verification, access to secure memory, and signature verification. Assuming that the delay function 101 of the glitch detector typically occupies a significant portion of the chip area, a considerable area of the chip may be inactive when not performing security-related functions. This fact can be used to optimize how glitch detectors can be implemented on the device.
[0033] According to this disclosure, the latency function 101 of the glitch detector can be substantially at least partially provided by another function in a hardware accelerator within the chip, which can be used for another purpose but can be repurposed to provide predictable latency for the glitch detector. This function can, for example, be used in other parts of the system within the chip, such as audio processing, video processing, machine learning, message hashing, encryption, an accelerator for data compression, or mathematical functions such as matrix multiplication. Functions available in hardware (HW) accelerators such as DSPs and GPUs can be used to replace at least a portion of the latency function 101. By sharing these functions with the glitch detector, the area occupied by the glitch detector on the chip can be reduced. The functions used for the glitch detector can be selected based on which functions the hardware accelerator requires when the chip performs security-related operations. For example, if security-related operations do not require a specific function in the hardware accelerator, that function can be repurposed to provide latency for the glitch detector.
[0034] like Figure 2As schematically shown, a typical HW accelerator 200 may contain multiple useful hardware blocks 201-206. Each block or computation module is used to compute a specific function. For example, a particular HW accelerator 200 may contain block 202 for computing the Fourier transform (FT), another block 203 for computing the inverse Fourier transform, and other blocks 201 and 204 for performing register and configuration functions. Other functions in blocks 205 and 206 are described in... Figure 2 The blocks can be arbitrarily named ABC and XYZ, and can also be implemented in HW accelerator 200. The entire HW accelerator 200 only uses some of the blocks 201-206 of a typical HW accelerator, for example, using block 204 to store its configuration. Other blocks are typically used only for computing specific functions and therefore may not always be needed.
[0035] Each of the useful functions within the HW accelerator 200 that are not needed during safe operation can also be used as a delay function for the glitch detector. Such functions may be referred to herein as computational delay functions, rather than the simple delay functions used, for example, in a normal glitch detector. Based on the examples above, it can be practically stated that… Figure 3 The schematic representation in the image is used to arrange the example spur detector 301. 0-3 301 burr detectors per unit 0-3 Including comparator 302 0-3 The comparator 302 0-3 Will come from delay function 303 0-3 Output and expected results 304 0-3 Comparison. From comparator 302 0-3 Output 305 0-3 This indicates whether a supply voltage glitch has been detected. This method can also be used to detect other types of glitches, such as clock glitches caused by fault injections attempting to manipulate the clock frequency. Each glitch detector 301 0-3 Configuration unit 306 0-3 Expected result 304 0-3 and delay function 303 0-3 Provide input.
[0036] In order to use the burr detector 301 0-3 In use, it can also serve as a delay function 303 0-3 Each of them can be configured by the corresponding configuration unit 306 0-3 The configuration can be changed to use a specific input with a known output (i.e., the expected computation result). Comparator 302 can then be used. 0-3 Compare the expected results 304 in the same manner as a conventional spur detector. 0-3 Check from the corresponding function 303 0-3 The output.
[0037] exist Figure 4a and 4b The diagram schematically illustrates a comparison between a conventional arrangement of separate hardware accelerators and glitch detectors and an arrangement involving shared functionality. Figure 4a The conventionally arranged integrated circuit (IC) 401 includes a hardware accelerator 402, which includes computing modules 4031 and 4032, a register module 404, and a configuration unit 405. IC 401 also includes a glitch detector 406, which includes a delay function 407, a configuration unit 408, and a comparator 409. The glitch detector 406 and the hardware accelerator 402 are separate units on IC 401, sharing only a common power supply voltage. As described above, the delay function 407 of the glitch detector 406 occupies a significant proportion of the total area required for the glitch detector 406, and this is only needed when IC 401 is performing safe operation.
[0038] According to this disclosure, IC 411 includes a hardware accelerator 412 having a configuration unit 418, a register module 414, and computing modules 4131, 4132, i.e., a hardware accelerator 402 similar to that of conventional IC 401. In this case, each of the computing modules 4131, 4132 is shared with a corresponding glitch detector 4161, 4162. Each glitch detector 4161, 4162 includes configuration units 4181, 4182 and comparators 4191, 4192. Each glitch detector 4161, 4162 may also include shared configuration modules 4201, 4202, which perform configuration functions usable by both the hardware accelerator 411 and the glitch detectors 4161, 4162.
[0039] Functions F1 and F2 in computation modules 4131 and 4132 can represent any function that can also be used to replicate the delay function that can be used by glitch detectors 4161 and 4162. Such functions can include, for example, Fourier transform, inverse Fourier transform, or other functions. Other examples of functional modules that can be repurposed to replicate the delay function include cryptographic hardware accelerators for performing operations such as public-key cryptography, symmetric-key cryptography, or hashing; DSP-related accelerators used in, for example, audio or image processing; and floating-point units. The computational function used by the glitch detector to replicate the delay function in at least part can be, for example, one of Fourier transform, inverse Fourier transform, cryptographic operations, digital signal processing operations, and floating-point arithmetic. Other functions can also be used to replicate the delay function.
[0040] The advantage of adding glitch detector functionality on top of the functionality available in the existing hardware accelerator is that the main functionality required for the glitch detector is provided by the functionality in the hardware accelerator 411, thereby reducing the overhead of incorporating each additional glitch detector. For each glitch detector 4161, 4162, only comparators 4191, 4192 and a set of configuration registers 4181, 4182 need to be added.
[0041] An important aspect of delay functionality is the existence of a critical path. The critical path is the longest path from the input to the output of a hardware block. The critical path has a direct impact on the clock speed that can be used in the device, thus imposing a constraint on the maximum clock speed at which the device will be operational. If the clock starts running faster, information will not propagate fully along the critical path, and the results will be incorrect. This fact can be used to implement glitch detectors.
[0042] To ensure that a critical path is used in instances of computationally delayed functions, special inputs can be selected for the function. This can be done by forcing the use of the longest combined path in the computation. Inappropriate examples would include multiplying by zero or adding to zero. More appropriate examples will depend on the specific computation being performed. Generally, non-trivial values should be used in the computation.
[0043] Furthermore, instead of having a single input, depending on the function, it may be necessary to have at least two different inputs (with two corresponding expected outputs). This ensures that switching of some internal registers ensures that the configured state is different in each loop. This may be necessary to ensure fault detection. With the same input used each time, a fault might be invalid in some parts of the circuit because some internal registers still contain values from previous calculations (which, in our case, are exactly the same), so the final result will still be correct. Therefore, in some examples, the glitch detector can alternate between two different inputs used to compute the delay function. Thus, in general, the glitch detector can be configured to provide multiple different inputs to the delay function provided by the computational function of the HW accelerator.
[0044] Not all functions of a power accelerator (HW) need to be suitable for replacing typical delay functions. For example, if the HW accelerator is very small and its critical path is too short, the function should not be used to replace a delay function. Typically, given the current clock frequency, the critical path of a delay function needs to be as long as possible. Ideally, the critical path of the HW accelerator's computation module should extend beyond or approach the one in the function it is trying to protect. The critical path is a design constraint that is checked at all steps of the IC design cycle. Therefore, the suitability of a particular HW accelerator can be determined during IC design.
[0045] In some examples, a given function in an HW accelerator with a critical path shorter than the required critical path can be appended with a small-latency function to extend its critical path, such as... Figure 5 The following is schematically illustrated. As in the example in Figure 4, the glitch detector 516 includes a comparator 519 arranged to compare the output from the delay function 501 with an expected result 520 to provide an output 521 for detecting glitches (e.g., supply voltage or clock frequency glitches). In this example, the delay function 501 is partially composed of an HW accelerator (…). Figure 5 The calculation module 513 (not shown) provides, and is in part provided, by an additional delay function 522 of the glitch detector 516. The configuration module 518 provides input to the additional delay function 522 in series with the calculation module 513, such that the total critical path is sufficient to provide an output to the comparator 519 that can be used to detect voltage glitch.
[0046] The additional short delay function 522 used as an extension can be implemented, for example, using a series arrangement of multiple alternating logic NOT gates 6011, 6012 and registers 6021, 6022, 6023, as follows: Figure 6 The diagram illustrates this schematically. Typical delay functions would usually require a long chain of NOT gates, but in this case, since part of the delay function is taken over by the computational modules of the HW accelerator, the chain can be made shorter.
[0047] When the glitch detector is not needed, such as when the device is not performing any security operations, the computation delay function can be used as intended by the HW accelerator, i.e., to compute content useful to the device. In this case, the glitch detector functionality can be disabled, and normal user input can be submitted to the function to compute useful results.
[0048] In some examples, if an HW accelerator has multiple functions that it can perform, at some point in time, some of these functions can perform useful computations, while others can be enabled for glitch detection as described above. Therefore, in general, when an HW accelerator includes multiple computation modules, the delay functionality for multiple glitch detectors can be provided by a subset of said multiple computation modules.
[0049] The apparatus and methods disclosed herein can be used to build glitch detectors by reusing some functionality from other hardware blocks from a microcontroller or SoC (System-on-a-Chip). This approach allows for the use of less hardware overall in the chip design and reduces security costs, i.e., the costs associated with using glitch detectors, thereby enabling more glitch detectors to be used for the same total IC area or a smaller total IC area to be used for the same functionality.
[0050] Figure 7 This is a flowchart illustrating an example method of operating an IC incorporating a glitch detector of the type described herein. In a first step 701, the IC is operated. If a safety operation is being performed at step 702, then at step 703, the computational module of the hardware accelerator provides a delay function for the glitch detector, and at step 704, the glitch detector is enabled. If a glitch is detected at step 705, the IC may enter a safety mode at step 706, and then the IC continues operation. Otherwise, the IC continues normal operation. If a safety operation is not being performed at step 702, the glitch detector may be disabled at step 707, and the computational module of the hardware accelerator is used for its normal purpose.
[0051] By reading this disclosure, those skilled in the art will understand other changes and modifications. Such changes and modifications may involve other equivalent features known in the field of spur detectors and that can be used as substitutes for or supplements to the features already described herein.
[0052] Although the appended claims relate to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or any novel combination of features or any generalized form thereof explicitly or implicitly disclosed herein, whether or not it relates to the same invention as currently claimed in any of the claims, and whether or not it alleviates any or all of the same technical problems as those alleviated by this invention.
[0053] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, various features described in the context of a single embodiment for brevity may also be provided individually or in any sub-combination. The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.
[0054] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a / an" does not exclude multiple, a single processor or other unit can perform the functions of several components described in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.
Claims
1. An integrated circuit (411), characterized in that, include: A hardware accelerator (412) includes computing modules (4131, 4132) configured to perform computing functions; and A spur detector (4161, 4162) includes a delay function (4131, 4132) and a comparator (4191, 4192), the comparators (4191, 4192) being arranged to compare the output from the delay function (4131, 4132) with an expected result to provide an output for detecting spurs. The delay function (4131, 4132) of the spur detectors (4161, 4162) is provided at least in part by the computation function of the computation modules (4131, 4132) in the hardware accelerator (412).
2. The integrated circuit (411) according to claim 1, characterized in that, The output from the delay functions (4131, 4132) is a delay.
3. The integrated circuit (411) according to claim 1, characterized in that, The output from the delay functions (4131, 4132) is the calculation result.
4. The integrated circuit (411) according to any one of the preceding claims, characterized in that, The computational function is one of Fourier transform, inverse Fourier transform, cryptographic operations, digital signal processing operations, and floating-point operations.
5. The integrated circuit (411) according to any one of the preceding claims, characterized in that, The burr detectors (4161, 4162) include configuration modules (4181, 4182, 4201, 4202) provided at least in part by the hardware accelerator (411).
6. The integrated circuit (411) according to any one of the preceding claims, characterized in that, The spur detectors (4161, 4162) are configured to provide multiple different inputs to the delay functions (4131, 4132).
7. The integrated circuit (411) according to any one of the preceding claims, characterized in that, The glitch detector (516) includes an additional delay function (522), which is configured to provide input to the additional delay function (522) serially with the computing module (513) to provide the output from the delay function (4131, 4132) to the comparator (519).
8. The integrated circuit (411) according to claim 7, characterized in that, The additional delay function (522) includes a series arrangement of multiple alternating logic NOT gates (6011, 6012) and registers (6021, 6022, 6023).
9. The integrated circuit (411) according to any one of the preceding claims, characterized in that, The computing module is one of a plurality of computing modules (4131, 4132), and the glitch detector is one of a plurality of glitch detectors (4161, 4162), the latency function of each glitch detector being provided at least in part by a corresponding computing module of the computing modules (4131, 4132) of the hardware accelerator (412).
10. A method for performing glitch detection in an integrated circuit (411), characterized in that, The integrated circuit (411) includes: A hardware accelerator (412) includes computing modules (4131, 4132) configured to perform computing functions; and A spur detector (4161, 4162) includes a delay function (4131, 4132) and a comparator (4191, 4192), the comparators (4191, 4192) being arranged to compare the output from the delay function (4131, 4132) with an expected result to provide an output for detecting spurs. The method includes: When the integrated circuit (411) is performing a security operation, the glitch detectors (4161, 4162) are operated, wherein the delay function (4131, 4132) of the glitch detectors (4161, 4162) is provided at least in part by the computing modules (4131, 4132) of the hardware accelerator (412).