Logic built-in self-test circuit and related test method thereof
By using signal blocking circuitry, including selectors and test registers, in LBIST testing, the unreliability of tests caused by unknown signals is resolved, enabling reliable testing of module-level circuits.
Patent Information
- Application Number
- CN202511658824.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-12
- Publication Date
- 2026-03-31
AI Technical Summary
In LBIST testing, the input of unknown state signals makes the test results unreliable and makes it impossible to determine the functional state of the chip circuit.
A signal blocking circuit, including a selector and a test register, is used to block unknown signals by modifying the connection between the input port and the module register through the controller, thereby enabling XB operation.
It effectively blocks unknown state signals, ensuring the reliability of LBIST test results, and can perform tests on specific module-level circuits, improving test accuracy.
Smart Images
Figure CN121763060A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing, and in particular to a logic built-in self-test circuit and its related testing method. Background Technology
[0002] Functional safety is a crucial factor that requires special consideration during the design of automotive chips. Certain circuit modules related to functional safety need to undergo periodic scanning and testing of their internal circuit logic using LBIST (logic build-in self-test) technology during chip operation to prevent defects and ensure chip safety.
[0003] LBIST is the most commonly used technique for online chip testing. One of the most significant impacts on it is the presence of unknown signals. Because LBIST test circuits use a set of registers to accumulate and store test results, if an unknown signal enters the test circuit, its specific circuit structure will cause all the final test results to become unknown, making it impossible to determine whether the test passed or failed. Therefore, when using LBIST technology, all input of unknown signals must be blocked. Summary of the Invention
[0004] This application provides at least one logic-built-in self-test circuit and its related testing method to solve the above-mentioned problems.
[0005] The first aspect of this application provides a logic-built-in self-test circuit for a chip module-level circuit, the chip module-level circuit including an input port and a module register, the input port being connected to the input terminal of the module register; the logic-built-in self-test circuit, used to test the module register when the connection between the input port and the input terminal of the module register is modified, includes: a signal blocking circuit connected between the input port and the input terminal of the module register, thereby modifying the connection between the input port and the input terminal of the module register, the signal blocking circuit including: a selector and a test register, wherein a first input terminal of the selector is connected to the input port, a second input terminal of the selector is connected to the output terminal of the test register, and the output terminal of the selector is connected to the input terminal of the module register; a controller connected to the selection terminal of the selector, connected to the scan input terminal, scan enable terminal and clock terminal of the module register, and connected to the scan input terminal, scan enable terminal and clock terminal of the test register.
[0006] In some embodiments, the signal blocking circuit further includes an inverter; wherein a first terminal of the inverter is connected to the input terminal of the test register, and a second terminal of the inverter is connected to the output terminal of the selector and the input terminal of the module register, respectively.
[0007] A second aspect of this application provides a testing method for a chip module-level circuit, the chip module-level circuit including an input port and a module register, the input port being connected to the input terminal of the module register, the testing method including: a controller determining the input port and configuring a signal blocking circuit for the input port; the controller modifying the connection between the input port and the input terminal of the module register to connect the input port to the input terminal of the module register through the signal blocking circuit, wherein the signal blocking circuit includes a selector and a test register, wherein a first input terminal of the selector is connected to the input port, a second input terminal of the selector is connected to the output terminal of the test register, and the output terminal of the selector is connected to the input terminal of the module register; when the connection between the input port and the input terminal of the module register is modified to connect the input port to the input terminal of the module register through the signal blocking circuit, the controller tests the module register, wherein the controller is connected to the selection terminal of the selector, to the scan input terminal, scan enable terminal, and clock terminal of the module register, and to the scan input terminal, scan enable terminal, and clock terminal of the test register.
[0008] In some embodiments, the controller determines the input port by executing a preset program, configures a signal blocking circuit for the input port, and modifies the connection between the input port and the input terminal of the module register to connect the input port to the input terminal of the module register through the signal blocking circuit.
[0009] In some embodiments, the controller tests the module register by: the controller outputting an enable signal to block unknown states to the selector, such that when the module register and the test register are working, the signal on the selector is pulled high to block unknown state signals from the input port.
[0010] In some embodiments, pulling the signal high on the selector's selector terminal further includes: the module register being input to the signal output by the test register.
[0011] In some embodiments, the controller outputs a first scan signal to the scan input terminal of the test register, outputs a second scan signal to the scan input terminal of the module register, outputs a scan enable signal to the scan enable terminals of the module register and the test register, and outputs a clock signal to the clock terminals of the module register and the test register, thereby enabling the module register and the test register to operate, wherein the first scan signal and the second scan signal are opposite signals.
[0012] A third aspect of this application provides a testing method for a chip module-level circuit, applied to a logic-built-in self-test circuit as described in the first aspect above. The chip module-level circuit includes multiple input ports and multiple module registers, wherein the multiple input ports are independent of each other, the multiple module registers are independent of each other, and each input port is connected to the input terminal of a corresponding module register. The testing method includes: a controller determining each input port and configuring a signal blocking circuit for each input port; the controller modifying the connection between each input port and the input terminal of the corresponding module register to connect each input port to the input terminal of the corresponding module register through the signal blocking circuit; and, when the connection between each input port and the input terminal of the corresponding module register is modified to connect each input port to the input terminal of the corresponding module register through the signal blocking circuit, the controller tests the module register.
[0013] The fourth aspect of this application provides a method for testing a chip, the chip including a plurality of first chip module-level circuits and a plurality of second chip module-level circuits, the testing method including: testing each of the plurality of first chip module-level circuits using the chip module-level circuit testing method as described in the second aspect above; wherein each second chip module-level circuit is not tested using the chip module-level circuit testing method as described in the second aspect above.
[0014] The fifth aspect of this application provides an electronic device including a memory and a processor coupled to each other. The processor is used to execute program instructions stored in the memory to implement the chip module-level circuit testing method in the second aspect above, or to implement the chip testing method in the fourth aspect above.
[0015] The chip module-level circuit includes an input port and a module register, with the input port connected to the input terminal of the module register. A built-in self-test circuit is used to test the module register when the connection between the input port and the module register is modified. This circuit includes a signal blocking circuit connected between the input port and the module register, thus preventing modification of the connection. The signal blocking circuit includes a selector and a test register, where the first input terminal of the selector is connected to the input port, the second input terminal of the selector is connected to the output terminal of the test register, and the output terminal of the selector is connected to the input terminal of the module register. A controller is connected to the selector's selection terminal, the scan input terminal, the scan enable terminal, and the clock terminal of the module register, and also to the scan input terminal, scan enable terminal, and clock terminal of the test register. This circuit blocks unknown-state signals from the input port, effectively implementing XB operation and thus effectively testing the chip module-level circuit.
[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.
[0018] Figure 1 This is a schematic diagram of the register structure according to an embodiment of this application; Figure 2 This is a schematic diagram of the scanning chain structure according to an embodiment of this application; Figure 3 This is a schematic diagram of the signal timing of the scan chain according to an embodiment of this application; Figure 4 This is a schematic diagram of the chip subsystem-level circuit of an embodiment of this application. Figure 1 ; Figure 5 This is a signal timing diagram of the chip subsystem-level circuit in an embodiment of this application. Figure 1 ; Figure 6 This is a schematic diagram of the chip subsystem-level circuit of an embodiment of this application. Figure 2 ; Figure 7 This is a signal timing diagram of the chip subsystem-level circuit in an embodiment of this application. Figure 2 ; Figure 8 This is a schematic diagram of the chip module-level circuit structure according to an embodiment of this application. Figure 1 ; Figure 9This is a schematic diagram of the logic built-in self-test circuit for chip module-level circuits according to an embodiment of this application; Figure 10 This is a signal timing diagram of the chip module-level circuit according to an embodiment of this application; Figure 11 This is a flowchart illustrating the testing method for chip module-level circuits according to an embodiment of this application. Figure 1 ; Figure 12 This is a schematic diagram of the chip module-level circuit structure according to an embodiment of this application. Figure 2 ; Figure 13 This is a flowchart illustrating the testing method for chip module-level circuits according to an embodiment of this application. Figure 2 ; Figure 14 This is a schematic diagram of the chip structure according to an embodiment of this application; Figure 15 This is a schematic flowchart of a chip testing method according to an embodiment of this application; Figure 16 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application; Figure 17 This is a schematic diagram of the structure of a non-volatile computer-readable storage medium according to an embodiment of this application. Detailed Implementation
[0019] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0020] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this document means two or more. Additionally, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0021] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0022] To facilitate understanding of this application, the LBIST test procedure is described below. In the LBIST test procedure, the typical approach is scanning, utilizing existing registers in the circuit under test to form a scan chain to transmit and capture data. A dedicated controller sends and receives data to the scan chain and controls its operation. Specifically, to utilize registers to form the scan chain, ordinary Class D flip-flops are replaced with scannable Class D flip-flops, such as... Figure 1 As shown, this allows multiple registers to form a scan chain. A standard Class D flip-flop includes a data input port D, a clock port CK, and a data output port Q. When the clock tick arrives, data is transmitted from D to Q. Compared to a standard Class D flip-flop, a scanable Class D flip-flop adds a scan input SI and a scan enable SE. Internally, the flip-flop essentially adds a selector. When the clock tick arrives (i.e., the rising edge of the clock signal arrives), if the scan enable SE is high, the signal is transmitted from the scan input SI to the output Q; if the scan input SE is low, the signal is transmitted from the input D to the output Q.
[0023] like Figure 2 As shown, taking three registers as an example, multiple registers DFF1-DFF3 are cascaded to form a scan chain. The controller is connected to the scan input terminal SI of the start register DFF1 and the output terminal Q of the end register DFF3, respectively. The controller sends a signal to the scan input terminal SI of the start register DFF1 and receives the signal through the output terminal Q of the end register DFF3, thus controlling the operation of the scan chain. Figure 2 A, B, and C in the diagram are internal signals only, not input / output ports.
[0024] The scan chain starts at the scan input SI of the start register DFF1. After the signal is transmitted inside the start register DFF1, it is sent out through the output Q of the start register DFF1 to the scan input SI of the next register, and so on, until the end register DFF3 is reached. The output Q of the end register DFF3 is the end of the scan chain. The scan enable SE of all registers is connected to the scan enable line of the controller, and the clock CK of all registers is connected to the clock line of the controller.
[0025] During the LBIST test, when the scan begins—that is, when the controller starts controlling the scan chain—it first enters the shifting phase. The controller pulls the scan enable line high, outputting a high-level signal to the scan enable terminal SE of each register. Simultaneously, the test signal is input through the scan input terminal SI of the start register DFF1. At the same time, the controller periodically outputs a clock signal through the clock line, ensuring the test signal reaches every register in the scan chain. For example, when the rising edge of the clock signal arrives, the register stores the signal acquired at its scan input terminal SI into its internal memory; when the falling edge of the clock signal arrives, the register outputs the stored signal to its output terminal Q. After the shift input, each register in the scan chain stores the signal. For example, the signals in the scan chain are as follows: Figure 3 As shown.
[0026] Next, the capture phase begins. The controller pulls the scan enable line low, that is, it outputs a low-level signal to the scan enable terminal SE of each register through the scan enable line. At the same time, the controller outputs a clock signal, which causes multiple registers DFF1-DFF3 to capture the signal at the input terminal D respectively. After combinational logic calculation, the signal is transmitted to its output terminal Q.
[0027] Subsequently, the shifting phase is repeated. The controller pulls the scan enable line high again and periodically outputs a clock signal. The data captured by the register output terminal Q is output to the controller through the scan chain. At the same time, a new round of test signals is input again through the scan input terminal SI of the start register DFF1, and so on in a loop.
[0028] Next, the controller stores the captured results and performs the next round of shift and capture operations. The newly captured results are then added to the results of the previous round, and this process repeats. After several shift and capture cycles, the controller obtains a cumulative result and compares it with a preset cumulative result. If the cumulative result differs from the preset result, it indicates a circuit defect, and the corresponding logic function is lost. If the cumulative result matches the preset result, it indicates the circuit is intact, thus completing the LBIST test process.
[0029] To facilitate understanding of this application, the process of performing LBIST testing on the chip subsystem-level circuit will be described first. For example... Figure 4 As shown, the chip subsystem-level circuit 40 includes an input port A and a first register DFF4, and the test circuit 50 includes a controller 51. The input port A is connected to the input terminal D of the first register DFF4, the scan input terminal SI of the first register DFF4 is connected to the controller 51, the scan enable terminal SE of the first register DFF4 is connected to the controller 51, and the clock terminal CK of the first register DFF4 is connected to the controller 51.
[0030] When performing LBIST testing on the chip subsystem-level circuit 40, registers are used to accumulate and store the test results. For example... Figure 5 As shown, when an unknown state signal exists at input port A and is input to input D of the first register DFF4, the output Q of the first register DFF4 will also output an unknown state signal. As a result, all the obtained test results will become unknown results. The controller 51 cannot compare the test results with the preset test results, and therefore cannot determine whether the chip subsystem circuit 40 has passed the test. Therefore, it is necessary to block the unknown state signal from input port A.
[0031] At this point, the chip subsystem-level circuit 40 also includes a second register DFF5, which is used to block unknown state signals from input port A from entering the first register DFF4, such as... Figure 6 As shown, when input port A is blocked, a selector MUX is added to the transmission path between input port A and the first register DFF4. The first terminal D0 of the selector MUX is connected to input port A, the second input terminal D1 is connected to the output terminal Q of the second register DFF5, the output terminal Z is connected to the input terminal D of the first register DFF4, and the selection terminal S is connected to the controller 51. The second register DFF5 does not contain any unknown state signals, for example, such as... Figure 7 The D, SI, and Q signals of the DFF5 are shown. Adding a selector MUX can be achieved using the X-bounding (XB, blocking unknown state signals) function of the Tessent tool.
[0032] like Figure 6 As shown, controller 51 outputs the XB enable signal x_bounding_en, for example, Figure 7 The MUX / S signal is shown, and the XB enable signal is output to the selection terminal S of the selector MUX. The controller 51 pulls the XB enable signal high on the selection terminal S of the selector MUX. When the XB enable signal is high, the output terminal Z of the selector MUX will output the signal received by the second input terminal D1. That is, the input terminal D of the first register DFF4 receives the signal from the output terminal Q of the second register DFF5. For example, as shown... Figure 7 The DFF4 / D signal shown blocks the unknown state signal at input port A.
[0033] As can be seen, the above method is used to perform XB operation when performing LBIST testing on subsystem-level circuits in a chip. However, the above method can only analyze and process the overall circuit and cannot operate on specific module circuits. In chip design scenarios without subsystems, when there are only specific module-level circuits, the above method is not applicable, especially in scenarios with a large number of module-level circuits.
[0034] Please see Figure 8 , Figure 8 This is a schematic diagram of the chip module-level circuit structure according to an embodiment of this application. Figure 1 The chip module-level circuit 80 includes an input port B and a module register DFF, with the input port B connected to the input terminal D of the module register DFF.
[0035] Chip module-level circuit 80 can refer to the module-level circuits within a chip that require LBIST testing. For example... Figure 9 As shown, the chip module-level circuit 80 is tested using a built-in logic self-test circuit 90. In other words, the built-in logic self-test circuit 90 is used to test the module register DFF if the connection between input port B and input D of the module register DFF is modified.
[0036] like Figure 9 As shown, the built-in self-test circuit 90 includes a signal blocking circuit 92 and a controller 91. The signal blocking circuit 92 is connected between the input port B and the input terminal D of the module register DFF, thereby modifying the connection between the input port B and the input terminal D of the module register DFF.
[0037] The signal blocking circuit 92 includes a selector T_MUX and a test register T_DFF. The first input terminal D0 of the selector T_MUX is connected to input port A, the second input terminal D1 of the selector T_MUX is connected to the output terminal Q of the test register T_DFF, and the output terminal Z of the selector T_MUX is connected to the input terminal D of the module register DFF. The controller 91 is connected to the selection terminal S of the selector T_MUX, the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the module register DFF, and also to the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the test register T_DFF.
[0038] like Figure 10 As shown, during the testing process of the chip module-level circuit 80 through the built-in logic self-test circuit 90, unknown state signals from input port B are also blocked, facilitating LBIST testing. The signal at input terminal D of the test register T_DFF is the input of an external device to the chip module-level circuit 80, and it differs from the signal at input terminal D of the existing register (i.e., the second register DFF5) within the chip subsystem-level circuit 40 used for LBIST testing of the aforementioned chip subsystem-level circuit 40.
[0039] In this embodiment, the chip module-level circuit 80 includes an input port B and a module register DFF, with input port B connected to the input terminal D of the module register DFF. A built-in self-test circuit 90 is used to test the module register DFF when the connection between input port B and the input terminal D of the module register DFF is modified. This circuit includes a signal blocking circuit 92 connected between input port B and the input terminal D of the module register DFF, thus preventing the modification of the connection. The signal blocking circuit 92 includes a selector T_MUX and a test register T_DFF. The first input terminal D0 of the MUX is connected to input port B. The second input terminal D1 of the selector T_MUX is connected to the output terminal Q of the test register T_DFF. The output terminal Z of the selector T_MUX is connected to the input terminal D of the module register DFF. The controller is connected to the selection terminal S of the selector T_MUX, the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the module register DFF, and the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the test register T_DFF. It can block the unknown state signal of input port B, effectively realize the XB operation, and thus effectively test the chip module-level circuit 80.
[0040] like Figure 9 As shown, in some embodiments, the signal blocking circuit 92 further includes an inverter T_INV, wherein the first terminal ZN of the inverter T_INV is connected to the input terminal D of the test register T_DFF, and the second terminal I of the inverter T_INV is connected to the output terminal Z of the selector T_MUX and the input terminal D of the module register DFF, respectively.
[0041] The inverter T_INV inverts the polarity of a signal. The signal at input D of module register DFF, after passing through inverter T_INV, is inverted at input D of test register T_DFF. For example, the signal at input D of module register DFF might be as follows: Figure 10 The DFF / D signal shown is used to test the signal at input D of register T_DFF. Figure 10 The T_DFF / D signal shown is the opposite of the DFF / D signal.
[0042] Please see Figure 11 , Figure 11 This is a flowchart illustrating the testing method for chip module-level circuits according to an embodiment of this application. Figure 1 Among them, the chip module-level circuit can be as follows: Figure 8 The chip module-level circuit 80 shown is detailed in the description of the above embodiment. This test method can be applied to logic-built-in self-test circuits, for example... Figure 9The controller 91 in the logic built-in self-test circuit 90 shown.
[0043] It should be noted that if substantially the same result is obtained, the method of this application is not based on... Figure 11 The sequence of processes shown is limited.
[0044] In some possible implementations, this method can be implemented by the controller calling computer-readable instructions stored in memory, such as... Figure 9 and Figure 11 As shown, the method may include the following steps: S111: Controller 91 determines input port B and configures signal blocking circuit 92 for input port B.
[0045] For the chip module-level circuit 80 that needs to be tested by LBIST, the input port B is obtained. The controller 91 determines the input port B that needs to be tested by LBIST and configures the signal blocking circuit 92 for the input port B. For example, the controller 91 can configure the signal blocking circuit 92 for the input port B by running a preset tool.
[0046] S112: The controller 91 changes the connection between input port B and input terminal D of module register DFF to connect input port B to input terminal D of module register DFF through signal blocking circuit 92.
[0047] The connection between input port B and input D of module register DFF is as follows: Figure 8 As shown, input port B is directly connected to input D of module register DFF. Input port B contains unknown signals, and for input port B to perform LBIST testing, it is necessary to block these unknown signals. Therefore, controller 91 modifies the connection between input port B and input D of module register DFF by connecting input port B to input D of module register DFF through signal blocking circuit 92. For example, connecting input port B to input D of module register DFF through signal blocking circuit 92 is as follows: Figure 9 As shown.
[0048] S113: When the connection between input port B and input terminal D of module register DFF is modified to connect input port B to input terminal D of module register DFF through signal blocking circuit 92, controller 91 tests module register DFF.
[0049] When the connection between input port B and input terminal D of module register DFF is modified to connect input port B to input terminal D of module register DFF through signal blocking circuit 92, controller 91 tests module register DFF. The test procedure is the same as the LBIST test procedure described above, and will not be repeated here.
[0050] In this embodiment, the chip module-level circuit 80 includes an input port B and a module register DFF. The input port B is connected to the input terminal D of the module register DFF. The testing method includes: a controller 91 determines the input port B and configures a signal blocking circuit 92 for the input port B; the controller 91 modifies the connection between the input port B and the input terminal D of the module register DFF to connect the input port B to the input terminal D of the module register DFF through the signal blocking circuit 92. The signal blocking circuit 92 includes a selector T_MUX and a test register T_DFF. The first input terminal D0 of the selector T_MUX is connected to the input port B, and the second input terminal D1 of the selector T_MUX is connected to the output terminal Q of the test register T_DFF. The output terminal Z of the selector T_MUX is connected to the input terminal D of the module register DFF. When the connection between the input port B and the input terminal D of the module register DFF is modified to connect the input port B to the input terminal D of the module register DFF through the signal blocking circuit 92, the controller 91 tests the module register DFF. The controller 91 is connected to the selection terminal S of the selector T_MUX, the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the module register DFF, and the scan input terminal SI, the scan enable terminal SE, and the clock terminal CK of the test register T_DFF. This can block the unknown state signal of the input port B, effectively realize the XB operation, and thus effectively test the chip module-level circuit 80.
[0051] In some embodiments, such as Figure 9 As shown, the controller 91 determines the input port B by executing a preset program, configures the signal blocking circuit 92 for the input port B, and modifies the connection between the input port B and the input terminal D of the module register DFF to connect the input port B to the input terminal D of the module register DFF through the signal blocking circuit 92.
[0052] The preset program can be a program written using TCL (test command language). The controller 91 executes the preset program to obtain the input port B that needs to be tested by LBIST, and configures the signal blocking circuit 92 for the input port B. At the same time, it modifies the connection between the input port B and the input terminal D of the module register DFF to connect the input port B to the input terminal D of the module register DFF through the signal blocking circuit 92, thereby completing the configuration of the signal blocking circuit 92 for the input port B.
[0053] For example, controller 91 can execute the preset program in a preset tool.
[0054] In some examples, the preset procedure includes commands to create circuit devices and connect ports, thereby configuring the signal blocking circuit 92 for input port B, and modifying the connection between input port B and input D of module register DFF to connect input port B to input D of module register DFF through the signal blocking circuit 92.
[0055] Specifically, the preset program is named add_xb_wrap and has variables instance and port_list. instance represents the name of the chip module-level circuit 80, and port_list represents a list of its input ports. In the preset program, a module register DFF, a test register T_DFF, and a selector T_MUX are created in the chip module-level circuit 80 using a create device command, for example, by creating the circuit device using the create_instance statement. Next, an input port B is connected to the input D of the module register DFF using a create connection command, for example, by creating the connection using the create_connection statement. Subsequently, a modification connection command is used to change the connection between input port B and the input D of the module register DFF so that input port B is connected to the input D of the module register DFF through the output Z of the selector T_MUX, for example, by modifying the connection using the move_connection statement. Finally, by creating a connection relationship statement, the input terminal D of the test register T_DFF is connected to the input terminal D of the module register DFF, the output terminal Q of the test register T_DFF is connected to the second input terminal D1 of the selector T_MUX, and the input port B is connected to the first input terminal D0 of the selector T_MUX. For example, the connection relationship is created by the create_connection statement, thereby configuring the signal blocking circuit 92 for the input port B through this preset program.
[0056] The aforementioned preset program is designed for the case where the built-in self-test circuit 90 does not include an inverter T_INV. Specifically, for the case where the built-in self-test circuit 90 includes an inverter T_INV, the signal blocking circuit 92 includes an inverter T_INV. In the preset program, a module register DFF, a test register T_DFF, an inverter T_INV, and a selector T_MUX are created in the chip module-level circuit 80 using a create_instance statement. Next, a connection relationship is created by connecting input port B to the input D of the module register DFF using a create_connection statement. Subsequently, a connection relationship is modified by changing the connection between input port B and the input D of the module register DFF so that input port B is connected to the input D of the module register DFF through the output Z of the selector T_MUX using a move_connection statement. Finally, by creating a connection relationship statement, the input terminal D of the test register T_DFF is connected to the first terminal ZN of the inverter T_INV, the second terminal I of the inverter T_INV is connected to the output terminal Z of the selector T_MUX and the input terminal D of the module register DFF, the output terminal Q of the test register T_DFF is connected to the second input terminal D1 of the selector T_MUX, and the input port B is connected to the first input terminal D0 of the selector T_MUX. For example, the connection relationship is created by the create_connection statement, thereby configuring the signal blocking circuit 92 for the input port B through this preset program.
[0057] In some embodiments, such as Figure 9 and Figure 10 As shown, the controller 91 tests the module register DFF, including: the controller 91 outputs an enable signal (i.e., the XB enable signal) to the selection terminal S of the selector T_MUX to block the unknown state, so that when the module register DFF and the test register T_DFF are working, the signal on the selection terminal S of the selector T_MUX will be pulled high to block the unknown state signal from the input port B.
[0058] like Figure 9 and Figure 10As shown, if an unknown state signal exists at input port B, the signal blocking circuit 92 is connected to input port B. The module register DFF and the test register T_DFF form a scan chain through cascading. The controller 91 tests the module register DFF by controlling the operation of the scan chain. When the controller 91 controls the scan chain to work, that is, when the module register DFF and the test register T_DFF are working, the XB enable signal x_bounding_en is output to the selection terminal S of the selector T_MUX. The output terminal Z of the selector T_MUX outputs the signal of the second input terminal D1 of the selector T_MUX to the input terminal D of the module register T_DFF. The signal of the second input terminal D1 of the selector T_MUX is the signal of the output terminal Q of the test register T_DFF, thereby blocking the unknown state signal at input port B.
[0059] In some embodiments, such as Figure 9 and Figure 10 As shown, pulling the signal high on the selector S of selector T_MUX further includes: the module register DFF being input to the signal output of test register T_DFF.
[0060] During the LBIST test described above, under the influence of the high-level XB enable signal, the selector T_MUX inputs the signal from the output Q of the test register T_DFF to the input D of the module register DFF. For example, as shown... Figure 10 The signals DFF / D and T_DFF / Q are shown.
[0061] In some embodiments, such as Figure 9 and Figure 10 As shown, controller 91 outputs a first scan signal to the scan input terminal SI of test register T_DFF, outputs a second scan signal to the scan input terminal SI of module register DFF, outputs a scan enable signal to the scan enable terminal SE of module register DFF and test register T_DFF, and outputs a clock signal to the clock terminal CK of module register DFF and test register T_DFF, thereby enabling module register DFF and test register T_DFF to operate. The first scan signal and the second scan signal are opposite signals. For example, the first scan signal could be as follows: Figure 10 The T_DFF / D signal shown can have the second scan signal as follows: Figure 10 The DFF / D signal shown.
[0062] In other words, the module register DFF and the test register T_DFF operate by receiving corresponding signals from the controller 91 at their respective ports. For example, the controller 91 outputs a second scan signal to the scan input terminal SI of the module register DFF, an output scan enable signal to the scan enable terminal SE of the module register DFF, and an output clock signal to the clock terminal CK of the module register DFF, thus putting the module register DFF into an active state. Simultaneously, the controller 91 outputs a first scan signal to the scan input terminal SI of the test register T_DFF, outputs an output scan enable signal to the scan enable terminal SE of the test register T_DFF, and outputs a clock signal to the clock terminal CK of the test register T_DFF, thus putting the test register T_DFF into an active state.
[0063] Please see Figure 12 , Figure 12 This is a schematic diagram of the chip module-level circuit structure according to an embodiment of this application. Figure 2 The chip module-level circuit 120 includes multiple input ports and multiple module registers. The input ports and module registers are independent of each other. Each input port is connected to the input terminal of a corresponding module register. For example, taking two input ports as an example, input port B is connected to the input terminal D of the corresponding module register DFF6, and input port C is connected to the input terminal D of the corresponding module register DFF7. The connection between input port B and the input terminal D of the corresponding module register DFF6 can be as described in the above embodiment. Figure 8 The circuit in the middle.
[0064] Please see Figure 13 , Figure 13 This is a flowchart illustrating the testing method for chip module-level circuits according to an embodiment of this application. Figure 2 Applied to the above embodiments Figure 9 The controller 91 with built-in self-test circuitry 90 in the logic module is a chip module-level circuit, such as... Figure 12 As shown. Figure 13 As shown, the testing method may include the following steps: S131: The controller 91 determines each input port and configures a signal blocking circuit 92 for each input port.
[0065] For the chip module-level circuit 120 that needs to be tested by LBIST, all input ports are acquired. The controller 91 determines the input port B that needs to be tested by LBIST and configures the signal blocking circuit 92 for the input port B, thereby performing the operation of configuring the signal blocking circuit 92 in a targeted manner for the chip module-level circuit 120 that needs to be tested by LBIST.
[0066] S132: The controller 91 modifies the connection between each input port and the input of the corresponding module register to connect each input port to the input of the corresponding module register through the signal blocking circuit 92; As described above for testing chip module-level circuits, the controller 91 executes a preset program to modify the connection between each input port and the input terminal of the corresponding module register, so that each input port is connected to the input terminal of the corresponding module register through the signal blocking circuit 92.
[0067] S133: When the connection between each input port and the input of the corresponding module register is modified to connect each input port to the input of the corresponding module register through the signal blocking circuit 92, the controller 91 tests the module registers, for example, the controller 91 tests module registers DFF6 and DFF7.
[0068] The controller 91 tests each module register, following the test procedure described in the chip module-level circuit test method above, which will not be repeated here.
[0069] It should be noted that the controller 91 tests each input port and its corresponding chip module-level circuit in the same way as the chip module-level circuit test method described in the above embodiment. For details, please refer to the description of the above embodiment, and it will not be repeated here.
[0070] In this embodiment, the chip module-level circuit 120 includes multiple input ports and multiple module registers. The multiple input ports and multiple module registers are independent of each other. Each input port is connected to the input terminal of the corresponding module register. The testing method includes: the controller 91 determines each input port and configures a signal blocking circuit 92 for each input port; the controller 91 modifies the connection between each input port and the input terminal of the corresponding module register to connect each input port to the input terminal of the corresponding module register through the signal blocking circuit 92; when the connection between each input port and the input terminal of the corresponding module register is modified to connect each input port to the input terminal of the corresponding module register through the signal blocking circuit 92, the controller 91 tests the module register, which can block the unknown state signal of the input port, effectively realize XB operation, and thus effectively test the chip module-level circuit 120.
[0071] Please see Figure 14 , Figure 14This is a schematic diagram of the chip structure according to an embodiment of this application. The chip 140 includes multiple first chip module-level circuits 141 and multiple second chip module-level circuits 142. The multiple first chip module-level circuits 141 are related to functional safety and require LBIST testing and XB processing. The multiple second chip module-level circuits 142 are not related to functional safety and do not require LBIST testing and XB processing. The first chip module-level circuits 141 can be those described in the above embodiment. Figure 9 The circuit in the middle.
[0072] Please see Figure 14 and Figure 15 , Figure 15 This is a flowchart illustrating a chip testing method according to an embodiment of this application. The testing method includes: Step S151: Test each of the multiple first chip module level circuits 141.
[0073] Each first chip module-level circuit 141 can be tested using the chip module-level circuit testing method described in the above embodiment, i.e., by using a logic-built-in self-test circuit.
[0074] Step S152: No test is performed on each second chip module-level circuit 142.
[0075] In other words, each second chip module-level circuit 142 is not tested using the chip module-level circuit test method described in the above embodiment.
[0076] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0077] Please see Figure 16 , Figure 16 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. The electronic device 160 includes a memory 161 and a processor 162 coupled to each other. The processor 162 is used to execute program instructions stored in the memory 161 to implement the steps of any of the above-described chip module-level circuit testing method embodiments, or to implement the steps of any of the above-described chip testing method embodiments. In a specific implementation scenario, the electronic device 160 may include, but is not limited to, a microcomputer or a server. Furthermore, the electronic device 160 may also include mobile devices such as laptops and tablets, without limitation.
[0078] Specifically, processor 162 controls itself and memory 161 to implement the steps of the test method embodiment for any of the aforementioned chip module-level circuits, or to implement the steps of the test method embodiment for any of the aforementioned chips. Processor 162 can also be referred to as a CPU (Central Processing Unit). Processor 162 may be an integrated circuit chip with signal processing capabilities. Processor 162 can also be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. A general-purpose processor can be a microprocessor or any conventional processor. Furthermore, processor 162 can be implemented using integrated circuit chips.
[0079] Please see Figure 17 , Figure 17 This is a schematic diagram of the structure of a non-volatile computer-readable storage medium according to an embodiment of this application. The non-volatile computer-readable storage medium 170 stores program instructions 171 that can be executed by a processor. The program instructions 171 are used to implement the steps of the test method embodiment of any of the above-described chip module-level circuits, or to implement the steps of the test method embodiment of any of the above-described chips.
[0080] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.
[0081] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.
[0082] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.
[0083] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0084] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0085] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims.
Claims
1. A logic-built-in self-test circuit for chip module-level circuits, characterized in that, The chip module-level circuit includes an input port and a module register, and the input port is connected to the input terminal of the module register; The logic has a built-in self-test circuit for testing the module register in the event that the connection between the input port and the input terminal of the module register is modified, including: A signal blocking circuit is connected between the input port and the input terminal of the module register, thereby modifying the connection between the input port and the input terminal of the module register. The signal blocking circuit includes a selector and a test register, wherein the first input terminal of the selector is connected to the input port, the second input terminal of the selector is connected to the output terminal of the test register, and the output terminal of the selector is connected to the input terminal of the module register. The controller is connected to the selection terminal of the selector, the scan input terminal, the scan enable terminal, and the clock terminal of the module register, and the scan input terminal, the scan enable terminal, and the clock terminal of the test register.
2. The circuit as described in claim 1, characterized in that, The signal blocking circuit also includes an inverter; The first terminal of the inverter is connected to the input terminal of the test register, and the second terminal of the inverter is connected to the output terminal of the selector and the input terminal of the function register.
3. A testing method for chip module-level circuits, characterized in that, The chip module-level circuit includes an input port and a module register, the input port being connected to the input terminal of the module register, and the test method including: The controller identifies the input port and configures a signal blocking circuit for the input port; The controller modifies the connection between the input port and the input terminal of the module register to connect the input port to the input terminal of the module register through the signal blocking circuit. The signal blocking circuit includes a selector and a test register. The first input terminal of the selector is connected to the input port, the second input terminal of the selector is connected to the output terminal of the test register, and the output terminal of the selector is connected to the input terminal of the function register. When the connection between the input port and the input terminal of the module register is modified to connect the input port to the input terminal of the module register through the signal blocking circuit, the controller tests the function register, wherein the controller is connected to the selection terminal of the selector, to the scan input terminal, scan enable terminal and clock terminal of the module register, and to the scan input terminal, scan enable terminal and clock terminal of the test register.
4. The method as described in claim 3, characterized in that, The controller determines the input port by executing a preset program, configures a signal blocking circuit for the input port, and modifies the connection between the input port and the input terminal of the module register to connect the input port to the input terminal of the module register through the signal blocking circuit.
5. The method as described in claim 3, characterized in that, The controller tests the function register, including: The controller outputs an enable signal to block unknown states to the selector's selector terminal, so that when the module register and the test register are working, the signal on the selector's selector terminal is pulled high, thereby blocking unknown state signals from the input port.
6. The method as described in claim 5, characterized in that, Pulling the signal high on the selection terminal of the selector further includes: The module register is input to the signal output by the test register.
7. The method as described in claim 5, characterized in that, The controller outputs a first scan signal to the scan input terminal of the test register, outputs a second scan signal to the scan input terminal of the module register, outputs a scan enable signal to the scan enable terminals of the module register and the test register, and outputs a clock signal to the clock terminals of the module register and the test register, thereby enabling the module register and the test register to operate, wherein the first scan signal and the second scan signal are opposite signals.
8. A testing method for chip module-level circuits, characterized in that, Applied to the logic-built-in self-test circuit as described in any one of claims 1-2, the chip module-level circuit includes multiple input ports and multiple module registers, the multiple input ports are independent of each other, the multiple module registers are independent of each other, and each input port is connected to the input terminal of the corresponding module register, the test method includes: The controller identifies each of the input ports and configures the signal blocking circuit for each of the input ports; The controller modifies the connection between each input port and the corresponding input terminal of the module register to connect each input port to the corresponding input terminal of the module register through the signal blocking circuit; When the connection between each input port and the corresponding input terminal of the module register is modified to connect each input port to the corresponding input terminal of the module register through the signal blocking circuit, the controller tests the function register.
9. A method for testing a chip, characterized in that, The chip includes multiple first chip module-level circuits and multiple second chip module-level circuits, and the testing method includes: Each of the plurality of first chip module-level circuits is tested using the method described in any one of claims 3-8; Each of the second chip module-level circuits is not tested using the method described in any one of claims 3-8.
10. An electronic device, characterized in that, It includes a memory and a processor that are coupled to each other, the processor being used to execute program instructions stored in the memory to implement the chip module-level circuit testing method of any one of claims 3-8 or the chip testing method of claim 9.