Method for improving breakdown consistency of power device by regulating and controlling photoetching doping window

Abstract

The invention provides a method for improving the breakdown consistency of a power device by regulating and controlling a photoetching doping window. The method comprises the following steps: acquiring a corresponding relation between photoetching exposure parameters and the size of a pattern opening in a doping region; providing a semiconductor substrate; providing a mask, wherein a target pattern for forming a doped region in the terminal region is defined on the mask; setting a target photoetching exposure parameter based on the corresponding relationship; exposing and developing the semiconductor substrate by using a mask so as to form a photoresist pattern on the semiconductor substrate, the opening size of the photoresist pattern in the terminal area being smaller than the size of a corresponding target pattern on the mask; and carrying out ion implantation on the semiconductor substrate by taking the photoresist pattern as a mask, and forming a doped region in the terminal region. The geometric size of the doped window is actively regulated and controlled by changing a photoresist pattern opening subjected to photoetching exposure, so that the mean value of the breakdown voltages of all power devices approaches to an ideal value in the statistical sense, and the standard deviation is minimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and more specifically, to a method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window. Background Technology

[0002] Breakdown voltage consistency (BVDSS) refers to the concentration and predictability of breakdown voltage values ​​among different chips within the same wafer, between different wafers within the same batch, or between different batches of power devices. In particular, the breakdown voltage difference under different bias currents is one of the core performance indicators of high-reliability power semiconductor devices (such as trench power MOSFETs). Especially in demanding applications such as automotive electronics and industrial control, devices must exhibit highly stable and predictable breakdown voltage characteristics within their operating voltage range. The breakdown voltage of a device is mainly determined by the electric field distribution of its internal PN junction. The deep P-well (DPW), as a key body extension and electric field modulation structure in power MOSFETs, directly affects the uniformity of the electric field distribution due to the uniformity of its geometry and doping profile, thus determining the concentration of breakdown voltage.

[0003] To improve the consistency of breakdown voltage, traditional optimization focuses on two dimensions: implantation process and mask design. One approach involves adjusting the ion implantation energy and dose to change the vertical junction depth and doping concentration of the depletion region (DPW), thereby modulating its expansion behavior. However, this method requires extensive experimental verification under specific implantation conditions, has a long development cycle, and may introduce new electrical parameter drift. Another approach directly alters the lateral pattern size of the DPW by modifying the mask design dimensions. However, this method is costly, requires re-fabrication of the mask, and may trigger adjustments to other related process steps, lacking flexibility. Furthermore, with the continuous shrinking of device feature sizes, the microscopic fluctuations in pattern transfer processes such as photolithography and etching increasingly affect the actual size of the DPW. Neither of these two methods effectively addresses lateral dimensional variations, resulting in uncontrollable fluctuations at the physical boundary positions of the DPW. This leads to a wide distribution of breakdown voltage, especially the difference in breakdown voltage under different bias currents, making tail-end failures difficult to eliminate and failing to meet the stringent yield and reliability requirements of automotive-grade devices. Summary of the Invention

[0004] In view of the problem of large fluctuations in breakdown voltage difference in the doped region in the prior art, this application provides a method and manufacturing method for improving the breakdown uniformity of power devices by adjusting the photolithography doping window. This method can actively suppress the micro-fluctuations in the DPW pattern size in a front-end manner without changing the mask design or the implantation process parameters, thereby improving the breakdown voltage uniformity of power devices.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, comprising:

[0006] Obtain the correspondence between photolithography exposure parameters and the opening size of the doped region pattern;

[0007] Provide a semiconductor substrate;

[0008] A photomask is provided, on which a target pattern is defined to form a doped region in the terminal region;

[0009] Based on the aforementioned correspondence, the target photolithography exposure parameters are set;

[0010] The semiconductor substrate is exposed and developed using the photomask to form a photoresist pattern on the semiconductor substrate, wherein the opening size of the photoresist pattern located in the terminal area is smaller than the size of the target pattern on the photomask;

[0011] Using the photoresist pattern as a mask, ion implantation is performed on the semiconductor substrate to form a doped region in the terminal region;

[0012] The subsequent processes are then executed to complete the fabrication of the power device containing the doped region.

[0013] Optionally, obtaining the correspondence between photolithography exposure parameters and the opening size of the doped region pattern includes:

[0014] A test substrate is provided, and using the mask, multiple exposures and developments are performed by adjusting the exposure dose E and focus value F in the photolithography process;

[0015] Measure and acquire the size data Z of the photoresist opening formed on the test substrate under different exposure parameter combinations (E, F);

[0016] Based on the size data Z, a model relating exposure parameters to aperture size is established through fitting.

[0017] Optionally, the relationship model is a linear model, expressed as: Z=K0+K1*E+K2*F; where K0, K1, and K2 are model coefficients obtained through fitting, and Z is the predicted photoresist aperture size.

[0018] Optionally, the values ​​of the model coefficients K0, K1, and K2 satisfy the following: K0 is between 350 and 450, K1 is between 0.7 and 1.1, and K2 is between -40 and -20.

[0019] Optionally, the photoresist aperture size Z is positively correlated with the exposure dose E, and the photoresist aperture size Z is negatively correlated with the focus value F.

[0020] Optionally, the size of the photoresist opening is 10% to 30% smaller than the size of the target pattern on the mask.

[0021] Optionally, the doped region is a doped well region in a power device, and the doped well region includes P-wells, N-wells, and a bulk region.

[0022] Optionally, the photomask may also define a target pattern for forming a doped region in the active region. By utilizing the correspondence between the photolithography exposure parameters and the opening size of the doped region pattern, the target exposure parameters are set to form the doped region pattern on the active region of the semiconductor substrate.

[0023] Optionally, the doped region is a deep P-well formed in the terminal region, and the deep P-well constitutes a field-limiting ring or a junction terminal extension structure.

[0024] As described above, the method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, the manufacturing method thereof, and the display device provided by the present invention have at least the following beneficial technical effects:

[0025] The technical solution provided in this application optimizes the PN junction geometry that determines the breakdown voltage by actively and precisely reducing the actual size of the doping window in the doped region by lowering the photolithography exposure dose. Experimental data shows that after applying the method of this invention, the average breakdown voltage difference (dBVDSS) under different bias currents is adjusted from 0.08 V~0.09 V under conventional processes to close to 0 V, eliminating the systematic electrical offset caused by excessively wide and inconsistent doping windows. The standardized control of the doping window size makes the position and intensity of the electric field concentration points (breakdown hot spots) inside all devices highly uniform. Experiments show that the dispersion of the breakdown voltage between devices (measured by the standard deviation of dBVDSS) is reduced from about 0.105 V in conventional processes to 0.014 V, and tail-end failure chips are basically eliminated.

[0026] Furthermore, the solution provided in this application requires no modification to the photomask, nor any adjustment to the ion implantation dose and energy. It significantly improves breakdown uniformity simply by fine-tuning the exposure dose of the lithography machine. This application transforms traditional process adjustments, which rely on engineers' experience and extensive experimentation, into a model. Through mathematical formulas, it clearly reveals the quantitative relationship between key lithography parameters and key dimensions, enabling accurate predictions and decisions based on the model. Attached Figure Description

[0027] Figure 1 The flowchart shown is a method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to Embodiment 1 of the present invention.

[0028] Figure 2The cross-sectional view of a deep P-well formed using conventional methods and the method provided in this application is provided in Embodiment 1 of the present invention.

[0029] Figure 3 The results show a comparison of the statistical distribution of breakdown voltage differences under different bias currents, achieved by adjusting the lithography dose to change the width of the deep P-well doping window under the same baseline process. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0032] Example 1

[0033] This embodiment provides a method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, such as... Figure 1 The diagram shows a flowchart of a method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, as provided in this embodiment; it includes the following steps:

[0034] S1: Obtain the correspondence between photolithography exposure parameters and the aperture size of the doped region pattern; S2: Provide a semiconductor substrate; S3: Provide a photomask with a target pattern defined on it to form a doped region in the terminal area; S4: Set the target photolithography exposure parameters based on the correspondence; S5: Expose and develop the semiconductor substrate using the photomask to form a photoresist pattern on the semiconductor substrate, wherein the aperture size of the photoresist pattern located in the terminal area is smaller than the design size of the corresponding pattern on the photomask; S6: Use the photoresist pattern as a mask to perform ion implantation on the semiconductor substrate to form a doped region in the terminal area. Specifically, it also includes S7: Perform subsequent processes to complete the fabrication of a power device containing the doped region.

[0035] Specifically, step S1, obtaining the correspondence between photolithography exposure parameters and the opening size of the doped region pattern, includes:

[0036] S11: Experimental Design; Provide a test substrate and use a photomask to perform multiple exposures and developments by adjusting the exposure dose E and focus value F in the photolithography process; S12: Pattern Formation and Data Acquisition; Measure and acquire the size data Z of the photoresist opening formed on the test substrate under different combinations of exposure parameters (E, F); S13: Model Fitting; Based on the size data Z, establish a quantitative relationship model between the exposure parameters and the opening size through fitting.

[0037] Specifically, S11, Experimental Design: A test substrate is provided, specifically a silicon wafer covered with photoresist of the same thickness as the product process. The mask used in the test experiment is the same as the mask used in subsequent product manufacturing steps, and the mask defines the target pattern for forming doped regions in the termination region. Generally, the pattern shape on the mask is designed according to actual needs, including concentric rings or strips for forming field-limiting rings. Specifically, the doped region in the active region is strip-shaped or grid-shaped; the doped region in the termination region is ring-shaped or strip-shaped, forming a field-limiting ring or junction termination extension structure. Specifically, the doped region is a doped well region in a power device, including P-wells, N-wells, and bulk regions, specifically including deep P-wells and deep N-wells. This embodiment uses the formation of a deep P-well in the termination region as an example for illustration.

[0038] Experimental Design: An experimental matrix was designed containing multiple combinations of process conditions. The core variables are two key parameters of the photolithography process: exposure dose (E) and focus value (F). The range of exposure dose E can cover the center value of the process window and its fluctuation range above and below it. For example, 5-7 levels can be selected within ±20% of the reference dose. The range of focus value F should cover the optimal focus point and its defocus range before and after it. For example, multiple levels can be selected within the range of -0.8 μm to +0.8 μm. By combining different E and F, a series of exposure parameter combinations (E, F) are formed, as shown in Table 1, which displays the experimental data for this embodiment: Exposure dose E values ​​include: 220, 240, 260, 280, 300, 320, 340, 360, 380, 400, 420; focus value F values ​​include: -0.8, -0.6, -0.4, -0.2, 0, 0.2, 0.4, 0.6, 0.8.

[0039]

[0040] For each parameter combination (E, F) in the experimental matrix, an independent photolithography process (including standard steps such as exposure, post-baking, and development) is performed on the test substrate. After development, the pattern aperture size (Z) of the photoresist corresponding to the deep P-well pattern in the terminal region is accurately measured on the test substrate using a critical-size scanning electron microscope (CD-SEM) or other equivalent measurement tools, in nm. For each parameter combination, measurements are typically taken at multiple measurement points (e.g., different locations on the chip) and averaged to obtain a representative pattern aperture size Z for that combination. Each group (E, F) and its corresponding measurement result Z are recorded. As shown in Table 1, each group (E, F) and its corresponding measurement result Z are recorded in the table.

[0041] Specifically, based on the data in Table 1, it can be observed that: under the condition of a fixed focus value F, as the exposure dose E gradually increases, the pattern opening size Z of the photoresist gradually increases; under the condition of a fixed exposure dose E, as the focus value F increases from -0.8 to 0.8, the pattern opening size Z of the photoresist gradually decreases.

[0042] S13. Model Fitting: Collect data sets (E, F, Z) for all experimental combinations. Based on these data, establish a quantitative relationship model between exposure parameters (E, F) and aperture size (Z) using mathematical fitting methods.

[0043] The relationship models obtained by fitting the data shown in Table 1 include linear response surface model and quadratic response surface model. The linear response surface model is expressed as: Z = K0 + K1 * E + K2 * F; where Z is the predicted photoresist aperture size; E is the exposure dose; F is the focus value; and K0, K1, and K2 are the model coefficients obtained through fitting. The physical law revealed by this model is that the aperture size Z is positively correlated with the exposure dose E and negatively correlated with the focus value F. The specific data of K0, K1, and K2 are determined by the actual process based on the photoresist, mask pattern, and basic process conditions. Generally, the values ​​of the model coefficients K0, K1, and K2 satisfy the following: K0 is between 350 and 450, K1 is between 0.7 and 1.1, and K2 is between -40 and -20. In this embodiment, according to the data shown in Table 1, K0 = 400, K1 = 0.92, and K2 = -25.

[0044] The expression for the quadratic response surface model is: Z = β0 + β1 * E + β2 * F + β3 * E 2+ β4*F 2 +β5*E*F; where Z is the predicted photoresist aperture size; E is the exposure dose; F is the focus value; β0, β1, β2, β3, β4, and β5 are all fitting coefficients. Compared to the linear response surface model, the quadratic model has additional terms, E... 2A negative coefficient indicates that the aperture size saturates with increasing exposure dose, and the rate of increase gradually slows down; F 2 Negative coefficients with large absolute values ​​indicate that the aperture size decreases parabolically when the focus value deviates from the optimal focal plane. Positive E*F cross-term coefficients indicate a weak synergistic interaction between exposure dose and focus value. In this embodiment, based on all experimental data shown in Table 1, the specific coefficient values ​​obtained by least squares regression fitting are: β0 = -128.5, β1 = 4.6, β2 = 94.8, β3 = -0.00735, β4 = -70.225, β5 = 0.152. The quadratic response surface model has a higher fitting degree than the linear response surface model and can more accurately describe the nonlinear variation behavior of the aperture size within the entire process window.

[0045] Optionally, it also includes S14, model validation: Validating the model using partial experimental data, predicting the opening size Z under the new parameter combination using the established model, and comparing it with the actual measured value Z. Calculating the prediction error to evaluate the accuracy and reliability of the model. Ensuring the model meets the accuracy requirements of subsequent process control.

[0046] S2: A semiconductor substrate is provided. Specifically, this embodiment illustrates the fabrication of a trench-type power MOSFET by forming an epitaxial layer on the semiconductor substrate, and a dielectric layer or semiconductor layer, such as a pad oxide layer or a buffer layer, is formed on the epitaxial layer. In this embodiment, a lightly doped N-type (N-) single-crystal silicon substrate is provided; an N-type epitaxial layer with a specific thickness and doping concentration is grown on this substrate using an epitaxial process. This epitaxial layer will serve as the drift region of the device. Before entering the deep P-well photolithography step in this embodiment, the surface of the semiconductor substrate is prepared for photoresist coating and patterning.

[0047] S3: Provide a mask on which a target pattern is defined to form a doped region in the terminal region;

[0048] Generally, the photomask includes a target pattern for defining the doped regions of the power device termination region. Optionally, the photomask may also include a target pattern for forming doped regions in the active region.

[0049] Generally, the target pattern is adjusted according to the actual problem to be solved, including ring-shaped, strip-shaped or combined geometric shapes. The purpose is to form field-limiting rings or junction termination extensions and other electric field mitigation structures in the terminal region of the silicon wafer edge after subsequent ion implantation, so as to improve the breakdown voltage of the device and stabilize its edge electric field.

[0050] S4: Based on the correspondence, set the target lithography exposure parameters;

[0051] Specifically, based on the desired electrical performance targets of the doped region in the power device termination area, the breakdown voltage and distribution consistency are considered. The target physical dimensions of the doped region in the termination area are determined, particularly the target size Z0 of its lateral opening. Generally, the target size Z0 is determined based on electrical simulations or historical yield data and is explicitly smaller than the design size of the corresponding pattern on the mask. Subsequently, the target size Z0 is used as a known quantity and substituted into the quantitative relationship model obtained in step S1. By solving this equation, one or more sets of target photolithography exposure parameters required to achieve the target size Z0 are calculated in reverse, namely the target exposure dose E0 and the target focus value F0.

[0052] S5: Exposure and development are performed on a semiconductor substrate using a photomask to form a photoresist pattern on the semiconductor substrate, wherein the opening size of the photoresist pattern located in the terminal area is smaller than the design size of the corresponding pattern on the photomask.

[0053] Specifically, a layer of photoresist is uniformly coated on the surface of the semiconductor substrate provided in step S2, and pre-baking is performed to remove the solvent. Then, the mask provided in step S3 is precisely aligned with the substrate. Using a lithography machine, the target photolithography exposure parameters set in step S4, including the target exposure dose E0 and the target focus value F0, are used to expose the coated substrate, projecting the target pattern of the terminal area on the mask onto the photoresist. After exposure, post-baking is performed to promote the completion of the photochemical reaction and improve the pattern contour, followed by development, thereby forming a three-dimensional photoresist pattern on the substrate surface.

[0054] S6: Using the photoresist pattern as a mask, ion implantation is performed on the semiconductor substrate to form a doped region in the terminal area;

[0055] Specifically, the photoresist pattern formed in step S5 is used as an implantation mask to perform ion implantation on the semiconductor substrate to form a terminal doped region. The core parameters of the implantation process, including the implanted species (e.g., boron ions B⁺ or BF₂⁺), implantation energy, and implantation dose, are completely consistent with the baseline process without applying the control method of this invention. This application only changes the geometry of the doped region by fine-tuning the front-end photolithography parameters, without changing the concentration and longitudinal distribution of the dopant itself, thereby avoiding unknown electrical variations that may be introduced by changing the implantation conditions.

[0056] A high-energy ion beam bombards the substrate surface vertically or at a certain angle. In areas uncovered by photoresist (i.e., at photoresist openings), the silicon crystal beneath is implanted with impurity ions, forming dopant. Areas covered by photoresist are protected. Because the photoresist openings in the terminal region are designed to be smaller, the actual lateral size of the doped region is correspondingly reduced, resulting in more precise and consistent boundary positions. After implantation, high-temperature annealing (such as rapid thermal annealing, RTA) is typically required to activate the implanted impurity atoms and repair lattice damage.

[0057] S7: Perform subsequent processes to complete the fabrication of power devices.

[0058] Optionally, a doped region may be formed in the active region. For example... Figure 2 The diagram shows cross-sectional views of deep P-wells formed using both conventional and methods provided in this embodiment. In conventional methods, the large doping window size of the deep P-well and the random variation in its boundary position due to process fluctuations lead to dispersed breakdown hotspots, uneven electric field distribution, and poor breakdown voltage consistency. However, using the method of this application, the actual width of the deep P-well is reduced, resulting in a more uniform depletion region boundary, a more concentrated and uniform electric field distribution, and the breakdown hotspots are locked at preset positions. This significantly improves the consistency of the device's breakdown voltage and reduces the risk of tail failure.

[0059] Optionally, following the standard process flow for power devices (such as trench MOSFETs), a series of subsequent manufacturing steps are performed. These steps typically include, but are not limited to: trench etching in the active region of the device to form a gate trench; growing a gate oxide layer; depositing and etching polysilicon to form the gate electrode; performing ion implantation and annealing in the body and source regions; depositing an interlayer dielectric layer and etching contact holes; depositing and patterning a metal layer to form the source, gate, and other electrodes; performing back-side thinning and back-side metallization to form the drain; and finally, dicing, packaging, and testing.

[0060] Specifically, this embodiment provides a set of control experiments to illustrate the technical effects achieved by the method provided in this application for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, such as... Figure 3As shown, this paper presents a comparison of the statistical distribution of breakdown voltage difference (dBVDSS) under different bias currents after adjusting the photolithography dose to change the actual doped window width of the deep P-well (DPW) under the same baseline process. Nine wafers were used and divided into four groups. The first group (01, 02, 03) was the control group using the conventional process, with its DPW width being the mask design value (1.8µm). The second group (04, 05), the third group (06, 07), and the fourth group (08, 09) were the experimental groups applying the method of this invention. By reducing the exposure dose, the DPW width was actively and consistently reduced to approximately 1.2µm, 1.35µm, and 1.4µm, respectively. The statistical data of the mean and standard deviation of dBVDSS for each group are shown below. Figure 3 As shown, in the first group, the conventional process (control group) DPW width is 1.8 µm, WAFER 01 has a dBVDSS value of 0.082 and a dBVDSS standard deviation of 0.096 V; WAFER 02 has a dBVDSS value of 0.087 and a dBVDSS standard deviation of 0.111 V; WAFER 03 has a dBVDSS value of 0.087 and a dBVDSS standard deviation of 0.108 V; In the second group, the DPW width is 1.2 µm, WAFER 04 has a dBVDSS value of -0.001 and a dBVDSS standard deviation of 0.012 V; WAFER 05 has a dBVDSS value of -0.001 and a dBVDSS standard deviation of 0.016 V; In the third group, the DPW width is 1.35 µm, WAFER... The dBVDSS value of WAFER 06 is -0.0156, and the standard deviation of dBVDSS is 0.038 V; the dBVDSS value of WAFER 07 is -0.0133, and the standard deviation of dBVDSS is 0.035 V; the width of the fourth group of DPW is 1.4 µm, the dBVDSS value of WAFER 08 is -0.006, and the standard deviation of dBVDSS is 0.0178 V; the dBVDSS value of WAFER 09 is -0.009, and the standard deviation of dBVDSS is 0.029 V.

[0061] The conventional process has a mean dBVDSS of approximately +0.085 V, exhibiting a significant positive bias. Using the method provided in this application, the mean dBVDSS of all experimental groups was adjusted to be extremely close to the ideal value of 0 V (absolute value ≤ 0.0078 V). Particularly in the second group, when the DPW width was adjusted to approximately 1.2 µm, the dBVDSS for WAFER 04 was -0.001 V, indicating that precise control of the DPW width can effectively eliminate geometric factors causing systematic shifts in breakdown voltage. Furthermore, the standard deviation of dBVDSS in the conventional process is as high as approximately 0.105 V, indicating performance dispersion among devices. Applying the method provided in this application significantly reduces this dispersion. In particular, in the second experimental group, when the DPW width was adjusted to approximately 1.2 µm, the standard deviation for WAFER 04 converged to approximately 0.012 V, an improvement of approximately one order of magnitude compared to the conventional process. This demonstrates that the control method provided by the present invention can actively control the geometry of the doping window by simply changing the opening of the photoresist pattern in the photolithography exposure, so that the breakdown voltage of all power devices can statistically approach the ideal value and minimize the standard deviation, which can significantly improve the uniformity of device performance within and between wafers.

[0062] Furthermore, experimental data clearly show that a narrower DPW is not always better; rather, there exists an optimal narrowing range that maximizes performance. In this embodiment, a DPW width of approximately 1.2 µm achieves optimal mean and standard deviation simultaneously. Specifically, the photoresist aperture size Z in the terminal area is reduced by 10% to 30% compared to the mask design size. Within this range, the mean of the breakdown voltage difference under different bias currents is corrected to near 0V, improving breakdown voltage consistency.

[0063] Generally, the photoresist aperture size Z in the terminal area is reduced by 5% to 40% compared to the mask design size. Furthermore, the photoresist aperture size Z in the terminal area is reduced by 10% to 30% compared to the mask design size.

[0064] Specifically, the proposed method of controlling the doping window size by adjusting photolithography exposure parameters to improve the consistency of device electrical parameters is not limited to the deep P-well termination structure of the trench power MOSFET in the aforementioned embodiments. It also includes Super-junction MOSFETs, which can be used for photolithographic doping window control in the P-pillar region or charge balance region, improving charge balance accuracy through active narrowing, and significantly enhancing breakdown voltage uniformity and avalanche withstand capability consistency; LDMOS, which can be used for size control of the injection window in the drift region or body region, optimizing the trade-off between breakdown voltage and specific on-resistance, and improving device matching characteristics; and shielded gate trench power MOSFETs, which can be used for window size control in the doped region below the shielding electrode or in the termination guard ring, further improving the high-voltage stability and reliability of the device.

[0065] The technical solution provided in this application optimizes the PN junction geometry that determines the breakdown voltage by actively and precisely reducing the actual size of the doping window in the doped region by lowering the photolithography exposure dose. Experimental data shows that after applying the method of this invention, the average breakdown voltage difference (dBVDSS) under different bias currents is adjusted from 0.08 V~0.09 V under conventional processes to close to 0 V, eliminating the systematic electrical offset caused by excessively wide and inconsistent doping windows. The standardized control of the doping window size makes the position and intensity of the electric field concentration points (breakdown hot spots) inside all devices highly uniform. Experiments show that the dispersion of breakdown voltage between devices is reduced from about 0.105 V in conventional processes to 0.014 V, and tail-end failure chips are basically eliminated.

[0066] Furthermore, the solution provided in this application requires no modification to the photomask, nor any adjustment to the ion implantation dose and energy. Control of critical dimensions can be achieved solely through fine-tuning the exposure dose of the lithography machine. This application transforms the reliance on engineers' experience and extensive experimentation in traditional process adjustments into a model. Through mathematical formulas, it clearly reveals the quantitative relationship between key lithography parameters and critical dimensions, enabling model-based prediction and decision-making.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window, characterized in that, include: Obtain the correspondence between photolithography exposure parameters and the aperture size of the photoresist pattern in the doped region; Provide a semiconductor substrate; A photomask is provided, on which a target pattern is defined to form a doped region in the terminal region; Based on the aforementioned correspondence, the target photolithography exposure parameters are set; The semiconductor substrate is exposed and developed using the photomask to form a photoresist pattern on the semiconductor substrate, wherein the opening size of the photoresist pattern located in the terminal area is smaller than the size of the target pattern on the photomask; Using the photoresist pattern as a mask, ion implantation is performed on the semiconductor substrate to form a doped region in the terminal region.

2. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 1, characterized in that, The relationship between photolithography exposure parameters and the aperture size of the photoresist pattern in the doped region includes: A test substrate is provided, and using the mask, multiple exposures and developments are performed by adjusting the exposure dose E and focus value F in the photolithography process; The size Z of the photoresist opening formed on the test substrate under different exposure parameter combinations (E, F) was measured and obtained; Based on the size Z of the etching opening, a model relating the exposure parameters to the opening size is established by fitting.

3. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 2, characterized in that, The relationship model is a linear model, expressed as: Z=K0+K1*E+K2*F; where K0, K1, and K2 are model coefficients obtained through fitting, and Z is the predicted photoresist aperture size.

4. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 3, characterized in that, The values ​​of the model coefficients K0, K1, and K2 are as follows: K0 is between 350 and 450, K1 is between 0.7 and 1.1, and K2 is between -40 and -20.

5. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 3, characterized in that, The photoresist aperture size Z is positively correlated with the exposure dose E, and the photoresist aperture size Z is negatively correlated with the focus value F.

6. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 1, characterized in that, The size of the photoresist opening is 10% to 30% smaller than the size of the target pattern on the photomask.

7. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 1, characterized in that, The doped region is a doped well region in a power device, and the doped well region includes P-wells, N-wells, and a bulk region.

8. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 1, characterized in that, The photomask also defines a target pattern for forming a doped region in the active region. By utilizing the correspondence between the photolithography exposure parameters and the opening size of the doped region pattern, the target exposure parameters are set to form a doped region pattern on the active region of the semiconductor substrate.

9. The method for improving the breakdown uniformity of power devices by adjusting the photolithographic doping window according to claim 7, characterized in that, The doped region is a deep P-well formed in the terminal region, and the deep P-well constitutes a field-limiting ring or a junction terminal extension structure.

Images