True random number generation method based on flash memory

Abstract

The invention provides a true random number generation method based on a flash memory, which comprises the following steps: integrally erasing a target block which comprises a plurality of word lines, and each word line comprises a plurality of storage units; obtaining a programming instruction and input data, and performing programming operation on part of word lines of the target block based on the programming instruction and the input data; within the set time, part of the word lines are read through reference voltage to obtain read data, and the reference voltage is set based on the threshold voltage of the storage unit; comparing the read data with the input data to obtain an error code position; and numbering the bit error position, converting the number into a corresponding bit 0 and a bit 1, and outputting a bit stream of the true random number based on the bit 0 and the bit 1. According to the invention, security function extension is carried out by using the existing storage chip, so that the problems of cost and compatibility of large-scale deployment of the true random number generator are solved.

Description

Technical Field

[0001] This invention relates to the field of true random number generation technology, and specifically to a flash memory-based true random number generation method. Background Technology

[0002] Random numbers are a crucial foundation of modern information security systems, widely used in key generation, encrypted communication, digital signatures, identity authentication, secure protocol handshakes, and blockchain consensus. In practical applications, random number generators can be broadly categorized into pseudo-random number generators (PRNGs) and true random number generators (TRNGs). Pseudo-random number generators typically utilize algorithms such as linear congruence or block ciphers / hash function extensions to generate long-period sequences using deterministic state machines given an initial seed. Their advantages include simplicity and speed; however, their randomness inherently depends on the unpredictability of the seed. If the seed is leaked or partially deduced by an attacker, the security of the generated sequence will be significantly reduced, making it difficult to meet the unpredictability and non-reproducibility requirements of high-security applications.

[0003] In contrast, true random number generators utilize inherent random noise or physical uncertainties in the physical world as entropy sources, such as thermal noise, shot noise, oscillator phase jitter, metastable state flips, power / ground bounce noise, and device process perturbations. They obtain random bit streams by collecting, digitizing, and post-processing this physical noise. Hardware TRNGs can directly generate high-entropy random numbers without relying on a secret seed, making them a key foundational module for building secure chips, cryptographic modules, IoT terminals, and security systems in automotive and industrial control scenarios.

[0004] Existing hardware true random number generators have proposed various implementation schemes, such as:

[0005] TRNGs based on oscillator jitter generate entropy sources by using phase noise and frequency jitter differences in multiple ring oscillators or voltage-controlled oscillators, and then output random bits after sampling and post-processing. Although this type of scheme has a relatively simple structure and is easy to integrate into digital circuits, its output randomness is sensitive to process technology, power supply voltage, operating temperature, and layout. In addition, in order to obtain sufficient jitter and output rate, a large number of oscillators are often required, resulting in large area and power consumption costs.

[0006] Metastable TRNGs utilize the random flip-flop / latch transitions that enter a metastable state within a critical sampling window as an entropy source. This type of structure can provide high bit rates, but its metastable behavior is highly sensitive to clock jitter, signal rising edges, device matching, and other factors. It is easily affected by process drift and environmental changes. In practical chips, complex calibration and symmetrical layout design are often required to ensure a balanced "0 / 1" distribution and stable entropy intensity.

[0007] TRNGs based on noisy devices (such as Zener diodes, avalanche diodes, and amplified thermal noise) amplify random noise through a dedicated analog front-end before comparison and sampling. This type of solution typically requires dedicated analog devices, precision bias circuits, and amplification circuits, increasing both process and design complexity. Furthermore, at advanced CMOS process nodes, the parameter dispersion of analog devices and process variations are more pronounced, posing challenges to mass production consistency and cross-process migration. Simultaneously, the analog front-end incurs additional static power consumption and area overhead, hindering its widespread adoption in large-scale SoCs / MCUs.

[0008] As can be seen, current mainstream quantum random number generators typically rely on dedicated hardware modules, resulting in large device size, high power consumption, and high cost, making them difficult to embed into resource-constrained edge devices. Against this backdrop, it is necessary to propose a hardware true random number generator solution with a simpler structure and lower implementation cost to meet the application requirements of next-generation security chips, IoT terminals, and high-security systems.

[0009] Flash memory, as a mature non-volatile storage medium, has become the mainstream choice for edge storage chips. The advantage of using flash memory for true random number generation lies in its ability to be massively integrated into various edge devices (such as IoT nodes and mobile terminals) without introducing additional hardware, offering inherent compatibility and low cost advantages. Furthermore, flash memory-based random number generation schemes possess low power consumption characteristics and can directly utilize existing readout circuits in the storage array, facilitating efficient random number extraction in resource-constrained edge environments and enabling highly integrated, low-cost chip-level true random number generators. Currently, a small number of works have implemented true random number generation in flash memory, typically using read noise or operation latency as entropy sources. Methods utilizing noise often rely on unconventional operations (such as intentional interruptions during regular erase / programming processes) to precisely adjust and maintain a stable threshold voltage, thereby ensuring stable random output, making them complex for engineering implementation. For methods using operation latency fluctuations as entropy sources, the random number extraction process is relatively complex, and the speed is difficult to improve. Summary of the Invention

[0010] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a true random number generation method based on flash memory. This solves the technical problems that existing random number generators (including classical hardware random number generators and quantum random number generators) require dedicated hardware devices, which are costly and not suitable for large-scale deployment at the edge. Furthermore, their environmental adaptability and robustness are still difficult to meet the requirements for reliable operation in actual edge scenarios.

[0011] To achieve the above-mentioned technical objectives, in a first aspect, the present invention provides a method for generating true random numbers based on flash memory, comprising the following steps:

[0012] The target block is completely erased. The target block includes multiple word lines, and each word line includes multiple memory cells. The threshold voltage of all memory cells in the target block returns to the lowest erase state.

[0013] Obtain programming instructions and input data, and perform programming operations on a portion of the word lines of the target block based on the programming instructions and input data;

[0014] Within a set time period, the read data is obtained by reading a portion of the word lines using a reference voltage, wherein the reference voltage is set based on the threshold voltage distribution of the memory cell array;

[0015] The read data is compared with the input data to determine the location of the error.

[0016] The error locations are numbered, and the numbers are converted into corresponding bits 0 and bits 1. A bit stream of truly random numbers is output based on the bits 0 and bits 1.

[0017] Compared with the prior art, the beneficial effects of the present invention include:

[0018] This invention utilizes 3D-NAND flash memory chips commonly found in devices such as mobile phones, tablets, and personal computers to directly implement a random number generator. This method leverages the charge tunneling effect inherent in 3D-NAND flash memory chips to generate truly random numbers. The generation of random numbers can be achieved using the internal circuitry of the flash memory chip and the hardware circuitry of the memory controller, avoiding or reducing the use of dedicated hardware.

[0019] This invention induces short-term data retention behavior through conventional commands (erase and program) on the flash memory chip, and reads the data within a set time and at a set reference voltage. Using controller hardware, error information is extracted and processed from the read data, and a random bit stream is output. It has the advantages of low cost and easier integration.

[0020] According to some embodiments of the present invention, programming operations are performed on a portion of the word lines of the target block based on the programming instructions and the input data, including the following steps:

[0021] The target block's word lines are programmed based on Gray code encoding and its correspondence with threshold voltage: Gray code maps n-bit binary values ​​to 2 in different ways. n There are 7 voltage levels, with the lowest voltage level being the erase state and the remaining 7 being the programming state.

[0022] According to some embodiments of the present invention, programming operations are performed on a portion of the word lines of the target block, including the following steps:

[0023] Programming is performed on word lines, simultaneously programming some or all of the memory units within a word line.

[0024] According to some embodiments of the present invention, the time limit is set to be no more than 10 seconds after the programming operation is performed on a portion of the word lines of the target block.

[0025] According to some embodiments of the present invention, the reference voltage is located to the left or right of the target read state corresponding to the memory cell.

[0026] According to some embodiments of the present invention,

[0027] When using the left-side reference voltage, it is required to be no less than the threshold voltage of the memory cell with the lowest threshold voltage of the most recently programmed state on its right side after programming, minus 0.1V. Different reference voltages are allowed for each word line.

[0028] If the right-side reference voltage is used, it must not be higher than the threshold voltage of the memory cell with the highest threshold voltage of the most recently programmed state on its left after programming. Different reference voltages are allowed for each word line.

[0029] Secondly, the technical solution of the present invention provides a design for a true random number generation system based on flash memory, including: a control and data processing module, a cache module and a flash memory chip, wherein the control and data processing module is used to send commands to erase a target block of the flash memory chip. The target block includes multiple word lines, each word line includes multiple memory cells, and the threshold voltage of all memory cells in the target block returns to the lowest erase state.

[0030] The flash memory chip acquires programming instructions and input data from the control and data processing module, and performs programming operations on a portion of the word lines of the target block based on the programming instructions and the input data;

[0031] Within a set time period, the control and data processing module reads the partial word lines using a reference voltage to obtain read data. The reference voltage is set based on the threshold voltage distribution of the storage unit. The read data is compared with the input data to obtain the error location.

[0032] Error locations are numbered and converted into corresponding bits 0 and 1. A bit stream of truly random numbers is output based on the bits 0 and 1. The bit stream is temporarily stored by the cache module and output by the control and data processing module for secure communication and encrypted computing scenarios of edge devices.

[0033] According to some embodiments of the present invention, the flash memory chip is a 3D-NAND flash memory chip.

[0034] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0035] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein the abstract drawings are to be completely consistent with one of the drawings in the specification:

[0036] Figure 1 A diagram of a flash memory array architecture provided in one embodiment of the present invention;

[0037] Figure 2 Gray code, threshold voltage distribution, and read reference voltage diagram are provided for one embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of a flash-based true random number generation system provided in one embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] It should be noted that although functional modules are divided in the system diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0041] Reference Figures 1 to 2 , Figure 1 A diagram of a flash memory array architecture provided in one embodiment of the present invention; Figure 2 A threshold voltage distribution and reading reference voltage diagram provided in one embodiment of the present invention;

[0042] In one embodiment, a flash memory-based true random number generation method includes the following steps: erasing a target block as a whole, the target block including multiple word lines, each word line including multiple memory cells, and the threshold voltage of all memory cells in the target block returning to the lowest erase state; acquiring programming instructions and input data, performing programming operations on a portion of the word lines of the target block based on the programming instructions and input data, and acquiring the threshold voltage of all memory cells performing the operation; reading data from a portion of the word lines using a reference voltage within a set time, the reference voltage being set based on the threshold voltage of the memory cells; comparing the read data with the input data to obtain the error location; numbering the error location and converting the number into corresponding bits 0 and bits 1, and outputting a bit stream of true random numbers based on bits 0 and bits 1.

[0043] like Figure 1 As shown, the array architecture of flash memory is as follows: A flash memory array contains several blocks, a block contains several word lines, and each word line contains several storage cells (e.g., 1024*8*16). Depending on the storage density, each word line can store 1-5 pages of data. When erasing flash memory, the entire block is erased. When programming, it is done word line by word, simultaneously programming all pages within a word line.

[0044] Threshold voltage distribution and reference voltage (dashed lines on both sides of each packet): Figure 2 This paper presents a basic mathematical model of voltage distribution based on Gray code. Gray code maps a 3-bit binary value to 8 voltage level states in different ways. The lowest voltage state is usually called the "erased state," and the remaining 7 states are called "programmed states." Each programmed state has a corresponding reference voltage adjacent to it. The reference voltage on the left is lower than the average threshold voltage of the corresponding programmed state, and the reference voltage on the right is higher than the average threshold voltage of the corresponding programmed state. For example, the "100" state corresponds to the left reference voltage RV2 and the right reference voltage RV3. Precise control of these states is crucial for ensuring correct data reading and writing. After all three pages are programmed, they can be read by applying the corresponding read reference voltages. In TLC NAND, an LSB page requires only two read reference voltages to complete a single read; a CSB page can be read by applying three read voltages; and extracting information from an MSB page requires two read voltages. If the threshold voltage of any bit crosses the read reference voltage and overflows into an adjacent state, a read error will occur.

[0045] This method mainly uses Figure 3 The device generates and extracts random numbers using the following method. The steps are as follows:

[0046] 1. The controller sends a command to erase the target block of the flash memory array;

[0047] 2. The controller sends commands and data, and uses the data to program the specified word lines (the number of selected word lines is 1 or more, but not all word lines in the entire block are filled; existing methods for generating random numbers require filling the entire block). The data can be arbitrary.

[0048] 3. After programming a specific word line, delay reading the word line by no more than 10 seconds. During the reading process, a specific read reference voltage must be used. The reference voltage can be located to the left or right of the corresponding target read state. When using a left-side reference voltage, it must be no lower than the threshold voltage of the memory cell with the lowest threshold voltage of the most recently programmed state to its right after programming, minus 0.1V; when using a right-side reference voltage, it must be no higher than the threshold voltage of the memory cell with the highest threshold voltage of the most recently programmed state to its left after programming. Different reference voltages can be selected for each word line.

[0049] Current methods detect bit errors by programming the entire block to change the threshold voltage of the target word line, rather than directly adjusting the reference voltage. However, these methods are slow and cannot achieve high-speed extraction because they require programming all word lines within the block. Our approach uses a specific reference voltage for reading, eliminating the need to program all word lines within the block.

[0050] 4. The controller sends a command to read a specific word line and receives the read data.

[0051] 5. Obtain the read data and compare it with the written data to determine the location of the error.

[0052] 6. Number the error locations and convert the numbers into corresponding bits 0 and 1. Conversion methods include parity, position mapping relationships, etc.

[0053] 7. Output bit stream.

[0054] 3D-NAND flash memory, as a mature non-volatile storage medium, has become the mainstream choice for edge storage chips and is widely used in edge devices and servers. The advantage of using flash memory for true random number generation lies in the fact that it eliminates the need for additional hardware, offering inherent compatibility and low cost. Furthermore, the existing flash memory and controllers at the edge naturally meet its power consumption and environmental adaptability requirements. Using existing commercial 3D-NAND chips, the expected output rate can reach over Mb / s, sufficient to cover the security scenarios of most edge devices such as mobile phones, tablets, cameras, and IoT gateways. Therefore, using 3D-NAND flash memory naturally meets the requirements of miniaturization, low power consumption, and low cost for edge devices, quickly solving the challenge of deploying random number generators at the edge.

[0055] The method of this invention relies entirely on the conventional operations (erasure, programming, and reading) of the flash memory chip itself to generate true random numbers, eliminating the need for additional dedicated random number generation circuits (such as ring oscillators, quantum optical components, etc.), effectively reducing usage costs. For devices already equipped with flash memory, this function can be enabled directly through software or firmware-level logic optimization without modifying the hardware structure. The entire process includes only a few core steps: erasure, programming, reading, comparison, and encoding, and each step is implemented based on standard flash memory instructions and quantifiable parameters. On the one hand, the erasure operation allows the memory cells to return to a unified initial state, laying the foundation for stable extraction of random signals later; on the other hand, the reference voltage is set based on the actual threshold voltage of the memory cell, which can flexibly adapt to different models and aging levels of flash memory chips. Whether it is a new high-performance flash memory or an old flash memory that has been used for a period of time, random numbers can be stably generated by adjusting parameters such as the reference voltage and setting time, demonstrating strong adaptability.

[0056] The method of this invention possesses inherent advantages in resisting attacks. Random numbers are generated in real-time through flash memory operations and are not pre-stored in any storage area, avoiding the security risk of pre-stored random numbers being stolen or tampered with. Error locations are strongly bound to the physical characteristics of the flash memory, making it difficult for attackers to precisely control or predict error locations through external intervention. Even if attackers attempt to disrupt randomness by altering the programming voltage or interfering with ambient temperature, these disturbances will only further exacerbate the disordered fluctuations in the threshold voltage of the storage cells, making error locations even more difficult to predict, thereby enhancing resistance to malicious attacks.

[0057] The method involves programming a portion of the word lines in a target block, including the following steps: programming specified word lines using data, where the number of selected word lines is one or more, but not filling all word lines in the entire block (traditional methods require filling the entire block); the data can be arbitrary; programming is performed line by line, simultaneously programming all storage units within a single word line. This invention effectively improves processing speed.

[0058] Reference Figure 3 , Figure 3 This is a schematic diagram of a flash-based true random number generation system provided in one embodiment of the present invention.

[0059] In one embodiment, a flash-based true random number generation system is applied to the flash-based true random number generation method described above. The system includes a control and data processing module, a cache module, and a flash memory chip. The control and data processing module sends commands to erase a target block of the flash memory chip. The target block includes multiple word lines, each word line including multiple memory cells. The threshold voltage of all memory cells in the target block returns to the lowest erase state. The flash memory chip receives programming instructions and input data from the control and data processing module and performs programming operations on some word lines of the target block based on the programming instructions and input data. Within a set time, the control and data processing module reads some word lines using a reference voltage, where the reference voltage is set based on the threshold voltage of the memory cells. The read data is compared with the input data to obtain the error location. The error locations are numbered and converted into corresponding bits 0 and 1. A bitstream of true random numbers is output based on bits 0 and 1. The bitstream is temporarily stored by the cache module and output by the control and data processing module for secure communication and encrypted computing scenarios of edge devices.

[0060] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0061] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

[0062] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A flash memory based true random number generation method, characterized by, The method comprises the steps of: erasing the target block as a whole, the target block comprising a plurality of word lines, each word line comprising a plurality of memory cells, the threshold voltages of all memory cells in the target block returning to the lowest erased state; obtaining programming instructions and input data, and performing programming operation on part of the word lines of the target block based on the programming instructions and the input data; reading the part of the word lines using a reference voltage within a set time to obtain read data, the reference voltage being set based on the threshold voltage distribution of the memory cell array; comparing the read data with the input data to obtain error code positions; numbering the error code positions and converting the numbers into corresponding bit 0 and bit 1, and outputting a bit stream of true random numbers based on the bit 0 and bit 1.

2. The flash memory based true random number generation method according to claim 1, wherein, The programming operation on part of the word lines of the target block based on the programming instructions and the input data comprises the steps of: A voltage distribution based on Gray code programs portions of the word lines of the target block: Gray code maps n-bit binary values into 2 n different voltage level states in a different way than binary code, with the lowest voltage state being an erase state and the remaining states being program states.

3. The flash memory based true random number generation method of claim 1, wherein, performing programming operation on part of the word lines of the target block, which comprises the steps of: performing programming by word line, and programming part or all of the memory cells in one word line at the same time.

4. The flash memory based true random number generation method of claim 1, wherein, The set time is not more than 10 seconds after the programming operation on part of the word lines of the target block.

5. The flash memory based true random number generation method of claim 1, wherein, The reference voltage is located on the left side or the right side of the target read state of the memory cells.

6. The flash memory based true random number generation method of claim 5, wherein, When the left side reference voltage is used, it is required to be not lower than the threshold voltage of the memory cell with the lowest threshold voltage of the nearest programmed state on the right side after programming minus 0.1V, and different reference voltages are allowed to be selected for each word line. When the right side reference voltage is used, it is required to be not higher than the threshold voltage of the memory cell with the highest threshold voltage of the nearest programmed state on the left side after programming, and different reference voltages are allowed to be selected for each word line.

7. A flash memory based true random number generation system, characterized by, The method is applied to the flash memory based true random number generation method in any one of claims 1 to 6, and comprises: a control and data processing module, a cache module and a flash memory chip, wherein the control and data processing module is used to send a command to erase a target block of the flash memory chip, the target block comprising a plurality of word lines, each word line comprising a plurality of memory cells, and the threshold voltages of all memory cells in the target block returning to the lowest erased state; the flash memory chip obtains programming instructions and input data from the control and data processing module, and performs programming operation on part of the word lines of the target block based on the programming instructions and the input data; within a set time, the control and data processing module reads the part of the word lines using a reference voltage to obtain read data, the reference voltage being set based on the threshold voltage distribution of the memory cell array, and the read data is compared with the input data to obtain error code positions; the error code positions are numbered, and the numbers are converted into corresponding bit 0 and bit 1, and a bit stream of true random numbers is outputted based on the bit 0 and bit 1, the bit stream being temporarily stored by the cache module, and the bit stream being outputted by the control and data processing module and used for secure communication and encryption calculation of a device.

8. A flash memory based true random number generation system according to claim 7, wherein, The flash memory chip is a three-dimensional stacked flash memory (3D NAND Flash) chip.

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