Internally interconnected small supercomputing system, device and cluster

Abstract

The invention provides an internal interconnection and intercommunication small supercomputing system, device and cluster. The system comprises a programmable processing unit, a plurality of high-speed serial interconnection ports, a high-speed data transmission module and a multi-level heterogeneous storage module, the high-speed serial interconnection port is used for connecting the computing unit; the high-speed data transmission module is used for sending the received to-be-processed task to the cache space of the programmable processing unit; the programmable processing unit is used for distributing to-be-processed tasks to the plurality of computing units for task processing based on a preset distribution strategy and receiving task processing results; and the multi-level heterogeneous storage module is used for storing the received task processing result. The programmable processing unit serves as an architecture center, various high-speed interfaces are managed and coordinated in a unified mode, an architecture and a management mechanism for interconnection and intercommunication of internal components of the small supercomputing system are achieved, and the data transmission efficiency is improved. The programmable processing unit distributes tasks to a plurality of computing units for parallel processing, so that the computing efficiency and the computing power utilization rate are improved.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing technology, and in particular to a small supercomputing system, device and cluster with internal interconnection. Background Technology

[0002] A supercomputing system is a computer system composed of multiple high-performance computing nodes connected by a high-speed interconnect network, capable of performing large-scale, complex scientific and engineering calculations. A miniature supercomputing system refers to a simplified or miniaturized version of a supercomputing system, designed to provide high-performance computing capabilities for research, enterprises, or specific fields at a lower cost, with a more compact architecture and flexible deployment.

[0003] Existing mini supercomputing systems typically interconnect internal modules using PCIe. However, this PCIe interconnection method leads to insufficient computing power utilization in distributed training and inference tasks due to communication bandwidth bottlenecks and inefficient scheduling of heterogeneous computing resources. Summary of the Invention

[0004] This invention provides an internally interconnected mini supercomputing system, device, and cluster to improve the computing power utilization and computational efficiency of the mini supercomputing system.

[0005] This invention provides a small supercomputing system with internal interconnection, comprising: a programmable processing unit, multiple high-speed serial interconnect ports, a high-speed data transmission module, and a multi-level heterogeneous storage module; The first end of the high-speed serial interconnect port is connected to the programmable processing unit, and the second end of the high-speed serial interconnect port is used to connect to the computing unit. The high-speed data transmission module is connected to the programmable processing unit and is used to receive the task to be processed and send the task to be processed to the cache space of the programmable processing unit. The programmable processing unit is used to allocate the tasks to be processed in the cache space to multiple computing units for task processing based on a preset traffic distribution strategy, and to receive the task processing results sent by the computing units and send the task processing results to the multi-level heterogeneous storage module. The multi-level heterogeneous storage module is connected to the programmable processing unit and is used to store the received task processing results.

[0006] According to the present invention, in a small supercomputing system with internal interconnection, the programmable processing unit is further configured to: Based on a lightweight neural network inference engine, the operating state of different computing units is predicted, and the prediction results of the operating state of the different computing units are determined. The predicted running status is used to determine the computing unit to execute the next microtask; the task to be processed includes multiple microtasks; the running status includes task load information, power consumption information, and performance status information.

[0007] According to the present invention, in a small supercomputing system with internal interconnection, the programmable processing unit is further configured to: After the task to be processed is stored in the cache space, a copy of the task to be processed is generated and sent to the multi-level heterogeneous storage module so that the multi-level heterogeneous storage module can receive and store the copy data. The copy data is used to resume the calculation process after the task to be processed is interrupted.

[0008] According to the present invention, a small supercomputing system with internal interconnection further includes: a network connection module; The first end of the network connection module is connected to the programmable processing unit, and the second end of the network connection module is used to connect to the external system of the mini supercomputing system. The network connection module is used to communicate with the external system of the mini supercomputing system.

[0009] The interconnected mini supercomputing system provided by the present invention further includes: a fault monitoring module; The fault monitoring module is connected to the programmable processing unit and is used to receive the operating status information of each module in the small supercomputing system obtained by the programmable processing unit, and to monitor each module based on the operating status information. The fault monitoring module is also used for: Based on the operational status information, the operational change trend of each module of the small supercomputing system is determined. If, based on the operational change trend, it is determined that there is an abnormal operation of a module in the supercomputing system, an alarm message is sent to the programmable processing unit. The fault monitoring module is also used to: analyze the operating status information based on a neural network model to determine real-time anomaly information and anomaly prediction information in the mini supercomputing system.

[0010] According to the present invention, in a small supercomputing system with internal interconnection, the fault monitoring module further includes a management communication channel and a data transmission channel; The fault monitoring module is connected to the programmable processing unit through a management communication channel and a data transmission channel. The data transmission channel is used to transmit operating status information, and the management communication channel is used to transmit alarm messages.

[0011] According to the present invention, a small supercomputing system with internal interconnection is provided, wherein the multi-level heterogeneous storage module includes a dynamic random access memory array, a serial configuration memory, and a removable solid-state storage medium. The dynamic random access memory array is used to perform real-time dynamic redundant storage of data with a storage frequency greater than a preset frequency range. The serial configuration memory is used to store data whose storage frequency is within the preset frequency range; The removable solid-state storage medium is used to store data with a storage frequency lower than a preset frequency range; The multi-level heterogeneous storage module is also used for: After receiving the task processing result, the target storage medium for storing the task processing result is determined according to the storage frequency of the task processing result; The task processing results are stored in the target storage medium.

[0012] The interconnected mini supercomputing system provided by the present invention further includes: a heterogeneous acceleration resource expansion interface; The first end of the heterogeneous acceleration resource expansion interface is connected to the programmable processing unit, and the second end of the heterogeneous acceleration resource expansion interface is used to connect to the heterogeneous computing module to build a heterogeneous fusion supercomputing system.

[0013] The present invention also provides a supercomputing device, including an internally interconnected small supercomputing system as described in any of the preceding claims.

[0014] The present invention also provides a supercomputing system cluster, comprising multiple interconnected small supercomputing systems as described in any of the above claims; The computing units of each mini supercomputing system are interconnected, and the high-speed data transmission modules of each mini supercomputing system are interconnected. Multiple mini supercomputing systems in the supercomputing system cluster are used to collaboratively process tasks.

[0015] The interconnected mini-supercomputing system, device, and cluster provided by this invention utilizes a programmable processing unit as the architecture center to uniformly manage and coordinate various high-speed interfaces (ports, storage, data transmission). This achieves the core architecture and coordination management mechanism for interconnecting internal components of the mini-supercomputing system, improving data transmission efficiency. Simultaneously, a high-speed data transmission module rapidly receives tasks and sends them to the programmable processing unit's cache space. The programmable processing unit, based on a preset task allocation strategy, distributes the tasks to multiple computing units for parallel processing via high-speed serial interconnect ports, fully exploiting the potential of computing resources and effectively improving overall computing efficiency and power utilization, thus enabling the mini-supercomputing system to fully realize its performance potential. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the internally interconnected mini supercomputing system provided by the present invention.

[0018] Figure 2 This is a schematic diagram of the task processing flow provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the system structure including a network connection module provided by the present invention.

[0020] Figure 4 This is a schematic diagram of the lightweight communication protocol provided by the present invention.

[0021] Figure 5 This is a schematic diagram of the structure of the multi-level heterogeneous storage module provided by the present invention.

[0022] Figure 6 This is a schematic diagram of the supercomputing system cluster structure provided by the present invention.

[0023] Figure 7 This is a schematic diagram of the structure of a single small supercomputing system provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] Figure 1 This is a schematic diagram of the internally interconnected small supercomputing system provided by the present invention, as shown below. Figure 1 As shown, the device includes a programmable processing unit 101, multiple high-speed serial interconnect ports 102, a high-speed data transmission module 103, and a multi-level heterogeneous storage module 104.

[0026] The first end of the high-speed serial interconnect port is connected to the programmable processing unit, and the second end of the high-speed serial interconnect port is used to connect to the computing unit. The mini supercomputing system, based on multiple computing units connected by multiple high-speed serial interconnect ports, achieves the effect of collaborative computing among multiple computing units.

[0027] Specifically, high-speed serial interconnect ports are used to connect programmable processing units and computing units. These high-speed ports are plug-and-play and can seamlessly accommodate and work with GPU or CPU accelerator cards. Users can flexibly connect multiple identical or heterogeneous computing units to the mini supercomputing system through these ports to form an aggregated computing resource pool, depending on application workload requirements.

[0028] This design directly and efficiently achieves the effect of collaborative computing among multiple computing units, and the overall computing throughput, parallel processing capability and total available video memory of the small supercomputing system are improved linearly or nearly linearly, meeting the needs of high-performance computing, AI training / inference, scientific simulation and other scenarios with extremely high and elastic growth requirements for computing power.

[0029] It should be noted that high-speed serial interconnect ports possess high-speed data transmission capabilities, enabling rapid exchange of large amounts of data between programmable processing units (CPUs) and computing units. This high-speed connection not only reduces data transmission latency but also improves the overall system's computational efficiency. For example, when handling large-scale scientific computing tasks, frequent data transfer between CPUs and computing units is required. High-speed serial interconnect ports ensure that data arrives at its destination promptly and accurately, avoiding computational stagnation caused by data transmission bottlenecks.

[0030] The high-speed data transmission module is connected to the programmable processing unit and is used to receive the task to be processed and send the task to be processed to the cache space of the programmable processing unit.

[0031] Specifically, the high-speed data transmission module supports asymmetric data compression / encryption pipelines. It serves as the interface between the mini-supercomputing system and external data sources. It receives tasks from various external data sources. The high-speed data transmission module has multiple data receiving interfaces, adaptable to different data formats and protocols, ensuring accurate reception of various types of tasks.

[0032] In addition, the high-speed data transmission module can be programmed with custom network protocol stacks (such as private RDMA protocol and low-latency transaction message parser) to achieve nanosecond-level packet filtering and forwarding.

[0033] The high-speed data transmission module enables high-speed data exchange between computing nodes and multi-level heterogeneous storage modules within the small supercomputing system during internal communication. It supports distributed training and inference tasks in the computing unit cluster and also supports dynamic allocation of communication traffic to improve communication efficiency.

[0034] In external communication, it can connect to external networks, facilitating system expansion. Multiple small supercomputing systems can be connected to form a large-scale cluster through the high-speed data transmission module. The high-speed data transmission module incorporates network flow control algorithms and data encryption technology to enhance the security and stability of data transmission. It supports flexible and varied network topology configurations to adapt to different application scenarios and needs. Optionally, the high-speed data transmission module can support photoelectric signal conversion and high-speed photoelectric collaborative transmission, providing a high-speed data transmission channel for small supercomputing systems to meet the needs of large data volumes. In AI training, it rapidly transmits model parameters and training samples. This module utilizes multi-channel, high-bandwidth transmission technology combined with cutting-edge signal processing algorithms to significantly improve transmission efficiency and reliability. It supports hot-swapping, greatly facilitating system expansion and maintenance.

[0035] Optionally, in order to effectively filter out high-frequency noise and harmonic interference caused by photoelectric conversion and high-speed signals, a ferrite bead can be deployed at the power supply position of the high-speed data transmission module, and two capacitors of different capacitance values ​​can be connected in parallel at each end to form a filter network.

[0036] Ferrite beads are passive components made of ferrite material. They exhibit high resistance at high frequencies, essentially acting as a resistor whose impedance changes with frequency. When high-frequency noise is present in a circuit, ferrite beads generate significant impedance to these high-frequency signals, converting the noise energy into heat and preventing it from propagating through power lines to high-speed data transmission modules or other circuit components. Different types of ferrite beads have different frequency characteristics. Appropriate beads can be selected based on specific needs to suppress high-frequency noise in specific frequency bands, such as filtering out high-frequency interference generated during photoelectric conversion.

[0037] Specifically, the circuit can use two different capacitance values: 100nF and 10uF. The 100nF capacitor has low equivalent series resistance and inductance, maintaining good capacitance characteristics even at higher frequencies. It is primarily used to filter high-frequency noise, quickly responding to changes in high-frequency signals and bypassing high-frequency noise to ground. The 10uF capacitor has a larger capacitance and provides better filtering in the low-frequency range. It can filter out some relatively low-frequency harmonic interference and power fluctuations, providing a relatively stable power supply for high-speed data transmission modules.

[0038] A low-pass filter network is formed by combining ferrite beads and capacitors. This circuit allows low-frequency signals (such as normal power signals and low-frequency data signals) to pass through, while presenting high impedance to filter out high-frequency noise and harmonic interference. Multiple combinations of ferrite beads and capacitors may be used in the circuit to form a multi-stage filtering structure, further enhancing the suppression capability for noise of different frequencies. This ensures that the high-speed data transmission module receives a clean and stable power supply, reduces the impact of noise on high-speed signal transmission, and improves the reliability and stability of data transmission.

[0039] After receiving a task to be processed, the high-speed data transmission module sends the task to the buffer space of the programmable processing unit. The buffer space temporarily stores the task to be processed.

[0040] Specifically, the processing flowchart for the tasks to be processed can be as follows: Figure 2 As shown in the task processing flowchart provided by the present invention, after receiving the task to be processed sent to the cache space by the high-speed data transmission module, the programmable processing unit reasonably allocates the task to be processed to multiple computing units for task processing based on a preset diversion strategy.

[0041] The preset task allocation strategy can comprehensively allocate tasks based on factors such as the performance characteristics of the computing units, the current load, and the type and complexity of the tasks to be processed. For example, for computationally intensive tasks, the programmable processing unit will prioritize allocating them to computing units with stronger computing capabilities; while for logic control intensive tasks, they may be allocated to other computing units. This intelligent task allocation method can fully leverage the strengths of each computing unit, improving the overall system's computational efficiency and resource utilization.

[0042] Specifically, different models of computing units differ in their computing capabilities, such as the number of cores, clock frequency, and architecture. For tasks with extremely high computational demands and high requirements for parallel computing, such as matrix operations in large-scale deep learning training, these tasks are preferentially assigned to the computing units with the strongest computing capabilities. For example, in a small supercomputing system with multiple computing units of different models, complex neural network training tasks are assigned to high-end computing units with more computing cores and higher memory bandwidth.

[0043] Different computing unit architectures are optimized for specific types of computation. For example, some computing unit architectures are extremely efficient at handling single-precision floating-point operations, while others may have advantages in handling half-precision floating-point operations or operations on specific instruction sets. For scientific simulation tasks that require a large number of single-precision floating-point calculations, these tasks should be assigned to computing units corresponding to computing unit architectures that excel in single-precision computation.

[0044] The system monitors the load metrics of each computing unit in real time, such as computing unit utilization, video memory usage, and task queue length. When a new task arrives, it prioritizes allocating it to the computing unit with the lightest load. For example, if monitoring tools detect that a certain computing unit has a short task queue and low video memory usage, the new image rendering task will be assigned to that computing unit to avoid situations where some computing units are overloaded while others are idle.

[0045] By setting a load threshold, when the load of a computing unit in the programmable processing unit exceeds the threshold, some tasks are automatically migrated to other computing units with lighter loads. For example, when the video memory utilization rate of a computing unit exceeds 90%, some subsequent tasks with lower video memory requirements are allocated to other computing units to ensure the overall stability of the small supercomputing system.

[0046] The tasks are categorized and assigned based on their computational patterns. For tasks such as graphics rendering and video encoding, which typically require significant parallel computing and graphics processing capabilities, priority is given to computing units with excellent graphics processing and parallel computing performance. However, for tasks involving complex algorithms and logical judgments, such as rule-based reasoning systems, if a computing unit has an advantage in related computations (e.g., by accelerating specific logical calculations), it can also be assigned, but its collaborative efficiency with other computing units must be considered.

[0047] The complexity of a task can be evaluated, and can be measured by factors such as computational load, data size, and algorithm complexity. High-complexity tasks, such as large-scale physics simulations, need to be assigned to computing units with strong computing power and large amounts of video memory; low-complexity tasks, such as simple image filtering, can be assigned to ordinary computing units with lighter workloads.

[0048] After completing the task processing, the computing unit sends the task processing results back to the programmable processing unit. Upon receiving these results, the programmable processing unit sends the task processing results to the multi-level heterogeneous storage module for storage.

[0049] The multi-level heterogeneous storage module is connected to the programmable processing unit and is used to receive the task processing results sent by the programmable processing unit and store the received task processing results.

[0050] The interconnected mini-supercomputing system provided by this invention uses a programmable processing unit as its core architecture, deeply integrating high-speed serial interconnect ports, high-speed data transmission modules, and multi-level heterogeneous storage modules to construct a hardware-level reconfigurable intelligent acceleration platform. Users can dynamically define the underlying functional logic of each module through the hardware programmable characteristics of the programmable processing unit, achieving full-stack customized acceleration of data flow, control flow, and computation flow.

[0051] Optionally, a supercomputing system cluster can be built based on multiple small supercomputing systems. The constructed supercomputing system cluster can be a large-scale inference and training system scalable to the kilocalorie level of computing units. To achieve this goal, the architecture adopts an innovative layered interconnection architecture: at the basic layer, namely the small supercomputing system with the aforementioned internal interconnection communication system and devices, four computing units are coupled through ultra-high-speed, low-latency computing unit tight interconnection technology. Each such unit is essentially a highly integrated, performance-optimized computing core module.

[0052] At a higher level, multiple such small supercomputing systems are efficiently interconnected and collaborated through high-bandwidth, low-latency cluster-level links. Simultaneously, the computing units within each small supercomputing system can be tightly coupled through the aforementioned computing unit interconnection technology. For example, placing two of these small supercomputing systems in a single server enables the interconnection of eight computing unit cards; placing eight servers in a rack expands to 64 cards; four racks create a medium-to-large supercomputing unit with 256 cards, and so on. This architectural design fundamentally breaks through the rigid limitations of a single physical server node in terms of the number of computing units it can accommodate, power supply, heat dissipation, and interconnection bandwidth. This makes it possible to integrate hundreds or thousands of computing units into a unified, programmable, giant pool of computing resources, ultimately achieving the strategic goal of building a massive computing unit cluster with thousands of cards.

[0053] Based on the above architecture, the advantages are: The high-speed serial interconnect port bus has high bandwidth, which, combined with the scheduling of programmable processing units, can fully leverage this advantage to meet the needs of large-scale data transmission by computing units, thereby improving training and inference speeds. Simultaneously, the mini supercomputer supports photoelectric signal conversion and collaborative transmission, enhancing transmission efficiency and reliability.

[0054] Compared to traditional parallel buses, the solution of this invention has lower latency, which is beneficial for improving the real-time performance of deep learning tasks.

[0055] By building a computing unit inference and training system with a programmable processing unit as the core, existing hardware resources can be fully utilized and investment costs can be reduced.

[0056] It adopts a variety of high-speed interfaces, and the internal high-speed data exchange can support distributed training and inference of computing unit clusters, while the external network connection facilitates system expansion and cluster construction.

[0057] The innovative layered interconnect architecture (tight coupling within the small supercomputing system + cluster-level network interconnection between systems) effectively overcomes the physical limitations of a single node (number of computing units, power supply, heat dissipation, interconnection bandwidth), providing a feasible solution for building a kilocalorie-level ultra-large-scale computing unit inference and training cluster.

[0058] The interconnected mini-supercomputing system provided by this invention uses a programmable processing unit as the architecture center to uniformly manage and coordinate various high-speed interfaces (ports, storage, data transmission), realizing the core architecture and coordination management mechanism for the interconnection of internal components of the mini-supercomputing system, thereby improving data transmission efficiency. Simultaneously, the high-speed data transmission module quickly receives tasks to be processed and sends them to the cache space of the programmable processing unit. The programmable processing unit, according to a preset task allocation strategy, distributes the tasks to multiple computing units for parallel processing via high-speed serial interconnect ports, fully exploiting the potential of computing resources, effectively improving overall computing efficiency and computing power utilization, and enabling the mini-supercomputing system to fully realize its performance.

[0059] In one embodiment, the programmable processing unit is further configured to: Based on a lightweight neural network inference engine, the operating state of different computing units is predicted, and the prediction results of the operating state of the different computing units are determined. The predicted running status is used to determine the computing unit to execute the next microtask; the task to be processed includes multiple microtasks; the running status includes task load information, power consumption information, and performance status information.

[0060] The programmable processing unit integrates a lightweight neural network inference engine, which is used to analyze and predict the task load, power consumption and performance status information of different computing units in real time, so as to predict the operating status of different computing units.

[0061] Based on the determined operational status prediction results, the programmable processing unit realizes dynamic and adaptive task pipeline orchestration, breaks down a large task into micro-task flows, and makes real-time decisions on which computing unit should send the next micro-task to complete it with the best energy efficiency ratio, thus realizing true integrated scheduling of perception and computing.

[0062] In one embodiment, the programmable processing unit is further configured to: After the task to be processed is stored in the cache space, a copy of the task to be processed is generated and sent to the multi-level heterogeneous storage module so that the multi-level heterogeneous storage module can receive and store the copy data. The copy data is used to resume the calculation process after the task to be processed is interrupted.

[0063] After the programmable processing unit generates the copy data, it sends the copy data to the multi-level heterogeneous storage module, so that the multi-level heterogeneous storage module stores the copy data.

[0064] If a task is interrupted during execution due to an unexpected event, such as a system failure or network fluctuation, the copy data in the multi-level heterogeneous storage module can be used to quickly restore the computation state before the interruption, restart the task processing flow, avoid starting the computation from scratch, greatly save time and resources, and improve the overall stability of the system and the efficiency of task processing.

[0065] Optionally, the programmable processing unit (PCU) can not only generate data copies but also create a fully synchronized digital twin computing process for each computing task on another idle computing unit. While the master unit performs computation, the PCU continuously compares the computing status checkpoints of the master and slave units. In the event of a master unit failure or a predicted failure (such as overheating), the PCU can seamlessly switch the computing task to the digital twin unit within milliseconds, achieving zero-perceptible fault switching and 100% computing task reliability.

[0066] Optionally, the high-speed data scheduler built into the programmable processing unit can distribute data according to a preset distribution strategy. The main path within the programmable processing unit is used to send the original tasks to be processed into the computing unit for preprocessing (such as quantization / sparserization). The bypass path within the programmable processing unit: after compressing the copy data, it is temporarily stored in a multi-level heterogeneous storage module via a high-speed data transmission module.

[0067] Heterogeneous computing acceleration: The programmable processing unit uses a pipelined parallel architecture to execute customized operators (such as gradient compression / custom activation functions), while calling external ASIC (Application-Specific Integrated Circuit) chips to handle specific computing loads through the heterogeneous acceleration resource expansion interface.

[0068] In one embodiment, it further includes: a network connectivity module; The first end of the network connection module is connected to the programmable processing unit, and the second end of the network connection module is used to connect to the external system of the mini supercomputing system. The network connection module is used to communicate with the external system of the mini supercomputing system.

[0069] A schematic diagram of the system architecture including the network connection module can be shown as follows: Figure 3 The system structure diagram including the network connection module provided by this invention is shown. The first end of the network connection module is connected to the programmable processing unit, and the second end of the network connection module is used to connect to the outside of the small supercomputing system.

[0070] The network connection module in the mini supercomputing system is mainly responsible for establishing stable and efficient Ethernet network communication, realizing data interaction between the mini supercomputing system and the outside world (such as monitoring stations), especially transmitting the real-time operating status information collected by the intelligent fault monitoring system to the administrator console.

[0071] The universal network connectivity module has the ability to automatically detect and configure network parameters, and can quickly establish a network connection with external systems based on preset network settings or dynamically acquired network information (such as via DHCP). It supports multiple network interface standards, such as common Ethernet interfaces and fiber optic interfaces, to adapt to different network environments and transmission requirements.

[0072] When sending data, this module encapsulates the hardware status information collected by the intelligent fault monitoring system, adding necessary headers and checksums according to Ethernet communication protocols (such as the TCP / IP protocol suite) to ensure the integrity and accuracy of the data during network transmission. Upon receiving instructions or data from the monitoring system, the module parses the data, extracts valid information, and transmits it to the relevant components within the mini-supercomputing system.

[0073] It supports multiple communication protocols to meet different application scenarios and needs. For example, for the transmission of hardware status information with high real-time requirements, the UDP protocol can be used to reduce data transmission latency; while for command interaction that requires reliable data transmission, the TCP protocol is used to ensure accurate data transmission.

[0074] In one embodiment, it further includes: a fault monitoring module; The fault monitoring module is connected to the programmable processing unit and is used to receive the operating status information of each module in the small supercomputing system obtained by the programmable processing unit, and to monitor each module based on the operating status information. The fault monitoring module is also used for: Based on the operational status information, the operational change trend of each module of the small supercomputing system is determined. If, based on the operational change trend, it is determined that there is an abnormal operation of a module in the supercomputing system, an alarm message is sent to the programmable processing unit. The fault monitoring module is also used to: analyze the operating status information based on a neural network model to determine real-time anomaly information and anomaly prediction information in the mini supercomputing system.

[0075] Adding a fault monitoring module to the mini supercomputing system and connecting it to the programmable processing unit (PLU) significantly improves the system's stability and reliability. The PLU collects operational status information from each module and transmits it to the fault monitoring module. Based on the received information, the fault monitoring module monitors each module in real time. Once an anomaly is detected in a module, such as overheating or data transmission errors, it can quickly locate the fault, issue timely alarms, and provide accurate information to maintenance personnel for rapid repair, ensuring the continuous and stable operation of the mini supercomputing system and reducing losses caused by faults.

[0076] The fault monitoring module has a dedicated management communication channel, separate from the data transmission channel, ensuring efficient transmission of management information and avoiding data congestion. Simultaneously, its communication process employs methods such as... Figure 4 The lightweight communication protocol shown in the schematic diagram of the lightweight communication protocol provided by this invention has a smaller RAM footprint, increased payload, and reduces the latency and bandwidth requirements of management information transmission, thereby improving management efficiency.

[0077] The frame structure of this lightweight communication protocol consists of multiple fields, in the following order: a synchronization header (24 bits), a preamble (the preamble is used here for analysis based on the synchronization header and subsequent structures; minor errors are assumed in the description, but the overall structure includes preamble and checksum components), a control field, an address field, a payload, a CRC24 checksum, and a frame end marker. This structure ensures data synchronization, correct addressing, effective data delivery, and integrity verification during transmission.

[0078] The synchronization header is primarily used to establish synchronization between the receiver and transmitter, helping the receiver identify the start of a data frame. Due to its 4-bit fault-tolerant design, the reliability of synchronization is enhanced, ensuring the receiver accurately identifies the frame start position even during transmission, despite noise interference or signal distortion. Through a specific bit pattern, the receiver determines the arrival of a data frame upon detecting a bit sequence matching the synchronization header characteristics and begins subsequent reception and decoding.

[0079] The 4-digit version number in the control field identifies the version number of the communication protocol. Different versions may differ in functionality, data format, etc. The version number enables the receiving end to correctly parse the data, ensuring the compatibility and scalability of the protocol.

[0080] The 4-bit type field in the control field indicates the type of data frame, such as whether it is a data frame, control frame, or management frame. Different types of frames differ in their processing methods and functions, and the receiving end performs corresponding processing operations based on the type field.

[0081] The 4-bit flags in the control field can be used to set various flag information, such as whether an acknowledgment is required, data priority, etc. These flags provide greater flexibility and control over communication.

[0082] The 4-digit sequence number in the control field is used to number data frames, helping the receiving end to identify the frame order and detect any frame loss or duplication. During data transmission, the sequence number ensures the correct ordering and integrity of the data.

[0083] The address field is used to specify the sender and receiver addresses of the data frame. This field can be in the form of dual 32-bit addresses or a single 64-bit device ID, which can flexibly adapt to different network topologies and device addressing requirements.

[0084] The payload carries the actual data that needs to be transmitted. This part occupies a large proportion of the frame structure and can accommodate a large amount of valid information to meet the data transmission requirements of different application scenarios. The data format in the payload depends on the specific application and can be various types of data, such as data collected by sensors, control commands, etc.

[0085] The CRC24 checksum is used to detect whether errors have occurred during data transmission. The sending end calculates the CRC24 checksum based on the payload and other data, and appends it to the data frame. Upon receiving the data frame, the receiving end performs the same CRC24 calculation and compares the result with the received checksum. If they match, it means no errors occurred during data transmission; if they do not match, it indicates that the data may have been interfered with or a transmission error has occurred. The receiving end can then request the sending end to retransmit the data to ensure its accuracy.

[0086] The end-of-frame (EOP) flag is used to indicate the end of a data frame. The receiver detects the EOP flag to determine that the reception of the current data frame is complete and prepares to receive the next frame. A clear EOP flag helps the receiver correctly segment data frames, avoids data confusion and incorrect parsing, and improves the stability and reliability of communication.

[0087] Each module of the mini supercomputing system, such as the computing unit, multi-level heterogeneous storage module, and network module, generates operational status information. For example, the computing unit's utilization rate, memory usage rate, and temperature; the multi-level heterogeneous storage module's disk read / write speed and remaining space; and the high-speed network connection module's bandwidth utilization rate and packet loss rate. This information is collected in real-time and accurately through an intelligent fault monitoring system.

[0088] The collected data is often scattered and in various formats, requiring integration and preprocessing. Data from different modules and of different types is converted and normalized according to a unified standard to facilitate subsequent analysis and processing.

[0089] The collected operational status information is arranged chronologically to form time series data. Statistical methods and data analysis techniques, such as moving averages and exponential smoothing, are used to analyze this time series data to determine the changing trends of the operational status of each module. For example, by calculating the moving average of the computing unit utilization rate over a period of time, the long-term trend of computing unit load can be observed; exponential smoothing can be used to predict changes in computing unit utilization rate in the near future.

[0090] Based on the design requirements and historical operating data of the mini supercomputing system, reasonable thresholds and benchmarks can be set for the operating status indicators of each module. For example, a safe threshold can be set for the temperature of the computing unit; when the temperature exceeds this threshold, the computing unit is considered to be at risk of overheating. For memory utilization, a normal range can be set; when the utilization exceeds this range, it may indicate that memory resources are strained.

[0091] By combining operational trends with set thresholds and benchmarks, it is possible to determine whether a module is experiencing operational anomalies. If a module's operational status indicators consistently deviate from the normal trend over a period of time and approach or exceed set thresholds, it can be determined that the module is experiencing operational anomalies. For example, if the utilization rate of a computing unit rises sharply in a short period of time and exceeds the threshold of the normal operating range, while the temperature also rises accordingly, it can be determined that the computing unit may be experiencing abnormal load or malfunction.

[0092] To avoid misjudgment based on a single indicator, multiple operational status indicators can be considered comprehensively for anomaly detection. For example, in addition to focusing on computing unit utilization, indicators such as memory usage and disk I / O latency should also be considered to comprehensively assess the overall operational status of the system. If multiple indicators show abnormal changes simultaneously, it can more accurately determine whether a module is experiencing operational anomalies.

[0093] Once a module is identified as having an operational anomaly, an alarm message is immediately generated. The alarm message should include key information such as the identifier of the abnormal module, the abnormal operational status indicators, and the time the anomaly occurred. After generating the alarm message, it is fed back to the programmable processing unit.

[0094] Upon receiving an alarm message, the programmable processing unit (PPU) will respond according to a pre-defined program. For example, the PPU can trigger corresponding fault handling mechanisms, such as adjusting the allocation of computing tasks, transferring some tasks from the malfunctioning module to other normal modules; or sending more detailed alarm information to the administrator console, notifying the administrator to take timely measures for fault diagnosis and repair.

[0095] The fault monitoring module is also used to identify real-time anomalies and predict anomalies in the mini supercomputing system when introducing spiking neural networks or other neuromorphic computing models to analyze massive amounts of operational status information. It can not only detect anomalies that have already occurred, but also use intelligent algorithms to back up data in advance to prevent future module failures and perform self-healing operations such as frequency reduction, task migration, and initiating backup data.

[0096] In one embodiment, the fault monitoring module further includes a management communication channel and a data transmission channel; The fault monitoring module is connected to the programmable processing unit through a management communication channel and a data transmission channel. The data transmission channel is used to transmit operating status information, and the management communication channel is used to transmit alarm messages.

[0097] The data transmission channel is responsible for transmitting the operating status information of each module in the mini supercomputing system, ensuring that the real-time operating data of each module, such as the load of the computing unit and the read / write status of the multi-level heterogeneous storage module, can be transmitted to the fault monitoring module in a timely and accurate manner.

[0098] When the fault monitoring module determines that there is a module malfunction in the system based on the operating status information, it will send an alarm message to the programmable processing unit through the management communication channel.

[0099] The dual-channel design separates data transmission from alarm management, avoiding information interference and greatly improving the efficiency and reliability of system fault monitoring and handling, thus ensuring the stable operation of the mini supercomputing system.

[0100] In one embodiment, the multi-level heterogeneous storage module includes a dynamic random access memory array, a serially configured memory, and a removable solid-state storage medium. The dynamic random access memory array is used to perform real-time dynamic redundant storage of data with a storage frequency greater than a preset frequency range. The serial configuration memory is used to store data whose storage frequency is within the preset frequency range; The removable solid-state storage medium is used to store data with a storage frequency lower than a preset frequency range; The multi-level heterogeneous storage module is also used for: After receiving the task processing result, the target storage medium for storing the task processing result is determined according to the storage frequency of the task processing result; The task processing results are stored in the target storage medium.

[0101] The multi-level heterogeneous storage module is built on a multi-layer heterogeneous storage architecture, and a detailed structural diagram can be seen as follows: Figure 5The structural diagram of the multi-level heterogeneous storage module provided by this invention is shown. Specifically, it includes: a dynamic random access memory array, which achieves hardware-level expansion of the physical address space between storage units through a bidirectional parallel interconnect bus, forming a unified addressing aggregated memory pool with a capacity that can be elastically expanded to four times that of a single device; a non-volatile storage coordination layer, integrating a serial configuration memory and a removable solid-state storage medium, constructing a three-level storage hotspot migration mechanism: high-frequency data (data with a storage frequency greater than a preset frequency range) resides in the dynamic random access memory array, mid-frequency data (data with a storage frequency within the preset frequency range) is cached in the serial configuration memory, and low-frequency data (data with a storage frequency less than the preset frequency range) is archived in the removable solid-state storage medium; and a hardware pass-through access channel, enabling the programmable processing unit to bypass the central processing unit and directly schedule heterogeneous storage resources, reducing data access latency to approximately 30% of traditional solutions.

[0102] Besides storing data according to frequency, high-frequency data can also refer to data collected or generated within a very short time interval. This data is characterized by very dense data points, rapid changes, large data volume, and potentially high noise levels. Low-frequency data can refer to data collected or generated within a relatively long time interval. This data is characterized by sparser data points, relatively slow changes, small data volume, and is typically smoother. The non-volatile storage coordination layer can be used to store configuration data for the programmable processing unit.

[0103] After receiving the task processing results, the multi-level heterogeneous storage module determines the target storage medium for storing the task processing results based on the storage frequency of the results. The target storage medium can be one of the following: a dynamic random access memory array, a serial configuration memory, or a removable solid-state storage medium.

[0104] If the task processing result is stored at a high frequency, the target storage medium is determined to be a dynamic random access memory array; if the task processing result is stored at a medium frequency, the target storage medium is determined to be a serial configuration memory; if the task processing result is stored at a low frequency, the target storage medium is determined to be a removable solid-state storage medium.

[0105] In one embodiment, it further includes: a heterogeneous acceleration resource extension interface; The first end of the heterogeneous acceleration resource expansion interface is connected to the programmable processing unit, and the second end of the heterogeneous acceleration resource expansion interface is used to connect to the heterogeneous computing module to build a heterogeneous fusion supercomputing system.

[0106] The heterogeneous acceleration resource expansion interface can be used to connect various functional modules (such as data acquisition modules, signal processing modules, etc.), providing rich functional expansion capabilities for small supercomputing systems and allowing users to flexibly configure system functions according to different application needs. The heterogeneous acceleration resource expansion interface can provide open programmable pin mapping, allowing users to define the physical layer communication protocol of proprietary accelerators (such as AI operator cores, cryptographic engines), and achieve seamless access to heterogeneous resources.

[0107] This extended interface employs a reconfigurable connection method, enabling seamless integration of heterogeneous computing modules with the mini supercomputing system to form a heterogeneous converged supercomputing system. Through optimized interface design, not only is data transmission rate improved, but compatibility is also enhanced, ensuring stable and efficient collaborative operation of various functional modules.

[0108] The present invention also provides a supercomputing device, including an internally interconnected small supercomputing system as described in any of the preceding claims.

[0109] This invention also provides a supercomputing system cluster, such as Figure 6 The supercomputing system cluster structure diagram provided by this invention is shown. This supercomputing system cluster is composed of multiple small supercomputing systems as described above. The structural diagram of a single small supercomputing system can be shown as follows... Figure 7 The structural schematic diagram of a single small supercomputing system provided by this invention is shown.

[0110] Each small supercomputing system uses GPUs as computing units, and the computing units of each small supercomputing system are interconnected. The high-speed data transmission modules of each small supercomputing system are interconnected, and multiple small supercomputing systems in the supercomputing system cluster are used to collaboratively process tasks.

[0111] Each module in the mini supercomputing system is deeply coupled with the programmable processing unit, forming a closed-loop acceleration ecosystem centered on the programmable processing unit: Network connectivity module: Enables small supercomputing systems with programmable processing units to achieve short-to-medium distance, medium-to-high speed network communication in a standard, reliable, and cost-effective manner, greatly expanding the application scope of supercomputing systems in embedded systems, network devices, industrial control, and edge computing. The network connectivity module can also receive alarms from fault monitoring systems (such as ECC error codes) and trigger circuit breaker mechanisms in adjacent systems via out-of-band (OOB) management networks.

[0112] High-speed data transmission module: This module brings powerful high-speed interconnect capabilities and data throughput to the programmable processing unit (PPU), greatly expanding its application scope. It enables the PPU to process, generate, and transmit massive data streams, becoming a core engine for building high-performance networks, real-time processing systems, distributed computing architectures, and data center acceleration applications. The high-speed data transmission module serves as an ultra-low-latency data channel between the PPU and external storage / heterogeneous systems. It receives the pre-processed training intermediate states (checkpoints / gradient snapshots) from the PPU. During multi-system joint training: PPU-A transmits the fragmented model parameters to the adjacent PPU-B. Users can customize a lightweight retransmission protocol, reducing protocol overhead by approximately 90% compared to conventional TCP / IP.

[0113] Other functions can also be customized (transmit compressed gradient tensors (200GB / s), receive neighbor node weight fragments, and back up data fragments from failed nodes). Heterogeneous acceleration resource expansion interface: provides a protocol-transparent interconnect backbone (such as CCIX / OpenCAPI); enables hardware resource pooling and function combination.

[0114] The constructed supercomputing system cluster can be a massively scaled inference and training system with computing units scalable to the kilocalorie level. To achieve this goal, the architecture adopts an innovative layered interconnect architecture: at the base layer, which is a small supercomputing system with the aforementioned internal interconnection communication system and devices, four computing units are coupled together through ultra-high-speed, low-latency computing unit tight interconnection technology. Each such unit is essentially a highly integrated, performance-optimized computing core module.

[0115] At a higher level, multiple such small supercomputing systems are efficiently interconnected and collaborated through high-bandwidth, low-latency cluster-level links. Simultaneously, the computing units within each small supercomputing system can be tightly coupled through the aforementioned computing unit interconnection technology. For example, placing two of these small supercomputing systems in a single server enables the interconnection of eight computing unit cards; placing eight servers in a rack expands to 64 cards; four racks create a medium-to-large supercomputing unit with 256 cards, and so on. This architectural design fundamentally breaks through the rigid limitations of a single physical server node in terms of the number of computing units it can accommodate, power supply, heat dissipation, and interconnection bandwidth. This makes it possible to integrate hundreds or thousands of computing units into a unified, programmable, giant pool of computing resources, ultimately achieving the strategic goal of building a massive computing unit cluster with thousands of cards.

[0116] Based on the above architecture, the advantages are: The high-speed serial interconnect port bus has high bandwidth, which, combined with the scheduling of programmable processing units, can fully leverage this advantage to meet the needs of large-scale data transmission by computing units, thereby improving training and inference speeds. Simultaneously, the mini supercomputer supports photoelectric signal conversion and collaborative transmission, enhancing transmission efficiency and reliability.

[0117] Compared to traditional parallel buses, the solution of this invention has lower latency, which is beneficial for improving the real-time performance of deep learning tasks.

[0118] Multi-layer heterogeneous storage architecture enables hardware-level expansion and intelligent hierarchical data storage, significantly improving storage capacity and data access speed, and optimizing storage resource utilization.

[0119] By building a computing unit inference and training system with a programmable processing unit as the core, existing hardware resources can be fully utilized and investment costs can be reduced.

[0120] It adopts a variety of high-speed interfaces, and the internal high-speed data exchange can support distributed training and inference of computing unit clusters, while the external network connection facilitates system expansion and cluster construction.

[0121] This mini supercomputing system is small in size, approximately 0.07 square meters, making it easy to deploy flexibly. Furthermore, both the high-speed data transmission module and the high-speed serial interconnect port support hot-swapping, allowing users to easily replace or add computing unit accelerators as needed.

[0122] The innovative layered interconnect architecture (tight coupling within the small supercomputing system + cluster-level network interconnection between systems) effectively overcomes the physical limitations of a single node (number of computing units, power supply, heat dissipation, interconnection bandwidth), providing a feasible solution for building a kilocalorie-level ultra-large-scale computing unit inference and training cluster.

[0123] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0124] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented through both software and hardware platforms. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, is the construction of a computing architecture based on a programmable processing unit. This architecture uses the programmable processing unit as the central hub to uniformly manage and coordinate various high-speed interfaces (ports, storage, data transmission), realizing the core architecture and coordination management mechanism for interconnecting internal components of a small supercomputing system, thereby improving data transmission efficiency.

[0125] The high-speed data transmission module quickly receives the tasks to be processed and sends them to the cache space of the programmable processing unit. The programmable processing unit distributes the tasks to multiple computing units for parallel processing through the high-speed serial interconnect port according to the preset distribution strategy, fully tapping the potential of computing resources, effectively improving the overall computing efficiency and computing power utilization, and enabling the performance of the small supercomputing system to be fully utilized.

[0126] Furthermore, based on multiple small supercomputing systems, supercomputing system clusters can be constructed. These clusters enable the integration of hundreds or thousands of computing units into a unified, programmable, massive pool of computing resources, ultimately achieving the strategic goal of building a kilocalorie-level ultra-large-scale computing unit cluster.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An internally interconnected small supercomputing system, characterized by, The system comprises: a programmable processing unit, a plurality of high-speed serial interconnection ports, a high-speed data transmission module, and a multi-level heterogeneous storage module; a first end of the high-speed serial interconnection port is connected to the programmable processing unit, and a second end of the high-speed serial interconnection port is used to connect a computing unit; the high-speed data transmission module is connected to the programmable processing unit, used to receive a to-be-processed task, and send the to-be-processed task to a cache space of the programmable processing unit; the programmable processing unit is used to distribute the to-be-processed task in the cache space to a plurality of computing units for task processing based on a preset shunting strategy, receive task processing results sent by the computing units, and send the task processing results to the multi-level heterogeneous storage module; the multi-level heterogeneous storage module is connected to the programmable processing unit, used to store the received task processing results.

2. The internally interconnected small supercomputing system of claim 1, wherein, The programmable processing unit is further used to: based on a lightweight neural network inference engine, predict running states of different computing units, and determine running state prediction results of the different computing units; the running state prediction results are used to determine a computing unit for executing a next micro task; the to-be-processed task comprises a plurality of micro tasks; and the running state comprises task load information, power consumption information, and performance state information.

3. The internally interconnected small supercomputing system of claim 1, wherein, The programmable processing unit is further used to: after the to-be-processed task is stored in the cache space, generate copy data of the to-be-processed task, and send the copy data to the multi-level heterogeneous storage module, so that the multi-level heterogeneous storage module stores the copy data after receiving the copy data; the copy data is used to resume a computing process after interruption of to-be-processed task execution.

4. The internally interconnected small supercomputing system of claim 1, wherein, Further comprising: a network connection module; a first end of the network connection module is connected to the programmable processing unit, and a second end of the network connection module is used to connect an external system of the small supercomputing system; the network connection module is used to communicate with the external system of the small supercomputing system.

5. The internally interconnected small supercomputing system of claim 1, wherein, Further comprising: a fault monitoring module; the fault monitoring module is connected to the programmable processing unit, used to receive running state information of each module in the small supercomputing system acquired by the programmable processing unit, and monitor the each module based on the running state information; the fault monitoring module is further used to: based on the running state information, determine a running change trend of each module in the small supercomputing system, and send an alarm message to the programmable processing unit when it is determined based on the running change trend that there is an abnormal running condition of a module in the supercomputing system; the fault monitoring module is further used to: based on a neural network model, analyze the running state information, and determine real-time abnormal information and abnormal prediction information in the small supercomputing system.

6. The small supercomputing system of internal interconnection and interworking according to claim 5, wherein, The fault monitoring module further comprises a management communication channel and a data transmission channel; the fault monitoring module is connected to the programmable processing unit through the management communication channel and the data transmission channel; the data transmission channel is used to transmit the running state information, and the management communication channel is used to transmit the alarm message.

7. The internally interconnected small supercomputing system of claim 1, wherein, The multi-level heterogeneous storage module comprises a dynamic random access memory array, a serial configuration memory, and a removable solid-state storage medium; The dynamic random access memory array is configured to store data with a storage frequency greater than a preset frequency range in real time and dynamically redundantly; The serial configuration memory is configured to store data with a storage frequency within the preset frequency range; The removable solid-state storage medium is configured to store data with a storage frequency less than the preset frequency range; The multi-level heterogeneous storage module is further configured to: After receiving the task processing result, determine a target storage medium for storing the task processing result according to a storage frequency of the task processing result; and store the task processing result in the target storage medium.

8. The internally interconnected small supercomputing system of claim 1, wherein, Further comprising: a heterogeneous acceleration resource expansion interface; a first end of the heterogeneous acceleration resource expansion interface is connected to the programmable processing unit, and a second end of the heterogeneous acceleration resource expansion interface is configured to be connected to a heterogeneous computing module to construct a heterogeneous fusion supercomputing system.

9. A supercomputing device, comprising: A small supercomputing system with internal interconnection and interworking as claimed in any one of claims 1-8.

10. A supercomputing system cluster, comprising: A plurality of small supercomputing systems with internal interconnection and interworking as claimed in any one of claims 1-8. The computing units of each small supercomputing system are connected to each other, the high-speed data transmission modules of each small supercomputing system are connected to each other, and the plurality of small supercomputing systems in the supercomputing system cluster are configured to cooperatively process tasks.

Images