Chip srma module splicing method and device

Abstract

The application provides an SRAM module splicing method and device in a chip, the method comprising: performing a screening operation on an SRAM basic unit instance set to obtain a candidate basic unit set; sequentially taking each SRAM basic unit in the candidate basic unit set as a splicing main body, determining the maximum instantiation number and the current remaining capacity of the splicing main body, cyclically selecting an SRAM basic unit with a capacity closest to the current remaining capacity for supplementary splicing and updating the remaining capacity until the remaining capacity is less than or equal to zero to form an effective splicing solution; calculating a key feature index of each effective splicing solution and determining an optimal splicing solution; and generating a hardware description language code corresponding to the optimal splicing solution to encapsulate the spliced multiple SRAM basic units into a target SRAM module. The application can improve splicing efficiency and ensure splicing quality.

Description

Technical Field

[0001] This application relates to the field of chip technology, and more specifically, to a method and apparatus for splicing SRAM modules in a chip. Background Technology

[0002] With the rapid development of integrated circuit technology, system-on-a-chip (SoC) functions are becoming increasingly powerful and their scale is constantly expanding, leading to a continuous increase in the demand for Static Random Access Memory (SRAM). As a core component in an SoC used for data caching and temporary storage, SRAM typically occupies more than 20%-30% of the total SoC area. Under the premise of meeting SoC performance requirements, SRAM power consumption and area optimization play a crucial role in the overall SoC's performance-to-area (PPA). Since the various intellectual property (IP) modules in an SoC often come from different vendors, for most SoC designers who are not IP source code developers, directly optimizing the IP source code is difficult, has a low return on investment, high time costs, and significant risks. Therefore, optimizing the implementation scheme of the SRAM module within the IP has become a key approach to improving the overall SoC's PPA.

[0003] In the existing technology, the common technical solution for instantiating SRAM modules in SOC design mainly involves manually selecting SRAM cell chips and splicing them together. Designers select suitable types from available SRAM cells based on experience and manually combine them to form SRAM modules that meet capacity and performance requirements.

[0004] However, when it comes to manually selecting splicing methods, due to the designer's limited experience and subjective judgment, it is difficult to comprehensively weigh multiple dimensions such as power consumption, area, and voltage drop, making it difficult to ensure that the splicing scheme achieves global optimization. At the same time, the process of manual selection, calculation, and combination is time-consuming and prone to problems such as parameter matching errors and omissions in combination logic, affecting design efficiency and reliability. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a method and apparatus for splicing SRAM modules in a chip, which can solve at least one of the above-mentioned problems.

[0006] In a first aspect, embodiments of this application provide a method for splicing SRAM modules in a chip, the method comprising:

[0007] The obtained set of SRAM basic cell instances is filtered to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the set of candidate basic cells is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module.

[0008] Each SRAM base unit in the candidate base unit set is used as the splicing body in turn. The maximum number of instantiations and the current remaining capacity of the splicing body are determined. The SRAM base unit with the capacity closest to the current remaining capacity is selected in a loop for supplementary splicing and the remaining capacity is updated until the remaining capacity is less than or equal to zero, so as to form an effective splicing solution.

[0009] Calculate the key feature indicators of each effective splicing solution, and determine the optimal splicing solution based on the key feature indicators;

[0010] Based on the optimal splicing solution, hardware description language code corresponding to the optimal splicing solution is generated to encapsulate the spliced ​​multiple SRAM basic units into the target SRAM module.

[0011] Secondly, embodiments of this application also provide an SRAM module splicing device in a chip, the device comprising:

[0012] The cell filtering module is used to filter the obtained set of SRAM basic cell instances to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the candidate basic cell set is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module.

[0013] The unit splicing module is used to sequentially use each SRAM basic unit in the candidate basic unit set as the splicing body, determine the maximum number of instantiations and the current remaining capacity of the splicing body, cyclically select the SRAM basic unit with the capacity closest to the current remaining capacity for supplementary splicing and update the remaining capacity until the remaining capacity is not greater than zero, so as to form an effective splicing solution.

[0014] The optimal solution determination module is used to calculate the key feature indicators of each effective splicing solution and determine the optimal splicing solution based on the key feature indicators.

[0015] The code generation module is used to generate hardware description language code corresponding to the optimal splicing solution based on the optimal splicing solution, so as to encapsulate the spliced ​​multiple SRAM basic units into the target SRAM module.

[0016] Thirdly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the SRAM module splicing method in the chip described above.

[0017] The SRAM module splicing method and apparatus provided in this application address the technical problems of low efficiency, error-proneness, and difficulty in guaranteeing optimal performance in manual SRAM module splicing, as well as the time-consuming and infeasible full-traversal splicing method in the prior art. It can automatically generate multiple effective splicing schemes for various SRAM basic units that meet the capacity and speed requirements of the target SRAM module, and select the optimal splicing solution based on the priority ranking of key feature indicators. This not only significantly reduces manual intervention and improves splicing efficiency, but also comprehensively explores splicing schemes that meet the requirements and selects the optimal splicing solution, ensuring splicing quality. Therefore, it efficiently and accurately achieves optimized SRAM module splicing, improving the overall PPA performance of the SOC chip.

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a method for splicing SRAM modules in a chip, provided as an embodiment of this application;

[0021] Figure 2 A flowchart illustrating another method for splicing SRAM modules in a chip, as provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the structure of an SRAM module splicing device in a chip provided in an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0024] Please see Figure 1 , Figure 1 This is a flowchart illustrating a method for splicing SRAM modules in a chip, as provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the method includes:

[0025] Step S101: Filter the obtained set of SRAM basic cell instances to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the candidate basic cell set is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module.

[0026] Step S102: Take each SRAM basic unit in the candidate basic unit set as the splicing body in turn, determine the maximum number of instantiations of the splicing body and the current remaining capacity, and cyclically select the SRAM basic unit with the capacity closest to the current remaining capacity to supplement the splicing and update the remaining capacity until the remaining capacity is less than or equal to zero, so as to form an effective splicing solution.

[0027] Step S103: Calculate the key feature indicators of each effective splicing solution, and determine the optimal splicing solution based on the key feature indicators;

[0028] Step S104: Based on the optimal splicing solution, generate the hardware description language code corresponding to the optimal splicing solution to encapsulate the spliced ​​multiple SRAM basic units into a target SRAM module.

[0029] The method provided in this application can automatically generate multiple effective splicing schemes of SRAM basic cells that meet the capacity and speed requirements of the target SRAM module, and select the optimal splicing solution according to the priority ranking of key feature indicators. Compared with the manual selection of splicing in the prior art, it greatly improves splicing efficiency and avoids human error. At the same time, compared with the scheme of traversing all splicing methods, it significantly reduces the computation time, ensures the high quality of splicing schemes, and provides a foundation for the chip to obtain better performance, power consumption and area.

[0030] The following is an exemplary description of steps S101 to S104 above:

[0031] In step S101, the obtained set of SRAM basic cell instances is filtered to obtain a set of candidate basic cells; the read / write speed of the SRAM basic cells in the candidate basic cell set is greater than or equal to the minimum read / write speed corresponding to the speed requirement of the target SRAM module, and the cell capacity is less than or equal to the required capacity of the target SRAM module.

[0032] The SRAM basic cell instance set is a collection that integrates all types of SRAM basic cells and their corresponding feature databases. Specifically, the SRAM basic cell instance set is constructed based on various SRAM basic cells generated by the SRAM compiler and the extracted feature information. It can cover SRAM basic cells of different capacities, types, and aspect ratios, providing rich candidate resources for exploring splicing schemes. For example, the SRAM basic cell instance set can include SRAM basic cells of various specifications such as 128x8bit, 256x16bit, and 512x32bit generated by the compiler according to set parameters, as well as feature information such as area, read / write speed, and power consumption of each SRAM basic cell.

[0033] The candidate basic unit set is a collection of SRAM basic units obtained after the screening operation. All SRAM basic units included in this set meet the basic screening criteria of read / write speed and unit capacity. Specifically, the candidate basic unit set is the core resource pool for SRAM module splicing. Subsequent selection of splicing subjects and supplementary splicing units must be performed from this set. The richness and accuracy of its units directly affect the diversity and feasibility of the splicing scheme.

[0034] Here, read / write speed refers to how quickly an SRAM base cell completes a single read / write operation. Essentially, it's the shortest time required for the SRAM to complete one read / write operation; the lower the read / write latency, the faster the read / write speed. Different SRAM base cells can have different read / write speeds, and these values ​​can be extracted from the technical data information table generated by the SRAM compiler.

[0035] Here, cell capacity refers to the amount of data that a single SRAM basic cell can store. It is usually determined by two dimensions: word depth and bit width, i.e., cell capacity = word depth × bit width. It is the core indicator for measuring the storage capacity of an SRAM cell. Specifically, different specifications of SRAM basic cells have different cell capacities, and their size can be determined according to the generation parameters of the SRAM compiler. For example, an SRAM basic cell with a word depth of 256 and a bit width of 32 bits has a cell capacity of 256 × 32 bits = 8192 bits.

[0036] Furthermore, the target SRAM module refers to the SRAM module to be assembled that meets the requirements of the SOC / IP design. It has preset requirements such as capacity and speed, and is the target object of the entire assembly. Specifically, the requirements of the target SRAM module are determined by the specific SOC / IP design scheme, and different SOC / IP designs may correspond to different target SRAM modules with different requirements.

[0037] The minimum read / write speed corresponding to the speed requirement of the target SRAM module refers to the minimum read / write speed threshold allowed for the SRAM basic cells contained within it to meet the performance requirements of the target SRAM module. This is a key performance condition for selecting SRAM basic cells. In other words, only when the actual read / write speed of the assembled module is not lower than the minimum read / write speed corresponding to the speed requirement of the target SRAM module can the design performance requirements be met. Here, the minimum read / write speed can be derived from the overall performance requirements of the SOC / IP design, ensuring that the read / write speed of the subsequently assembled SRAM module matches the overall operating rhythm of the SOC / IP.

[0038] The required capacity of the target SRAM module refers to the total storage capacity that the target SRAM module needs to have. It is determined by the storage requirements of the SOC / IP design and serves as the core capacity benchmark for subsequent splicing scheme exploration. Specifically, the required capacity is also determined by two dimensions: word depth and bit width. Their values ​​can be determined in conjunction with specific application scenarios and data storage requirements.

[0039] In the above steps, SRAM basic cells in the SRAM basic cell instance set can be filtered according to preset screening conditions to eliminate SRAM basic cells that do not meet the requirements of the target SRAM module, thereby obtaining a set of candidate cells that meet the basic requirements for splicing. The preset screening conditions refer to a read / write speed greater than or equal to the minimum read / write speed corresponding to the speed requirement of the target SRAM module and a cell capacity less than or equal to the required capacity of the target SRAM module. Therefore, this dual-condition screening achieves precise selection of SRAM basic cells, ensuring that the subsequently spliced ​​SRAM module meets performance requirements while reducing the number of candidate cells in the splicing scheme exploration, thus reducing computational load.

[0040] In one optional embodiment, the SRAM base cell instance set is obtained through the following steps:

[0041] Based on the word depth, bit width step size, and configuration parameters supported by the SRAM compiler, various SRAM basic cells of different capacities, types, and aspect ratios are generated, and a technical data information table corresponding to each SRAM basic cell is output. Based on the technical data information table, the effective feature information of each SRAM basic cell is extracted. The effective feature information includes area, read / write speed, and power consumption. The effective feature information is classified according to the type of SRAM basic cell, and a corresponding JSON format file is generated for each type of SRAM basic cell. The JSON format file is used to record the effective feature information of all SRAM basic cells under that type to form a feature database of SRAM basic cells. The SRAM basic cells of each type and the corresponding feature database are integrated to form a set of SRAM basic cell instances.

[0042] Here, an SRAM compiler refers to a software tool capable of generating various SRAM basic cells based on set parameters. It supports different word depths, bit width steps, and configuration parameters, enabling the generation of diverse SRAM basic cells. For example, SRAM compilers are commonly used IP generation tools in chip design, and different process manufacturers typically provide corresponding SRAM compilers. This compiler can generate compliant SRAM basic cells based on user-defined word depth steps (e.g., 64, 128, 256), bit width steps (e.g., 8-bit, 16-bit, 32-bit), and other configuration parameters (e.g., read / write mode, power supply voltage), and output a technical data information table containing key technical parameters of the cell.

[0043] The technical data information table is the core basis for extracting effective feature information. The technical data information table can typically contain information such as the specifications of the SRAM basic cell (e.g., word depth, bit width, capacity), performance parameters (e.g., read / write speed, operating frequency), power consumption parameters (e.g., dynamic power consumption, static power consumption, leakage current), and physical parameters (e.g., area). This information needs to be accurately extracted to ensure the completeness and accuracy of the subsequent feature database.

[0044] Here, effective feature information refers to the key feature parameters extracted from the technical data information table that play a crucial role in the selection and optimization of SRAM module splicing schemes. These mainly include area, read / write speed, and power consumption. Among them, area determines the physical size of the SRAM module, read / write speed determines the speed at which the SRAM module is read and written, and power consumption determines the energy consumption of the SRAM module. This information will serve as the core basis for subsequent splicing scheme selection and optimal solution determination.

[0045] For example, power consumption refers to the electrical energy consumed by the SRAM base cell during operation, including dynamic power consumption and static power consumption, which is an important indicator for measuring the energy efficiency of SRAM cells. Dynamic power consumption refers to the power consumption generated by the SRAM base cell during read and write operations, which is positively correlated with the operating frequency and the number of read and write operations; static power consumption refers to the power consumption generated by the SRAM base cell in the idle state, mainly caused by leakage current, and is related to the supply voltage and process node.

[0046] Furthermore, JSON format files are a lightweight data exchange format used to store valid characteristic information categorized by the type of SRAM basic unit. They are easy to read and parse, facilitating subsequent querying and retrieval of characteristic information. Specifically, JSON format files are named and categorized according to the type of SRAM basic unit (e.g., synchronous SRAM, asynchronous SRAM, single-port SRAM, dual-port SRAM, etc.). Internally, the file records the specifications and valid characteristic information of each SRAM basic unit in key-value pairs. For example, the JSON format file corresponding to synchronous single-port SRAM may contain multiple sets of key-value pairs, each set corresponding to a synchronous single-port SRAM basic unit. The keys include word depth, bit width, capacity, area, read / write speed, dynamic power consumption, and static power consumption, while the corresponding values ​​are the specific parameters of that unit.

[0047] Here, the feature database refers to a database composed of JSON format files corresponding to all types of SRAM basic cells, used to centrally store and manage the valid feature information of SRAM basic cells. For example, the feature database can be managed in the form of a file directory, with JSON format files corresponding to different types of SRAM basic cells stored in different subdirectories, facilitating quick querying and extraction of feature information by type. In this way, integrating all types of SRAM basic cells and their corresponding feature databases forms a collection of SRAM basic cell instances.

[0048] This enables the association and binding of SRAM basic units with feature databases, building an integrated resource pool. This eliminates the need for subsequent repeated data extraction or matching, providing a unified input interface for subsequent automated filtering and splicing algorithms. It can significantly improve the automation and smoothness of the entire SRAM module splicing process.

[0049] In one optional embodiment, step S101 specifically includes:

[0050] Traverse the SRAM basic cell instance set, and extract the read / write speed and cell capacity of each SRAM basic cell based on the feature database of SRAM basic cells; remove SRAM basic cells from the SRAM basic cell instance set whose read / write speed is less than the minimum read / write speed corresponding to the speed requirement of the target SRAM module, to obtain the SRAM basic cell instance set to be processed; remove SRAM basic cells from the SRAM basic cell instance set to be processed whose cell capacity is greater than the required capacity of the target SRAM module, to obtain the candidate basic cell set.

[0051] In the above steps, each SRAM basic cell in the SRAM basic cell instance set is accessed sequentially to extract feature information and make conditional judgments for all SRAM basic cells. Specifically, the traversal operation can be implemented using a loop iteration method, sequentially reading the cell identifier in the SRAM basic cell instance set, and then extracting the corresponding read / write speed and cell capacity parameters from the feature database based on the cell identifier.

[0052] Specifically, the set of SRAM basic cell instances can be filtered twice to obtain a set of candidate basic cells. The first filtering removes SRAM basic cells whose read / write speed is less than the minimum read / write speed required by the target SRAM module. The second filtering removes SRAM basic cells whose cell capacity is greater than the required capacity of the target SRAM module.

[0053] In this embodiment, hierarchical screening can avoid the increased logical complexity caused by one-time multi-condition screening. The screening process is clear and controllable. The final candidate basic unit set only retains units that meet the core requirements, which greatly reduces the number of units that the subsequent splicing algorithm needs to traverse, reduces the time complexity of the algorithm, and avoids the waste of resources caused by invalid units participating in the splicing operation.

[0054] In step S102, each SRAM basic unit in the candidate basic unit set is used as the splicing body in turn. The maximum number of instantiations and the current remaining capacity of the splicing body are determined. The SRAM basic unit with the capacity closest to the current remaining capacity is selected in a loop for supplementary splicing and the remaining capacity is updated until the remaining capacity is less than or equal to zero, so as to form an effective splicing solution.

[0055] In this context, the splicing entity refers to the SRAM base unit that serves as the core splicing unit in a particular splicing process. The selection order of the splicing entity can be determined by the ranking result of the candidate base unit set. In other words, the selection of the splicing entity can proceed sequentially, and each SRAM base unit in the candidate base unit set has the opportunity to participate in the exploration of splicing schemes as a splicing entity, thereby ensuring the diversity of splicing schemes.

[0056] Here, the maximum number of instantiations refers to the maximum number of splicing entities that can be used within the current splicing dimension. Its value can be obtained by rounding down the ratio of the target SRAM module's required capacity within the current splicing dimension to the capacity of the splicing entities within the current dimension. Specifically, the calculation of the maximum number of instantiations needs to be combined with the specific splicing dimension (word depth or bit width) to ensure that the total capacity of the splicing entities does not exceed the target capacity's requirement in that dimension. For example, when splicing in the word depth dimension, if the target SRAM module requires a word depth of 1024 and the splicing entity C has a word depth of 512, then the maximum number of instantiations = 1024 / 512 = 2, meaning that the splicing entity C can be used a maximum of 2 times in this dimension.

[0057] The current remaining capacity refers to the capacity that the target SRAM module still needs to supplement after using the maximum number of instantiations of the splicing body in the current splicing dimension. Its value is the difference between the target capacity and the total capacity of the splicing body. Specifically, the current remaining capacity is the capacity benchmark for subsequent supplementary splicing. If the remaining capacity is greater than zero, other SRAM base units need to be selected for supplementary splicing; if the remaining capacity is less than or equal to zero, the splicing of the current dimension is completed. For example, in the word depth dimension, if the target required word depth is 1024, the word depth of splicing body C is 512, the maximum number of instantiations is 2, and its total word depth is 512 × 2 = 1024, then the current remaining word depth = 1024 - 1024 = 0, and the splicing of this dimension is completed.

[0058] Here, supplementary splicing refers to the splicing process where, after the main splicing unit has been used and there is still remaining capacity, other units are selected to supplement the remaining capacity. The supplementary units must be selected from the candidate basic unit set, and their capacity must be closest to the current remaining capacity. The core of supplementary splicing is to select units with capacities closest to the remaining capacity, thereby reducing the number of subsequent supplementary splicing operations and improving splicing efficiency.

[0059] In the above steps, an effective splicing solution refers to a splicing scheme that can meet the capacity requirements of the target SRAM module. It is composed of splicing sub-schemes in the word depth and bit width dimensions, and all the combined SRAM basic cells exist in the candidate basic cell set. Optionally, the effective splicing solution can be verified through sub-scheme combination and validity to ensure the feasibility of the solution.

[0060] like Figure 2 As shown, step S102 specifically includes the following steps:

[0061] Step a: Sort the SRAM basic cells in the candidate basic cell set in descending order of capacity;

[0062] Step b: Perform the following splicing operations in the word depth dimension and bit width dimension respectively: Take each SRAM basic unit in the sorted candidate basic unit set as the splicing body in turn, calculate the maximum number of instantiations of the splicing body and the current remaining dimension capacity, and cyclically select the SRAM basic unit with the capacity closest to the current remaining dimension capacity for supplementary splicing, calculate the maximum number of instantiations of the supplementary spliced ​​SRAM basic unit and the updated remaining dimension capacity, until the updated remaining dimension capacity is less than or equal to zero, forming multiple splicing sub-schemes in the word depth dimension and multiple splicing sub-schemes in the bit width dimension respectively;

[0063] Step c: Perform a full combination of the word depth dimension splicing sub-scheme and the bit width dimension splicing sub-scheme, and verify whether each SRAM basic cell after the combination exists in the candidate basic cell set;

[0064] Step d: If the verification passes, the combination of the splicing sub-schemes is determined as a candidate valid splicing solution; if the verification fails, the combination of the splicing sub-schemes is abandoned, and the next splicing sub-scheme in the word depth dimension is selected and recombined with the splicing sub-scheme in the current bit width dimension, or the next splicing sub-scheme in the bit width dimension is selected and recombined with the splicing sub-scheme in the current word depth dimension, and step c is repeated.

[0065] Step e: Repeat step d until all feasible splicing sub-schemes are traversed, and all verified splicing sub-schemes are determined as valid splicing solutions.

[0066] In step a above, the SRAM basic cells in the candidate basic cell set are arranged in descending order of capacity. The purpose is to prioritize the selection of large-capacity cells as the main splicing components, thereby reducing the number of splicing cells and lowering the splicing complexity. Specifically, the descending capacity sorting can be based on the numerical value of the cell capacity, with cells having larger numerical values ​​appearing first.

[0067] In step b above, word depth refers to the number of rows of data stored in the SRAM module. Word depth is the number of rows of data; each word depth corresponds to one row of data. Concatenating word depth refers to achieving the target word depth by superimposing the word depths of multiple units. Specifically, the total word depth is increased by connecting multiple SRAM base units in parallel along the word depth direction. For example, if the target word depth is 1024, two SRAM base units with a word depth of 512 can be concatenated along the word depth direction to achieve a total word depth of 1024.

[0068] The bit width dimension refers to the number of columns of data stored in an SRAM module. Bit width is the number of bits per data cell. Bit width concatenation refers to achieving the target bit width by stacking the bit widths of multiple cells. Specifically, bit width concatenation expands the data transmission width of an SRAM module by connecting multiple SRAM base cells in series along the bit width direction, thus increasing the total bit width. For example, if the target bit width is 32 bits, concatenating two 16-bit SRAM base cells along the bit width dimension will achieve a total bit width of 32 bits.

[0069] Specifically, a concatenation sub-scheme refers to a concatenation scheme formed under a single dimension (word depth or bit width), including the SRAM base unit used in that dimension and the corresponding maximum number of instantiations. Each concatenation sub-scheme corresponds to the concatenation requirement of only one dimension, and different concatenation subjects will form different concatenation sub-schemes. For example, in the word depth dimension, if the target word depth is 1024, when using a 1024x32bit unit as the concatenation subject, the maximum number of instantiations is 1, the remaining word depth is 0, and the resulting concatenation sub-scheme is one 1024x32bit unit (word depth dimension); when using a 512x32bit unit as the concatenation subject, the maximum number of instantiations is 2, the remaining word depth is 0, and the resulting concatenation sub-scheme is two 512x32bit units (word depth dimension).

[0070] The current remaining dimension capacity refers to the remaining capacity after using the splicing body in the current splicing dimension. Its calculation method is the same as the current remaining capacity, but it is limited to a specific splicing dimension. For example, the current remaining dimension capacity needs to be calculated separately for the word depth and bit width dimensions to ensure that the splicing in each dimension can meet the corresponding requirements.

[0071] The updated remaining dimension capacity refers to the remaining capacity of the current concatenated dimension after supplementary concatenation. Its value is the difference between the remaining dimension capacity before supplementary concatenation and the total capacity of the supplementary concatenation units. Specifically, the updated remaining dimension capacity is the basis for determining whether the current dimension concatenation is complete. For example, in the word depth dimension, the remaining word depth before supplementary concatenation is 512. If a 512x32-bit unit is selected as the supplementary concatenation unit, and the maximum number of instantiations is 1, the total word depth is 512×1=512. Then, the updated remaining word depth = 512-512=0, and the word depth dimension concatenation is complete.

[0072] In step c above, full combination refers to combining all splicing sub-schemes in the word depth dimension with all splicing sub-schemes in the bit width dimension one by one to explore all possible combinations of splicing schemes. For example, the full combination operation can be implemented using a Cartesian product to ensure that no feasible sub-scheme combination is missed. For instance, if there are 2 splicing sub-schemes (S1, S2) in the word depth dimension and 3 splicing sub-schemes (W1, W2, W3) in the bit width dimension, then the combined forms after full combination are S1+W1, S1+W2, S1+W3, S2+W1, S2+W2, S2+W3.

[0073] Further, this step checks whether the SRAM base cell corresponding to the combined splicing sub-scheme exists in the candidate base cell set. This is to ensure the feasibility of the splicing scheme and avoid selecting non-existent cells for splicing. The verification operation needs to determine the corresponding SRAM base cell specification based on the combined word depth and bit width, and then check whether this specification exists in the candidate base cell set. For example, if the word depth sub-scheme corresponds to a word depth of 512 and the bit width sub-scheme corresponds to a bit width of 16 bits, then the combined cell specification is 512x16 bits. If a cell of this specification exists in the candidate set, the verification passes; otherwise, the verification fails.

[0074] In steps d and e above, the verified splicing sub-schemes are combined to form candidate valid splicing solutions. These solutions possess the basic conditions to become valid splicing solutions and need to be further traversed and filtered to determine the final valid splicing solution. Candidate valid splicing solutions are feasible splicing schemes, but there may be multiple ones. The optimal solution needs to be selected subsequently through the calculation and ranking of key feature indicators.

[0075] In steps a to e above, the maximum number of instantiations of the splicing body is obtained by rounding down the ratio of the required capacity of the target SRAM module in the current splicing dimension to the capacity of the splicing body in the current splicing dimension. The current remaining dimension capacity is obtained by the difference between the required capacity of the target SRAM module in the current splicing dimension and the capacity of a first number of splicing bodies in the current splicing dimension, where the first number is the same as the maximum number of instantiations of the splicing body. The current splicing dimension includes the current bit width dimension and the current word depth dimension. The maximum number of instantiations of the supplementary splicing SRAM base units is obtained by rounding down the ratio of the current remaining dimension capacity in the current splicing dimension to the capacity of the supplementary splicing SRAM base units in the current splicing dimension. The updated remaining dimension capacity is obtained by the difference between the current remaining dimension capacity in the current splicing dimension and the capacity of a second number of supplementary splicing SRAM base units in the current splicing dimension, where the second number is the same as the maximum number of instantiations of the supplementary splicing SRAM base units.

[0076] The rounding down process involves rounding the ratio of two values ​​to the largest integer not exceeding that ratio. This ensures that the total capacity of the main splicing unit or supplementary splicing units does not exceed the required capacity of the current dimension. The first quantity refers to the maximum number of times the main splicing unit can be instantiated, i.e., the number of times the main splicing unit is used in the current dimension. Its product with the capacity of the main splicing unit is the total capacity of the main splicing unit. The second quantity refers to the maximum number of times the supplementary splicing SRAM base units can be instantiated, i.e., the number of times the supplementary splicing units are used in the current dimension. Its product with the capacity of the supplementary splicing units is the total capacity of the supplementary splicing units. Here, the value of the second quantity can be determined based on the current remaining dimension capacity to be as close as possible to the remaining capacity.

[0077] Through steps a to e above, the splicing requirements of the target SRAM module are broken down into two dimensions: word depth and bit width. This allows for flexible matching of SRAM base cells to meet different capacity requirements. The splicing sub-schemes generated in each dimension have independent optimization space, exploring better cell combinations in their respective dimensions. After combination, they can cover more diverse splicing possibilities, improving the accuracy of the final scheme's adaptation to the target requirements. In addition, full combination traversal ensures that no potential valid splicing combinations are missed, guaranteeing the integrity of the splicing scheme. The validity verification after combination can directly filter out invalid schemes that do not have corresponding SRAM base cells, avoiding subsequent calculation of key feature indicators for unachievable schemes and saving computing resources. The recombination logic after verification failure can automatically switch splicing sub-schemes to continue exploring, realizing automated iterative generation of splicing schemes.

[0078] In step S103, the key feature indexes of each effective splicing solution are calculated, and the optimal splicing solution is determined based on the key feature indexes.

[0079] Key performance indicators (KPIs) are the core metrics used to evaluate the quality of effective splicing solutions. These include total area, minimum read / write speed, and total power consumption, which directly reflect the performance of the splicing solution. For example, KPIs are the core basis for selecting the optimal splicing solution, with different indicators corresponding to different performance requirements. For instance, for SOC designs sensitive to chip area, total area is a key evaluation metric; for low-power chip designs, total power consumption is a key evaluation metric; and for high-performance chip designs, minimum read / write speed is a key evaluation metric.

[0080] The total area refers to the sum of the areas of all SRAM basic cells in an effective splicing solution, reflecting the physical size of the SRAM module formed by splicing. Specifically, the total area is related to the number of splicing cells and the area of ​​each individual cell; the more cells and the larger the area of ​​each individual cell, the larger the total area. For example, if an effective splicing solution contains two SRAM basic cells with an area of ​​0.02 mm² and one SRAM basic cell with an area of ​​0.01 mm², then the total area of ​​this solution is 0.02 × 2 + 0.01 × 1 = 0.05 mm².

[0081] The minimum read / write speed refers to the minimum read / write speed among all SRAM basic cells in the effective splicing solution, which directly determines the module's maximum operating frequency. The minimum read / write speed is determined by the cell with the lowest read / write speed in the splicing solution, because this SRAM basic cell will become the performance bottleneck of the entire SRAM module.

[0082] Total power consumption refers to the sum of the power consumption of all SRAM base cells in the effective splicing solution, including the sum of dynamic power consumption and the sum of static power consumption, reflecting the total energy consumption of the spliced ​​SRAM module. Total power consumption is a core metric of concern in low-power design, and its magnitude is related to the power consumption characteristics and the number of times the SRAM base cells are instantiated.

[0083] In the above steps, the optimal splicing solution refers to the solution with the best key characteristic indicators among all valid splicing solutions, which is specifically determined by the priority order of the key characteristic indicators. Specifically, the optimal splicing solution is the one that meets the core requirements of SOC / IP design. For example, if the design requirement prioritizes minimizing the area, and a certain valid splicing solution has the smallest total area, then that solution is the optimal splicing solution; if the design requirement prioritizes minimizing power consumption, then the solution with the lowest total power consumption is the optimal splicing solution.

[0084] In one optional embodiment, step S103 specifically includes the following steps:

[0085] Based on the area, read / write speed, and power consumption of each SRAM basic cell stored in the feature database, and the maximum number of instantiations of each SRAM basic cell corresponding to the word depth-dimensional and bit width-dimensional splicing sub-schemes in each effective splicing solution, key feature indicators for each effective splicing solution are calculated. These key feature indicators include total area, minimum read / write speed, and total power consumption. All effective splicing solutions are then hierarchically sorted according to the priority of these key feature indicators. The effective splicing solution associated with the key feature indicator with the highest priority is ranked first. The effective splicing solution ranked first after sorting is selected as the optimal splicing solution.

[0086] In the above steps, hierarchical sorting refers to sorting the key feature indicators according to their priority order, first sorting the indicators with the highest priority, then sorting the indicators with the next highest priority, and so on, to achieve an orderly arrangement of all valid splicing solutions. Optionally, hierarchical sorting can ensure that core design requirements are met first. For example, if the priority order is set as minimum total area > minimum total power consumption > maximum minimum read / write speed, then all valid splicing solutions are first sorted by total area from smallest to largest. For solutions with the same total area, they are then sorted by total power consumption from lowest to highest. For solutions with the same total area and total power consumption, they are finally sorted by minimum read / write speed from largest to smallest. The solution ranked first is the optimal solution.

[0087] Further, the total area is calculated through the following steps: the sum of the first product of the area of ​​each SRAM base cell corresponding to the word depth dimension splicing sub-scheme in the effective splicing solution and the maximum number of instantiations of the SRAM base cell, and the sum of the second product of the area of ​​each SRAM base cell corresponding to the bit width dimension splicing sub-scheme and the maximum number of instantiations of the SRAM base cell; the sum of the first product and the second product is then summed to obtain the total area.

[0088] The first product sum refers to the sum of the products of the area of ​​each SRAM basic cell and its instantiation count in the word-depth concatenation sub-scheme, reflecting the total surface area of ​​the word-depth concatenation cells. Calculating the first product sum requires traversing all cells in the word-depth concatenation sub-scheme. For example, if the word-depth concatenation sub-scheme contains two cells with an area of ​​0.02 mm² (instantiation count 2) and one cell with an area of ​​0.01 mm² (instantiation count 1), then the first product sum is 0.02 × 2 + 0.01 × 1 = 0.05 mm².

[0089] The second product sum refers to the sum of the products of the area of ​​each SRAM basic cell and its instantiation count in the bit-width dimension splicing sub-scheme, reflecting the total area of ​​the bit-width dimension splicing cells. Calculating the second product sum requires traversing all cells in the bit-width dimension splicing sub-scheme. For example, if the bit-width dimension splicing sub-scheme contains one cell with an area of ​​0.03 mm² (instantiation count 1), then the second product sum is 0.03 × 1 = 0.03 mm².

[0090] Simultaneously, the total power consumption is calculated through the following steps: Calculate the sum of the dynamic power consumption of each SRAM base unit corresponding to the word depth dimension splicing sub-scheme in the effective splicing solution and the third product of the maximum instantiation count of that SRAM base unit, and the sum of the dynamic power consumption of each SRAM base unit corresponding to the bit width dimension splicing sub-scheme and the fourth product of the maximum instantiation count of that SRAM base unit; sum the sum of the third and fourth products to obtain the total dynamic power consumption; calculate the sum of the static power consumption of each SRAM base unit corresponding to the word depth dimension splicing sub-scheme in the effective splicing solution and the fifth product of the maximum instantiation count of that SRAM base unit, and the sum of the static power consumption of each SRAM base unit corresponding to the bit width dimension splicing sub-scheme and the sixth product of the maximum instantiation count of that SRAM base unit; sum the sum of the fifth and sixth products to obtain the total static power consumption; sum the total dynamic power consumption and the total static power consumption to obtain the total power consumption.

[0091] The third product sum refers to the sum of the products of the dynamic power consumption of each SRAM basic cell and its instantiation count in the word-depth concatenation sub-scheme, reflecting the total dynamic power consumption of the word-depth concatenation cells. The calculation of the third product sum requires consideration of the cell's dynamic power consumption parameter and the number of instantiations. For example, if the word-depth concatenation sub-scheme contains two cells with a dynamic power consumption of 0.5mW / MHz (instantiation count 2), then the third product sum is 0.5 × 2 × 2 = 2mW / MHz (here, the instantiation count is 2, the dynamic power consumption of each cell is 0.5mW / MHz, so the total dynamic power consumption of a single cell is 0.5 × 2, and for two cells it is 0.5 × 2 × 2).

[0092] The fourth product sum refers to the sum of the products of the dynamic power consumption of each SRAM base cell and its instantiation count in the bit-width dimension splicing sub-scheme, reflecting the total dynamic power consumption of the bit-width dimension splicing units. The calculation method for the fourth product sum is the same as that for the third product sum. For example, if the bit-width dimension splicing sub-scheme contains one cell with a dynamic power consumption of 0.3mW / MHz (instantiation count 1), then the fourth product sum is 0.3 × 1 × 1 = 0.3mW / MHz.

[0093] Furthermore, the total dynamic power consumption refers to the sum of the dynamic power consumption of all SRAM basic cells in the effective splicing solution. Its magnitude is positively correlated with the operating frequency and is an important component of the total power consumption. Total dynamic power consumption = (sum of the third product + sum of the fourth product) × operating frequency. For example, if the sum of the third product is 2mW / MHz, the sum of the fourth product is 0.3mW / MHz, and the operating frequency is 100MHz, then the total dynamic power consumption is (2 + 0.3) × 100 = 230mW.

[0094] The fifth product sum refers to the sum of the products of the static power consumption of each SRAM basic cell and its instantiation count in the word-depth concatenation sub-scheme, reflecting the total static power consumption of the word-depth concatenation cells. The calculation of the fifth product sum requires consideration of both the cell's static power consumption parameter and the instantiation count. For example, if the word-depth concatenation sub-scheme contains two cells with a static power consumption of 0.1mW (instantiation count 2), then the fifth product sum is 0.1 × 2 × 2 = 0.4mW.

[0095] The sixth product sum refers to the sum of the products of the static power consumption of each SRAM base cell and its instantiation count in the bit-width dimension splicing sub-scheme, reflecting the total static power consumption of the bit-width dimension splicing units. The calculation method for the sixth product sum is the same as that for the fifth product sum. For example, if the bit-width dimension splicing sub-scheme contains one cell with a static power consumption of 0.2mW (instantiation count 1), then the sixth product sum is 0.2 × 1 × 1 = 0.2mW.

[0096] Furthermore, the total static power consumption refers to the sum of the static power consumption of all SRAM basic cells in the effective splicing solution. Its magnitude is related to the leakage current characteristics of the cells and is one of the components of the total power consumption. The total static power consumption = the sum of the fifth product + the sum of the sixth product. For example, if the sum of the fifth product is 0.4mW and the sum of the sixth product is 0.2mW, then the total static power consumption is 0.4 + 0.2 = 0.6mW.

[0097] In addition, the priority order can include one of the following: minimum total area as the first priority, minimum total power consumption as the first priority, or maximum minimum read / write speed as the first priority.

[0098] The "minimum total area as the first priority" approach prioritizes the total area as the most crucial evaluation metric, selecting the optimal layout solution with the smallest total area. This approach is suitable for SOC / IP design scenarios where chip area is critical. This priority order is applicable to scenarios with limited chip area, such as SOC designs in portable electronic devices. For instance, if a portable device has a limited budget for its SOC chip area and must strictly control the area of ​​each module, then setting the minimum total area as the first priority and selecting the layout solution with the smallest total area is appropriate.

[0099] The "lowest total power consumption as the first priority" approach prioritizes the lowest total power consumption as the most critical evaluation metric, selecting the optimal solution based on this metric. This approach is suitable for low-power SoC / IP design scenarios. This priority order also applies to battery-powered electronic devices such as smartphones, tablets, and IoT sensors. For example, if an IoT sensor requires long-term battery power and has extremely high power consumption requirements, then the lowest total power consumption would be prioritized, and the solution with the lowest total power consumption would be selected.

[0100] The "maximum minimum read / write speed as the first priority" approach prioritizes the minimum read / write speed as the core evaluation metric, selecting the optimal concatenation solution with the highest minimum read / write speed. This approach is suitable for high-performance SoC / IP design scenarios. This priority order is applicable to devices with high processing speed requirements, such as high-performance servers and graphics processing units (GPUs). For example, a high-performance server's SoC needs to process large amounts of data quickly, placing extremely high demands on the read / write speed of the SRAM module. In this case, the "maximum minimum read / write speed as the first priority" approach is used, selecting the concatenation solution with the highest minimum read / write speed.

[0101] In step S104, based on the optimal splicing solution, hardware description language code corresponding to the optimal splicing solution is generated to encapsulate the spliced ​​multiple SRAM basic units into a target SRAM module.

[0102] Hardware description language (HDL) code refers to programming language code used to describe the hardware structure and function of digital circuits. Commonly used languages ​​include Verilog and VHDL. It is used to transform the optimal concatenation solution into synthesizable circuit design code. Specifically, the HDL code must accurately reflect the connection relationships and operating modes of each SRAM basic unit in the optimal concatenation solution, ensuring that it can be transformed into a physical circuit by synthesis tools. For example, Verilog code can be used to define instantiated modules for each SRAM basic unit, implement word depth and bit width concatenation through signal connections, and encapsulate it into a unified target SRAM module interface.

[0103] Furthermore, the multiple assembled SRAM basic units are integrated into a unified target SRAM module, providing a standard interface while hiding the internal assembly details, facilitating subsequent SOC / IP integration. During the packaging process, the input / output interfaces of the target SRAM module must be defined, including address lines, data lines, control lines, and clock lines, ensuring compatibility with other modules in the SOC / IP. For example, the packaged target SRAM module provides address lines, data lines, read / write control lines, and clock lines, allowing other modules to access the target SRAM module through these standard interfaces.

[0104] This application addresses the technical problems of low efficiency, error-proneness, and difficulty in guaranteeing optimal performance in manual SRAM module splicing in the prior art, as well as the excessive time consumption and poor feasibility of the full traversal splicing method. It can automatically generate various effective splicing schemes of SRAM basic units that meet the capacity and speed requirements of the target SRAM module, and select the optimal splicing solution based on the priority ranking of key feature indicators. This not only significantly reduces manual intervention and improves splicing efficiency, but also comprehensively explores splicing schemes that meet the requirements and selects the optimal splicing solution, ensuring splicing quality. In this way, it can efficiently and accurately achieve optimized splicing of SRAM modules and improve the overall PPA performance of the SOC chip.

[0105] Based on the same inventive concept, this application also provides an SRAM module splicing device in a chip corresponding to the SRAM module splicing method in the chip. Since the principle of the device in this application is similar to the SRAM module splicing method in the chip described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0106] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of an SRAM module splicing device in a chip provided in an embodiment of this application. Figure 3 As shown, the device 300 includes:

[0107] The cell filtering module 301 is used to perform filtering operations on the obtained set of SRAM basic cell instances to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the set of candidate basic cells is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module.

[0108] The unit splicing module 302 is used to sequentially take each SRAM basic unit in the candidate basic unit set as the splicing body, determine the maximum number of instantiations and the current remaining capacity of the splicing body, cyclically select the SRAM basic unit with the capacity closest to the current remaining capacity for supplementary splicing and update the remaining capacity until the remaining capacity is not greater than zero, so as to form an effective splicing solution.

[0109] The optimal solution determination module 303 is used to calculate the key feature indicators of each effective splicing solution and determine the optimal splicing solution based on the key feature indicators.

[0110] The code generation module 304 is used to generate hardware description language code corresponding to the optimal splicing solution according to the optimal splicing solution, so as to encapsulate the spliced ​​multiple SRAM basic units into the target SRAM module.

[0111] The apparatus provided in this application solves the technical problems of low efficiency, error-proneness, and difficulty in guaranteeing optimal performance in manual SRAM module splicing in the prior art, as well as the excessive time consumption and poor feasibility of the full traversal splicing method. It can automatically generate a variety of effective splicing schemes of SRAM basic units that meet the capacity and speed requirements of the target SRAM module, and select the optimal splicing solution according to the priority ranking of key feature indicators. This not only greatly reduces manual intervention and improves splicing efficiency, but also comprehensively explores splicing schemes that meet the requirements and selects the optimal splicing solution, ensuring splicing quality. In this way, it can efficiently and accurately achieve optimized splicing of SRAM modules and improve the overall PPA performance of the SOC chip.

[0112] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 as well as Figure 2 The steps of the SRAM module splicing method in the chip shown in the method embodiment can be found in the method embodiment for specific implementation, and will not be repeated here.

[0113] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0114] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0115] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0116] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0117] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0118] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for splicing SRAM modules in a chip, characterized in that, The method includes: The obtained set of SRAM basic cell instances is filtered to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the set of candidate basic cells is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module. Step a) Sort the SRAM base units in the candidate base unit set in descending order of capacity; Step b) Perform the following splicing operations in the word depth and bit width dimensions respectively: Take each SRAM base unit in the sorted candidate base unit set as the splicing body, calculate the maximum number of instantiations and the current remaining dimension capacity of the splicing body, and cyclically select the SRAM base unit whose capacity is closest to the current remaining dimension capacity for supplementary splicing. Calculate the maximum number of instantiations and the updated remaining dimension capacity of the supplementary spliced ​​SRAM base units until the updated remaining dimension capacity is less than or equal to zero, forming multiple splicing sub-schemes in the word depth dimension and multiple splicing sub-schemes in the bit width dimension respectively; Step c) Perform a full combination of the splicing sub-schemes in the word depth dimension and the splicing sub-schemes in the bit width dimension, and verify whether each SRAM base unit in the combined form exists in the candidate base unit set; Step d) If the verification passes, then group the... The combination of splicing sub-schemes is determined as a candidate valid splicing solution. If the verification fails, the combination of splicing sub-schemes is abandoned, and the next splicing sub-scheme in the word depth dimension is selected and recombined with the splicing sub-scheme in the current bit width dimension, or the next splicing sub-scheme in the bit width dimension is selected and recombined with the splicing sub-scheme in the current word depth dimension. Step c is repeated; step e is repeated, and step d is repeated until all feasible splicing sub-scheme combinations are traversed, and all verified splicing sub-scheme combinations are determined as valid splicing solutions. The maximum number of instantiations of the splicing body is obtained by rounding down the ratio of the required capacity of the target SRAM module in the current splicing dimension to the capacity of the splicing body in the current splicing dimension. The maximum number of instantiations of the supplementary splicing SRAM basic unit is obtained by rounding down the ratio of the current remaining dimension capacity in the current splicing dimension to the capacity of the supplementary splicing SRAM basic unit in the current splicing dimension. Calculate the key feature indicators of each effective splicing solution, and determine the optimal splicing solution based on the key feature indicators; Based on the optimal splicing solution, hardware description language code corresponding to the optimal splicing solution is generated to encapsulate the spliced ​​multiple SRAM basic units into the target SRAM module.

2. The method according to claim 1, characterized in that, To obtain a collection of SRAM basic cell instances, follow these steps: Based on the word depth, bit width step size and configuration parameters supported by the SRAM compiler, generate SRAM basic cells of various capacities, types and aspect ratios that it can support, and output the technical data information table corresponding to each SRAM basic cell. Based on the aforementioned technical data information table, effective feature information for each SRAM basic cell is extracted; the effective feature information includes area, read / write speed, and power consumption. The effective feature information is classified according to the type of SRAM basic unit, and a corresponding JSON format file is generated for each type of SRAM basic unit. The JSON format file is used to record the effective feature information of all SRAM basic units under that type, so as to form the feature database of the SRAM basic units. All types of SRAM basic cells and their corresponding feature databases are integrated to form a set of SRAM basic cell instances.

3. The method according to claim 2, characterized in that, The step of filtering the obtained set of SRAM basic cell instances to obtain a candidate basic cell set includes: Traverse the set of SRAM basic cell instances and extract the read / write speed and cell capacity of each SRAM basic cell based on the feature database of the SRAM basic cells; Remove SRAM basic units from the SRAM basic unit instance set whose read / write speed is less than the minimum read / write speed corresponding to the speed requirement of the target SRAM module, and obtain the SRAM basic unit instance set to be processed. From the set of SRAM basic cell instances to be processed, remove SRAM basic cells whose cell capacity is greater than the required capacity of the target SRAM module to obtain a candidate basic cell set.

4. The method according to claim 1, characterized in that, The current remaining dimension capacity is obtained by the difference between the required capacity of the target SRAM module in the current splicing dimension and the capacity of a first number of splicing entities in the current splicing dimension, wherein the first number is the same as the maximum number of instantiations of the splicing entities; the current splicing dimension includes the current bit width dimension and the current word depth dimension; The updated remaining dimension capacity is obtained by the difference between the current remaining dimension capacity under the current splicing dimension and the capacity of the second number of supplementary splicing SRAM base units under the current splicing dimension, where the second number is the same as the maximum number of instantiations of the supplementary splicing SRAM base units.

5. The method according to claim 1, characterized in that, The calculation of key feature indicators for each valid splicing solution, and the determination of the optimal splicing solution based on the key feature indicators, includes: Based on the area, read / write speed, and power consumption of each SRAM basic cell stored in the feature database, and the maximum number of instantiations of each SRAM basic cell corresponding to the word depth dimension splicing sub-scheme and the bit width dimension splicing sub-scheme in each effective splicing solution, the key feature indicators of each effective splicing solution are calculated respectively; the key feature indicators include total area, minimum read / write speed, and total power consumption. All valid splicing solutions are hierarchically sorted according to the priority of key feature indicators; among them, the valid splicing solutions associated with the key feature indicators with the highest priority are ranked first. The optimal splicing solution is the one that is ranked first after sorting.

6. The method according to claim 5, characterized in that, The total area is calculated using the following steps: Calculate the sum of the first product of the area of ​​each SRAM base cell corresponding to the word depth dimension splicing sub-scheme in the effective splicing solution and the maximum number of instantiations of the SRAM base cell, and the sum of the second product of the area of ​​each SRAM base cell corresponding to the bit width dimension splicing sub-scheme and the maximum number of instantiations of the SRAM base cell. The total area is obtained by summing the sum of the first product and the sum of the second product.

7. The method according to claim 5, characterized in that, The total power consumption is calculated using the following steps: Calculate the sum of the third product of the dynamic power consumption of each SRAM base cell corresponding to the word depth dimension splicing sub-scheme and the maximum number of instantiations of the SRAM base cell, and the sum of the fourth product of the dynamic power consumption of each SRAM base cell corresponding to the bit width dimension splicing sub-scheme and the maximum number of instantiations of the SRAM base cell; sum the sum of the third product and the sum of the fourth product to obtain the total dynamic power consumption; Calculate the sum of the static power consumption of each SRAM base unit corresponding to the word depth dimension splicing sub-scheme in the effective splicing solution and the fifth product of the maximum number of instantiations of the SRAM base unit, and the sum of the static power consumption of each SRAM base unit corresponding to the bit width dimension splicing sub-scheme and the sixth product of the maximum number of instantiations of the SRAM base unit. The sum of the fifth product and the sum of the sixth product are summed to obtain the total static power consumption. The total power consumption is obtained by summing the sum of the dynamic power consumption and the sum of the static power consumption.

8. The method according to claim 5, characterized in that, The priority order includes one of the following: minimum total area as the first priority, minimum total power consumption as the first priority, and maximum minimum read / write speed as the first priority.

9. An SRAM module splicing device in a chip, characterized in that, The device includes: The cell filtering module is used to filter the obtained set of SRAM basic cell instances to obtain a set of candidate basic cells; the read and write speed of the SRAM basic cells in the candidate basic cell set is greater than or equal to the minimum read and write speed corresponding to the speed requirement of the target SRAM module and the cell capacity is less than or equal to the required capacity of the target SRAM module. The unit splicing module is used for: step a) sorting the SRAM basic units in the candidate basic unit set in descending order of capacity; step b) performing the following splicing operations in the word depth and bit width dimensions respectively: taking each SRAM basic unit in the sorted candidate basic unit set as the splicing body, calculating the maximum number of instantiations and the current remaining dimension capacity of the splicing body, cyclically selecting the SRAM basic unit with the capacity closest to the current remaining dimension capacity for supplementary splicing, calculating the maximum number of instantiations and the updated remaining dimension capacity of the supplementary spliced ​​SRAM basic unit, until the updated remaining dimension capacity is less than or equal to zero, forming multiple splicing sub-schemes in the word depth dimension and multiple splicing sub-schemes in the bit width dimension respectively; step c) performing a full combination of the splicing sub-schemes in the word depth dimension and the splicing sub-schemes in the bit width dimension, and verifying whether each SRAM basic unit in the combined form exists in the candidate basic unit set; step d) if the verification passes, If the verification fails, the group of splicing sub-schemes is discarded, and the next splicing sub-scheme in the word depth dimension is selected and recombined with the splicing sub-scheme in the current bit width dimension, or the next splicing sub-scheme in the bit width dimension is selected and recombined with the splicing sub-scheme in the current word depth dimension, and step c is repeated; step e and step d are repeated until all feasible splicing sub-scheme combinations are traversed, and all verified splicing sub-scheme combinations are determined as valid splicing solutions; the maximum number of instantiations of the splicing body is obtained by rounding down the ratio of the required capacity of the target SRAM module in the current splicing dimension to the capacity of the splicing body in the current splicing dimension; the maximum number of instantiations of the supplementary splicing SRAM basic unit is obtained by rounding down the ratio of the current remaining dimension capacity in the current splicing dimension to the capacity of the supplementary splicing SRAM basic unit in the current splicing dimension. The optimal solution determination module is used to calculate the key feature indicators of each effective splicing solution and determine the optimal splicing solution based on the key feature indicators. The code generation module is used to generate hardware description language code corresponding to the optimal splicing solution based on the optimal splicing solution, so as to encapsulate the spliced ​​multiple SRAM basic units into the target SRAM module.

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