Integrative chip of sensing and storage, sensing operation unit control circuit and method

Abstract

The application discloses a sensing and storage integrated chip, a sensing operation unit control circuit and a method. The sensing operation unit control circuit comprises a row control module and a column control module. The row control module and the column control module each comprise a plurality of control logic units, each of which corresponds to a row or a column of a sensing operation unit array. The control logic unit comprises a mode selection module and three function logic blocks. The mode selection module is used for switching the output of the control logic unit to different function logic blocks in response to a global mode selection signal, so as to realize different access modes of the sensing operation unit. The application only needs simple control timing input, and can realize three typical operations of the PE: 1. random access of the PE; 2. area selection of the PE; and 3. activation of the PE coordinate readout. Therefore, only simple control timing is needed to realize the three access modes, and the access speed and flexibility are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits and signal processing, and in particular to an integrated sensing, storage, and computing chip, a sensing and computing unit control circuit, and a method. Background Technology

[0002] Traditional von Neumann architectures, due to the separation of storage and processing units, generate significant energy consumption and latency during frequent data transfers, gradually reaching a performance bottleneck when processing high-speed sensor data. In contrast, integrated sensing, storage, and computing architectures significantly reduce data movement by integrating sensing, storage, and computing functions into a single circuit unit, thus exhibiting substantial advantages in energy efficiency and speed.

[0003] A typical integrated sensor-memory-computing chip has the following simplified structure diagram: Figure 1 As shown, Figure 1 In this context, "PE" stands for Sensing and Computing Unit, which is arranged in an array. Each Sensing and Computing Unit (PE) in the inductive memory chip requires precise selection before accessing any operation, especially signal reading or writing. Currently, PE access, selection, and information exchange are mostly accomplished by inputting control signals from the row control module (ROW_CTRL) and column control module (COL_CTRL) to the PE. This involves determining the control timing of the working logic based on different functional requirements, designing digital circuits to output the control signals for each function, and then transmitting these control signals to the PE array through the logic buffers of ROW_CTRL and COL_CTRL. This inevitably increases the design complexity of the digital system and requires a dedicated digital clock. Furthermore, the complex control timing of different functions introduces signal delays when transferring from the digital system to the analog system.

[0004] Therefore, how to efficiently and flexibly access one or more units in the array is the key to realizing chip functionality. There is an urgent need for a control scheme for the sensing and computing unit of the sensing and computing chip that can reduce design complexity, reduce resource consumption, improve access speed and enhance flexibility. Summary of the Invention

[0005] The present invention aims to provide an integrated sensing, storage, and computing chip, a sensing and computing unit control circuit, and a method to solve the technical problems of high design difficulty, high resource consumption, long signal delay, and poor flexibility caused by relying on complex digital control systems in the prior art.

[0006] A sensing and computing unit control circuit for an integrated sensing, storage and computing chip includes: a row control module and a column control module; each row control module and column control module contains multiple control logic units, and each control logic unit corresponds to a row or a column of the sensing and computing unit array.

[0007] The control logic unit includes a mode selection module and three functional logic blocks. The mode selection module is used to switch the output of the control logic unit to different functional logic blocks in response to a global mode selection signal, so as to realize different access modes to the perception and processing unit. The functional logic blocks include:

[0008] The first functional logic block is configured to receive an address signal and decode the address signal to output a row / column selection signal for random access to a single sensing operation unit.

[0009] The second functional logic block is configured to receive a start address signal and an end address signal, and generate a region selection signal for continuously selecting multiple sensing operation units based on the start address signal and the end address signal.

[0010] The third functional logic block is configured to receive activation status signals from the corresponding row or column sensing operation unit, and according to the logic state of the activation status signal, to perform logic transmission in multiple cascaded control logic units to locate the row or column coordinates of the activated sensing operation unit, and output coordinate encoding through an encoder.

[0011] Furthermore, the first functional logic block contains an address decoder that takes a binary row / column address as input and outputs a row / column selection signal with only one valid bit.

[0012] Furthermore, the second functional logic block includes a reset control terminal, a start address loading terminal, and an end address loading terminal;

[0013] When the reset control terminal is active, all area selection signals are set to active.

[0014] When the starting address loading terminal is valid, the corresponding address selection signal is kept valid according to the input starting address, and the other selection signals are set to invalid.

[0015] When the end address loading terminal is valid, all selection signals in the corresponding address to the start address region are set to valid according to the input end address, while the remaining selection signals remain invalid.

[0016] Furthermore, the third functional logic block includes a cascaded logic unit. The cascaded logic unit receives the transmission signal from the previous level control logic unit and the activation status signal of its own level, outputs it to the next level control logic unit, and can output the coordinate validity signal of its own level to the encoder when the corresponding sensing and calculation unit of its own level is activated and the transmission signal of the previous level is valid.

[0017] A method for controlling the sensing and computing unit of a sensing, storage, and computing integrated chip, applied to the control circuit described above, includes:

[0018] The access mode is selected by inputting a global mode selection signal to the control logic unit in the row control module and column control module;

[0019] Based on the selected access mode, a corresponding control signal is input to the control logic unit to generate an access control signal for the sensing and computing unit array.

[0020] Furthermore, when the random access mode is selected, the method includes: inputting the row address and column address of the target perception operation unit to the row control module and the column control module; decoding the address by the first functional logic block to make the row selection signal and column selection signal of the corresponding row and column valid, thereby selecting a single target perception operation unit.

[0021] Furthermore, when a region access mode is selected, the method includes the steps of:

[0022] Input a reset signal to the row control module and column control module to make all row selection signals and column selection signals valid;

[0023] Input the region start address into the row control module and column control module and trigger the start loading signal, keep the row selection signal and column selection signal corresponding to the start address valid, and set the other selection signals to invalid;

[0024] Input the region end address to the row control module and column control module and trigger the end loading signal. Set all row selection signals and column selection signals in the region from the end address to the start address to be valid, and keep the other selection signals invalid, thereby selecting all sensing operation units in the continuous region defined by the start address and end address.

[0025] Furthermore, when the active coordinate readout mode is selected, the method includes the following steps:

[0026] Configure the row control module to region access mode to select all rows, and configure the column control module to coordinate positioning mode;

[0027] The activated unit in the sensing and processing unit array outputs an activation status signal to the corresponding column control logic unit;

[0028] The third functional logic block in the column control module performs cascaded logic transmission according to the activation status signal, locates the column where the first activated sensing and processing unit is located, and outputs the coordinate code of that column.

[0029] While outputting column coordinates, a valid column selection signal triggers the sensing and processing unit on the corresponding column, and then the third functional logic block in the row control module locates and outputs the row coordinates of the activated unit.

[0030] Clear the activation state of the sensing and processing units whose coordinates have been read, and repeat the above positioning and output steps until the coordinates of all activated sensing and processing units have been read.

[0031] A sensing-memory-computing integrated chip includes a sensing and computing unit array and a sensing and computing unit control circuit as described above.

[0032] Furthermore, the sensing computing unit in the sensing computing unit array includes a coordinate positioning interface circuit, which includes:

[0033] An activation flag latch is used to store a flag signal indicating whether the sensing operation unit is activated;

[0034] The first controlled output unit has its enable terminal connected to the row selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the column data line; the first controlled output unit is configured to output the status of the flag signal to the column data line when the row selection signal is valid.

[0035] The second controlled output unit has its enable terminal connected to the column selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the row data line; the second controlled output unit is configured to output the status of the flag signal to the row data line when the column selection signal is valid.

[0036] The column data lines and row data lines are connected to the column control module and the row control module, respectively, and are used to collaboratively determine the coordinates of the activated sensing and computing units in the array in coordinate readout mode.

[0037] Compared with the prior art, the present invention has the following significant advantages:

[0038] The integrated sensing, storage, and computing chip, sensing and computing unit control circuit, and method of this invention only require simple control timing inputs to achieve three typical operations on the PE: 1. random access to the PE; 2. region selection of the PE; 3. activation of PE coordinate readout. These three functions only require a small number of digitally generated global control signals, which significantly reduces the number of digital signals compared to conventional methods. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1This is a simplified diagram of the existing sensor-in-memory computing chip system module structure.

[0041] Figure 2 This is a system architecture diagram of the sensing and computing unit control circuit according to an embodiment of the present invention.

[0042] Figure 3 This is a block diagram of the control logic unit (CTRL_UNIT) according to an embodiment of the present invention.

[0043] Figure 4 This is a schematic diagram of a random access single sensing operation unit according to an embodiment of the present invention.

[0044] Figure 5 This is a cascaded circuit diagram of the second functional logic block (Block_B) according to an embodiment of the present invention.

[0045] Figure 6 This is a schematic diagram illustrating the working principle of the region selection mode according to an embodiment of the present invention.

[0046] Figure 7 This is a cascaded circuit diagram of the third functional logic block (Block_C) according to an embodiment of the present invention.

[0047] Figure 8 This is a circuit diagram of the coordinate positioning interface of the sensing and computing unit according to an embodiment of the present invention.

[0048] Figure 9 This is a schematic diagram showing the connection between the sensing and computing unit and the row and column control module according to an embodiment of the present invention.

[0049] Figure 10 This is a schematic diagram illustrating the working principle of the activation coordinate readout mode according to an embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0052] Example 1

[0053] like Figure 1-2As shown, a sensing and computing unit control circuit for an integrated sensing, storage, and computing chip includes a PE (sensing and computing unit) array, a COL_CTRL (column control module), and a ROW_CTRL (row control module). Each row control module and column control module integrates multiple CTRL_UNIT (control logic units) with identical structures, and each control logic unit corresponds to a row or column of the PE array.

[0054] like Figure 3 As shown, the core of the control logic unit includes a mode selector MUX3 and a functional core composed of multiple functional logic blocks, namely, a first functional logic block Block_A, a second functional logic block Block_B, and a third functional logic block Block_C. The mode selector receives a two-bit global mode selection signal SEL<1:0>, switching the output path to function A (mode_A), function B (mode_B), or function C (mode_C). Function A corresponds to the first functional logic block: used for random access; function B corresponds to the second functional logic block: used for region selection; and function C corresponds to the third functional logic block: used for activation coordinate readout.

[0055] The first functional logic block Block_A is configured to receive address signals and decode the address signals to output row / column selection signals for random access to a single sensing operation unit;

[0056] The second functional logic block Block_B is configured to receive a start address signal and an end address signal, and generate a region selection signal for continuously selecting multiple sensing operation units based on the start address signal and the end address signal.

[0057] The third functional logic block, Block_C, is configured to receive activation status signals from the corresponding row or column sensing operation unit, and to perform logical transmission in multiple cascaded control logic units according to the logical state of the activation status signal, so as to locate the row coordinates or column coordinates of the activated sensing operation unit, and output coordinate encoding through the encoder.

[0058] The schematic diagram of the control logic unit CTRL_UNIT circuit is as follows: Figure 3 As shown, three functions are mainly selected by the selection signal SEL<1:0>, and the configuration description is as follows:

[0059] (1) When SEL<1:0>=00, the Block_A path is selected, and the Block_A control signal is output by CTRL to realize the random access PE function;

[0060] (2) When SEL<1:0>=01, the Block_B path is selected, and the Block_B control signal is output by CTRL to realize the PE function of region selection;

[0061] (3) When SEL<1:0>=10, the Block_C path is selected, the CTRL outputs the Block_C control signal, and the Block_C path outputs the corresponding coordinate data through the Encoder module to activate the PE coordinate output function.

[0062] Function A corresponds to the first functional logic block Block_A: it implements random access. The first functional logic block Block_A contains an address decoder, which takes the binary row / column address A as input. <n:0>The output has only one valid row / column selection signal. For example... Figure 2 As shown, the row access signal RCTRL <n:0>And column access signal CCTRL <m:0>The outputs are from the CTRL ports of each CTRL_UNIT in ROW_CTRL and COL_CTRL, respectively. The row and column addresses are input in binary encoding to the Block_A input terminal A of each CTRL_UNIT in ROW_CTRL and COL_CTRL. <n:0>.

[0063] When this feature is enabled, the CTRL_UNIT input SEL<1:0> for both rows and columns is configured to 00. After the row and column address are input to the decoder of Block_A, the access signal RCTRL is activated. <n:0>and CCTRL <m:0>Each will generate a valid bit. When both the row and column access signals of the PE are valid, it means that the PE is selected. Based on different row and column addresses, access to any PE in the array can be achieved.

[0064] like Figure 4 As shown, when it is necessary to access the sensing unit A at coordinates (1,1) in the array, the SEL<1:0>=00 is configured for all control logic units. The row control module and column control module receive address "1" respectively. In their respective control logic units, function A decodes address "1", causing the row control module to output RCTRL. <1> =1, column control module outputs CCTRL <1> =1. A unit is selected if and only if the row and column selection signals of a sensing operation unit are simultaneously valid, thereby completing the random access and operation of unit A.

[0065] like Figure 5 As shown, function B corresponds to the second functional logic block Block_B: used to implement region selection. The second functional logic block contains a cascaded circuit based on latches and logic gates, receiving global reset, start address loading, and end address loading signals. The second functional logic block includes a reset control terminal, a start address loading terminal, and an end address loading terminal. When the reset control terminal is valid, all region selection signals are set to valid. When the start address loading terminal is valid, the corresponding address selection signal is kept valid according to the input start address, while the remaining selection signals are set to invalid. When the end address loading terminal is valid, all selection signals within the region from the corresponding end address to the start address are set to valid according to the input end address, while the remaining selection signals remain invalid. Figure 5 and Figure 6 As shown, taking the area of ​​rows 1 to 3 and columns 0 to 2 as an example, select all PEs within this area. First, set SEL<1:0>=01. Perform three operations on the row control module:

[0066] 1) Activate the global reset signal SET, making all values ​​of RCTRL<3:0> equal to 1;

[0067] 2) Input the starting address "1" and activate the LOAD_ST signal, then set RCTRL. <1> Keep it at 1, and set the rest to 0;

[0068] 3) Input the end address "3" and activate the LOAD_ED signal, set RCTRL<3:2> to 1, and keep the rest at 0. Finally, we get RCTRL<3:1>=111.

[0069] Performing the same operation on the column control module yields CCTRL<2:0>=111. Consequently, all nine sensing and processing units within this continuous area are simultaneously selected. This function is primarily used for simultaneous access to multiple PE signals for reading and writing, such as... Figure 6 The area that can be selected by this function is a continuous range of rows and columns, with the maximum area being the entire array.

[0070] When this feature is enabled, all CTRL_UNIT control signals SEL<1:0>=01 in rows and columns, selecting... Figure 3 The output path of Block_B in the middle.

[0071] The following is combined Figure 3 Explain the principle behind implementing region selection; to achieve... Figure 6 Region selection, Figure 2 The marked access signals must satisfy RCTRL<3:1>=111, CCTRL<2:0>=111, and all other control signals must be 0.

[0072] The following details the implementation of ROW_CTRL outputting RCTRL<3:1>=111. The cascading relationship of the Block_B circuit in the CTRL_UNIT within the ROW_CTRL module is as follows: Figure 5 As shown, the expected function is achieved through the following three control processes.

[0073] (1) Output Reset: The global reset signal SET of ROW_CTRL is "1", at which time RCTRL <n:0>All are "1";

[0074] (2) Loading region start address: The first row of the row address input is used as the starting row for region selection. The global signal LOAD_ST is "1". At this time, the RCTRL is output. <1> =1, and all other RCTRL signals are set to 0;

[0075] (3) Loading region end address: The third row of the row address input is used as the end row of the region selection. The global signal LOAD_ED is "1". At this time, the output RCTRL<3:1>=111 is displayed, and the rest of the RCTRL signals remain 0.

[0076] By following the three steps above and using the same control method, CCTRL<2:0>=111 can be achieved. This completes the process. Figure 6 All nine PEs, A1 to A9, were selected simultaneously.

[0077] It can be seen that within the range of the PE array, any continuous region can be accessed via... Figure 5 In the Block_B function, the selected row / column region is completed through the three operations described above: reset, load the starting address, and load the ending address.

[0078] Function C corresponds to the third functional logic block Block_C: used to implement activation coordinate readout. This third functional logic block includes cascaded logic units. Each cascaded logic unit receives the transmission signal from the preceding control logic unit and the activation status signal of its current level, outputs it to the next level control logic unit, and can output a valid coordinate signal to the encoder when the corresponding sensing and processing unit is activated and the transmission signal from the preceding level is valid. For example... Figure 3 As shown, the third functional logic block contains logic gates AND2 and NOR3B that receive signals from the preceding stage and the activation status signal of this stage, as well as an encoder connected to NOR3B, used to output coordinate codes after the target is located. The cascading relationship between the Block_C circuits in the CTRL_UNIT within the ROW_CTRL and COL_CTRL modules is as follows: Figure 7 As shown. Among them, CDATA is the column data line, which is the core signal line for the coordinate readout function.

[0079] Each PE also has a coordinate positioning interface circuit inside, such as Figure 8 The diagram shows a schematic of the coordinate positioning interface circuit in a PE. Figure 8 In this context, ENINV is an inverter with an enable pin. Figure 8 Both CSEL and RSEL are ENINV enable signals. The connection relationship between PE and the CTRL_UNIT circuits in ROW_CTRL and COL_CTRL is as follows: Figure 9 As shown. RSEL and CSEL are derived from the RCTRL and CCTRL signals output by the row control module (ROW_CTRL) and column control module (COL_CTRL), respectively, and are used to select all PEs in a certain row or column. This circuit mainly includes: an activation flag latch, a first controlled output unit (ENINV controlled by RSEL), and a second controlled output unit (ENINV controlled by CSEL).

[0080] The activation flag latch is used to store a flag signal indicating whether the sensing operation unit is activated. If the activation flag latch TAG-latch stores "1", it means that the PE is activated. For example, when the sensing operation unit detects a specific sensing signal (such as light intensity exceeding a threshold), completes a specific operation task, or is preset by external logic, it can be set to activate the PE.

[0081] The first controlled output unit has its enable terminal connected to the row selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the column data line; the first controlled output unit is configured to output the status of the flag signal to the column data line when the row selection signal is valid.

[0082] The second controlled output unit has its enable terminal connected to the column selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the row data line; the second controlled output unit is configured to output the status of the flag signal to the row data line when the column selection signal is valid.

[0083] The column data lines and row data lines are connected to the column control module and the row control module, respectively, and are used to collaboratively determine the coordinates of the activated sensing and computing units in the array in coordinate readout mode.

[0084] During operation, when the row control module (ROW_CTRL) selects a row via the RSEL signal, the first controlled output unit in all PEs of that row is enabled, outputting its activation state to the column data line (CDATA) for the column control module (COL_CTRL) to perform horizontal coordinate positioning. Similarly, when the column control module selects a column via the CSEL signal, the second controlled output unit in all PEs of that column is enabled, outputting its activation state to the row data line (RDATA) for the row control module to perform vertical coordinate positioning.

[0085] Taking the output of "Activated PE" on the x-axis as an example for detailed explanation, the principle for outputting the y-axis is the same, see [link to relevant documentation]. Figure 10 Assume that perception processing units C, B, A, D, and E are the activated units. First, configure the row control module SEL=01 (region mode selects all rows) and the column control module SEL=10 (coordinate positioning mode). Coordinate positioning: Since the PEs of all rows are selected, the CDATA corresponding to columns 1, 3, and 4 where the activated PE unit is located... <1> CDATA <3> CDATA <4> The coordinate positioning circuit in PE is set to 0, and all others are 1. Figure 10 The second column is not activated (PE). In the Block_C cascade corresponding to the cascade function C of the column control module, such as... Figure 7 and Figure 9 The logic is passed from the first column. Since CDATA in the first column is low, its PREVIOUS_C remains 1, and NEXT_C outputs 0, causing PREVIOUS_C in all subsequent columns to be 0. Coordinate output: Enables the global output signal EOUT. At this time, only the function C block in the first column outputs a valid signal because its PREVIOUS_C=1, triggering the encoder to output column coordinate encoding "001". The number of encoding bits depends on the size of the PE array; here, a 3-bit (three-digit binary) coordinate encoding is used as an example. Simultaneously, a valid CCTRL... <1> The signal will select all cells in the first column. Similar to column coordinate positioning, the RDATA signal of rows 1, 2, and 3 containing activated cells C, B, and A in the first column is pulled low. A similar cascaded positioning is performed in function block C of the row control module, ultimately outputting the row coordinate code "001" for cell C. Subsequent readout: After reading the coordinates of cell C, its internal activation flag is cleared. The above positioning process is repeated. Since there are still two activated PEs (B and A) in the first column, the coordinates of that column are still output. However, the activation flag of C has been cleared. Therefore, when positioning the vertical coordinate of the activated PE in the first column, the row coordinates of B will be output, thus reading the coordinates of cell B. This process continues until the coordinates of all activated cells are read sequentially. Figure 10 As shown, assuming that the PE with the acquired bright spot is defined as the activated PE, this function can read out the coordinates of all bright spot PEs in the array. Figure 10 The shaded areas A, B, C, D, and E are all active PEs. (This is achieved through...) Figure 2 The control logic units (ROW_CTRL and COL_CTRL) can serially read out the horizontal and vertical coordinate information of the active PEs. The reading order is determined by the row and column order of each active PE; for example, PEs with the highest horizontal and vertical coordinates can be output first. Figure 10 For example, the circuit output activates the PE coordinates in the following order: C(1,1), B(1,2), A(1,3), D(3,2), E(4,4).

[0086] Figure 10 The process of reading the "Active PE" coordinates is as follows:

[0087] (1) Initial state reset:

[0088] In ROW_CTRL, the CTRL_UNIT control signal SEL<1:0>=01 selects the Block_B path;

[0089] The CTRL_UNIT control signal SEL<1:0>=10 in COL_CTRL selects the Block_C path;

[0090] Figure 7 All EOUT values ​​remain "0", and all PREVIOUS_C (pre-amp enable signal) and NEXT_C (output next stage) values ​​are "1".

[0091] The TAG-latch in the PE outputs a flag signal. Figure 10 The TAG-latch output of the five PEs A, B, C, D, and E is "1".

[0092] (2) Coordinate positioning:

[0093] ROW_CTRL first selects the entire row range using function 2, then... Figure 9 As can be seen, the RSEL signal in all PEs is "1", so the CDATA output of the five PEs A, B, C, D, and E is 0, while the CDATA output of the other PEs remains high.

[0094] Since these 5 PEs are located in columns 1, 3, and 4, combined with... Figure 9 The connection relationship shows that COL_CTRL's CDATA <1> CDATA <3> CDATA <4> All are "0", and the rest remain "1".

[0095] pass Figure 7 After the logic transfer between Block_C circuits, only the PREVIOUS_C signal in Block_C of the first column CTRL_UNIT remains "1", while the PREVIOUS_C signal of all subsequent Block_C circuits is "0".

[0096] (3) Output of horizontal coordinate:

[0097] After completing the previous logic pass, the global signal EOUT is "1", and at this point only CCTRL is active. <1> =1, all others are "0". (From...) Figure 3 As can be seen, the Block_C path is connected to the encoder. When the signal of this path is "1", the encoder outputs the encoded sequence corresponding to the column, which is used as the horizontal coordinate data.

[0098] When completing the x-axis output, due to the CCTRL output of COL_CTRL... <1> =1, by Figure 9 As can be seen, the CSEL of all PEs in the first column will be "1", which will enable the vertical coordinate positioning output. The vertical coordinate positioning and output are completed by the Block_C circuit in ROW_CTRL.

[0099] (4) Output of the vertical axis:

[0100] When CCTRL <1> When valid (high level "1"), all PEs in column 1 are selected, such as... Figure 9 As shown, the CSEL signals of these PEs are valid. In the first column, there are three activated PEs: C, B, and A, whose TAG-latch is 1 and they are in an active state. The TAG-latch of the remaining PEs is "0".

[0101] When a column is selected and CSEL=1, the activation state (TAG-latch output) of each PE in that column will affect the corresponding RDATA line through its own other ENINV (controlled by CSEL).

[0102] For column 1, only PEs C, B, and A are activated. Therefore, only the RDATA lines of the rows corresponding to PEs C, B, and A (rows 1, 2, and 3) are pulled low to "0". The PEs of the other rows in this column (rows 0, 4, 5...m) are not activated, and their ENINV outputs are in a high-impedance state, which does not affect RDATA. Therefore, the RDATA lines of these rows remain at the high level "1" after reset.

[0103] Each CTRL_UNIT in the row control module (ROW_CTRL) maintains the region selection mode (SEL=01, Block_B path). Their internal Block_C circuits are also connected in a cascaded manner (similar to...). Figure 7 (Column cascade), logical transfer begins from the Block_C module corresponding to row 0.

[0104] The "0" / "1" states on the RDATA line are sent to the corresponding row's Block_C as input signals. Therefore, the RDATA lines corresponding to rows 1, 2, and 3... <1> RDATA <2> RDATA <3> All are 0, and the rest remain 1.

[0105] according to Figure 7 Similar to the logic, the Block_C corresponding to the first line determines that it is the first active line to be processed, so it sets its NEXT_R output to "0" to prevent the activation signal from being passed on.

[0106] The PREVIOUS_R input of all subsequent lines (lines 2, 3, 4, ...) of the Block_C module becomes "0" because the previous NEXT_R=0, so coordinate output will not be triggered.

[0107] After the column coordinate output stabilizes, or is synchronized by the timing controller, a row coordinate output enable signal (e.g., ROUT) is set to "1". At this time, only the Block_C of the first row is activated because its PREVIOUS_R=1 and it is itself (RDATA). <1> =0) and output a valid signal. This valid signal triggers the encoder of the line control module to output the binary code of the line coordinates of the PE C, such as "001".

[0108] At this point, the complete coordinates (column: 001, row: 001) of the first activation point C(1,1) have been read.

[0109] (5) Serial reading of the coordinates of subsequent activation points:

[0110] After the coordinates of one point are read out, the system will enter the next loop and read out all active points serially using the same mechanism.

[0111] Clear read flag: After reading the coordinates of PE_C, the control logic clears the "1" state of the TAG-latch inside PE_C (for example, resets it to "0"), indicating that the point has been processed.

[0112] Loop positioning:

[0113] The system restarts positioning from column coordinates. Figure 10 The coordinates shown are defined (columns correspond to the x-direction sequence, rows correspond to the y-direction sequence). Although the PE_C activation flag has been cleared, there are still two active PEs, B and A, in the column where C is located. Therefore, CDATA... <1> It remains at 0.

[0114] The cascaded circuit of the column control module is scanned again. This is because the first column CDATA in the x-direction... <1> If the value is "0", the corresponding Block_C module PREVIOUS_C remains at 1, and NEXT_C outputs 0, causing all subsequent columns to have PREVIOUS_C values ​​of 0. Because there are still active PEs (B and A) in this column whose coordinates have not been read, the cascade scan will prioritize locking this column, and the Block_C of the first column in the x-direction will still be determined as the "first active column", and its column coordinates will continue to be output.

[0115] After the system reads column coordinate "001" and selects all PEs in that column again, only RDATA remains. <2> RDATA <3> The first value is 0, and the rest are 1. After being processed by the Block_C logic of the row control module, the row coordinate "010" is output, and then the coordinates of the second active PE, B (1, 2), are output.

[0116] Repeat until complete: Clear the flag at PE coordinate B.

[0117] The system continues this process: it locates and reads the next activation point A(1,3) in column 1; then it locates and reads D(3,2) in column 3; and finally it locates and reads E(4,4) in column 4.

[0118] The coordinate reading process ends when all CDATA lines in all columns are "1" (indicating no remaining active points).

[0119] Through the above method, Figure 10 The five "active PEs" A, B, C, D, and E will prioritize outputting the x and y coordinates of C. Simply clear the TAG-latch in each "active PE" to zero, and you can output the coordinates of all target PEs.

[0120] Example 2

[0121] This invention proposes a control method for the sensing and computing unit of a sensing, storage, and computing integrated chip, comprising:

[0122] The access mode is selected by inputting a global mode selection signal to the control logic unit in the row control module and column control module;

[0123] Based on the selected access mode, a corresponding control signal is input to the control logic unit to generate an access control signal for the sensing and computing unit array.

[0124] In this embodiment, when the random access mode is selected, the method includes: inputting the row address and column address of the target perception operation unit to the row control module and the column control module; decoding the address by the first functional logic block to make the row selection signal and column selection signal of the corresponding row and column valid, thereby selecting a single target perception operation unit.

[0125] In this embodiment, when a region access mode is selected, the method includes the following steps:

[0126] Input a reset signal to the row control module and column control module to make all row selection signals and column selection signals valid;

[0127] Input the region start address into the row control module and column control module and trigger the start loading signal, and set the row selection signal and column selection signal other than the start address to invalid;

[0128] Input the region end address to the row control module and column control module and trigger the end loading signal to set all selection signals in the region from the start address to the end address to be valid, thereby selecting all sensing and processing units in the continuous region defined by the start address and the end address.

[0129] In this embodiment, when the active coordinate readout mode is selected, the method includes the following steps:

[0130] Configure the row control module to region access mode to select all rows, and configure the column control module to coordinate positioning mode;

[0131] The activated unit in the sensing and processing unit array outputs an activation status signal to the corresponding column control logic unit;

[0132] The third functional logic block in the column control module performs cascaded logic transmission according to the activation status signal, locates the column where the first activated sensing and processing unit is located, and outputs the coordinate code of that column.

[0133] While outputting column coordinates, a valid column selection signal triggers the sensing and processing unit on the corresponding column, and then the third functional logic block in the row control module locates and outputs the row coordinates of the activated unit.

[0134] Clear the activation state of the sensing and processing units whose coordinates have been read, and repeat the above positioning and output steps until the coordinates of all activated sensing and processing units have been read.

[0135] This invention also provides an integrated sensing, storage, and computing chip, including a sensing and computing unit array and the aforementioned sensing and computing unit control circuit. This unit circuit is implemented in an analog system, requiring only simple control timing inputs to perform three typical operations on the PE: 1. Random access to the PE; 2. Region selection of the PE; 3. Activation of PE coordinate readout. These three functions require only a small number of digitally generated global control signals, significantly reducing the number of digital signals compared to conventional methods. Furthermore, this invention proposes a readout circuit that can implement the above three operating modes in very few steps without increasing the design complexity of the digital system.

[0136] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0137] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0138] It should be noted that in the examples and description of this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0139] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A method for controlling the sensing and computing unit of a sensing, storage, and computing integrated chip, characterized in that, The sensing and processing unit includes: The row control module and the column control module; each row control module and the column control module contains multiple control logic units, each control logic unit corresponding to a row or a column of the sensing and computing unit array; The control logic unit includes a mode selection module and three functional logic blocks. The mode selection module is used to switch the output of the control logic unit to different functional logic blocks in response to a global mode selection signal, so as to realize different access modes to the perception and processing unit. The functional logic blocks include: The first functional logic block is configured to receive an address signal and decode the address signal to output a row / column selection signal for random access to a single sensing operation unit. The second functional logic block is configured to receive a start address signal and an end address signal, and generate a region selection signal for continuously selecting multiple sensing operation units based on the start address signal and the end address signal. The third functional logic block is configured to receive the activation status signal from the sensing operation unit of the corresponding row or column, and according to the logic state of the activation status signal, to perform logic transmission in multiple cascaded control logic units to locate the row coordinates or column coordinates of the activated sensing operation unit, and output coordinate encoding through the encoder. The sensing and computing unit control method includes the following steps: The access mode is selected by inputting a global mode selection signal to the control logic unit in the row control module and column control module; According to the selected access mode, the corresponding control signal is input to the control logic unit to generate access control signal for the sensing and computing unit array; When the active coordinate readout mode is selected, the method includes the following steps: Configure the row control module or column control module to a region access mode to select any continuous range of rows or columns, the size of which is determined by the start and end addresses of the second functional logic block, and configure the column control module or row control module to a coordinate positioning mode. The activated unit in the sensing and processing unit array outputs an activation status signal to the corresponding column control logic unit or row control logic unit; The third functional logic block in the column control module or row control module performs cascaded logic transmission according to the activation status signal, locates the column or row where the first activated sensing operation unit is located within the selected range, and outputs the coordinate code of the column or row. While outputting column or row coordinates, a valid column or row selection signal triggers the sensing and processing unit on the corresponding column or row, and then the third functional logic block in the row control module or column control module locates and outputs the row or column coordinates of the activated unit. Clear the activation state of the sensing and processing units whose coordinates have been read, and repeat the above positioning and output steps until the coordinates of all activated sensing and processing units have been read.

2. The control method according to claim 1, characterized in that, When the random access mode is selected, the method includes: inputting the row address and column address of the target perception operation unit into the row control module and the column control module; decoding the address by the first functional logic block to make the row selection signal and column selection signal of the corresponding row and column valid, thereby selecting a single target perception operation unit.

3. The control method according to claim 2, characterized in that, When a region access mode is selected, the method includes the following steps: Input a reset signal to the row control module and column control module to make all row selection signals and column selection signals valid; Input the region start address into the row control module and column control module and trigger the start loading signal, keep the row selection signal and column selection signal corresponding to the start address valid, and set the other selection signals to invalid; Input the region end address to the row control module and column control module and trigger the end loading signal. Set all row selection signals and column selection signals in the region from the end address to the start address to be valid, and keep the other selection signals invalid, thereby selecting all sensing operation units in the continuous region defined by the start address and end address.

4. The control method according to claim 1, characterized in that, The first functional logic block contains an address decoder that takes a binary row / column address as input and outputs a row / column selection signal with only one valid bit.

5. The control method according to claim 4, characterized in that, The second functional logic block includes a reset control terminal, a start address loading terminal, and an end address loading terminal; When the reset control terminal is active, all area selection signals are set to active. When the starting address loading terminal is valid, the corresponding address selection signal is kept valid according to the input starting address, and the other selection signals are set to invalid. When the end address loading terminal is valid, all selection signals in the corresponding address to the start address region are set to valid according to the input end address, while the remaining selection signals remain invalid.

6. The control method according to claim 5, characterized in that, The third functional logic block includes a cascaded logic unit. The cascaded logic unit receives the transmission signal from the previous level control logic unit and the activation status signal of its own level, outputs it to the next level control logic unit, and can output the coordinate validity signal of its own level to the encoder when the corresponding sensing and processing unit of its own level is activated and the transmission signal of the previous level is valid.

7. A sensing-memory-computing integrated chip, characterized in that, It includes a sensing and computing unit array and a control circuit corresponding to the sensing and computing unit control method as described in any one of claims 1-6.

8. The integrated sensing, memory, and computing chip according to claim 7, characterized in that, The sensing and computing unit array includes a coordinate positioning interface circuit, which comprises: An activation flag latch is used to store a flag signal indicating whether the sensing operation unit is activated; The first controlled output unit has its enable terminal connected to the row selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the column data line; the first controlled output unit is configured to output the status of the flag signal to the column data line when the row selection signal is valid. The second controlled output unit has its enable terminal connected to the column selection signal, its input terminal connected to the output terminal of the activation flag latch, and its output terminal connected to the row data line; the second controlled output unit is configured to output the status of the flag signal to the row data line when the column selection signal is valid. The column data lines and row data lines are connected to the column control module and the row control module, respectively, and are used to collaboratively determine the coordinates of the activated sensing and computing units in the array in coordinate readout mode.

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