A method for generating a comprehensive design constraint file, an electronic device, and a storage medium
By automatically obtaining the list of atomic units for chip design using a target block list and mapping file, and combining this with a generation script to generate a synthesis design constraint file, the inefficiency of traditional chip design methods is solved, achieving efficient and accurate constraint file generation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 沐曦集成电路(南京)有限公司
- Filing Date
- 2026-03-02
- Publication Date
- 2026-05-15
AI Technical Summary
In chip design, traditional methods for generating synthesis design constraint files are inefficient and error-prone, especially when the number of tiles increases. This results in a large amount of repetitive work and makes it difficult to ensure the consistency and integrity of the constraints.
The system automatically obtains the list of atomic units for the current block using a pre-set target block list file and target block mapping file, and then generates a comprehensive design constraint file using a generation script, thus avoiding manual intervention.
It improves the accuracy and efficiency of obtaining the atomic unit list, ensures the correctness and consistency of the constraint file, and solves the problems of inefficiency and error-proneness in traditional methods.
Smart Images
Figure CN121766227B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a method for generating integrated design constraint files, an electronic device, and a storage medium. Background Technology
[0002] In the front-end synthesis and back-end implementation of very large-scale integrated circuits (VLSI), to address design complexity and tool limitations, chips are typically divided into dozens or even hundreds of tiles (chip blocks) to support parallel development, local optimization, and module reuse. Under this architecture, not only are global interconnect structures such as Network-on-Chip (NOC) physically divided into multiple tiles, but other critical modules with global functionalities—such as clock / reset distribution networks, low-power control logic, and PCIe controllers—inevitably span multiple tile boundaries. Although these modules logically belong to a unified functional entity, their physical distribution necessitates that each tile independently generates Synopsys Design Constraints (SDC) files for its contained module fragments.
[0003] Traditional processes rely on module designers providing general SDC (Software Design Code) guidelines, which are then used by each tile manager to manually write specific constraints within their current tile. However, this method has significant drawbacks: firstly, tile managers often lack a deep understanding of the overall architecture, interface protocols, and timing behavior across tile modules, making omissions or mismatches common when converting general rules into specific constraints; secondly, with the surge in the number of tiles, the repetitive workload of writing and reviewing SDCs increases dramatically, leading to inefficiency and difficulty in ensuring the consistency and completeness of constraints. Therefore, there is an urgent need for an SDC generation method that reduces workload and improves efficiency while ensuring SDC correctness. Summary of the Invention
[0004] To address the aforementioned technical problems, the present invention adopts the following technical solution: a method for generating a synthesis design constraint file, the method comprising the following steps: receiving multiple blocks corresponding to a chip design; for each block, performing the following synthesis design constraint file generation steps: obtaining the name of the current block; querying a preset target block list file based on the name of the current block; wherein, the target block list file includes a list of names of target blocks distributed across target modules; if the name of the current block exists in the target block list file, then querying a preset target block mapping file based on the name of the current block to obtain a list of atomic units corresponding to the current block; wherein, the target block mapping file includes at least one mapping relationship, each mapping relationship associating a target block with its included list of atomic units, the atomic unit being the smallest functional unit in the target module; controlling a generation script to generate constraint sub-files for each atomic unit according to the list of atomic units corresponding to the current block; generating a synthesis design constraint file for the current block based on the constraint sub-files of each atomic unit in the current block.
[0005] Furthermore, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, wherein the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the above-described method.
[0006] In addition, the present invention provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.
[0007] The present invention has at least the following beneficial effects:
[0008] The method for generating a comprehensive design constraint file provided in this invention automatically obtains a list of all atomic units required for the current block through a pre-set target block list file and target block mapping file, without traversing the RTL source code, which greatly improves the accuracy and efficiency of obtaining the atomic unit list. Furthermore, it combines a generation script to generate constraint sub-files for each atomic unit, thereby obtaining the comprehensive design constraint file for the current block. This method generates the comprehensive design constraint file for the current block efficiently without manual intervention, fundamentally solving the problems of low efficiency and error susceptibility in traditional methods. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 A flowchart illustrating a method for generating a comprehensive design constraint file, as provided in an embodiment of the present invention;
[0011] Figure 2 The present invention provides a logical flowchart of a method for generating a comprehensive design constraint file. Detailed Implementation
[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0013] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.
[0014] Please see Figure 1 The document illustrates a flowchart of a method for generating integrated design constraint files, the method comprising the following steps:
[0015] S100 receives multiple blocks corresponding to the chip design.
[0016] A tile, also known as a chip tile, refers to a sub-module block with specific functions or physical boundaries, obtained by dividing the overall chip circuit at the physical or logical level. This division is carried out during the logic synthesis stage or the physical implementation stage.
[0017] It should be noted that the method for generating integrated design constraint files provided by this invention is an automated generation method implemented through scripts.
[0018] S300, please refer to Figure 2 For each block, perform the following steps to generate the integrated design constraint file:
[0019] S310, retrieve the name of the current block.
[0020] S330, query a preset target block list file based on the name of the current block; wherein, the target block list file includes a list of names of target blocks distributed by the target module; if the name of the current block exists in the target block list file, then query a preset target block mapping file based on the name of the current block to obtain a list of atomic units corresponding to the current block; wherein, the target block mapping file includes at least one mapping relationship, each mapping relationship associating a target block with its included list of atomic units, wherein the atomic unit is the smallest functional unit in the target module.
[0021] Among them, the target module has global functional characteristics, and its distribution range may cover multiple consecutive or non-consecutive blocks. The block with the partial design of the target module is the target block.
[0022] In one implementation, the target module is a NOC network, a clock / reset distribution network, low-power control logic, or a PCIe controller. Other target modules with global functional characteristics also fall within the protection scope of this invention.
[0023] The target block list file contains a list of all blocks in the chip design where the target module is distributed. As an example, the target block list file might include {tile_1, tile_3, tile_4}. This target block list file allows the system to quickly determine whether tile_1 is an element in the target block list file by querying it. Using this target block list file, the system avoids traversing and analyzing all dozens or even hundreds of blocks in the chip design, and can accurately locate only a few target blocks relevant to the target module. Subsequently, the system will only perform subsequent steps on these listed target blocks, improving the generation process of the synthesis design constraint file.
[0024] The target block mapping file records the affiliation between target blocks and their subordinate atomic units. Specifically, this target block mapping file defines at least one mapping entry, where each entry maps a specific target block as a key to a list of instance names of multiple atomic units. As an example, a mapping entry could be: tile_1:[au_1,au_2,au_3]. This file allows the system to quickly retrieve the set of all its subordinate atomic units {au_1,au_2,au_3} by querying tile_1. By querying the target block mapping file, the list of atomic units corresponding to each target block can be obtained quickly and accurately without traversing all atomic units in the entire chip design database, significantly reducing processing complexity. The target block mapping file ensures absolute consistency and accuracy in the correspondence between target blocks and atomic units, avoiding errors caused by manual maintenance, thereby ensuring the correctness of the generated synthesis design constraint file.
[0025] It should be noted that the present invention can isolate the impact of design changes through the target block list file and the target block mapping file. When the distribution or instantiation of the target module changes due to design iteration, it is only necessary to update the current target block list file and the target block mapping file. The core processing logic of the synthesis design constraint file generation method provided by the present invention can adapt to the new design without modification.
[0026] In one implementation, the target block list or target block mapping file is either created manually or automatically generated by a tool based on the instantiation and layout information of the target module.
[0027] In this context, an atomic unit is the fundamental, indivisible unit within the target module and represents the smallest granularity for executing subsequent constraint configurations. These atomic units are recorded in the target block mapping file and associated with their parent target blocks. When constraints need to be generated for a target block, the system queries the target block mapping file to obtain a precise list of all atomic units corresponding to that target block, and then generates a corresponding comprehensive design constraint file for each atomic unit in the list.
[0028] In one implementation, the atomic unit is a standard logic unit, such as an AND gate or a flip-flop. Atomic units classified in other ways also fall within the scope of this invention.
[0029] S350, the control generation script generates constraint sub-files for each atomic unit based on the list of atomic units corresponding to the current block.
[0030] Specifically, the script reads the list of atomic units corresponding to the current block and iterates through each atomic unit in the list. For each atomic unit, the script generates a constraint sub-file according to preset rules.
[0031] In one implementation, S350 includes performing the following steps for each atomic unit:
[0032] S351, Get the instance name of the current atomic unit.
[0033] In this context, the instance name of an atomic unit refers to the unique identifier assigned when an atomic module is instantiated. The same atomic module can be instantiated multiple times to generate different copies, and the instance names of the atomic units obtained from each instantiation can be different. As an example, if the atomic module named au_module_A is instantiated twice, the instance names will be au_1 and au_2, respectively.
[0034] It should be noted that in the embodiments of the present invention, the target module and the atomic module are different modules. The target module is the upper-level logic module for which constraints need to be generated, and the target module includes multiple reusable atomic modules. During chip implementation, each atomic module is instantiated once or multiple times in the design to generate specific instances, i.e., atomic units.
[0035] S352, based on the instance name of the current atomic unit, look up the instance module mapping table to obtain the atomic module name bound to the current atomic unit; wherein, the instance module mapping table stores the mapping relationship between at least one atomic module name and its corresponding at least one instantiated instance name.
[0036] The instance module mapping table records the mapping relationship between each atomic module and its instantiated instances. For example, a mapping relationship might be: au_module_A:[au_1,au_2]. This instance module mapping table allows the system to quickly retrieve the name of the atomic module au_module_A bound to au_1 by querying au_1. By looking up the instance module mapping table, the system can quickly and accurately determine which atomic module the instance name originated from, further reducing the complexity of the lookup and avoiding errors caused by manual maintenance.
[0037] S353, based on the name of the atomic module bound to the current atomic unit, search the preset constraint template library to obtain the preset constraint sub-file; wherein, the constraint template library includes the preset constraint sub-file bound to each atomic module.
[0038] The preset constraint subfile predefines constraints such as clock constraints and timing constraints. Clock constraints include clock frequency, clock source, and clock domain partitioning. Timing constraints include minimum path delay between two signals and minimum path delay across clock domains.
[0039] It should be noted that the constraint template library strictly guarantees that multiple different atomic units instantiated from the same atomic module have the same preset constraint subfile, avoiding errors caused by manual writing and ensuring strict consistency of the generated comprehensive design constraint files.
[0040] The pre-built constraint template library can be stored externally or integrated into the script.
[0041] In one implementation, the pre-defined constraint template library is stored in an external file system and dynamically loaded by the generation script. That is, the pre-defined constraint template library is provided as an external file. As an example, the system pre-defines a template directory, where each atomic module corresponds to a pre-defined constraint sub-file. The generation script obtains this directory path by reading a configuration file or command-line parameters and searches for the matching pre-defined constraint sub-file based on the atomic module name. This approach decouples the script and the constraint template library, facilitating independent updates to the constraint template library and script reuse. For example, multiple projects can share the same script but use different constraint template libraries.
[0042] In one implementation, the pre-built constraint template library is integrated within the generation script and can be directly invoked at runtime without external input. As an example, the template library integrated within the generation script is implemented using a dictionary data structure. Each dictionary contains multiple entries, each with the atomic module name as the key and the complete content of a pre-defined constraint sub-file as the value. At runtime, the script directly indexes this dictionary by module name to retrieve the content of the constraint sub-file. This method requires no additional configuration, no external dependencies, and ensures consistency of the execution environment.
[0043] In one implementation, the preset constraint template library includes a mapping relationship with atomic module names as keys and the contents of constraint subfiles as values.
[0044] S354, Generate the constraint subfile for the current atomic unit according to the preset constraint subfile.
[0045] It should be noted that during the generation of the constraint subfile for the current atomic unit, the instance module mapping table improves the efficiency of retrieving preset constraint subfiles from the constraint template library. The setting of preset constraint subfiles further improves the generation efficiency, and the two work together to significantly enhance the overall efficiency of constraint subfile generation. Preset constraint subfiles also further ensure the strict consistency and correctness of the generated comprehensive design constraint files.
[0046] In one implementation, step S354, generating a constraint subfile for the current atomic unit based on the preset constraint subfile, further includes:
[0047] S3541, Based on the hierarchical position of the current atomic unit in the target module, the instance name of the current atomic unit and the names of its various levels are concatenated to generate the global path instance name of the current atomic unit.
[0048] The hierarchical position refers to the nested path of the current atomic unit within the hierarchical design structure of the target module. It is formed by sequentially connecting the names of the module instances traversed from the top-level module to the current atomic unit. As an example, if the global path instance name of the current atomic unit is au_name.moudle_a.singnal_a, then singnal_a is the instance name of the current atomic unit, mousel_a is the instance name of the parent node of the current atomic unit, and au_name is the parent node of mousel_a, i.e., the top-level module. Each atomic unit can be uniquely identified through its global path instance name, allowing for precise constraint configuration for each atomic unit.
[0049] S3542, Obtain at least one atomic module name from the preset constraint subfile.
[0050] It's important to note that the preset constraint subfile is written using atomic module names as placeholders. Once the atomic module is instantiated at a specific level, simply replacing the atomic module name with the actual global path instance name will generate a valid constraint. The placeholder itself is not the final valid path, but rather a marker to be replaced, used to reserve space in the preset constraint subfile, indicating that the atomic module name is temporarily used to represent the location that will eventually be replaced by the global path instance name.
[0051] S3543, replace each atomic module name in the preset constraint sub-file with the global path instance name of the current atomic unit, and generate the constraint sub-file of the current atomic unit.
[0052] In one implementation, replacement is performed using regular expression matching; other types of replacement methods also fall within the scope of protection of this invention.
[0053] It should be noted that generating the constraint subfile for the current atomic unit only requires replacing the atomic module name in the preset constraint subfile with the global path instance name of the current atomic unit. This not only ensures the strict consistency of the generated integrated design constraint file, but also significantly improves the efficiency of constraint subfile generation. Furthermore, it avoids human error and ensures the correctness of the constraint subfile.
[0054] S370 generates a comprehensive design constraint file for the current block based on the constraint subfiles of each atomic unit in the current block.
[0055] In one implementation, the synthesis design constraint file for the current block is formed by concatenating the constraint sub-files of each atomic unit in the current block. Concatenation refers to sequentially connecting the constraint sub-files of each atomic unit according to module dependencies or topological order to form a single constraint file for subsequent synthesis.
[0056] In summary, the method for generating a comprehensive design constraint file provided by this invention can automatically and unambiguously obtain the complete list of atomic units required for the current block without traversing the RTL source code, thanks to a pre-set target block list file and target block mapping file. This significantly improves the accuracy and efficiency of obtaining the atomic unit list. Furthermore, by combining the generation script to generate constraint sub-files for each atomic unit, the comprehensive design constraint file for the current block is obtained. Thus, the comprehensive design constraint file for the current block is generated efficiently without manual intervention, fundamentally solving the pain points of low efficiency and error susceptibility in traditional methods.
[0057] In one implementation, please refer to Figure 2 The S330 also includes:
[0058] S331, If the name of the current block is not in the target block list file, perform the following steps:
[0059] S3311, If the current block is not the last block, then perform the step of generating the integrated design constraint file for the next block.
[0060] It should be noted that if the name of the current block is not in the target block list file, it means that the current block does not include the atomic units of the target module, and therefore it is skipped.
[0061] S3312, If the current block is the last block, then the generation step of the synthesis design constraint file ends. That is, if the last block does not contain atomic units of the target module, it means that all blocks have been traversed, and the generation step ends.
[0062] Embodiments of the present invention also provide a non-transitory computer-readable storage medium that can be disposed in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiments, wherein the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiments.
[0063] Embodiments of the present invention also provide an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.
[0064] Embodiments of the present invention also provide a computer program product including program code, which, when the program product is run on an electronic device, causes the electronic device to perform the steps of the methods described above in various exemplary embodiments of the present invention.
[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0066] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.
Claims
1. A method for generating integrated design constraint files, characterized in that, The method includes the following steps: Receive multiple blocks corresponding to the chip design; For each block, perform the following steps to generate the integrated design constraint file: Get the name of the current block; The system queries a pre-set target block list file based on the name of the current block; wherein the target block list file includes a list of names of target blocks distributed across the target modules; if the name of the current block exists in the target block list file, the system queries a pre-set target block mapping file based on the name of the current block to obtain a list of atomic units corresponding to the current block; wherein the target block mapping file includes at least one mapping relationship, each mapping relationship associating a target block with its included list of atomic units, wherein an atomic unit is the smallest functional unit in the target module; The control generation script generates constraint sub-files for each atomic unit based on the list of atomic units corresponding to the current block; Generate the comprehensive design constraint file for the current block based on the constraint subfiles of each atomic unit in the current block.
2. The method according to claim 1, characterized in that, The control generation script generates constraint sub-files for each atomic unit based on the list of atomic units corresponding to the current block, including: For each atomic unit, the following steps are performed: Get the instance name of the current atomic unit; Based on the instance name of the current atomic unit, the name of the atomic module bound to the current atomic unit is obtained by looking up the instance module mapping table; wherein, the instance module mapping table stores the mapping relationship between at least one atomic module name and at least one corresponding instantiated instance name; The preset constraint template library is searched based on the name of the atomic module to which the current atomic unit is bound, and a preset constraint sub-file is obtained; wherein, the constraint template library includes a preset constraint sub-file corresponding to each module; Based on the preset constraint sub-file, generate the constraint sub-file for the current atomic unit.
3. The method according to claim 2, characterized in that, The step of generating a constraint subfile for the current atomic unit based on the preset constraint subfile further includes: Based on the hierarchical position of the current atomic unit in the target module, the instance name of the current atomic unit and the names of its various levels are concatenated to generate the global path instance name of the current atomic unit; Obtain at least one atomic module name from the preset constraint subfile; Replace each atomic module name in the preset constraint subfile with the global path instance name of the current atomic unit to generate the constraint subfile of the current atomic unit.
4. The method according to claim 2, characterized in that, The pre-set constraint template library is stored in an external file system and is dynamically loaded by the generation script.
5. The method according to claim 2, characterized in that, The pre-built constraint template library is integrated into the generated script and can be directly called at runtime.
6. The method according to claim 2, characterized in that, The pre-set constraint template library includes a mapping relationship with the atomic module name as the key and the content of the constraint sub-file as the value.
7. The method according to claim 1, characterized in that, After querying the preset target block list file based on the name of the current block, the process also includes: If the name of the current block is not in the target block list file, perform the following steps: If the current block is not the last block, then perform the step of generating the integrated design constraint file for the next block; If the current block is the last block, then the generation step of the integrated design constraint file ends.
8. The method according to claim 1, characterized in that, The integrated design constraint file of the current block is composed of constraint sub-files of each atomic unit in the current block.
9. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-8.
10. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 9.