Multi-junction edge-emitting semiconductor laser and preparation method thereof
By using alternating wet and dry etching methods, a self-aligned stepped ridge waveguide is gradually formed, solving the problems of cumbersome processes and high costs in the fabrication of multi-junction edge-emitting semiconductor lasers, and achieving the effects of simplifying the process and improving the yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-03-31
AI Technical Summary
Existing methods for fabricating multi-junction edge-emitting semiconductor lasers are cumbersome and costly. Multiple photolithography steps result in stringent requirements for alignment accuracy, large overlay errors, and a high risk of interface contamination, which affects the uniformity of device performance and yield.
A self-aligned stepped ridge waveguide is gradually formed by alternating wet and dry etching. Through the cycle of wet and dry etching, multiple steps are formed layer by layer downwards. The last round of etching removes the suspended tunnel layer, simplifying the process and reducing costs.
It greatly simplifies the process flow, reduces production costs, improves the consistency of device morphology and yield, and reduces environmental pollution and the consumption of photolithography resources.
Smart Images
Figure CN121769652A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of laser technology, and particularly relates to a multi-junction edge-emitting semiconductor laser and its fabrication method. Background Technology
[0002] Multi-junction edge-emitting semiconductor lasers (MILs) can achieve higher output power at lower operating currents by connecting multiple PN junctions in series in the vertical direction. They are widely used in fields such as fiber pumping, solid-state laser pumping, and material processing. To achieve efficient electrical connection between the PN junctions, tunnel junctions are usually grown between them.
[0003] In chip manufacturing, ridge waveguides need to be fabricated on the chip to form current injection channels and control optical modes. For multi-junction structures, stepped ridge waveguides can optimize current spread and optical field confinement. Currently, the standard method for fabricating such structures involves multiple patterning steps, each requiring photolithography and etching. That is, for each step, a complete process of resist coating, exposure, development, etching, and resist removal is performed, with the step sculpted by precisely controlling the depth of each etching step. This traditional method has the following inherent drawbacks: cumbersome and costly process; multiple photolithography steps lead to long production cycles and consume large amounts of photoresist and masks; stringent alignment accuracy requirements; overlay errors between multiple photolithography steps can compromise the accuracy of the step morphology, affecting device performance uniformity and yield; high risk of interface contamination; frequent photoresist coating and removal can introduce contaminants; and environmental pollution, generating large amounts of chemical waste. Therefore, there is an urgent need in the field for a fabrication method that simplifies the process, reduces costs, and improves process stability. Summary of the Invention
[0004] In view of this, the present invention aims to provide a multi-junction edge-emitting semiconductor laser and a method for fabricating the same, which at least helps to reduce the difficulty of fabricating multi-junction edge-emitting semiconductor lasers.
[0005] To achieve the above objectives, the technical solution created by this invention is implemented as follows: This invention provides a method for fabricating a multi-junction edge-emitting semiconductor laser, comprising: providing a substrate; forming a stacked structure on the substrate, the stacked structure including M PN junction layers stacked from bottom to top, a tunnel junction layer located between two adjacent PN junction layers, and a capping layer located at the top layer, wherein the material system of the PN junction layers is different from that of the tunnel junction layers, and M is an integer greater than 1; forming a mask layer with etching windows on the surface of the stacked structure away from the substrate; performing M rounds of etching steps, each round of etching step including a wet etching process and a dry etching process performed sequentially, wherein the wet etching process isotropically etches the capping layer and the PN junction layers through the etching windows, and the dry etching process longitudinally etches the tunnel junction layer through the etching windows; after the M rounds of etching steps, trenches are formed in the stacked structure corresponding to the etching windows, and the side of the stacked structure facing the trenches is stepped.
[0006] Furthermore, the size of the trench enclosed by the upper PN junction layer is larger than the size of the trench enclosed by the lower PN junction layer, and the size of the trench enclosed by the tunnel junction layer is the same as the size of the trench enclosed by the lower PN junction layer adjacent to the tunnel junction layer.
[0007] Furthermore, the etching rate of the wet etching process on the cap layer and PN junction layer is greater than that on the tunnel junction layer; the ratio of the etching rate of the wet etching process on the cap layer and PN junction layer to the etching rate of the wet etching process on the tunnel junction layer is greater than 99:1.
[0008] Furthermore, after completing the wet etching process of the final etching step and before performing the dry etching process of the final etching step, the method for fabricating a multi-junction edge-emitting semiconductor laser also includes: removing the mask layer. The dry etching process in the final etching step is used to remove the tunnel junction layer suspended on the side of the trench.
[0009] Furthermore, the mask layer has at least two elongated etching windows spaced apart. After the M-round etching step, two trenches spaced apart are formed in the stacked structure. The stacked structure between the two trenches serves as a stepped ridge waveguide for a multi-junction edge-emitting semiconductor laser.
[0010] Furthermore, the PN junction layer is a GaAs system, and the tunnel junction layer is an InP system.
[0011] Furthermore, the etching liquid in the wet etching process is a mixed solution of phosphoric acid, hydrogen peroxide, and water. The volume ratio of phosphoric acid, hydrogen peroxide, and water in the mixed solution is a:b:c, where a is in the range of 0.5 to 2, b is in the range of 0.5 to 2, and c is in the range of 3 to 10.
[0012] Furthermore, the dry etching process is an inductively coupled plasma etching process, and the etching gases in the dry etching process include chlorine and argon.
[0013] Furthermore, M=3, the stacked structure includes three PN junction layers stacked from bottom to top, a tunnel junction layer between adjacent PN junction layers, and a capping layer on top. The three PN junction layers stacked from bottom to top are the first PN junction, the second PN junction, and the third PN junction. The tunnel junction layer between the first and second PN junctions is the first tunnel junction, and the tunnel junction layer between the second and third PN junctions is the second tunnel junction. Three etching steps are performed. The first etching step uses a wet etching process to remove the capping layer and the third PN junction corresponding to the etching window, and then... The second etching step involves removing the second tunnel junction corresponding to the etching window using a dry etching process. The second etching step first uses a wet etching process to remove the second PN junction corresponding to the etching window, while simultaneously performing lateral etching on the third PN junction exposed on the trench sidewall. Then, a dry etching process is used to remove the first tunnel junction corresponding to the etching window. The third etching step first uses a wet etching process to remove the first PN junction corresponding to the etching window, while simultaneously performing lateral etching on the third and second PN junctions exposed on the trench sidewall. Finally, a dry etching process is used to remove the first and second tunnel junctions suspended on the trench side.
[0014] Another aspect of this invention provides a multi-junction edge-emitting semiconductor laser, which is formed using the aforementioned multi-junction edge-emitting semiconductor laser fabrication method. The multi-junction edge-emitting semiconductor laser includes: a substrate; a stacked structure on the substrate, the stacked structure including M PN junction layers stacked from bottom to top, a tunnel junction layer located between two adjacent PN junction layers, and a capping layer located on the top layer, wherein the material system of the PN junction layers is different from the material system of the tunnel junction layers, and M is an integer greater than 1; the stacked structure has trenches, and the side of the stacked structure facing the trenches is stepped.
[0015] Compared with existing technologies, the present invention achieves the following beneficial effects: In the fabrication method of the multi-junction edge-emitting semiconductor laser provided by the present invention, wet etching of the PN junction layer and dry etching of the tunnel junction layer are alternately cycled. The two etching techniques are used to selectively etch the material, gradually forming a self-aligned step-shaped ridge waveguide. The dry etching process in the last etching step removes the residual tunnel junction layer suspended at each level of the step. Through the cycle of wet etching and dry etching, self-aligned multi-level steps can be formed layer by layer from the top layer downwards. The fabrication method of the multi-junction edge-emitting semiconductor laser provided by the present invention solves the problems of cumbersome process, difficult alignment and high cost caused by multiple photolithography in traditional technology. It greatly simplifies the process flow, reduces production costs and improves the consistency of device morphology and yield. Attached Figure Description
[0016] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figures 1 to 6 A schematic diagram illustrating the fabrication process of the multi-junction edge-emitting semiconductor laser described in the embodiments of the present invention. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.
[0018] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0019] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0021] The invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0022] Reference 1 to Figure 6 This invention provides a method for fabricating a multi-junction edge-emitting semiconductor laser, comprising: providing a substrate 10; forming a stacked structure 40 on the substrate 10, the stacked structure 40 including M PN junction layers stacked from bottom to top, a tunnel junction layer located between two adjacent PN junction layers, and a capping layer 16 located at the top layer, wherein the material system of the PN junction layers is different from that of the tunnel junction layers, and M is an integer greater than 1; forming a mask layer 18 with etching windows on the surface of the stacked structure 40 away from the substrate 10; performing M rounds of etching steps, each round of etching steps including a wet etching process and a dry etching process performed sequentially, wherein the wet etching process isotropically etches the capping layer 16 and the PN junction layers through the etching windows, and the dry etching process longitudinally etches the tunnel junction layer through the etching windows; after the M rounds of etching steps, a trench 20 is formed in the stacked structure 40 corresponding to the etching windows, and the side of the stacked structure 40 facing the trench 20 is stepped.
[0023] Among them, the mask layer 18 is a hard mask that serves as an etch barrier layer. The wet etching process is used to selectively etch the capping layer 16 and the PN junction layer, and naturally stops at the tunnel junction layer below.
[0024] Furthermore, the size of the trench enclosed by the upper PN junction layer is larger than the size of the trench enclosed by the lower PN junction layer, and the size of the trench enclosed by the tunnel junction layer is the same as the size of the trench enclosed by the lower PN junction layer adjacent to the tunnel junction layer.
[0025] Furthermore, the etching rate of the wet etching process on the capping layer 16 and the PN junction layer is greater than that on the tunnel junction layer; the ratio of the etching rate of the wet etching process on the capping layer 16 and the PN junction layer to the etching rate of the wet etching process on the tunnel junction layer is greater than 99:1.
[0026] Furthermore, after completing the final wet etching process and before performing the final dry etching process, the multi-junction edge-emitting semiconductor laser fabrication method also includes: removing the mask layer 18. The dry etching process in the final etching step is used to remove the suspended tunnel junction layer on the side of the trench 20. It is understood that because the wet etching process laterally etches the PN junction layer below the tunnel junction layer, the side of the trench 20 has a suspended residual tunnel junction layer.
[0027] Furthermore, the mask layer 18 has at least two elongated etching windows spaced apart. After the M-round etching step, two trenches 20 spaced apart are formed in the stacked structure 40. The stacked structure 40 between the two trenches 20 serves as a stepped ridge waveguide 30 for a multi-junction edge-emitting semiconductor laser.
[0028] Furthermore, the PN junction layer is a GaAs system, and the tunnel junction layer is an InP system.
[0029] Furthermore, the etching liquid in the wet etching process is a mixed solution of phosphoric acid, hydrogen peroxide, and water. The volume ratio of phosphoric acid, hydrogen peroxide, and water in the mixed solution is a:b:c, where a is in the range of 0.5 to 2, b is in the range of 0.5 to 2, and c is in the range of 3 to 10. In some examples, a=1, b=1, and c=5.
[0030] Furthermore, the dry etching process is an inductively coupled plasma etching process, and the etching gases in the dry etching process include chlorine and argon.
[0031] Furthermore, M=3, and the stacked structure 40 includes three PN junction layers stacked from bottom to top, a tunnel junction layer located between two adjacent PN junction layers, and a capping layer 16 on the top layer. The three PN junction layers stacked from bottom to top are a first PN junction 11, a second PN junction 13, and a third PN junction 15. The tunnel junction layer located between the first PN junction 11 and the second PN junction 13 is the first tunnel junction 12, and the tunnel junction layer located between the second PN junction 13 and the third PN junction 15 is the second tunnel junction 14. Three etching steps are performed. In the first etching step, a wet etching process is used to remove the capping layer 16 and the third PN junction 15 corresponding to the etching window, thereby exposing the second tunnel junction 14 corresponding to the etching window. Then, a dry etching process is used to remove the second tunnel junction 14 corresponding to the etching window. The first PN junction 14 is exposed, thus exposing the second PN junction 13 corresponding to the etched window. The second etching step first uses a wet etching process to remove the second PN junction 13 corresponding to the etched window, and at the same time performs lateral etching on the third PN junction 15 exposed on the sidewall of the trench 20, thus exposing the first tunnel junction 12 corresponding to the etched window. Then, a dry etching process is used to remove the first tunnel junction 12 corresponding to the etched window, thus exposing the first PN junction 11 corresponding to the etched window. The third etching step first uses a wet etching process to remove the first PN junction 11 corresponding to the etched window, and at the same time performs lateral etching on the third PN junction 15 and the second PN junction 13 exposed on the sidewall of the trench 20. Then, a dry etching process is used to remove the first tunnel junction 12 and the second tunnel junction 14 suspended on the side of the trench 20.
[0032] In some embodiments, the mask layer 18 includes at least one of silicon oxide and silicon nitride. An initial mask layer 17 can be formed by plasma-enhanced chemical vapor deposition, and then the initial mask layer 17 can be patterned by photolithography and etching processes to form a mask layer 18 with etching windows.
[0033] In some embodiments, the substrate 10 may be made of GaAs, and the corresponding film layers may be grown sequentially from bottom to top by a metal-organic chemical vapor deposition process to form a stacked structure 40.
[0034] In some embodiments, each PN junction layer includes an n-type confinement layer, an active region, and a p-type confinement layer stacked sequentially from bottom to top.
[0035] In some embodiments, the capping layer 16 is a heavily doped p-type GaAs layer.
[0036] In some embodiments, the specific steps after forming the stacked structure 40 may be as follows: a silicon oxide thin film with a thickness in the range of 200nm to 300nm is grown as an initial mask layer 17 using plasma-enhanced chemical vapor deposition. Subsequently, photoresist is spin-coated on the initial mask layer 17, and a strip pattern of a ridge waveguide is formed by a single ultraviolet lithography and development. Using the photoresist as a mask, reactive ion etching based on gases such as CF4 is used to accurately transfer the strip pattern to the initial mask layer 17 below to form a patterned mask layer. Finally, residual photoresist is completely removed by oxygen plasma ashing and organic solvent cleaning.
[0037] In some embodiments, M=3, and the M-round etching steps are as follows: The sample with the mask layer is immersed in a specific etching solution for wet etching. The etching solution is a mixed solution of phosphoric acid, hydrogen peroxide, and deionized water. The etching solution has a high isotropic etching rate for GaAs material, but an extremely low etching rate for InP material and mask layer 18. The etching solution etches away the third PN junction 15 and capping layer 16 that are not covered by the mask layer. After longitudinally etching away the third PN junction 15 and capping layer 16, the etching automatically stops on the surface of the second tunnel junction 14. At the same time, laterally, the etching solution performs lateral etching on the third PN junction 15 and capping layer 16, causing the portion of the third PN junction 15 and capping layer 16 below the mask layer 18 adjacent to the trench 20 to be hollowed out, forming the prototype of the first step. Subsequently, dry etching is used to remove the mask layer 18. The second tunnel junction 14 corresponding to the etching window is then subjected to a second round of wet etching and dry etching. The second round of wet etching automatically stops on the surface of the first tunnel junction 12 and forms a deeper side etching on the second PN junction 13, thereby defining the second step. The second round of dry etching removes the first tunnel junction 12 corresponding to the etching window on the mask layer 18, exposing the bottom first PN junction 11. Then, a third round of wet etching and dry etching is performed. The third round of wet etching etches the first PN junction 11 to the required depth, forming the third step. At this time, at the step of each step, a section of tunnel junction remnant with the same width as the side etching of the upper layer is suspended. These remnant tunnel junctions will hinder the longitudinal transmission of current in the actual device, so they are removed by the third round of dry etching.
[0038] In some embodiments, after the third round of wet etching and before the third round of dry etching, the preparation method further includes: removing the mask layer, which can be done using a buffered oxide etchant to remove the mask layer 18, resulting in a structure with tunnel junction residue on the sidewalls after the mask layer is removed.
[0039] The third round of dry etching is the final global dry etching process. The third round of dry etching does not have precise endpoint control. It is only necessary to ensure that the etching time is sufficient to completely remove all the remaining parts of the laterally suspended tunnel junctions. The third round of dry etching is anisotropic and can effectively bombard and etch away these suspended tunnel junctions from the side without significantly affecting the already formed step body. After this step is completed, the final stepped ridge waveguide 30 with clean sidewalls, complete structure, and can be used for efficient current injection is obtained.
[0040] In some embodiments, subsequent processes also include: forming a passivation layer, photolithography to open windows, evaporating p-side ohmic contact electrodes, evaporating n-side ohmic contact electrodes, alloying, cleaving, packaging, and other standard processes, finally completing the fabrication of the multi-junction edge-emitting semiconductor laser.
[0041] This invention revolutionarily simplifies the multiple photolithography steps required to fabricate the stepped ridge waveguide 30 into a single step, significantly shortening the process cycle and reducing production costs. Furthermore, it utilizes the intrinsic etching selectivity of the material to achieve natural stopping and high-precision self-alignment, completely eliminating overlay errors and improving morphological consistency and yield. In addition, it saves photolithography resources, reduces chemical waste and process steps, lowers costs, and also reduces environmental pollution and surface contamination risks. Moreover, the width of each step can be flexibly designed by adjusting the wet etching time, resulting in strong morphological control.
[0042] In another aspect, the present invention provides a multi-junction edge-emitting semiconductor laser, which is formed using the aforementioned multi-junction edge-emitting semiconductor laser fabrication method. It should be noted that the same or corresponding parts as described above can be referred to the aforementioned embodiments, and will not be repeated here.
[0043] The multi-junction edge-emitting semiconductor laser includes: a substrate 10; a stacked structure 40 on the substrate 10, the stacked structure 40 including M PN junction layers stacked from bottom to top, a tunnel junction layer located between two adjacent PN junction layers, and a capping layer 16 located on the top layer, the material system of the PN junction layers is different from the material system of the tunnel junction layer, and M is an integer greater than 1; the stacked structure 40 has a trench 20, and the side of the stacked structure 40 facing the trench 20 is stepped.
[0044] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.
[0045] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.
Claims
1. A method for fabricating a multi-junction edge-emitting semiconductor laser, characterized in that, The application relates to a multi-junction edge-emitting semiconductor laser preparation method. The application comprises the following steps: providing a substrate; forming a stack structure on the substrate, the stack structure comprising M layers of PN junction layers, tunnel junction layers between adjacent two layers of PN junction layers and a cover layer on the top layer, the material system of the PN junction layers being different from that of the tunnel junction layers, M being an integer greater than 1; forming a mask layer with etching windows on the surface of the stack structure away from the substrate; 2. The method of claim 1, wherein performing M rounds of etching steps, each round of etching step comprising a wet etching process and a dry etching process performed in sequence, the wet etching process performing isotropic etching on the cover layer and the PN junction layers through the etching windows, the dry etching process performing longitudinal etching on the tunnel junction layers through the etching windows, and after the M rounds of etching steps, a groove is formed in the stack structure corresponding to the etching windows, and the side of the stack structure towards the groove is in a stepped shape.
3. The method of claim 1, wherein the method further comprises: The size of the part of the groove surrounded by the PN junction layer on the upper layer is greater than that of the part of the groove surrounded by the PN junction layer on the lower layer, and the size of the part of the groove surrounded by the tunnel junction layer is the same as that of the part of the groove surrounded by the lower PN junction layer adjacent to the tunnel junction layer. The etching rate of the wet etching process on the cover layer and the PN junction layers is greater than that on the tunnel junction layers; 4. The method of claim 1, wherein The ratio of the etching rate of the wet etching process on the cover layer and the PN junction layers to that on the tunnel junction layers is greater than 99:
1.
5. The method of claim 1, wherein After the wet etching process of the last round of etching steps is completed, before the dry etching process of the last round of etching steps is performed, the multi-junction edge-emitting semiconductor laser preparation method further comprises: removing the mask layer, and the dry etching process in the last round of etching steps is used for removing the suspended tunnel junction layer on the side of the groove.
6. The method of claim 1, wherein The mask layer has at least two long-strip-shaped etching windows arranged at intervals, and after the M rounds of etching steps, two grooves are formed in the stack structure arranged at intervals, and the stack structure between the two grooves serves as a stepped ridge-shaped waveguide of the multi-junction edge-emitting semiconductor laser.
7. The method of claim 1 or 6, wherein The PN junction layer is of a GaAs system, and the tunnel junction layer is of an InP system.
8. The method of claim 1 or 6, wherein The etching liquid of the wet etching process is a mixed solution of phosphoric acid, hydrogen peroxide and water, and the ratio of the volume of phosphoric acid, the volume of hydrogen peroxide and the volume of water in the mixed solution is a:b:c, wherein a is in the range of 0.5-2, b is in the range of 0.5-2, and c is in the range of 3-10.
9. The method of claim 1, wherein The dry etching process is an inductively coupled plasma etching process, and the etching gas of the dry etching process comprises chlorine and argon. M=3, the stack structure comprises 3 layers of PN junction layers, tunnel junction layers between adjacent two layers of PN junction layers and a cover layer on the top layer, the 3 layers of PN junction layers from bottom to top are a first PN junction, a second PN junction and a third PN junction, the tunnel junction layer between the first PN junction and the second PN junction is a first tunnel junction, and the tunnel junction layer between the second PN junction and the third PN junction is a second tunnel junction. The first round of etching steps removes the cap layer and the third PN junction corresponding to the etching window by using a wet etching process, and then removes the second tunnel junction corresponding to the etching window by using a dry etching process; The second round of etching steps removes the second PN junction corresponding to the etching window by using a wet etching process, and then removes the first tunnel junction corresponding to the etching window by using a dry etching process; The third round of etching steps removes the first PN junction corresponding to the etching window by using a wet etching process, and then removes the first tunnel junction and the second tunnel junction corresponding to the etching window by using a dry etching process.
10. A multi-junction edge-emitting semiconductor laser, characterized by The multi-junction edge-emitting semiconductor laser is formed by using the multi-junction edge-emitting semiconductor laser preparation method in any one of claims 1 to 9, and the multi-junction edge-emitting semiconductor laser comprises: a substrate; a stack structure on the substrate, the stack structure comprising M layers of PN junction layers, tunnel junction layers between adjacent two layers of PN junction layers, and a cap layer on the top layer, the material system of the PN junction layer being different from the material system of the tunnel junction layer, and M being an integer greater than 1; the stack structure having a groove, and the side of the stack structure facing the groove being stepped.