Electronic component including stacked plurality of semiconductor wafers and method of manufacturing same

Abstract

The invention provides an electronic component and a preparation method thereof. The electronic component comprises a first semiconductor wafer, a second semiconductor wafer, a third semiconductor wafer, a fourth semiconductor wafer and a fifth semiconductor wafer. The second semiconductor wafer is stacked on the first semiconductor wafer and electrically connected with the first semiconductor wafer through hybrid bonding. The fourth semiconductor wafer is stacked on the third semiconductor wafer and electrically connected with the third semiconductor wafer through hybrid bonding. The third semiconductor wafer is stacked on the second semiconductor wafer and electrically connected with the second semiconductor wafer through a plurality of bumps. The fifth semiconductor chip is arranged below the first semiconductor chip and is electrically connected with the first semiconductor chip through a plurality of electronic connectors.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 901,151 (i.e., priority date "September 30, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to an electronic component and a method for fabricating the same. More particularly, it relates to an electronic component comprising stacked semiconductor wafers and a method for fabricating the same. Background Technology

[0003] Semiconductor electronic components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor electronic components continues to shrink to meet the ever-increasing demands for computing power. However, the risks associated with this shrinkage are becoming increasingly frequent and impactful. Therefore, challenges remain in improving quality, yield, performance, and reliability while reducing complexity.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides an electronic component including a first semiconductor wafer; a second semiconductor wafer stacked on the first semiconductor wafer and electrically connected to the first semiconductor wafer via hybrid bonding; a third semiconductor wafer stacked on the second semiconductor wafer and electrically connected to the second semiconductor wafer via a plurality of bumps; a fourth semiconductor wafer stacked on the third semiconductor wafer and electrically connected to the third semiconductor wafer via hybrid bonding; and a fifth semiconductor wafer disposed below the first semiconductor wafer and electrically connected to the first semiconductor wafer via a plurality of electronic connectors.

[0006] Another embodiment of this disclosure provides an electronic component including a first component, a second component, a base semiconductor wafer, and a carrier structure. The first component includes a first semiconductor wafer and a second semiconductor wafer stacked on the first semiconductor wafer, the second semiconductor wafer being electrically connected to the first semiconductor wafer via hybrid bonding. The second component includes a third semiconductor wafer and a fourth semiconductor wafer stacked on the third semiconductor wafer, the fourth semiconductor wafer being electrically connected to the third semiconductor wafer via hybrid bonding. The base semiconductor wafer is disposed below the first component and electrically connected to the first component via a plurality of electronic connectors. The carrier structure is disposed above the second component and electrically connected to the second component via hybrid bonding. The second component is electrically connected to the first component via a plurality of bumps. The first component is electrically connected to the base semiconductor wafer via a plurality of electronic connectors.

[0007] Another embodiment of this disclosure provides a method for fabricating an electronic component. The method includes forming a first assembly comprising a first semiconductor wafer, a second semiconductor wafer, and a plurality of electronic connectors, wherein the second semiconductor wafer is stacked on the first semiconductor wafer, and the electronic connectors are connected to the first semiconductor wafer; forming a second assembly comprising a third semiconductor wafer, a fourth semiconductor wafer, and a plurality of bumps, wherein the fourth semiconductor wafer is stacked on the third semiconductor wafer, and the bumps are connected to the third semiconductor wafer; and forming a third assembly comprising a fifth semiconductor wafer and a plurality of external connectors, wherein the third assembly includes a fifth lower structure and a fifth upper structure, and the external connectors are connected to the fifth lower structure. The method comprises: forming a carrier structure including a carrier substrate, a plurality of through-semiconductor vias penetrating the carrier substrate, a plurality of conductive plates located on the carrier substrate and the through-semiconductor vias, and a bonding layer located on the carrier substrate and covering the conductive plates; electrically connecting the second component to the first component via the plurality of bumps; electrically connecting the first component to the third component via a plurality of electronic connectors; encapsulating the first component, the second component, and the third component using a peripheral package surrounding the first component, the second component, and located on the third component; and performing a hybrid bonding to electrically connect the carrier structure to the second component and the peripheral package.

[0008] The technical features and advantages of this disclosure have been broadly summarized above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0009] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0010] Figure 1 This is a cross-sectional schematic diagram illustrating electronic components of some embodiments of the present disclosure.

[0011] Figure 2 This is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0012] Figures 3 to 11 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0013] Figures 12 to 17 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0014] Figures 18 to 20 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0015] Figure 21 This is a cross-sectional schematic diagram illustrating a stage of an electronic device manufacturing method according to some embodiments of the present disclosure.

[0016] Figure 22 This is an enlarged schematic diagram illustrating some embodiments of the present disclosure. Figure 21 Through-hole semiconductor via.

[0017] Figures 23 to 24 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0018] Figures 25 to 28 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0019] Figure 29This is a flowchart illustrating methods for fabricating electronic components according to some embodiments of this disclosure.

[0020] The annotations in the attached figures are explained as follows:

[0021] 1: First Semiconductor Wafer

[0022] 1': First wafer

[0023] 1": Unit

[0024] 2: Second semiconductor wafer

[0025] 2′: Second wafer

[0026] 2": Unit

[0027] 3: Third semiconductor wafer

[0028] 3": Unit

[0029] 4: Fourth Semiconductor Wafer

[0030] 5: Fifth Semiconductor Wafer

[0031] 5': Fifth semiconductor chip

[0032] 6: Electronic components

[0033] 8: Intermediary layer

[0034] 9: Semiconductor Structure

[0035] 10: First base

[0036] 11: Lower surface

[0037] 11": Lower surface

[0038] 12: Upper surface

[0039] 12": Upper surface

[0040] 13: Side surface

[0041] 13": Side surface

[0042] 14: First conductive structure

[0043] 15: First lower structure

[0044] 16: First upper structure

[0045] 17: First conductive via

[0046] 18: First package

[0047] 19: Divider

[0048] 20: Second base

[0049] 21: Lower surface

[0050] 22: Upper surface

[0051] 23: Side surface

[0052] 24: Second conductive structure

[0053] 25: Second lower structure

[0054] 26: Second upper structure

[0055] 27: Second conductive via

[0056] 29: Divider line

[0057] 30: Third base

[0058] 31: Lower surface

[0059] 31": Lower surface

[0060] 32: Upper surface

[0061] 32": Upper surface

[0062] 33: Side surface

[0063] 33": Side surface

[0064] 34: Third conductive structure

[0065] 35: Third lower structure

[0066] 36: Third upper structure

[0067] 37: Third conductive via

[0068] 38: Third package

[0069] 40: Fourth base

[0070] 41: Lower surface

[0071] 42: Upper surface

[0072] 43: Side surface

[0073] 44: Fourth conductive structure

[0074] 45: Fourth lower structure

[0075] 49: Divider

[0076] 50: Fifth base

[0077] 51: Lower surface

[0078] 52: Upper surface

[0079] 53: Side surface

[0080] 55-2: Second Surface

[0081] 54: Fifth conductive structure

[0082] 55-1: First surface

[0083] 55: Fifth lower structure

[0084] 56: Fifth upper structure

[0085] 57: Fifth conductive via

[0086] 61: Bump

[0087] 62: Lower filler

[0088] 63: Electronic connector

[0089] 64: Protective Materials

[0090] 65: Peripheral package

[0091] 66: External connector

[0092] 71: First Component

[0093] 72: Second Component

[0094] 73: Third Component

[0095] 80: Base

[0096] 84: Conductive Structure

[0097] 85: Upper Structure

[0098] 87: Conductive via

[0099] 92: Semiconductor components

[0100] 94: Solder

[0101] 96: External Connector

[0102] 101: First Surface

[0103] 102: Second Surface

[0104] 151: First lower dielectric layer

[0105] 152: First lower solder pad

[0106] 161: First upper dielectric layer

[0107] 162: First upper solder pad

[0108] 181: First Surface

[0109] 182: Second Surface

[0110] 201: First Surface

[0111] 202: Second Surface

[0112] 251: Second lower dielectric layer

[0113] 252: Second lower solder pad

[0114] 261: Second upper dielectric layer

[0115] 262: Second upper solder pad

[0116] 351: Third lower dielectric layer

[0117] 352: Third lower solder pad

[0118] 361: Third upper dielectric layer

[0119] 362: Third upper solder pad

[0120] 381: First Surface

[0121] 382: Second Surface

[0122] 401: First Surface

[0123] 451: Fourth lower dielectric layer

[0124] 452: Fourth lower solder pad

[0125] 501: First Surface

[0126] 502: Second Surface

[0127] 503: Through-hole opening

[0128] 510: Fifth grain

[0129] 511: Wire

[0130] 513: Contact pad

[0131] 551: Passivation layer

[0132] 552: Conductive layer

[0133] 561: Fifth upper dielectric layer

[0134] 562: Fifth upper solder pad

[0135] 581: Part One

[0136] 582: Part Two

[0137] 700: Carrier Structure

[0138] 700: Carrier Structure

[0139] 701: Carrier substrate

[0140] 701TS: Top Surface

[0141] 705: Through-semiconductor via

[0142] 705TS: Top surface

[0143] 707: Conductive plate

[0144] 709: Bonding layer

[0145] 711: Upper surface

[0146] 713: Lower surface

[0147] 715: Side surface

[0148] 801: Intermediate bonding layer

[0149] 851: Dielectric layer

[0150] 852: Solder pad

[0151] 900: Preparation Method

[0152] AL: Adhesive layer

[0153] BL: Barrier Layer

[0154] FL: Fill layer

[0155] HDU: Heat dissipation unit

[0156] IL: Isolation layer

[0157] SL: Seed layer

[0158] S901: Steps

[0159] S902: Steps

[0160] S903: Steps

[0161] S904: Steps

[0162] S905: Steps

[0163] S906: Steps. Detailed Implementation

[0164] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0165] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0166] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0167] Figure 1 This is a cross-sectional schematic diagram illustrating electronic component 6 in some embodiments of this disclosure. Please refer to... Figure 1In some embodiments, electronic component 6 can be defined as a semiconductor electronic component or semiconductor electronic structure comprising a plurality of semiconductor wafers arranged in a stacked configuration. Therefore, electronic component 6 can be a stacked structure having a plurality of stacked memory elements (e.g., dynamic random access memory (DRAM)). For example, electronic component 6 can be high bandwidth memory (HBM). In some embodiments, electronic component 6 may include a first component 71 (e.g., including a first semiconductor wafer 1 and a second semiconductor wafer 2), a second component 72 (e.g., including a third semiconductor wafer 3 and a fourth semiconductor wafer 4), a third component 73 (e.g., including a fifth semiconductor wafer 5 and a plurality of external connectors 66), a plurality of bumps 61, a filler 62, a plurality of electronic connectors 63, a protective material 64, a peripheral package 65, and a carrier structure 700.

[0168] The first semiconductor wafer 1 may have a lower surface 11 (e.g., a first surface) and an upper surface 12 (e.g., a second surface), and may have a side surface 13 extending between the lower surface 11 and the upper surface 12. The first semiconductor wafer 1 may include a first base 10, a first conductive structure 14, a first lower structure 15, a first upper structure 16, a plurality of first conductive vias 17, and a first package 18. The first semiconductor wafer 1 may be a memory wafer, such as a dynamic random access memory (DRAM) wafer.

[0169] For example, the first base 10 may be a semiconductor substrate, which may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the first base 10 may include an insulator-on-semiconductor substrate, such as an insulator-on-silicon (SOI) substrate, an insulator-on-germanium (SGOI) substrate, or an insulator-on-germanium (GOI) substrate. The first base 10 may have a first surface 101 (e.g., a lower surface) and a second surface 102 (e.g., an upper surface) opposite to the first surface 101.

[0170] The first conductive structure 14 may be disposed on a first surface 101 (e.g., the lower surface) of the first base 10. For example, in some embodiments, the first conductive structure 14 may include a plurality of front-end line (FEOL) elements, including resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof. In some embodiments, the first conductive structure 14 may also include at least one back-end line (BEOL) interconnect pattern, such as a plurality of patterned circuit layers electrically connected to the FEOL elements. In some embodiments, the first conductive structure 14 may also include at least one dielectric layer or at least one dielectric structure that may be used to cover the FEOL elements and the BEOL interconnect pattern.

[0171] A first conductive via 17 may extend through the first base 10 and be electrically connected to the first conductive structure 14. In some embodiments, the bottom end of the first conductive via 17 may extend beyond the first surface 101 (e.g., the lower surface) of the first base 10 and may extend into the first conductive structure 14. In some embodiments, the first conductive via 17 may be a single-wafer structure, and a length of the first conductive via 17 may be greater than a thickness of the first base 10. In some embodiments, an upper surface of the first conductive via 17 may be substantially coplanar with a second surface 102 (e.g., the upper surface) of the first base 10. In some embodiments, the upper surface of the first conductive via 17 may be exposed through the second surface 102 (e.g., the upper surface) of the first base 10.

[0172] A first lower structure 15 may be disposed on a first conductive structure 14. The first lower structure 15 may be a hybrid bonding (HB) structure or a solder bonding structure, and may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower dielectric layer 151 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each first lower pad 152 may be an HB pad and may include Cu or Al. The first lower pads 152 may be embedded in the first lower dielectric layer 151 and may be exposed through the first lower dielectric layer 151. The first lower pads 152 may be surrounded by the first lower dielectric layer 151. The first lower pads 152 may be electrically connected to a BEOL interconnect pattern of the first conductive structure 14. In some embodiments, the first lower pads 152 may be electrically connected to a first conductive via 17 via the first conductive structure 14.

[0173] In some embodiments, a lower surface of the first lower solder pad 152 may be substantially aligned with a lower surface of the first lower dielectric layer 151. In some embodiments, the lower surface of the first lower solder pad 152 may be exposed through the lower surface of the first lower dielectric layer 151. In some embodiments, an upper surface of the first lower solder pad 152 may be substantially aligned with an upper surface of the first lower dielectric layer 151. In some embodiments, the upper surface of the first lower solder pad 152 may contact the first conductive structure 14. In some embodiments, a thickness of the first lower solder pad 152 may be substantially equal to a thickness of the first lower dielectric layer 151.

[0174] The first upper structure 16 may be disposed on the second surface 102 (e.g., the upper surface) of the first base 10. The first upper structure 16 may be an HB structure and may include a first upper dielectric layer 161 and a plurality of first upper pads 162.

[0175] The first upper dielectric layer 161 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each first upper pad 162 may be an HB pad and may include Cu or Al. The first upper pad 162 may be embedded in the first upper dielectric layer 161 and may be exposed through the first upper dielectric layer 161. The first upper pad 162 may be surrounded by the first upper dielectric layer 161. The first upper pad 162 may be electrically connected to the first conductive via 17. In some embodiments, the first upper pad 162 may directly contact the first conductive via 17. The first upper pad 162 may be electrically connected to the first lower pad pad 152 via the first conductive via 17 and the first conductive structure 14.

[0176] In some embodiments, an upper surface of the first upper solder pad 162 may be substantially aligned with an upper surface of the first upper dielectric layer 161. In some embodiments, the upper surface of the first upper solder pad 162 may be exposed through the upper surface of the first upper dielectric layer 161. In some embodiments, a lower surface of the first upper solder pad 162 may be substantially aligned with a lower surface of the first upper dielectric layer 161. In some embodiments, the lower surface of the first upper solder pad 162 may contact the first conductive via 17. In some embodiments, a thickness of the first upper solder pad 162 may be substantially equal to a thickness of the first upper dielectric layer 161.

[0177] A first encapsulation member 18 may be disposed around a first base 10, a first conductive structure 14, a first lower structure 15, and a first upper structure 16. The first encapsulation material 18 may include a molded part with or without fillers. In some embodiments, one side surface of the first base 10, one side surface of the first conductive structure 14, one side surface of the first lower structure 15, and one side surface of the first upper structure 16 may be aligned with each other or coplanar. In some embodiments, the first encapsulation member 18 may cover and contact the side surfaces of the first base 10, the first conductive structure 14, the first lower structure 15, and the first upper structure 16.

[0178] In some embodiments, the lower surface 11 of the first semiconductor wafer 1 may include the lower surface of the first lower bonding pad 152, the lower surface of the first lower dielectric layer 151, and the lower surface of the first package 18. The upper surface 12 of the first semiconductor wafer 1 may include the upper surface of the first upper bonding pad 162, the upper surface of the first upper dielectric layer 161, and the upper surface of the first package 18. The side surface 13 of the first semiconductor wafer 1 may be one side surface of the first package 18. In some embodiments, the first semiconductor wafer 1 may not include the first package 18.

[0179] The second semiconductor wafer 2 may be stacked on the first semiconductor wafer 1 and electrically connected to the first semiconductor wafer 1 by hybrid bonding or metal-to-metal bonding. The second semiconductor wafer 2 may have a lower surface 21 (e.g., a first surface) and an upper surface 22 (e.g., a second surface), and may have a side surface 23 extending between the lower surface 21 and the upper surface 22. The lower surface 21 (e.g., the first surface) of the second semiconductor wafer 2 may directly contact the upper surface 12 of the first semiconductor wafer 1. The side surface 23 of the second semiconductor wafer 2 may be substantially aligned with or coplanar with the side surface 13 of the first semiconductor wafer 1.

[0180] The second semiconductor wafer 2 may include a second base 20, a second conductive structure 24, a second lower structure 25, a second upper structure 26, and a plurality of second conductive vias 27. The second semiconductor wafer 2 may be a memory wafer, such as a dynamic random access memory (DRAM) wafer.

[0181] The second base 20 of the second semiconductor wafer 2 may be the same as or similar to the first base 10 of the first semiconductor wafer 1. For example, the second base 20 may be a semiconductor substrate and may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (GaAs), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the second base 20 may include an insulator-on-semiconductor substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The second base 20 may have a first surface (e.g., a lower surface) and a second surface (e.g., an upper surface) opposite the first surface. Figure 1 As shown, the width of the second base 20 of the second semiconductor wafer 2 can be greater than the width of the first base 10 of the first semiconductor wafer 1.

[0182] The second conductive structure 24 of the second semiconductor wafer 2 may be the same as or similar to the first conductive structure 14 of the first semiconductor wafer 1. The second conductive structure 24 may be disposed on a first surface (e.g., the lower surface) of the second base 20. In some embodiments, for example, the second conductive structure 24 may include multiple FEOL elements, including resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC elements, or combinations thereof. In some embodiments, the second conductive structure 24 may also include at least one BEOL interconnect pattern, such as multiple patterned circuit layers electrically connected to the FEOL elements. In some embodiments, the second conductive structure 24 may also include at least one dielectric layer or at least one dielectric structure covering the FEOL elements and the BEOL interconnect pattern. Figure 1 As shown, the width of the second conductive structure 24 of the second semiconductor wafer 2 can be greater than the width of the first conductive structure 14 of the first semiconductor wafer 1.

[0183] The second conductive via 27 may extend through the second base 20 and be electrically connected to the second conductive structure 24. In some embodiments, the bottom end of the second conductive via 27 may extend beyond the first surface (e.g., the lower surface) of the second base 20 and into the second conductive structure 24. In some embodiments, the second conductive via 27 may be a single-wafer structure, and a length of the second conductive via 27 may be greater than a thickness of the second base 20. In some embodiments, an upper surface of the second conductive via 27 may be substantially coplanar with the second surface (e.g., the upper surface) of the second base 20. In some embodiments, the upper surface of the second conductive via 27 may be exposed through the second surface (e.g., the upper surface) of the second base 20.

[0184] The second lower structure 25 of the second semiconductor wafer 2 may be the same as or similar to the first lower structure 15 of the first semiconductor wafer 1. The second lower structure 25 may be disposed on the second conductive structure 24. The second lower structure 25 may be an HB structure, which may include a second lower dielectric layer 251 and a plurality of second lower bonding pads 252. The second lower dielectric layer 251 may be an HB dielectric layer, which may include SiO2, SiCN, and / or SiON. Each second lower bonding pad 252 may be an HB bonding pad and may include Cu or Al. The second lower bonding pads 252 may be embedded in the second lower dielectric layer 251 and may be exposed through the second lower dielectric layer 251. The second lower bonding pads 252 may be surrounded by the second lower dielectric layer 251. The second lower bonding pads 252 may be electrically connected to the BEOL interconnect pattern of the second conductive structure 24. In some embodiments, the second lower bonding pads 252 may be electrically connected to the second conductive via 27 via the second conductive structure 24.

[0185] In some embodiments, a lower surface of the second lower solder pad 252 may be substantially aligned with a lower surface of the second lower dielectric layer 251. In some embodiments, the lower surface of the second lower solder pad 252 may be exposed through the lower surface of the second lower dielectric layer 251. In some embodiments, an upper surface of the second lower solder pad 252 may be substantially aligned with an upper surface of the second lower dielectric layer 251. In some embodiments, the upper surface of the second lower solder pad 252 may contact the second conductive structure 24. In some embodiments, a thickness of the second lower solder pad 252 may be substantially equal to a thickness of the second lower dielectric layer 251.

[0186] like Figure 1As shown, the width of the second lower structure 25 of the second semiconductor wafer 2 may be greater than the width of the first lower structure 15 of the first semiconductor wafer 1. The second lower structure 25 of the second semiconductor wafer 2 can be bonded and electrically connected to the first upper structure 16 of the first semiconductor wafer 1 via hybrid bonding. For example, the second lower dielectric layer 251 of the second semiconductor wafer 2 can be attached, bonded, or adhered to the first upper dielectric layer 161 and the first package 18 of the first semiconductor wafer 1. The second lower dielectric layer 251 of the second semiconductor wafer 2 can be bonded to the first upper dielectric layer 161 of the first semiconductor wafer 1 via dielectric-dielectric bonding. In some embodiments, the second semiconductor wafer 2 can directly contact the first package 18 of the first semiconductor wafer 1.

[0187] The second lower bonding pad 252 of the second semiconductor wafer 2 can be attached, bonded, or electrically connected to the first upper bonding pad 162 of the first semiconductor wafer 1 via metal-to-metal bonding. In some embodiments, the second lower bonding pad 252 of the second semiconductor wafer 2 can directly contact the first upper bonding pad 162 of the first semiconductor wafer 1. The width of the second lower bonding pad 252 of the second semiconductor wafer 2 can be substantially equal to the width of the first upper bonding pad 162 of the first semiconductor wafer 1. The second semiconductor wafer 2 and the first semiconductor wafer 1 can be in face-to-face contact.

[0188] The second upper structure 26 of the second semiconductor wafer 2 may be the same as or similar to the first upper structure 16 of the first semiconductor wafer 1. The second upper structure 26 may be disposed on the second surface (e.g., the upper surface) of the second base 20. The second upper structure 26 may be an HB structure or a solder joint structure, which may include a second upper dielectric layer 261 and a plurality of second upper pads 262.

[0189] The second upper dielectric layer 261 may be an HB dielectric layer, which may include SiO2, SiCN, and / or SiON. Each second upper pad 262 may be an HB pad and may include Cu or Al. The second upper pad 262 may be embedded in the second upper dielectric layer 261 and may be exposed through the second upper dielectric layer 261. The second upper pad 262 may be surrounded by the second upper dielectric layer 261. The second upper pad 262 may be electrically connected to the second conductive via 27. In some embodiments, the second upper pad 262 may directly contact the second conductive via 27. The second upper pad 262 may be electrically connected to the second lower pad 252 via the second conductive via 27 and the second conductive structure 24.

[0190] In some embodiments, an upper surface of the second upper solder pad 262 may be substantially aligned with an upper surface of the second upper dielectric layer 261. In some embodiments, the upper surface of the second upper solder pad 262 may be exposed through the upper surface of the second upper dielectric layer 261. In some embodiments, a lower surface of the second upper solder pad 262 may be substantially aligned with a lower surface of the second upper dielectric layer 261. In some embodiments, the lower surface of the second upper solder pad 262 may contact the second conductive via 27. In some embodiments, a thickness of the second upper solder pad 262 may be substantially equal to a thickness of the second upper dielectric layer 261.

[0191] In some embodiments, the lower surface 21 of the second semiconductor wafer 2 may include the lower surface of the second lower bonding pad 252 and the lower surface of the second lower dielectric layer 251. The upper surface 22 of the second semiconductor wafer 2 may include the upper surface of the second upper bonding pad 262 and the upper surface of the second upper dielectric layer 261. The side surface 23 of the second semiconductor wafer 2 may include one side surface of the second base 20, one side surface of the second conductive structure 24, one side surface of the second lower structure 25, and one side surface of the second upper structure 26. In some embodiments, the side surfaces of the second base 20, the second conductive structure 24, the second lower structure 25, and the second upper structure 26 may be aligned with each other or coplanar.

[0192] The second component 72 may be stacked on top of the first component 71. The second component 72 may be spaced apart from the first component 71. The second component 72 may include a third semiconductor wafer 3 and a fourth semiconductor wafer 4 stacked on the third semiconductor wafer 3 and electrically connected to the third semiconductor wafer 3 by hybrid bonding. The second component 72 may be electrically connected to the first component 71 via a bump 61. The bump 61 may include a reflowable material such as AgSn. In some embodiments, the bump 61 may include solder balls, solder bumps, or microbumps. Furthermore, a lower filler 62 may be disposed between the second component 72 and the first component 71 and may cover the bump 61.

[0193] A third semiconductor wafer 3 may be stacked on the second semiconductor wafer 2 and electrically connected to the second semiconductor wafer 2 via bumps 61. The third semiconductor wafer 3 may have a lower surface 31 (e.g., a first surface) and an upper surface 32 (e.g., a second surface), and may have a side surface 33 extending between the lower surface 31 and the upper surface 32. The lower surface 31 (e.g., the first surface) of the third semiconductor wafer 3 may be spaced apart from the upper surface 22 of the second semiconductor wafer 2. A lower filler 62 may be disposed between the lower surface 31 of the third semiconductor wafer 3 and the upper surface 22 of the second semiconductor wafer 2 to cover the bumps 61.

[0194] The third semiconductor chip 3 may be the same as or similar to the first semiconductor chip 1. The third semiconductor chip 3 may include a third base 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36, a plurality of third conductive vias 37, and a third package 38. The third semiconductor chip 3 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0195] The third base 30 of the third semiconductor wafer 3 may be the same as or similar to the first base 10 of the first semiconductor wafer 1. The third base 30 may have a first surface (e.g., a lower surface) and a second surface (e.g., an upper surface) opposite the first surface. Figure 1 As shown, the width of the third base 30 of the third semiconductor wafer 3 can be substantially equal to the width of the first base 10 of the first semiconductor wafer 1.

[0196] The third conductive structure 34 of the third semiconductor wafer 3 may be the same as or similar to the first conductive structure 14 of the first semiconductor wafer 1. The third conductive structure 34 may be disposed on the first surface (e.g., the lower surface) of the third base 30. In some embodiments, the third conductive structure 34 may include a plurality of FEOL elements and at least one BEOL interconnect pattern. Figure 1 As shown, the width of the third conductive structure 34 of the third semiconductor wafer 3 can be substantially equal to the width of the first conductive structure 14 of the first semiconductor wafer 1.

[0197] The third conductive via 37 may extend through the third base 30 and be electrically connected to the third conductive structure 34. In some embodiments, the bottom end of the third conductive via 37 may extend beyond the first surface (e.g., the lower surface) of the third base 30 and extend into the third conductive structure 34. In some embodiments, an upper surface of the third conductive via 37 may be substantially coplanar with the second surface (e.g., the upper surface) of the third base 30.

[0198] The third lower structure 35 of the third semiconductor wafer 3 may be the same as or similar to the first lower structure 15 of the first semiconductor wafer 1. The third lower structure 35 may be disposed on the third conductive structure 34. The third lower structure 35 may be an HB structure or a solder joint structure, which may include a third lower dielectric layer 351 and a plurality of third lower pads 352. The third lower dielectric layer 351 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each third lower pad 352 may be an HB pad and may include Cu or Al. The third lower pads 352 may be embedded in the third lower dielectric layer 351 and may be exposed through the third lower dielectric layer 351. The third lower pads 352 may be electrically connected to the BEOL interconnect pattern of the third conductive structure 34. In some embodiments, the third lower pads 352 may be electrically connected to the third conductive via 37 via the third conductive structure 34.

[0199] like Figure 1 As shown, the width of the third lower structure 35 of the third semiconductor wafer 3 can be substantially equal to the width of the first lower structure 15 of the first semiconductor wafer 1. The third lower pad 352 of the third lower structure 35 of the third semiconductor wafer 3 can be bonded and electrically connected to the second upper pad 262 of the second upper structure 26 of the second semiconductor wafer 2 via bump 61.

[0200] The third upper structure 36 of the third semiconductor wafer 3 may be the same as or similar to the first upper structure 16 of the first semiconductor wafer 1. The third upper structure 36 may be disposed on the second surface (e.g., the upper surface) of the third base 30. The third upper structure 36 may be an HB structure, which may include a third upper dielectric layer 361 and a plurality of third upper pads 362.

[0201] The third upper dielectric layer 361 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each third upper pad 362 may be an HB pad and may include Cu or Al. The third upper pad 362 may be embedded in the third upper dielectric layer 361 and may be exposed through the third upper dielectric layer 361. The third upper pad 362 may be electrically connected to the third conductive via 37. In some embodiments, the third upper pad 362 may be electrically connected to the third lower pad 352 via the third conductive via 37 and the third conductive structure 34.

[0202] The third package 38 of the third semiconductor wafer 3 may be the same as or similar to the first package 18 of the first semiconductor wafer 1. The third package 38 may be disposed around the third base 30, the third conductive structure 34, the third lower structure 35, and the third upper structure 36. The third package 38 may cover and contact the side surfaces of the third base 30, the third conductive structure 34, the third lower structure 35, and the third upper structure 36.

[0203] In some embodiments, the lower surface 31 of the third semiconductor wafer 3 may include the lower surface of the third lower bonding pad 352, the lower surface of the third lower dielectric layer 351, and the lower surface of the third package 38. The upper surface 32 of the third semiconductor wafer 3 may include the upper surface of the third upper bonding pad 362, the upper surface of the third upper dielectric layer 361, and the upper surface of the third package 38. The side surface 33 of the third semiconductor wafer 3 may be one side surface of the third package 38. In some embodiments, the third semiconductor wafer 3 may not include the third package 38.

[0204] A fourth semiconductor wafer 4 may be stacked on top of a third semiconductor wafer 3 and electrically connected to the third semiconductor wafer 3 by hybrid bonding or metal-to-metal bonding. The fourth semiconductor wafer 4 may have a lower surface 41 (e.g., a first surface) and an upper surface 42 (e.g., a second surface), and may have a side surface 43 extending between the lower surface 41 and the upper surface 42. The lower surface 41 (e.g., the first surface) of the fourth semiconductor wafer 4 may directly contact the upper surface 32 of the third semiconductor wafer 3. The side surface 43 of the fourth semiconductor wafer 4 may be substantially aligned with or coplanar with the side surface 33 of the third semiconductor wafer 3.

[0205] The fourth semiconductor chip 4 may be the same as or similar to the second semiconductor chip 2. The fourth semiconductor chip 4 may include a fourth base 40, a fourth conductive structure 44, and a fourth lower structure 45. The fourth semiconductor chip 4 may be a memory chip, such as a dynamic random access memory (DRAM) chip.

[0206] The fourth base 40 of the fourth semiconductor wafer 4 may be the same as or similar to the second base 20 of the second semiconductor wafer 2. For example... Figure 1 As shown, the width of the fourth base 40 of the fourth semiconductor wafer 4 can be greater than the width of the third base 30 of the third semiconductor wafer 3. The thickness of the fourth base 40 of the fourth semiconductor wafer 4 can be greater than the thickness of the third base 30 of the third semiconductor wafer 3.

[0207] The fourth conductive structure 44 of the fourth semiconductor wafer 4 may be the same as or similar to the second conductive structure 24 of the second semiconductor wafer 2. The fourth conductive structure 44 may be disposed on the first surface (e.g., the lower surface) of the fourth base 40. In some embodiments, the fourth conductive structure 44 may include a plurality of FEOL elements and at least one BEOL interconnect pattern. Figure 1 As shown, the width of the fourth conductive structure 44 of the fourth semiconductor wafer 4 can be greater than the width of the third conductive structure 34 of the third semiconductor wafer 3.

[0208] The fourth semiconductor wafer 4 may or may not include a conductive via extending in the fourth base 40 and electrically connected to the fourth conductive structure 44.

[0209] The fourth lower structure 45 of the fourth semiconductor wafer 4 may be the same as or similar to the third lower structure 35 of the third semiconductor wafer 3. The fourth lower structure 45 may be disposed on the fourth conductive structure 44. The fourth lower structure 45 may be an HB structure, which may include a fourth lower dielectric layer 451 and a plurality of fourth lower bonding pads 452. The fourth lower dielectric layer 451 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each fourth lower bonding pad 452 may be an HB bonding pad and may include Cu or Al. The fourth lower bonding pads 452 may be embedded in the fourth lower dielectric layer 451 and may be exposed through the fourth lower dielectric layer 451. The fourth lower bonding pads 452 may be electrically connected to the BEOL interconnect pattern of the fourth conductive structure 44.

[0210] like Figure 1 As shown, the width of the fourth lower structure 45 of the fourth semiconductor wafer 4 can be greater than the width of the third lower structure 35 of the third semiconductor wafer 3. The fourth lower structure 45 of the fourth semiconductor wafer 4 can be bonded and electrically connected to the third upper structure 36 of the third semiconductor wafer 3 through hybrid bonding. For example, the fourth lower dielectric layer 451 of the fourth semiconductor wafer 4 can be attached, bonded, or adhered to the third upper dielectric layer 361 and the third package 38 of the third semiconductor wafer 3. The fourth lower dielectric layer 451 of the fourth semiconductor wafer 4 can be bonded to the third upper dielectric layer 361 of the third semiconductor wafer 3 through dielectric-dielectric bonding. Therefore, the fourth semiconductor wafer 4 can directly contact the third package 38 of the third semiconductor wafer 3.

[0211] The fourth lower pad 452 of the fourth semiconductor wafer 4 can be attached, bonded, or electrically connected to the third upper pad 362 of the third semiconductor wafer 3 via metal-to-metal bonding. The fourth semiconductor wafer 4 and the third semiconductor wafer 3 can be in face-to-face contact.

[0212] In some embodiments, the lower surface 41 of the fourth semiconductor wafer 4 may include the lower surface of the fourth lower bonding pad 452 and the lower surface of the fourth lower dielectric layer 451. The upper surface 42 of the fourth semiconductor wafer 4 may include the second surface (e.g., the upper surface) of the fourth base 40.

[0213] The third component 73 may be stacked below the first component 71. The third component 73 may include a fifth semiconductor wafer 5 and a plurality of external connectors 66. In some embodiments, the third component 73 may not include the external connectors 66.

[0214] The fifth semiconductor wafer 5 may have a lower surface 51 (e.g., a first surface) and an upper surface 52 (e.g., a second surface), and may have a side surface 53 extending between the lower surface 51 and the upper surface 52. The fifth semiconductor wafer 5 may include a fifth base 50, a fifth conductive structure 54, a plurality of fifth conductive vias 57, a fifth lower structure 55, a fifth upper structure 56, and a plurality of fifth dies 510. The fifth semiconductor wafer 5 may be a controller wafer, such as an application processor (AP) wafer.

[0215] For example, the fifth base 50 may be a semiconductor substrate and may include silicon (Si), doped silicon, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. The fifth base 50 may have a first surface 501 (e.g., an upper surface) and a second surface 502 (e.g., a lower surface) opposite to the first surface 501.

[0216] The fifth conductive structure 54 may be disposed on the first surface 501 (e.g., the upper surface) of the fifth base 50. In some embodiments, the fifth conductive structure 54 may include a plurality of FEOL elements and at least one BEOL interconnect pattern.

[0217] A fifth lower structure 55 may be disposed on a fifth base 50. The fifth lower structure 55 may include a passivation layer 551 and a conductive layer 552, wherein the conductive layer 552 includes a first portion 581 and a second portion 582. A lower surface of the passivation layer 551 may be substantially aligned with the lower surface 51 (e.g., the first surface) of the fifth semiconductor wafer 5. The conductive layer 552 may be embedded in the passivation layer 551 and may be exposed through the passivation layer 551. In some embodiments, the conductive layer 552 may be surrounded by the passivation layer 551. In some embodiments, the conductive layer 552 may be electrically connected to an external connector 66. In some embodiments, the conductive layer 552 may be electrically connected to a fifth conductive via 57.

[0218] In some embodiments, the lower surface of the conductive layer 552 may be substantially aligned with the lower surface of the passivation layer 551. In some embodiments, the lower surface of the conductive layer 552 may be exposed through the lower surface of the passivation layer 551. In some embodiments, an upper surface of the conductive layer 552 may be substantially aligned with an upper surface of the passivation layer 551. In some embodiments, the upper surface of the conductive layer 552 may contact the fifth base 50 and the fifth conductive via 57. In some embodiments, a thickness of the conductive layer 552 may be substantially equal to a thickness of the passivation layer 551.

[0219] A fifth upper structure 56 may be disposed on a fifth conductive structure 54. The fifth upper structure 56 may be an HB structure or a solder joint structure, and may include a fifth upper dielectric layer 561 and a plurality of fifth upper pads 562. The fifth upper dielectric layer 561 may be an HB dielectric layer and may include SiO2, SiCN, and / or SiON. Each fifth upper pad 562 may be an HB pad and may include Cu or Al. The fifth upper pads 562 may be embedded in the fifth upper dielectric layer 561 and may be exposed through the fifth upper dielectric layer 561. The fifth upper pads 562 may be electrically connected to the BEOL interconnect pattern of the fifth conductive structure 54.

[0220] The fifth conductive via 57 may extend through the fifth base 50 and may be electrically connected to the fifth conductive structure 54 and the first portion 581 of the conductive layer 552. In some embodiments, one end of the fifth conductive via 57 may extend into the fifth conductive structure 54.

[0221] The fifth grain 510 may be disposed in the second surface 502 (e.g., the lower surface) of the base, wherein each fifth grain 510 may include a plurality of contact pads 513 disposed on the fifth grain and connected to the fifth conductive structure 54, and may include a plurality of wires 511 disposed in the lower surface of the fifth grain and connected to the first portion 581 of the conductive layer 552.

[0222] An external connector 66 may be disposed on the lower surface 51 of the fifth semiconductor wafer 5 for external connection. The external connector 66 may include a reflowable material such as AgSn. In some embodiments, the external connector 66 may include solder balls, solder bumps, or microbumps. The external connector 66 may be disposed on the conductive layer 552 of the fifth lower structure 55 of the fifth semiconductor wafer 5.

[0223] In some embodiments, the lower surface 51 of the fifth semiconductor wafer 5 may include the lower surface of the passivation layer 551 and the lower surface of the conductive layer 552. The upper surface 52 of the fifth semiconductor wafer 5 may include the upper surface of the fifth upper bonding pad 562 and the upper surface of the fifth upper dielectric layer 561.

[0224] The first lower pad 152 of the first lower structure 15 of the first semiconductor wafer 1 can be bonded and electrically connected to the fifth upper pad 562 of the fifth upper structure 56 of the fifth semiconductor wafer 5 via an electronic connector 63. The electronic connector 63 may include a reflowable material such as AgSn. In some embodiments, the electronic connector 63 may include solder balls, solder bumps, or microbumps. Furthermore, a protective material 64 (e.g., a filler) may be disposed between the first semiconductor wafer 1 and the fifth semiconductor wafer 5 and may cover the electronic connector 63.

[0225] The peripheral package 65 may be a molded part with or without filler. The peripheral package 65 may encapsulate a first semiconductor wafer 1, a second semiconductor wafer 2, a third semiconductor wafer 3, a fourth semiconductor wafer 4, and a fifth semiconductor wafer 5. The peripheral package 65 may cover the side surface 13 of the first semiconductor wafer 1, the side surface 23 of the second semiconductor wafer 2, the side surface 33 of the third semiconductor wafer 3, the side surface 43 of the fourth semiconductor wafer 4, and the top surface 52 of the fifth semiconductor wafer 5.

[0226] As described above, in some embodiments, the third component 73 may not include the external connector 66. In this case, the encapsulation operation using the peripheral package 65 as the package can be performed before the external connector 66 is formed.

[0227] The carrier structure 700 may be disposed above the second component 72 and the peripheral package 65. The carrier structure 700 may include a carrier substrate 701, a heat dissipation unit (HDU), and a bonding layer 709.

[0228] For example, the carrier substrate 701 may include silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, gallium, gallium arsenide, indium arsenide, indium phosphide or other group IV-IV, III-V or II-VI semiconductor materials.

[0229] The heat dissipation unit (HDU) may include a plurality of conductive plates 707 and a plurality of through-semiconductor vias (TSVs) 705. The TSVs 705 may be disposed in a carrier substrate 701. In some embodiments, the sidewalls of the TSVs 705 may taper slightly, for example, between about 85 degrees and about 88 degrees. In some embodiments, the width of the TSVs 705 may be between about 1 μm and about 22 μm, or between about 5 μm and about 15 μm. In some embodiments, the depth of the through-semiconductor vias 705 may be between about 20 μm and about 160 μm, or between about 50 μm and about 130 μm. The conductive plates 707 may be formed on the carrier substrate 701 and spaced apart from each other. Each conductive plate 707 may be connected to two or more TSVs 705. For example, the conductive plate 707 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The conductive plate 707 and TSV 705 together constitute the heat dissipation unit HDU.

[0230] In some embodiments, only one conductive plate 707 may be formed on the carrier substrate 701 and connected to all TSVs 705. In some embodiments, the upper surface 705TS of the TSV 705 of the carrier structure 700 is substantially coplanar with the upper surface 701TS of the carrier substrate 701.

[0231] A bonding layer 709 may be disposed on a carrier substrate 701 and cover the conductive plate 707. In some embodiments, for example, the bonding layer 709 may include an organic material selected from undoped silicate glass, silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, or combinations thereof. In some embodiments, for example, the bonding layer 709 may include a polymer layer of epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or the like.

[0232] In some embodiments, electronic component 6 further includes an intermediate bonding layer 801 disposed between the second component 72 and the bonding layer 709 and between the peripheral package 65 and the bonding layer 709. In some embodiments, the intermediate bonding layer 801 may include the same material as the bonding layer 709, but is not limited thereto. In some embodiments, for example, the intermediate bonding layer 801 may include an organic material selected from undoped silicate glass, silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, and combinations thereof. In some embodiments, for example, the intermediate bonding layer 801 may include a polymer layer of epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or the like.

[0233] in accordance with Figure 1 In the embodiments of this disclosure shown, during operation of electronic component 6, the heat accumulated during operation is conducted to the surrounding environment via conductive plate 707 and through-hole semiconductor via 705 (i.e., heat dissipation unit HDU). Therefore, the thermal conductivity of electronic component 6 is improved.

[0234] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor structure 9 of some embodiments of the present disclosure. The semiconductor structure 9 may include an interposer 8, an electronic component 6, a semiconductor component 92, and a plurality of external connectors 96.

[0235] Intermediate layer 8 may include a base 80, a conductive structure 84, an upper structure 85, and a plurality of conductive vias 87. For example, the base 80 may be a semiconductor substrate and may include silicon (Si), doped silicon, germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials.

[0236] A conductive structure 84 may be disposed on the base 80. In some embodiments, the conductive structure 84 may include a redistribution layer (RDL) structure. A conductive via 87 may extend through the base 80 and be electrically connected to the conductive structure 84.

[0237] The upper structure 85 may be disposed on the conductive structure 84. The upper structure 85 may include a dielectric layer 851 and a plurality of solder pads 852. The dielectric layer 851 may be a solder resist layer. The solder pads 852 may be embedded in the dielectric layer 851 and may be exposed through the dielectric layer 851.

[0238] An external connector 96 may be disposed on the lower surface of the interposer layer 8 for external connection. The external connector 96 may include a reflowable material such as AgSn. Therefore, the external connector 96 may include solder balls, solder bumps, or microbumps. The external connector 96 may be disposed on the conductive via 87.

[0239] Figure 2 Electronic component 6 can be Figure 1 Electronic component 6. Electronic component 6 can be bonded and electrically connected to the pads 852 of the interposer 8 via an external connector 66.

[0240] Semiconductor element 92 can be a logic chip or a logic die. Semiconductor element 92 can be bonded and electrically connected to the pads 852 of the interposer layer 8 via a plurality of solders 94. Therefore, electronic element 6 can be electrically connected to semiconductor element 92 via interposer layer 8.

[0241] Figures 3 to 28 This is a cross-sectional schematic diagram illustrating various stages of an electronic device fabrication method according to some embodiments of the present disclosure.

[0242] Please refer to Figures 3 to 11 A first component 71 may be provided, comprising a first semiconductor wafer 1 and a second semiconductor wafer 2. The manufacture of the first component 71 will be described below.

[0243] Please refer to Figure 3 A first wafer 1' may be provided. The first wafer 1' may include a first base 10, a first conductive structure 14, a first lower structure 15, and a plurality of first conductive vias 17. Figure 3 The first base 10, the first conductive structure 14, the first lower structure 15, and the first conductive via 17 can be respectively connected to Figure 1 The first base 10, the first conductive structure 14, the first lower structure 15, and the first conductive via 17 are the same or similar. The first wafer 1' may define multiple dividing lines 19. The first base 10 may have a first surface 101 (e.g., a lower surface) and a second surface 102 (e.g., an upper surface) opposite to the first surface 101.

[0244] A first conductive structure 14 may be disposed on a first surface 101 (e.g., a lower surface) of a first base 10. A first conductive via 17 may extend into the first base 10 and be electrically connected to the first conductive structure 14. A first lower structure 15 may be disposed on the first conductive structure 14. The first lower structure 15 may include a first lower dielectric layer 151 and a plurality of first lower pads 152. The first lower pads 152 may be embedded in the first lower dielectric layer 151 and may be exposed through the first lower dielectric layer 151.

[0245] Please refer to Figure 4 The first base 10 may be thinned from the second surface 102 (e.g., the upper surface) to expose the first conductive via 17. Next, a first upper structure 16 may be formed on the second surface 102 of the first base 10. The first upper structure 16 may include a first upper dielectric layer 161 and a plurality of first upper pads 162. The first upper pads 162 may be embedded in the first upper dielectric layer 161 and may be exposed through the first upper dielectric layer 161. The first upper pads 162 may be electrically connected to the first conductive via 17.

[0246] Please refer to Figure 5 The first wafer 1' can be divided along the dividing line 19 to form a plurality of units 1". The unit 1" has a lower surface 11" (e.g., a first surface) and an upper surface 12" (e.g., a second surface), and has a side surface 13" extending between the lower surface 11" and the upper surface 12".

[0247] Please refer to Figure 6 A second wafer 2' may be provided. The second wafer 2' may include a second base 20, a second conductive structure 24, a second lower structure 25, and a plurality of second conductive vias 27. Figure 6 The second base 20, the second conductive structure 24, the second lower structure 25, and the second conductive via 27 can be respectively connected to Figure 1 The second base 20, the second conductive structure 24, the second lower structure 25, and the second conductive via 27 are the same or similar. The second base 20 may have a first surface 201 (e.g., a lower surface) and a second surface 202 (e.g., an upper surface) opposite to the first surface 201.

[0248] The second conductive structure 24 may be disposed on the first surface 201 (e.g., the lower surface) of the second base 20. The second conductive via 27 may extend into the second base 20 and be electrically connected to the second conductive structure 24. A second lower structure 25 may be disposed on the second conductive structure 24. The second lower structure 25 may include a second lower dielectric layer 251 and a plurality of second lower pads 252. The second lower pads 252 may be embedded in the second lower dielectric layer 251 and may be exposed through the second lower dielectric layer 251.

[0249] Please refer to Figure 7 Multiple units 1" can be attached to the second wafer 2' by hybrid bonding. The first upper dielectric layer 161 of unit 1" can be attached, bonded or adhered to the second lower dielectric layer 251 of the second wafer 2' by dielectric-dielectric bonding. The first upper pad 162 of unit 1" can be attached, bonded or electrically connected to the second lower pad 252 of the second wafer 2' by metal-to-metal bonding.

[0250] Please refer to Figure 8 A first package 18 may be formed or disposed on the second lower structure 25 to cover unit 1". The first package 18 may have a first surface 181 (e.g., a lower surface) and a second surface 182 (e.g., an upper surface) opposite the first surface 181. The first surface 181 of the first package 18 may be lower than the lower surface 11" of unit 1". The second surface 182 of the first package 18 may contact the second lower structure 25. In some embodiments, the first package 18 may cover the side surface 13" and the lower surface 11" of unit 1".

[0251] Please refer to Figure 9 The second base 20 may be thinned from the second surface 202 (e.g., the upper surface) to expose the second conductive via 27. Next, a second upper structure 26 may be formed on the second surface 202 of the second base 20. The second upper structure 26 may include a second upper dielectric layer 261 and a plurality of second upper pads 262. The second upper pads 262 may be embedded in the second upper dielectric layer 261 and may be exposed through the second upper dielectric layer 261. The second upper pads 262 may be electrically connected to the second conductive via 27.

[0252] Please refer to Figure 10 The first package 18 may be thinned from a first surface 181 (e.g., the lower surface) to expose unit 1". The first surface 181 (e.g., the lower surface) of the first package 18 may be substantially coplanar with the lower surface 11" of unit 1". Next, a plurality of electronic connectors 63 may be formed or disposed on the first lower pad 152 of the first lower structure 15 of unit 1". The electronic connectors 63 may include a reflowable material such as AgSn. Meanwhile, the second wafer 2' and the first package 18 may define a plurality of dividing lines 29.

[0253] Please refer to Figure 11The second wafer 2' and the first package 18 can be cleaved along the dividing line 29 to form a plurality of first components 71. Each first component 71 may include a first semiconductor wafer 1 and a second semiconductor wafer 2 stacked on the first semiconductor wafer 1 and electrically connected to the first semiconductor wafer 1 by hybrid bonding. The first semiconductor wafer 1 may include a cell 1" and a first package 18. The second semiconductor wafer 2 may be a portion cleaved from the second wafer 2'. Figure 11 The first component 71 can be with Figure 1 The first component 71 is the same as or similar to it.

[0254] Please refer to Figures 12 to 17 A second component 72 may be provided, comprising a third semiconductor wafer 3 and a fourth semiconductor wafer 4. The manufacture of the second component 72 is described below.

[0255] Please refer to Figure 12 A fourth wafer 4' may be provided. The fourth wafer 4' may include a fourth base 40, a fourth conductive structure 44, and a fourth lower structure 45. Figure 12 The fourth base 40, the fourth conductive structure 44, and the fourth lower structure 45 can be respectively connected with Figure 1 The fourth base 40, the fourth conductive structure 44, and the fourth lower structure 45 are the same or similar.

[0256] A fourth conductive structure 44 may be disposed on a first surface 401 (e.g., a lower surface) of the fourth base 40. A fourth lower structure 45 may be disposed on the fourth conductive structure 44. The fourth lower structure 45 may include a fourth lower dielectric layer 451 and a plurality of fourth lower pads 452. The fourth lower pads 452 may be embedded in the fourth lower dielectric layer 451 and may be exposed through the fourth lower dielectric layer 451.

[0257] Please refer to Figure 13 Multiple units 3" may be provided. Units 3" may be the same as or similar to unit 1". Unit 3" may have a lower surface 31" (e.g., a first surface) and an upper surface 32" (e.g., a second surface), and may have a side surface 33" extending between the lower surface 31" and the upper surface 32". The third semiconductor wafer 3 may be the same as or similar to the first semiconductor wafer 1. Unit 3" may include a third base 30, a third conductive structure 34, a third lower structure 35, a third upper structure 36 and a plurality of third conductive vias 37, which are respectively connected to... Figure 1 The third base 30, the third conductive structure 34, the third lower structure 35, the third upper structure 36 and the third conductive through hole 37 are the same or similar.

[0258] Please refer to Figure 14Unit 3" can be attached to the fourth wafer 4' by hybrid bonding. The third upper dielectric layer 361 of unit 3" can be attached, bonded or adhered to the fourth lower dielectric layer 451 of the fourth wafer 4' by dielectric-dielectric bonding. The third upper pad 362 of unit 3" can be attached, bonded or electrically connected to the fourth lower pad 452 of the fourth wafer 4' by metal-to-metal bonding.

[0259] Please refer to Figure 15 A third package 38 may be formed or disposed on the fourth lower structure 45 to cover the unit 3". The third package 38 may have a first surface 381 (e.g., a lower surface) and a second surface 382 (e.g., an upper surface) opposite the first surface 381. The second surface 382 of the third package 38 may contact the fourth lower structure 45. The third package 38 may cover the side surface 33" and the lower surface 31" of the unit 3".

[0260] In some embodiments, the third package 38 may be thinned from the first surface 381 (e.g., the lower surface) to expose the unit 3". In some embodiments, the first surface 381 of the third package 38 may be substantially coplanar with the lower surface 31" of the unit 3".

[0261] Please refer to Figure 16 Multiple bumps 61 may be formed or disposed on the third lower pad 352 of the third lower structure 35 of unit 3". The bumps 61 may include a reflowable material such as AgSn. Meanwhile, the fourth wafer 4′ and the third package 38 may define multiple dividing lines 49.

[0262] Please refer to Figure 17 The fourth wafer 4' and the third package 38 can be divided along the dividing line 49 to form a plurality of second components 72. The second components 72 may include a third semiconductor wafer 3 and a fourth semiconductor wafer 4 stacked on the third semiconductor wafer 3 and electrically connected to the third semiconductor wafer 3 by hybrid bonding. The third semiconductor wafer 3 may include a cell 3" and a third package 38. The fourth semiconductor wafer 4 may be a portion diced from the fourth wafer 4'. Figure 17 The second component 72 can be with Figure 1 The second component 72 is the same as or similar to it.

[0263] Please refer to Figures 18 to 20 A third component 73 may be provided. The manufacture of the third component 73 is described below.

[0264] Please refer to Figure 18 A fifth semiconductor wafer 5 may be provided. The fifth semiconductor wafer 5 may include a fifth base 50, a fifth conductive structure 54, a fifth upper structure 56, a plurality of fifth conductive vias 57, and a plurality of fifth dies 510. Figure 18 The fifth base 50, the fifth conductive structure 54, the fifth upper structure 56, the fifth conductive via 57, and the fifth grain 510 can be respectively connected with Figure 1 The fifth base 50, the fifth conductive structure 54, the fifth upper structure 56, the fifth conductive via 57, and the fifth die 510 are the same or similar. The fifth semiconductor wafer 5 may have a lower surface 51 (e.g., a first surface) and an upper surface 52 (e.g., a second surface), and may have a side surface 53 extending between the lower surface 51 and the upper surface 52.

[0265] It should be understood that the fifth semiconductor chip 5 can be part of a wafer during the manufacturing process. Once the manufacturing process is complete, the fifth semiconductor chip 5 can be diced from the wafer.

[0266] Please refer to Figure 19 A passivation layer 551 may be deposited on the lower surface 51 (e.g., a first surface) of the fifth semiconductor wafer 5 and may cover the fifth conductive via 57, the fifth die 510, and the fifth base 50. It should be understood that the fifth semiconductor wafer 5' may be flipped before the deposition of the passivation layer 551. Next, a conductive layer 552 may be formed through the passivation layer. In other words, the conductive layer 552 may be embedded in the passivation layer 551. The conductive layer 552 may include a plurality of first portions 581 and second portions 582, wherein each first portion 581 / second portion 582 is spaced apart from each other and electrically isolated. In some embodiments, the first portions 581 of the conductive layer 552 are electrically connected to a plurality of wires 511 of the fifth die 510, and the second portions 582 of the conductive layer 552 are electrically connected to the fifth conductive via 57. In some embodiments, the second portions 582 of the conductive layer 552 are isolated from the first portions 581 of the conductive layer 552. The passivation layer 551 may have a first surface 55-1 (e.g., an upper surface) and a second surface 55-2 (e.g., a lower surface) opposite to the first surface 55-1. In some embodiments, the upper surface of the conductive layer 552 is coplanar with the first surface 55-1 (e.g., the upper surface) of the passivation layer 551, and the lower surface of the conductive layer 552 is coplanar with the second surface 55-2 (e.g., the lower surface) of the passivation layer 551.

[0267] Please refer to Figure 20Multiple external connectors 66 may be disposed on the lower surface of the conductive layer 552 for external connection. In some embodiments, the external connectors 66 may be connected to the fifth conductive structure 54 via a second portion 582 of the conductive layer 552 and a fifth conductive via 57. In some embodiments, the external connectors 66 may be connected to the fifth die 510 via a first portion 581 of the conductive layer 552 and a wire 511. In some embodiments, the external connectors 66 may include a reflowable material such as AgSn. In some embodiments, the external connectors 66 may include solder balls, solder bumps, or microbumps.

[0268] Please refer to Figures 21 to 24 A carrier structure 700 containing a heat dissipation unit HDU can be provided. The manufacture of the carrier structure 700 is described below.

[0269] Please refer to Figure 21 A carrier substrate 701 with multiple vias 703 can be provided. Next, multiple through-semiconductor vias (TSVs) 705 can be formed to fill the via openings 503. Figure 20 The carrier substrates 701 and TSV 705 can be respectively with Figure 1 The carrier substrate 701 and TSV 705 are the same or similar. The carrier substrate 701 may have a lower surface 713 (e.g., a first surface) and an upper surface 711 (e.g., a second surface), and may have a side surface 715 extending between the lower surface 713 and the upper surface 711. In some embodiments, after the TSV 705 is formed, a planarization process may be performed such that the upper surface of the TSV 705 is substantially coplanar with the upper surface 711 (e.g., the second surface) of the carrier substrate 701.

[0270] Figure 22 yes Figure 21 An enlarged schematic diagram of the TSV 705. (See attached image.) Figure 22 As shown, TSV 705 may include a filler layer FL, a seed layer SL, an attachment layer AL, a barrier layer BL, and an isolation layer IL. The isolation layer IL may be conformally formed in the via 703 and may have a U-shaped cross-sectional profile. For example, in some embodiments, the isolation layer IL may include silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The thickness of the isolation layer IL may be between about 50 nm and about 200 nm. Alternatively, in some embodiments, for example, the isolation layer IL may include parylene, epoxy resin, or poly(p-xylene). The thickness of the isolation layer IL may be between about 1 μm and about 5 μm. The isolation layer IL ensures electrical isolation of the filler layer FL within the carrier substrate 701.

[0271] Please refer to Figure 23Multiple conductive plates 707 can be formed on the carrier substrate 501, and the multiple conductive plates 707 can be spaced apart from each other. Each conductive plate 707 can be connected to two or more TSVs 705. For example, the conductive plates 707 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The conductive plates 707 and TSVs 705 together constitute the heat dissipation unit (HDU).

[0272] Please refer to Figure 24 A bonding layer 709 may be formed on the carrier substrate 701 to cover the conductive plate 707. A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps. In some embodiments, for example, the bonding layer 709 may include an organic material selected from undoped silicate glass, silicon nitride, silicon nitride oxide, silicon oxide, silicon oxynitride, and / or combinations thereof. In some embodiments, for example, the bonding layer 709 may include a polymer layer of epoxy resin, polyimide, benzocyclobutene, polybenzoxazole, or the like. The fabrication technique for the bonding layer 709 may include a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. The carrier substrate 701, the heat dissipation unit (HDU), and the bonding layer 709 together constitute the carrier structure 700. The carrier structure 700 may be used to bond with another die (or another wafer) to form an intermediate stack structure for further bonding procedures.

[0273] Please refer to Figures 25 to 28 An electronic component 6 may be provided, comprising a first assembly 71 (e.g., including a first semiconductor wafer 1 and a second semiconductor wafer 2), a second assembly 72 (e.g., including a third semiconductor wafer 3 and a fourth semiconductor wafer 4), a third assembly 73 (e.g., including a fifth semiconductor wafer 5 and a plurality of external connectors 66), a plurality of bumps 61, a filler 62, a plurality of electronic connectors 63, a protective material 64, a peripheral package 65, a carrier structure 700, and an intermediate bonding layer 801. The manufacture of the electronic component 6 is described below.

[0274] Please refer to Figure 25 The second component 72 can be engaged and electrically connected to the first component 71 via the bump 61. In some embodiments, a filler 62 can be formed or disposed in a space between the second component 72 and the first component 71 to cover the bump 61.

[0275] Please refer to Figure 26The first component 71 and the second component 72 can be engaged and electrically connected to the third component 73 via the electronic connector 63. In some embodiments, a protective material 64 can be formed or disposed between the first component 71 (or the first semiconductor wafer 1) and the third component 73 (or the fifth semiconductor wafer 5) to cover the electronic connector 63.

[0276] Please refer to Figure 27 It can form an external package 65 to encapsulate the first component 71 (including the first semiconductor wafer 1 and the second semiconductor wafer 2), the second component 72 (including the third semiconductor wafer 3 and the fourth semiconductor wafer 4) and the third component 73 (including the fifth semiconductor wafer 5 and a plurality of external connectors 66).

[0277] Please refer to Figure 28 A carrier structure 700 can be bonded to the second component 72 via an intermediate bonding layer 801. It should be understood that the carrier structure 700 can be flipped before being bonded to the second component 72. Once the carrier structure 700 is bonded to the second component 72, the electronic component 6 is obtained.

[0278] Figure 29 This is a flowchart illustrating a method 900 for preparing electronic component 6 according to some embodiments of this disclosure.

[0279] In some embodiments, the fabrication method 900 may include step S901, providing a first component, the first component including a first semiconductor wafer and a second semiconductor wafer stacked on the first semiconductor wafer and electrically connected to the first semiconductor wafer by hybrid bonding. For example, such as Figure 11 As shown, a first component 71 may be provided. The first component 71 includes a first semiconductor wafer 1 and a second semiconductor wafer 2 stacked on the first semiconductor wafer 1 and electrically connected to the first semiconductor wafer 1 by hybrid bonding.

[0280] In some embodiments, the fabrication method 900 may include step S902, providing a second component, the second component including a third semiconductor wafer and a fourth semiconductor wafer stacked on the third semiconductor wafer and electrically connected to the third semiconductor wafer by hybrid bonding. For example, such as Figure 17 As shown, a second component 72 may be provided. The second component 72 includes a third semiconductor wafer 3 and a fourth semiconductor wafer 4 stacked on the third semiconductor wafer 3 and electrically connected to the third semiconductor wafer 3 by hybrid bonding.

[0281] In some embodiments, the fabrication method 900 may include step S903, electrically connecting the second component to the first component via a plurality of bumps. For example, such as Figure 25As shown, the second component 72 can be electrically connected to the first component 71 via a plurality of bumps 61.

[0282] In some embodiments, the fabrication method 900 may include step S904, electrically connecting the first component to a third component 73, which includes a fifth semiconductor wafer and a plurality of external connectors 66, via a plurality of electronic connectors. For example, such as Figure 26 As shown, the second component 72 can be electrically connected to the third component 73 via multiple electronic connectors 63.

[0283] In some embodiments, the preparation method 900 may include step S905, encapsulating the first component, the second component, and the third component. For example, such as Figure 27 As shown, the peripheral package 65 can encapsulate the first component 71, the second component 72, and the third component 73.

[0284] In some embodiments, the preparation method 900 may include step S906, connecting a carrier structure to the second component via hybrid bonding. For example, such as Figure 28 As shown, the carrier structure 700 is connected to the second component 72 via a hybrid bonding process. It should be understood that the carrier structure 700 is flipped before being bonded to the second component 72.

[0285] One embodiment of this disclosure provides an electronic component including a first semiconductor wafer; a second semiconductor wafer stacked on the first semiconductor wafer and electrically connected to the first semiconductor wafer via hybrid bonding; a third semiconductor wafer stacked on the second semiconductor wafer and electrically connected to the second semiconductor wafer via a plurality of bumps; a fourth semiconductor wafer stacked on the third semiconductor wafer and electrically connected to the third semiconductor wafer via hybrid bonding; and a fifth semiconductor wafer disposed below the first semiconductor wafer and electrically connected to the first semiconductor wafer via a plurality of electronic connectors.

[0286] Another embodiment of this disclosure provides an electronic component including a first component, a second component, a base semiconductor wafer, and a carrier structure. The first component includes a first semiconductor wafer and a second semiconductor wafer stacked on the first semiconductor wafer, the second semiconductor wafer being electrically connected to the first semiconductor wafer via hybrid bonding. The second component includes a third semiconductor wafer and a fourth semiconductor wafer stacked on the third semiconductor wafer, the fourth semiconductor wafer being electrically connected to the third semiconductor wafer via hybrid bonding. The base semiconductor wafer is disposed below the first component and electrically connected to the first component via a plurality of electronic connectors. The carrier structure is disposed above the second component and electrically connected to the second component via hybrid bonding. The second component is electrically connected to the first component via a plurality of bumps. The first component is electrically connected to the base semiconductor wafer via a plurality of electronic connectors.

[0287] Another embodiment of this disclosure provides a method for fabricating an electronic component. The method includes forming a first assembly comprising a first semiconductor wafer, a second semiconductor wafer, and a plurality of electronic connectors, wherein the second semiconductor wafer is stacked on the first semiconductor wafer, and the electronic connectors are connected to the first semiconductor wafer; forming a second assembly comprising a third semiconductor wafer, a fourth semiconductor wafer, and a plurality of bumps, wherein the fourth semiconductor wafer is stacked on the third semiconductor wafer, and the bumps are connected to the third semiconductor wafer; and forming a third assembly comprising a fifth semiconductor wafer and a plurality of external connectors, wherein the third assembly includes a fifth lower structure and a fifth upper structure, and the external connectors are connected to the fifth lower structure. The method comprises: forming a carrier structure including a carrier substrate, a plurality of through-semiconductor vias penetrating the carrier substrate, a plurality of conductive plates located on the carrier substrate and the through-semiconductor vias, and a bonding layer located on the carrier substrate and covering the conductive plates; electrically connecting the second component to the first component via the plurality of bumps; electrically connecting the first component to the third component via a plurality of electronic connectors; encapsulating the first component, the second component, and the third component using a peripheral package surrounding the first component, the second component, and located on the third component; and performing a hybrid bonding to electrically connect the carrier structure to the second component and the peripheral package.

[0288] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0289] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. An electronic component comprising: a first semiconductor die; a second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die by hybrid bonding; a third semiconductor die stacked on the second semiconductor die and electrically connected to the second semiconductor die via a plurality of bumps; a fourth semiconductor die stacked on the third semiconductor die and electrically connected to the third semiconductor die by hybrid bonding; and a fifth semiconductor die disposed below the first semiconductor die and electrically connected to the first semiconductor die via a plurality of electronic connectors.

2. The electronic component of claim 1, wherein a lower surface of the second semiconductor die is in contact with an upper surface of the first semiconductor die.

3. The electronic component of claim 1, wherein a lower surface of the third semiconductor die is spaced apart from an upper surface of the second semiconductor die.

4. The electronic component of claim 1, wherein a lower surface of the fourth semiconductor die is in contact with an upper surface of the third semiconductor die.

5. The electronic component of claim 1, wherein a lower surface of the first semiconductor die is spaced apart from an upper surface of the fifth semiconductor die.

6. The electronic component of claim 3, further comprising an underfill disposed between the lower surface of the third semiconductor die and the upper surface of the second semiconductor die and configured to cover the plurality of bumps.

7. The electronic component of claim 5, further comprising an underfill disposed between the lower surface of the first semiconductor die and the upper surface of the fifth semiconductor die and configured to cover the plurality of electronic connectors.

8. The electronic component of claim 1, further comprising a peripheral package to encapsulate the first semiconductor die, the second semiconductor die, the third semiconductor die, the fourth semiconductor die, and the fifth semiconductor die.

9. The electronic component of claim 8, further comprising a carrier structure disposed above the fourth semiconductor die and the peripheral package.

10. The electronic component of claim 9, further comprising an intermediate bonding layer disposed on the fourth semiconductor die and the peripheral package and between the fourth semiconductor die and the carrier structure.

11. The electronic component of claim 10, wherein the carrier structure comprises: a carrier base disposed above the intermediate bonding layer; and a plurality of through-semiconductor vias disposed in the carrier base above the intermediate bonding layer; a bonding layer disposed between the carrier base and the intermediate bonding layer; and a plurality of conductive pads disposed in the bonding layer of the carrier structure and in contact with the through-semiconductor vias of the carrier structure.

12. An electronic component comprising: a first assembly comprising a first semiconductor die and a second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die by hybrid bonding; ​ ​ a second assembly including a third semiconductor die and a fourth semiconductor die stacked on the third semiconductor die and electrically connected to the third semiconductor die by hybrid bonding; a base semiconductor die disposed below the first assembly and electrically connected to the first assembly via a plurality of electronic connectors; and a carrier structure disposed above the second assembly and electrically connected to the second assembly by hybrid bonding, wherein the second assembly is electrically connected to the first assembly via a plurality of bumps; wherein the first assembly is electrically connected to the base semiconductor die via a plurality of electronic connectors.

13. The electronic component of claim 12, wherein the plurality of bumps comprises a reflowable material.

14. The electronic component of claim 12, wherein the first semiconductor die comprises: a first base; a first conductive structure disposed on a first surface of the first base; a first lower structure disposed on the first conductive structure; and a first upper structure disposed on a second surface of the first base, wherein the second surface of the first base is opposite the first surface of the first base, wherein the second semiconductor die comprises: a second base; a second conductive structure disposed on the second base; a second lower structure disposed on the second conductive structure; and a second upper structure disposed on the second base.

15. The electronic component of claim 14, wherein the first semiconductor die further comprises a first encapsulant disposed around the first base, the first conductive structure, the first lower structure, and the first upper structure, wherein the second semiconductor die contacts the first encapsulant.

16. The electronic component of claim 12, wherein the third semiconductor die comprises: a third base; a third conductive structure disposed on the third base; a third lower structure disposed on the third conductive structure; and a third upper structure disposed on the third base, wherein the fourth semiconductor die comprises: a fourth base; a fourth conductive structure disposed on the fourth base; and a fourth lower structure disposed on the fourth conductive structure.

17. The electronic component of claim 16, wherein the third semiconductor die further comprises a third encapsulant disposed around the third base, the third conductive structure, the third lower structure, and the third upper structure, wherein the fourth semiconductor die contacts the third encapsulant.

18. The electronic component of claim 12, wherein the base semiconductor die comprises: a base; a conductive structure disposed on the base; a lower structure disposed on the base portion; an upper structure disposed on the conductive structure; and a plurality of conductive vias extending through the base and electrically connected to the conductive structure.

19. The electronic component of claim 18, wherein the lower structure comprises: a passivation layer disposed on the base; and a conductive layer embedded in the passivation layer and electrically connected to the conductive vias.

20. The electronic component of claim 18, wherein the upper structure comprises: an upper dielectric layer; and a plurality of upper solder pads embedded in the upper dielectric layer. ​ ​ ​ ​ ​

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